2019 10th International Power Electronics, Drive Systems and Technologies Conference (PEDSTC)

12-14 February, Shiraz University, Iran

A Single-Switch High Step-Up DC-DC Converter Based

on Integrating Coupled Inductor and Voltage Multiplier
Cell for Renewable Energy Applications
Mahmoodreza Eskandarpour Azizkandi1, Farzad Sedaghati1,*, Hossein Shayeghi1, Senior Member, IEEE,
Morteza Dezhbord2
1
Department of Electrical Engineering, University of Mohaghegh Ardabili, Ardabil, Iran
2
Department of Electrical Engineering, University of Tabriz, Tabriz, Iran
m.eskandarpour@student.uma.ac.ir, farzad.sedaghati@uma.ac.ir, hshayeghi@gmail.com, m.dezhbord95@ms.tabrizu.ac.ir

Abstract - In this paper, a high step-up, single switch, non- capacitor converters, the high current stress on the
isolated, coupled inductor based DC-DC converter is proposed for semiconductors is the major problem. [9]. With regulating the
sustainable energy applications. A high voltage gain is achieved turn ratio in coupled-inductor based converters a high step up
by applying a coupled inductor and two voltage multiplier cells in
voltage gain can be obtained. However, the leakage inductance
the structure of proposed converter. The passive clamp that is
connected to the main switch recovers the coupled inductor energy makes a high voltage spike across the main switch and
leakage inductance energy and limits the voltage spike on the decreases the overall efficiency. Thus, to solve this issue,
power switch. Thus, low on-state resistance of the power switch converters based on coupled inductor with clamp circuit have
can be adapted to decrease the conduction loss. The features such been presented in [10-19]. High voltage gain, low voltage
as coupled inductor with a low turn ratio, high voltage conversion stress of semiconductors and leakage inductance’s energy
ratio in suitable duty cycles, , high efficiency, recycled energy of recovery are the main advantages of these converters. Some
leakage inductor and low voltage stress on the power switches high step up single switch converters are proposed in the
and diodes make the presented converter appropriate for recently published papers. However, in these converters, the
sustainable energy applications. The steady state analysis and
voltage gain is not large enough.
voltage stress of the power switch and diodes of the converter are
expressed in detail. Finally, simulation results in PSIM software This paper proposes a high step up single switch DC-DC
have been presented to confirm the performance of the suggested converter that is composed of voltage multiplier cells and a
structure. coupled inductor, in order to increase converter voltage
conversion ratio. Continuous conduction mode (CCM)
Index Terms – DC-DC converter, Coupled inductor, Single operation of the suggested topology in is discussed in this
switch, Voltage multiplier cell, Low voltage stress.
paper. Also, the suggested structure is compared with several
recent high step up topologies to demonstrate its advantages.
I. INTRODUCTION
The overall advantages of the suggested DC-DC converter are
In recent years, by growing emissions of carbon dioxide high voltage gain without extreme duty cycle, reduced voltage
and increasing environmental problems, such as global stress among semiconductors, low conduction and switching
warming and climate change the demand for sustainable losses, high efficiency and recycled energy of leakage
energy has been enhanced. The sustainable energy resources inductor.
such as photovoltaics (PV) and fuel cell (FC) generally need
high step up DC-DC converters in their output section to
II. OPERATION PRINCIPLE OF PROPOSED DC-DC CONVERTER
increase and regulate their output voltage [1]. The main
features of the high step up DC-DC converters are High Fig. 1 illustrates power circuit of suggested DC-DC
voltage gain, high efficiency and low voltage stress on
components. Recently, various DC-DC converters have been
presented to boost the conversion ratio of voltage [2, 3].
Generally, isolated converters have a high voltage
conversion ratio due to utilizing transformers with large turn
ratio. However, these converters have low conversion
efficiency and poor performance because of leakage
inductance [4, 5]. Switched inductor boost converters and
switched capacitor boost converters are common as well [6-8].
These converters have been utilized widely to obtain high
voltage gain. However, in switched inductor topologies, the
voltage stress among components is high and in the switched Fig. 1 Equivalent circuit of proposed DC-DC converter.

978-1-5386-9254-7/19/$31.00 ©2019 IEEE

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converter including power switch S, six diodes D1, D2, D3, D4,
D5 and DO, six capacitors C1- C5 and CO, one coupled inductor
and one output load, RO. According to Fig. 1, the coupled
inductor is modelled as an ideal transformer with the leakage
inductor, LLk and magnetic inductor, Lm. Also, NP and NS are
the numbers of primary and secondary winding turn of the
coupled inductor.
In order to simplify the suggested structure steady state
analysis, the following assumptions are considered:
1) All semiconductor components are considered to be ideal.
2) All capacitors size are large enough as voltage of the
capacitors are assumed to be constant.
3) The coupled inductor turn ratio, n, is identical to NS/NP.
The suggested converter operation principle in CCM
consists of 5 modes. Fig. 2 indicates the current flow path of
the presented structure at several time transitions and the
operation modes equivalent circuit are also depicted in Fig.
3. The five states are expressed as follow:
Mode 1 [t0, t1]: In the first mode, the switch S is turned on,
and diodes D3, D4 and DO are conducting. According to Fig.
3(a), the currents of leakage and magnetizing inductance
increase linearly. The C2 and C5 capacitors are charged and the
energy of the C3 and C4 and the coupled inductor secondary
side are transferred to the load. This time interval finishes
when the leakage inductance current reaches to the
magnetizing inductance current.
Mode 2 [t1, t2]: In the second mode, the switch S is still on and
the diodes D1, D3, D4 and DO are off and the diodes D2 and D5
are on as demonstrated in Fig. 3(b). In this mode, the capacitor
C4 is charged via the capacitor C5. The input source supplied
the leakage and magnetic inductors. Moreover, the C3
capacitor is charged via the transformer secondary side, and
the load is supplied by the CO. The second mode finishes as
the main switch is blocked. Fig. 2 Main waveforms of suggested DC-DC converter at CCM operation.
Mode 3 [t2, t3]: In the third mode, as demonstrated in Fig.
3(c), the switch S is turned off, and diodes D1, D2 and D5 are This time transition ends by turning on the main power switch
conducting. The current of leakage inductance reduces linearly again. It is important to say that in each time interval the
and flows among D1 diode and makes it on. Capacitors C2, C4 voltage across LK is different from another, thus LK is charged
and C5 are discharged and the CO provides energy to the load. by different slopes and also discharged by different slopes.
This state finishes when the iLm and iLk become identical.
Mode 4 [t3, t4]: In the fourth mode, the switch S is still off, and
diodes D1, D3, D4 and DO are conducting and diodes D2 and D5 III. STEADY-STATE ANALYSIS OF PROPOSED CONVERTER
are off. In this mode, the iLk and iLm reduces linearly. In Fig.
3(d) the current flow direction is illustrated. The input source To simplify steady state analysis of the converter, only
Vin and capacitors C3 and C4 charge CO and supply energy to stages 2, 4 and 5 are considered since these time intervals are
the RO. The Lk is demagnetized to C1 capacitor among diode large enough in comparison with stages 1 and 3. Also, the
D1 and this diode is conducting until the energy of LK is coupled inductor leakage inductance is neglected in the
entirely absorbed. Therefore, this stage finishes when the analysis. At mode 2, the main switch S is turned on, and the
diode D1 current reaches zero and turns off. input DC source is supplied Lm. So, the following equations
Mode 5 [t4, t5]: In the last mode, as illustrated in Fig. 3(e), the can be obtained according to Fig. 3(b):
diodes D3, D4 and DO are in on-state and the switch S is still V Lm =V in (1)
blocked. The iLk and iLm reduces linearly, too. In this mode, the
V C 3 − V C 1 −V C 2 = nV in (2)
input DC voltage, Vin and capacitors C3, C4 energy and both
sides of transformer charge the CO and provide the energy of And the following equation can be expressed as follow:
the RO.

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 DT s Ts
0 V in dt + DT (V in −V C 1 )dt = 0
s
(8)

DT s Ts
0 V in dt + DT (V in −V C 5 +V C 2 +V C 3 )dt = 0
s
(9)

From (8), the voltage across capacitor C1 is equal to (10).

V
V C 1 = in (10)
1− D
By using (6) and (10), the voltage across capacitor C2 is
achieved as follows:
nD
VC 2 = V in (11)
1− D
According to (2), (10) and (11), the voltage across capacitor
C3 is obtained by the following equation:
(n + 1)
VC 3 = V in (12)
1− D
From (9), and also by using (11) and (12), the voltage across
capacitor C5 is derived as follows:
(2 + n + nD )
VC 5 = V in (13)
1− D
Also, by replacing (10), (11) and (13) into (3), the VC4 is
determined as given in (14).
(n + 1)
VC 4 = V in (14)
1− D
From (7), (13) and (14), the voltage gain of the converter in
CCM, MCCM, is calculated as follows:
V (3 + 2n + nD )
M CCM = O = (15)
V in (1 − D )
The voltage gain of the converter in CCM, MCCM, versus
duty cycle, D, and coupled inductor turn ratio, n, is indicated
in Fig. 4. The voltage gain of the suggested DC-DC converter
is higher than the traditional boost DC-DC converter when the
turn ratio of coupled inductor is zero, The voltage conversion
ratio enhances significantly with increasing the coupled
inductor turn ratio.

Fig. 3 Current direction of operating modes during a period in CCM, (a)

Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, and (e) Mode 5.

V C 4 + V C 2 +V C 1 −V C 5 = 0 (3)
During modes 4 and 5, the magnetizing inductance is
discharged and the switch S is blocked. The voltage across the
Lm can be achieved as given in the following:
V Lm =V in −V C 1 (4)
V Lm =V in −V C 5 +V C 2 +V C 3 (5)
Voltage of capacitor C2, VC2, is determined as given in (6). Fig. 4 Voltage gain of presented converter, MCCM, versus switch S duty cycle,
V C 2 = nV C 1 − nV in (6) D, and coupled inductor turns ratio, n.

The following equation is achieved for the output voltage in

mode 4: IV. DESIGN PROCEDURE OF PROPOSED DC-DC CONVERTER
V O =V C 4 +V C 5 (7)
A. Voltage Stress Analysis
The following equations are determined by applying the volt- In order to choose proper semiconductor devices for
second balance law of inductor for Lm,: suggested topology, the voltage stress on the semiconductors,

529
such as power switch and diodes, are determined. The voltage TABLE 1. COMPARISON OF PRESENTED DC-DC CONVERTER WITH
SOME SIMILAR TOPOLOGIES.
stresses on S, D1~D5 and DO are obtained during CCM
Components Number Voltage Switch
operation as given in the following equations: conversio voltage
1 Reference Diode Cap Switch Core ratio stress
V stress −S 1 =V stress − D1 = V in (16)
1− D Presented 6 6 1 1 3+2n+nd M +n
n converter Vin
V stress −D 3 = V in (17) (1−D) 3n+3
1− D
Converter 6 6 1 1 1+2n+nd M +n
(n + 1) Vin
V stress −D 2,4,5,O = V in (18) in [18] (1−D) 3n+1
1− D
B. Capacitors Design Converter 6 6 1 1 1+2n+nd M +n
To obtain the voltage of the capacitors C1~C5, (10)-(14) in [17] Vin
(1−D) 3n+1
are used. The size of the capacitors C1~C5 is determined since,
the charges produced or absorbed by these capacitors are Converter 6 6 1 1 2+2n+nd M +n
in [19] Vin
equal: (1−D) 3n+2
ΔQ i I O T S Converter 5 5 1 1 2+3n−nd M −n
Ci = = (19) Vin
ΔV i rV i in [15] (1−D) 2n+2
where Vi is the capacitor average voltage and r is capacitor
Converter 5 5 1 1 2+2n−nd M −n
voltage ripple factor . in [16] Vin
(1−D) n+2
M=MCCM=VO / Vin

V. COMPARISON STUDY
90
In this section, some comparisons are presented to clarify
80
the suggested structure performance and confirm the above Proposed converter
Proposed in [17], [18]
analysis. The main merits of the suggested topology and 70
Proposed in [19]
Voltage gain (Mccm)

similar topologies presented in [15-19] are indicated in Table 60 Proposed in [16]

Proposed in [15]
1. According to this table, the components of the suggested 50
structure with considering the voltage conversion ratio is equal 40
with the converters proposed in [17-19], but the voltage gain
30
of the presented topology is higher than these topologies [17-
20
19]. Comparison results of the voltage gain of the suggested
topology and the other structures presented for various duty 10

cycles are indicated in Fig. 5(a). According to this figure, the 0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
suggested topology have a higher voltage gain than the other Duty cycle (D)
topologies for all ranges of duty cycles (even for very low duty (a)
cycles). Fig. 5(b) demonstrates the relevance among the 0.4
normalized voltage stress across main switch of the presented
Normilized switch voltage stress (Vs/Vo)

Proposed converter
0.35
structure and other structures. According to this figure, the Proposed in [17, 18]
Proposed in [19]
presented structure has less normalized voltage stress on the 0.3 Proposed in [16]
Proposed in [15]
main switch under the same voltage gain versus other 0.25
topologies. However, for the voltage gain less than 10, the
0.2
normalized voltage stress in structures presented in [15] and
[16] is less than the suggested structure. Therefore, the overall 0.15
efficiency will be increased and the implementation cost of the 0.1
suggested topology will be reduced.
0.05

0
VI. SIMULATION RESULTS 0 10 20 30 40 50
Voltage gain (Mccm=Vo/Vin)
To validate performance of presented converter, the (b)
simulation results in PSIM software are presented. The Fig. 5 Comparison of suggested structure with some recent high step up
converters: (a) voltage gain of various structures and presented converter for
specifications of the suggested topology are given as follow: several duty cycles, and (b) normalized voltage stress of switches against
Output power: 400W; input voltage: 30V; output voltage: voltage gain in several structures (n=2).
443V; switching frequency: 50kHz; C1~C5: 47uF; CO: 180uF;
Lm: 100 uH; n=NS/NP=2; duty cycle: 0.5. The simulation results of the presented topology are
shown in Figs. 6 and 7. The waveform of the output voltage is

530
depicted in Fig. 6(a). According to this figure, the measured
voltage is 443V. The waveforms of the capacitors C1~C5
voltage are demonstrated in Fig. 6(b). The leakage and
magnetizing inductance current are illustrated in Fig. 6(c).
These waveforms are similar to Fig. 2 that confirm the
theoretical analysis. The power switch current and voltage
stress are demonstrated in Fig. 7(a). The power switch voltage
stress is about 58V. Thus, a power switch with low on-state
resistance can be used. Also, according to Fig. 7(a), the duty
ratio of the presented topology is 50%. The voltage stress
(a)
waveforms of diodes D1, D2, D4, D3, D5 and DO are presented
in Figs. 7(b) and 7(c), respectively. The voltage stress of the
diodes validates the related analysis. Also, the currents of
diodes D1, D3, D4 and D5 are depicted in Fig. 7(d).

(b)

(a)

(c)

(b)

(d)
Fig. 7 Simulation results of presented DC-DC converter (a) voltage and
current of switch S, (b) voltage waveform of diodes D1, D2 and D4, (c) voltage
waveform of diodes D3, D5 and DO, and (d) current waveform of diodes D1,
D3, D4 and D5

The suggested topology efficiency for different output

powers is illustrated in Fig. 8. It is considered that rDS is
25m Ω and rD1~rD5, rDO, rLp , rLs , rC1~rC5, and rCO are 10m Ω .

(c)
Fig. 6 Simulation results of suggested DC-DC converter. (a) output voltage,
(b) voltage waveform of capacitors C1~C5, and (c) magnetizing and leakage
current of coupled-inductor.
The threshold voltages of the diodes D1, D2, D3, D4, D5 and DO
are also considered to be 1.5V, 0.7V, 0.8V, 0.7V, 0.7V and
0.7V respectively. The obtained efficiency of the suggested
structure for the output power of 400W is about 91.4% and the

531

Fig. 8 Efficiency of presented DC-DC converter.
obtained maximum efficiency under the output power of 110W
is 95.7%.
Finally, according to the simulation results, the feasibility
and performance of the suggested topologies are confirmed.
Several features of the suggested structures such as reduced
voltage stress across main switch and diodes, high voltage gain
in a suitable duty cycles with a low transformer turn ratio,
recycled leakage inductor and high efficiency make it
appropriate for sustainable energy applications.
VI. CONCLUSIONS
A high step up, non-isolated, high voltage gain DC-DC
converter was presented in this paper. By using voltage
multiplier cells and a coupled inductor, a high voltage gain is
obtained for the suggested topology. The voltage stress across
the power switch in the presented structure is low and power
switch with low on-state resistance can be chosen. The steady-
state analysis, operating principle and design procedure of the
presented structure are provided. Then, the presented topology
is compared with several similar converters where the
comparison results show that the proposed topology voltage
gain is higher and voltage stress on switching components is
lower than the other converters. Finally, to demonstrate the
performance of the presented structure, simulation results
under the output power of 400W were presented.
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