Papilio Pro Datasheet

Papilio Pro
Contents
Overview
The Papilio Pro is an Open Source FPGA development board based on the Xilinx Spartan 6 LX9 FPGA
Spartan 6 LX FPGA. It has 48 I/O lines, dual channel USB, integrated JTAG Power
programmer, 64Mb SDRAM, and an efficient switching power supply. SDRAM
Dual Channel USB
SPI Flash
I/O
Oscillator
JTAG
Reset
User LED
Links
License
Images
Papilio Pro - Pin Assignments

C B A
GND P114 GND P99 P100
32 0 16 015 15
P115 P97 P98
33 1 17 114 14
3V3 P116 3V3 P92 P93
34 2 18 213 13
5V P117 5V P87 P88
35 3 19 312 12 AH
CL BL
P118 P84 P85 5V
36 4 20 411 11
P119 P82 P83 3V3
37 5 21 510 10
P120 P80 P81
38 6 22 6 9 9
P121 P78 P79 GND
39 7 23 7 8 8
GND P123 GND P74 P75
40 8 24 8 7 7
P124 P95 P67
41 9 25 9 6 6
3V3 P126 3V3 P62 P66
42 10 26 10 5 5
5V P127 5V P59 P61
43 11 27 11 4 4 AL
CH BH
P131 P57 P58 5V
Spartan 6 LX9 FPGA (Datasheet) 44 12 28 12 3 3
P132 P55 P56 3V3
High efficiency LTC3419 Step Down Dual Voltage Regulator (Datasheet) 45 13 29 13 2 2
P133 P50 P51
Dual Channel FTDI FT2232 USB 2.0 Full Speed Interface (Datasheet) 46 14 30 14 1 1
P134 P47 P48
64Mbit Micron MT48LC4M16 SDRAM (Datasheet) 47 15 Arduino Pins 31 15 0 0
GND
64Mbit Macronix MX25L6445 SPI Flash (Datasheet) Device: xc6slx9-2-tqg144 CLK

Package: TQG144 P94 31.25ns
48 I/O pins arranged in a Papilio Wing form factor Speed: -2 32MHz
32Mhz Crystal Oscillator

Sp artan 6 LX9 FP GA
The Papilio Pro's Spartan 6 FPGA offers some exciting new features over the
Spartan 3:
Digital Signal Processing (DSP) Slices
18 DSP48A1 Slices for DSP functions.
Clock Management Tile (CMT)
The Papilio One (Spartan 3E) offered 4 Digital Clock Managers (DCM) but did not
offer any Phase-Locked Loops (PLL). The Papilio Pro (Spartan 6) offers the more
flexible CMT which provides both DCM's and PLL's!
New I/O Standards
The Papilio Pro (Spartan 6) has direct TMDS I/O support which
means that DVI and HDMI interfaces can be implemented without
any extra chips.
MultiBoot Support
You can load multiple bit files into the SPI Flash and setup the first
bit file to select which one will be loaded. With some work we could
make a ZPUino based bootloader that would have a VGA interface to
choose which bit file to load.
BRAM Memory Blocks
FPGA Schematic
The Spartan 6 allows 18Kbit BRAM blocks to be split into two 9Kbit
BRAM blocks.
There is more built in SRAM - there is 64KByte of internal SRAM which is just enough to recreate the Commodore 64!
Papilio Board 18Kbit BRAM Blocks Max SRAM Usable SRAM
Papilio Pro 32 576Kbit (72KByte) 512Kbit (64KByte)
Papilio One 500K 20 360Kbit (45KByte) 320Kbit (40KByte)
Papilio One 250K 12 216Kbit (27KByte) 192Kbit (24KByte)
BRAM's are 18Kbit in size including two parity bits. In most cases the two parity bits are not used
so the BRAM's usable size becomes 16Kbit. If your design can use an 18 bit wide bus then it is
possible to utilize the parity bits for data and gain access to all 18Kbit memory space.
P ow er
One of the big improvements with the

Papilio Pro is its power supply. The
Spartan 6 simplifies the power
requirements which allowed us to use a
high efficiency LTC3419 switching
power supply at about the same
component cost as the Papilio One's
power supply. The linear regulators
used in the Papilio One would noticeably heat up when a
complicated, high speed design, like the ZPUino, was running. With
the Papilio Pro there is no detectable heat generated, even when the
most demanding designs are running!
Power Schematic
SDRAM
The Papilio Pro includes a 64Mbit Micron MT48LC4M16 SDRAM

chip. This additional SDRAM will open up a whole new breed of FPGA
applications for the Papilio. The timing requirements and refresh
signals of the SDRAM chip do make interfacing it more of a challenge
than interfacing regular SRAM, or the internal BRAM. We are working
on a SDRAM controller that you can drop into your designs so the
SDRAM can be used like regular SRAM.
SDRAM Desig ns
Hamster's SDRAM Controller

Alvie's ZPUino SDRAM controller. (derived from Hamster's SDRAM controller).
Wishbone wrapper for Alvie's SDRAM controller.
XAPP 394 Interfacing Mobile SDRAM with CPLD's.
The ZPUino Soft Processor includes a SDRAM controller which gives your ZPUino sketches
8MByte of code space!
Dual C hannel US B
The Papilio Pro uses the same FT2232 dual channel USB chip that the Papilio
One does.
Channel A is connected to the Papilio Pro in an Asynchronous serial UART

configuration that is capable of speeds up to 2MHz.
Channel B is connected to the JTAG pins of the Papilio Pro and provides
very fast programming of the FPGA (500mS).
USB Schematic
Direction (FPGA Arduino Papilio Wing Papilio Pro

Name Function
Perspective) Pin Pin Pin
FPGA Serial Receive

RX Input N/A N/A P101
(MISO)
FPGA Serial Transmit

TX Output N/A N/A P105
(MOSI)
SP I Flash
The 64Mbit Macronix MX25L6445 SPI Flash chip is the largest

ever included with a Papilio FPGA. It is the largest available in
the 8-SOIC footprint, and is included for good reason! The new
multi-boot feature of the Spartan 6 means we can put as many
FPGA bit files on the SPI Flash as will fit and use a "golden
image" to select which one will boot at startup. Spartan 6 LX9 bit files are
333KBytes in size which means that the Papilio Pro can save up to 23 bit files in SPI Flash. Or, we can save and retrieve user
data using techniques like the SmallFS filesystem or bootstrap code that loads data from SPI Flash to SRAM at startup.

Name Function
FLASH_CS Output SPI Flash Chip Select N/A N/A P38
FLASH_CLK Output SPI Flash Clock N/A N/A P70
SPI Flash Master Out Slave In

FLASH_MOSI Output N/A N/A P64
(MOSI)
SPI Flash Master In Slave Out

FLASH_MISO Input N/A N/A P65
(MISO)
I/ O
The I/O of the Papilio Pro is backwards

compatible with the Papilio One, all existing
Papilio Wings and MegaWings work with the
Papilio Pro.
The major difference between the Papilio Pro and

Papilio One with respect to User I/O is the
available voltage levels. The Papilio Pro sets all
I/O voltage pins to 3.3V while the Papilio One can
switch between 1.2V, 2.5V, and 3.3V. This was a
seldom used feature that was dropped in the
Papilio Pro for greater compatibility. Additionally,
the Papilio Pro does not provide a 2.5V power rail,
the 2.5V pin on the Wing Header is left unconnected. There are no Wings or MegaWings that use 2.5V
power and there probably never will be... 3.3V seems to be the defacto standard for current peripherals.
O sci l la to r
The Papilio Pro has a 32Mhz oscillator that can be converted to

any speed desired inside the FPGA using the Clock
Management Tile (CMT). There are two PLLs and two Digital
Clock Managers (DCM) available for your designs.

Name Function
External 32Mhz
CLK Input N/A N/A P94
Oscillator
J TA G
The JTAG header on the Papilio Pro is provided for a couple different
reasons:
Use a Xilinx Programming Cable
If you want to use the Xilinx tools such as EDK, Chipscope, or Impact with the
Papilio you need a way to use a Xilinx programming cable. The Papilio has a Xilinx
JTAG header but the problem is that in the default mode the FT2232D USB chip is
connected to the JTAG pins and interferes with programming. What is needed is to
put the FT2232 into a mode where the JTAG pins go into High-Z leaving the Xilinx JTAG pins free for the
programming cable. To learn more about using a Xilinx Programming Cable visit the original forum post or blog post.
Bypass the FPGA and use the FT2232 as a JTAG/SPI/MPSSE Programmer
The Papilio Pro provides the JP4 pin header, jumping this header will hold the Spartan 6 FPGA in a reset state which
frees up the JTAG pins to be controlled by the FT2232. OpenOCD, FlashRAM, and any other FT2232 based software
should work directly with this method.
Name Direction (FPGA Perspective) Function Arduino Pin Papilio Wing Pin Papilio Pro Pin
JTAG_TMS Input JTAG TMS N/A N/A P107
JTAG_TCK Input JTAG TCK N/A N/A P109
JTAG_SI Input JTAG SI N/A N/A P64
JTAG_SO Output JTAG SO N/A N/A P65

Reset
Pressing the reset button will cause the Spartan 6 FPGA to

do a hard reset and reload the first bit file from SPI Flash.
This is a pretty drastic measure that will wipe out anything
running on the FPGA. In most cases it is more desirable to
utilize a user button to perform a reset within your design
that just initializes all registers to zero.
RESET Input FPGA Reset N/A N/A P37
User LE D
The Papilio Pro provides one user LED that is connected directly to the Spartan 6 FPGA. It is not
shared with any of the I/O pins and can be controlled directly from your VHDL or sketches.
LED1 Output USER LED1 N/A N/A P112
Papilio Pro is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
Papilio Pro copyright Jack Gassett, Gadget Factory.
© Gadget Factory 2009-2013

3V3 delays 1V2 start 3V3
U5
L1
2 4
RUN1 SW1 3.3uH
9
RUN2 R14
5V0 1
22u/6V3
VFB1
3 6K8 1%
MODE
C48
1K5 1%
R15
7 1V2
VIN
VIW2@2 VIW2@1 VIW1@4 VIW1@3 5V
VIW1@1 VIW1@2
10u/10V
3V3W2@2 3V3W2@1 3V3W1@4 3V3W1@3 3V3
3V3W1@1 3V3W1@2 GND GND
C49
L2
2V5W2@2 2V5W2@1 2V5W1@4 2V5W1@3 2V5W1@1 2V5W1@2 8
SW2 3.3uH
GNDW2@2 GNDW2@1 GNDW1@4 GNDW1@3 GND
GNDW1@1 GNDW1@2 5
GND R16
6 10
22u/6V3
GND VFB2
1K5 1%
C50
1K5 1%
LTC3419EMS
R17
3V3 1V2 3V3 3V3 3V3 3V3 3V3 GND
GND GND
3V3
IC1P
GND
1
VDD
5V
14
VDD
27
VDD
3
VDDQ
9
VDDQ
43 VI 1 PWRIN
VDDQ
Green
49 2
PWR
VDDQ
6
VSSQ
12
VSSQ GND
46
VSSQ
52
VSSQ GND
28 3V3 1V2
VSS
41
VSS
54
VSS
MT48LC64M4A2 108 129 128

GND VCCAUX VCCINT
113 20 19
GND VCCAUX VCCINT
13 36 28
GND VCCAUX VCCINT
GND 130 53 52
GND VCCAUX VCCINT
136 90 89
GND VCCAUX VCCINT
25
GND
3 U8BVCCAUX U8BVCCINT
GND
49 6SLX9TQG144 6SLX9TQG144
GND
54
GND
68
GND
GND
77 Power Requirements
GND
91 VCCINT requires 1.2V
GND
96 VCCAUX requires 3.3V
VCCO's are 3.3V (no longer selectable) Power Section
U8BGND
6SLX9TQG144 Copyright 2012 Gadget Factory, LLC
GND
See more details at www.GadgetFactory.net
5V0
TCK
3 VI
2 5V U3
1 3 24 USB_TCK TDI
0.1uF
0.1uF
VCC ADBUS0
C11
42 23 USB_TDI
C4
PWRSELECT VCC ADBUS1

4
RESET# ADBUS2
22 TDO
3V3
14
VCCIOA ADBUS3
21 USB_TMS
GND GND 3V3
31
VCCIOB ADBUS4
20
19
C7 ADBUS5
46 17 TMS
GND GND
AVCC ADBUS6
16
0.1uF C5 ADBUS7
6
3V3OUT
1 0.1uF ACBUS0
15 USB_TXD
8 13
2 USBDM ACBUS1
7 12
3 USBDP ACBUS2
4 ACBUS3
11 USB_RXD
5 10 3V3
0.1uF
5 RSTOUT# SI/WUA
C9
6MHz
C12
40
BDBUS0
X1
43 39
27pF XTIN BDBUS1
GND GND 38
GND
BDBUS2
5V0 44 37
C6 XTOUT BDBUS3
36
BDBUS4
U1 35
27pF BDBUS5
6
VCC CS
5 EECS_A 48 EECS BDBUS6
33
CLK
4 EESK 1
EESK BDBUS7
32
3 EEDATA_A 2 3V3
0.1uF
DI EEDATA
2 1
C3
30
GND DO
47
BCBUS0
29
RX
TEST BCBUS1 Green
93C46B 45
GND BCBUS2
28
GND GND 93LC46B 9
GND BCBUS3
27 3V3
18
GND SI/WUB
26 3V3 TX
25
5V0
GND Green
34 41
GND PWREN#
FT2232D
GND
USB Section
Copyright 2012 Gadget Factory, LLC
This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike License.
To view a copy of this license, visit http://creativecommons.org/ ; or, (b) send a letter to Creative Commons, 171 2nd Street, Suite 300, San Francisco, California, 94105, USA.
6SLX9TQG144
U8B0 3V3
112 LED1 103 W1_A[1..16],W1_B[1..16],W2_A[1..16]
IO_L66P_SCP1_0 VCCO_1
111 76
IO_L66N_SCP0_0 VCCO_1 COCOON_48BIT COCOON_48BIT
115 W2_A2 86
IO_L65P_SCP3_0 VCCO_1 A
114 W2_A1 3V3 OSC_IN 104 B A
IO_L65N_SCP2_0 IO_L1N_VREF_1
117 W2_A4 USB_RXD 105 A16@2 W2_A16 W1_B16 B16@1 A1@1 W1_A1
IO_L64P_SCP5_0 IO_L1P_1
116 W2_A3 3V3 GND USB_TXD 101 A15@2 W2_A15 W1_B15 B15@1 A2@1 W1_A2
IO_L64N_SCP4_0 IO_L32N_1
119 W2_A6 102 A14@2 W2_A14 W1_B14 B14@1 A3@1 W1_A3
IO_L63P_SCP7_0 IO_L32P_1
118 W2_A5 W1_B1 99 A13@2 W2_A13 W1_B13 B13@1 A4@1 W1_A4
IO_L63N_SCP6_0 IO_L33N_1
121 W2_A8 W1_A16100 A12@2 W2_A12 W1_B12 B12@1 A5@1 W1_A5
IO_L62P_0 IO_L33P_1
120 W2_A7 W1_B2 97 A11@2 W2_A11 W1_B11 B11@1 A6@1 W1_A6
IO_L62N_VREF_0 U7 IO_L34N_1
124W2_A10 W1_A15 98 A10@2 W2_A10 W1_B10 B10@1 A7@1 W1_A7
IO_L37P_GCLK13_0 IO_L34P_1
123 W2_A9 FLASH_CS 1 8 3V3 OSC_IN 94 A9@2 W2_A9 W1_B9 B9@1 A8@1 W1_A8
IO_L37N_GCLK12_0 CS VCC IO_L40N_GCLK10_1
127W2_A12 FLASH_SO 2 7 3V3 W1_B10 95 A8@2 W2_A8 W1_B8 B8@1 A9@1 W1_A9
IO_L36P_GCLK15_0 MISO HOLD IO_L40P_GCLK11_1
126W2_A11 3V3 3 6FLASH_SCK W1_B3 92 A7@2 W2_A7 W1_B7 B7@1 W1_A10
A10@1
IO_L36N_GCLK14_0 WP SCK IO_L41N_GCLK8_1
132W2_A14 GND 4 5 FLASH_SI W1_A14 93 A6@2 W2_A6 W1_B6 B6@1 A11@1W1_A11
IO_L35P_GCLK17_0 GND MOSI IO_L41P_GCLK9_IRDY1_1
131W2_A13 W1_B4 87 A5@2 W2_A5 W1_B5 B5@1 W1_A12
A12@1
IO_L35N_GCLK16_0 IO_L42N_GCLK6_TRDY1_1
134W2_A16 FLASH-SPI-25XXSMD1 W1_A13 88 A4@2 W2_A4 W1_B4 B4@1 W1_A13
A13@1
IO_L34P_GCLK19_0 IO_L42P_GCLK7_1
133W2_A15 W1_B5 84 A3@2 W2_A3 W1_B3 B3@1 W1_A14
A14@1
IO_L34N_GCLK18_0 IO_L43N_GCLK4_1
IO_L4P_0
138 A2 W1_A12 85 IO_L43P_GCLK5_1 A2@2 W2_A2 W1_B2 B2@1 W1_A15
A15@1
IO_L4N_0
137 A3 W1_B6 82 IO_L45N_1 A1@2 W2_A1 W1_B1 B1@1 W1_A16
A16@1
IO_L3P_0
140 A0 W1_A11 83 IO_L45P_1
IO_L3N_0
139 A1 W1_B7 80 IO_L46N_1
142 BA1 W1_A10 81 U$1WING2 U$1WING1
IO_L2P_0 IO_L46P_1
A[0..18],D[0..15],CS,WE,OE,BHE,BLE,CAS,RAS
IO_L2N_0
141 A10 W1_B8 78 IO_L47N_1
144 W1_A9 79 JTAG
GND
IO_L1P_HSWAPEN_0 IO_L47P_1
IO_L1N_VREF_0
143 BA0 W1_B9 74 IO_L74N_DOUT_BUSY_1
135 3V3 W1_A8 75 U$1JTAG 6SLX9TQG144
VCCO_0 IO_L74P_AWAKE_1 U8BNA
VCCO_0
125 JTAG_REF 3V3
VCCO_0
122 CY7C1041D U8B1 JTAG_GND GND 107
TMS
IS61WV25616 3V3 6SLX9TQG144 JTAG_TCK TCK TMS 106 TDO
TDO TDO 110
W1_A[1..16],W1_B[1..16],W2_A[1..16]
IS62WV51216 JTAG_TDO TDI

6SLX9TQG144 42 JTAG_TDI TDI TDI 109
VCCO_2 TCK
U8B3 63
VCCO_2 JTAG_TMS TMS TCK 73 SUSPEND
2 RAS 3V3 72
IO_L83P_3 IC1 CMPCS_B_2
1 CS 71 COCOON_48BIT GND
IO_L83N_VREF_3 DONE_2
6 WE CLK 38 40 3V3 69
IO_L52P_3 CLK NC IO_L1N_M0_CMPMISO_2
IO_L52N_3
5 CAS CKE 37 CKE FLASH_SCK 70 IO_L1P_CCLK_2 JTAG Configuration
8 DQ7 CS 19 2 DQ0 W1_A6 66 HSWAP low pulls up all pins during configuration
IO_L51P_3 CS DQ0 IO_L2N_CMPMOSI_2
7 DQML 4 DQ1 W1_A7 67 M0 high, M1 low puts FPGA in Master Serial / SPI mode
IO_L51N_3 DQ1 IO_L2P_CMPCLK_2
IO_L50P_3
10 DQ1 DQML 15 DQML DQ2
5 DQ2 FLASH_SI 64
IO_L3N_MOSI_CSI_B_MISO0_2 PROG_B asserted causes a JTAG reconfiguration
IO_L50N_3
9 DQ0 DQMH 39 DQMH DQ3
7 DQ3 FLASH_SO 65 IO_L3P_D0_DIN_MISO_MISO1_2
12 DQ3 8 DQ4 W1_A5 61
IO_L49P_3 DQ4 IO_L12N_D2_MISO3_2
LED1
IO_L49N_3
11 DQ2 BA0 20 BA0 DQ5
10 DQ5 W1_B11 62
IO_L12P_D1_MISO2_2
IO_L44P_GCLK21_3
15 DQ5 BA1 21 BA1 DQ6
11 DQ6 W1_B12 59
IO_L13N_D10_2
14 DQ4 13 DQ7 60 3V3
GND
IO_L44N_GCLK20_3 DQ7 IO_L13P_M1_2

17 DQMH A0 23 42 DQ8 W1_B13 57
IO_L43P_GCLK23_3 A0 DQ8 IO_L14N_D12_2
16 DQ6 A1 24 44 DQ9 W1_A4 58
LED1 390
IO_L43N_GCLK22_IRDY2_3 A1 DQ9 IO_L14P_D11_2 SW1

22 DQ9 A2 25 45 DQ10 W1_B14 55
IO_L42P_GCLK25_TRDY2_3 A2 DQ10 IO_L30N_GCLK0_USERCCLK_2 EVQQ2
21 DQ8 A3 26 47 DQ11 W1_A3 56
A3 DQ11
Green
IO_L42N_GCLK24_3 IO_L30P_GCLK1_D13_2
47K
24 DQ11 A4 29 48 DQ12 W1_B15 50 REBOOT B A

IO_L41P_GCLK27_3 A4 DQ12 IO_L31N_GCLK30_D15_2 JP4
23 DQ10 A5 30 50 DQ13 W1_A2 51 B' A' REBOOT 1
IO_L41N_GCLK26_3 A5 DQ13 IO_L31P_GCLK31_D14_2
27 DQ13 A6 31 51 DQ14 W1_B16 47 2
IO_L37P_3 A6 DQ14 IO_L48N_RDWR_B_VREF_2
26 DQ12 A7 32 53 DQ15 W1_A1 48 GND
IO_L37N_3 A7 DQ15 IO_L48P_D7_2
30 DQ15 A8 33 A5 45
IO_L36P_3 A8 IO_L49N_D4_2 GND GND
29 DQ14 A9 34 16 WE A4 46
IO_L36N_3 A9 WE IO_L49P_D3_2
33 CKE A10 22 A7 43
IO_L2P_3 A10 IO_L62N_D6_2
32 CLK A11 35 17 CAS A6 44
IO_L2N_3 A11 CAS IO_L62P_D5_2
35 A11 A12 36 18 RAS A9 40
IO_L1P_3 A12 RAS IO_L64N_D9_2
IO_L1N_VREF_3
34 A12
3V3
A8 41
IO_L64P_D8_2 FPGA Section
VCCO_3
4 MT48LC64M4A2 FLASH_CS 38 IO_L65N_CSO_B_2
VCCO_3
31 39
IO_L65P_INIT_B_2 Copyright 2012 Gadget Factory, LLC
VCCO_3
18 REBOOT 37
PROGRAM_B_2
This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike License. U8B2
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PWRIN
USB
PWR
PWRSELECT
3
2
LED1 R12
RX
1
TX
R13
U7
IC1 JP4
SW1
LX4 LX9
11
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011 Product Specification
General Description
The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The
thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous
Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that
delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-
up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation
DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power-
optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-
cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for
high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable
designers to focus on innovation as soon as their development cycle begins.
Summary of Spartan-6 FPGA Features
• Spartan-6 Family: • Integrated Memory Controller blocks
• Spartan-6 LX FPGA: Logic optimized • DDR, DDR2, DDR3, and LPDDR support
• Spartan-6 LXT FPGA: High-speed serial connectivity • Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)
• Designed for low cost • Multi-port bus structure with independent FIFO to reduce
• Multiple efficient integrated blocks design timing issues
• Optimized selection of I/O standards • Abundant logic resources with increased logic capacity
• Staggered pads • Optional shift register or distributed RAM support
• High-volume plastic wire-bonded packages • Efficient 6-input LUTs improve performance and
• Low static and dynamic power minimize power
• 45 nm process optimized for cost and low power • LUT with dual flip-flops for pipeline centric applications
• Hibernate power-down mode for zero power • Block RAM with a wide range of granularity
• Suspend mode maintains state and configuration with • Fast block RAM with byte write enable
multi-pin wake-up, control enhancement • 18 Kb blocks that can be optionally programmed as two
• Lower-power 1.0V core voltage (LX FPGAs, -1L only) independent 9 Kb block RAMs
• High performance 1.2V core voltage (LX and LXT • Clock Management Tile (CMT) for enhanced performance
FPGAs, -2, -3, and -3N speed grades) • Low noise, flexible clocking
• Multi-voltage, multi-standard SelectIO™ interface banks • Digital Clock Managers (DCMs) eliminate clock skew
• Up to 1,080 Mb/s data transfer rate per differential I/O and duty cycle distortion
• Selectable output drive, up to 24 mA per pin • Phase-Locked Loops (PLLs) for low-jitter clocking
• 3.3V to 1.2V I/O standards and protocols • Frequency synthesis with simultaneous multiplication,
• Low-cost HSTL and SSTL memory interfaces division, and phase shifting
• Hot swap compliance • Sixteen low-skew global clock networks
• Adjustable I/O slew rates to improve signal integrity • Simplified configuration, supports low-cost standards
• High-speed GTP serial transceivers in the LXT FPGAs • 2-pin auto-detect configuration
• Up to 3.2 Gb/s • Broad third-party SPI (up to x4) and NOR flash support
• High-speed interfaces including: Serial ATA, Aurora, • Feature rich Xilinx Platform Flash with JTAG
1G Ethernet, PCI Express, OBSAI, CPRI, EPON, • MultiBoot support for remote upgrade with multiple
GPON, DisplayPort, and XAUI bitstreams, using watchdog protection
• Integrated Endpoint block for PCI Express designs (LXT) • Enhanced security for design protection
• Low-cost PCI® technology support compatible with the • Unique Device DNA identifier for design authentication
33 MHz, 32- and 64-bit specification. • AES bitstream encryption in the larger devices
• Efficient DSP48A1 slices • Faster embedded processing with enhanced, low cost,
• High-performance arithmetic and signal processing MicroBlaze™ soft processor
• Fast 18 x 18 multiplier and 48-bit accumulator • Industry-leading IP and reference designs
• Pipelining and cascading capability
• Pre-adder to assist filter applications
© 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS160 (v2.0) October 25, 2011 www.xilinx.com

Product Specification 1
Spartan-6 FPGA Feature Summary

Table 1: Spartan-6 FPGA Feature Summary by Device
Configurable Logic Blocks (CLBs) Block RAM Blocks
Memory
Endpoint Maximum Total Max
Device Logic Max DSP48A1 CMTs(5)
Controller
Blocks for
Cells(1) GTP I/O User
Slices(3) Blocks
Slices(2) Flip-Flops Distributed 18 Kb(4) Max (Kb)
(Max)(6) PCI Express Transceivers Banks I/O
RAM (Kb)
XC6SLX4 3,840 600 4,800 75 8 12 216 2 0 0 0 4 132

XC6SLX9 9,152 1,430 11,440 90 16 32 576 2 2 0 0 4 200
XC6SLX16 14,579 2,278 18,224 136 32 32 576 2 2 0 0 4 232
XC6SLX25 24,051 3,758 30,064 229 38 52 936 2 2 0 0 4 266
XC6SLX45 43,661 6,822 54,576 401 58 116 2,088 4 2 0 0 4 358
XC6SLX75 74,637 11,662 93,296 692 132 172 3,096 6 4 0 0 6 408
XC6SLX100 101,261 15,822 126,576 976 180 268 4,824 6 4 0 0 6 480
XC6SLX150 147,443 23,038 184,304 1,355 180 268 4,824 6 4 0 0 6 576
XC6SLX25T 24,051 3,758 30,064 229 38 52 936 2 2 1 2 4 250
XC6SLX45T 43,661 6,822 54,576 401 58 116 2,088 4 2 1 4 4 296
XC6SLX75T 74,637 11,662 93,296 692 132 172 3,096 6 4 1 8 6 348
XC6SLX100T 101,261 15,822 126,576 976 180 268 4,824 6 4 1 8 6 498
XC6SLX150T 147,443 23,038 184,304 1,355 180 268 4,824 6 4 1 8 6 540
Notes:
1. Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
2. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
3. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
4. Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
5. Each CMT contains two DCMs and one PLL.
6. Memory Controller Blocks are not supported in the -3N speed grade.

Spartan-6 FPGA Device-Package Combinations and Available I/Os

Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in Table 2.
Due to the transceivers, the LX and LXT pinouts are not compatible.
Table 2: Spartan-6 Device-Package Combinations and Maximum Available I/Os

Package CPG196(1) TQG144(1) CSG225(2) FT(G)256(3) CSG324 FG(G)484(3,4) CSG484(4) FG(G)676(3) FG(G)900(3)
Body Size 8x8 20 x 20 13 x 13 17 x 17 15 x 15 23 x 23 19 x 19 27 x 27 31 x 31
(mm)
Pitch (mm) 0.5 0.5 0.8 1.0 0.8 1.0 0.8 1.0 1.0
User User User User User
Device User I/O User I/O User I/O User I/O GTPs
I/O
GTPs
I/O
GTPs
I/O
GTPs
I/O
GTPs
I/O
XC6SLX4 106 102 132
XC6SLX9 106 102 160 186 NA 200
XC6SLX16 106 160 186 NA 232
XC6SLX25 186 NA 226 NA 266
XC6SLX45 NA 218 NA 316 NA 320 NA 358
XC6SLX75 NA 280 NA 328 NA 408
XC6SLX100 NA 326 NA 338 NA 480
XC6SLX150 NA 338 NA 338 NA 498 NA 576
XC6SLX25T 2 190 2 250
XC6SLX45T 4 190 4 296 4 296
XC6SLX75T 4 268 4 292 8 348
XC6SLX100T 4 296 4 296 8 376 8 498
XC6SLX150T 4 296 4 296 8 396 8 540
Notes:
1. There is no memory controller on the devices in these packages.
2. Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the
XC6SLX4.
3. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
4. These packages support two of the four memory controllers in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and
XC6SLX150T devices.
Configuration
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits
is between 3 Mb and 33 Mb depending on device size and user-design implementation options. The configuration storage
is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling
the PROGRAM_B pin Low. Several methods and data formats for loading configuration are available.
Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations,
master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and
16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an
external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan
protocols to load bit-serial configuration data.

The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration
process typically executes the following sequence:
• Detects power-up (power-on reset) or PROGRAM_B when Low.
• Clears the whole configuration memory.
• Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.
• Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
• Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the
DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.
The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods
used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial
flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash.
Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using
Spartan-6 FPGAs in TQG144 and CPG196 packages.
Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored in a
single configuration source. The FPGA application controls which configuration to load next and when to load it.
Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier that is useful for tracking purposes, anti-
cloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.
Readback
Most configuration data can be read back without affecting the system’s operation.
CLBs, Slices, and LUTs

Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical
columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice
contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and
sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.
Expert designers can also instantiate them.
SLICEM
One quarter (25%) of Spartan-6 FPGA slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a
6-input LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These
LUTs can also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register
(SRL32), or as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop
within the CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.
SLICEL
One quarter (25%) of Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the
memory/shift register function.
SLICEX
One half (50%) of Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the
arithmetic carry option and the wide multiplexers.

Clock Management
Each Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually or
cascaded.
DCM
The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270° (CLK0, CLK90, CLK180, and
CLK270). It also provides a doubled frequency CLK2X and its complement CLK2X180. The CLKDV output provides a
fractional clock frequency that can be phase-aligned to CLK0. The fraction is programmable as every integer from 2 to 16,
as well as 1.5, 2.5, 3.5 . . . 7.5. CLKIN can optionally be divided by 2. The DCM can be a zero-delay clock buffer when a clock
signal drives CLKIN, while the CLK0 output is fed back to the CLKFB input.
Frequency Synthesis
Independent of the basic DCM functionality, the frequency synthesis outputs CLKFX and CLKFX180 can be programmed to
generate any output frequency that is the DCM input frequency (FIN) multiplied by M and simultaneously divided by D, where
M can be any integer from 2 to 32 and D can be any integer from 1 to 32.
Phase Shifting
With CLK0 connected to CLKFB, all nine CLK outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, and CLKFX180) can be shifted by a common amount, defined as any integer multiple of a fixed delay. A fixed DCM
delay value (fraction of the input period) can be established by configuration and can also be incremented or decremented
dynamically.
Spread-Spectrum Clocking
The DCM can accept and track typical spread-spectrum clock inputs, provided they abide by the input clock specifications
listed in the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. Spartan-6 FPGAs can generate a spread-
spectrum clock source from a standard fixed-frequency oscillator.
PLL
The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in
conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of
400 MHz to 1,080 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O)
adapt the VCO to the required application.
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO
output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the
VCO within its controllable frequency range.
The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive
one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).
Clock Distribution
Each Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short
propagation delay, and extremely low skew.
Global Clock Lines

In each Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock lines
must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function.
Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.
I/O Clocks
I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer
(SERDES) circuits, as described in the I/O Logic section.

Block RAM
Every Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two
completely independent ports that share only the stored data.
Synchronous Operation
Each memory access, whether read or write, is controlled by the clock. All inputs, data, address, clock enables, and write
enables are registered. The data output is always latched, retaining data until the next operation. An optional output data
pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation in dual-port mode, the data output can reflect either the previously stored data, the newly written
data, or remain unchanged.
Programmable Data Width

• Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32).
• The x9, x18, and x36 configurations include parity bits. The two ports can have different aspect ratios.
• Each block RAM can be divided into two completely independent 9 Kb block RAMs that can each be configured to any
aspect ratio from 8K x 1 to 512 x 18, with 256 x 36 supported in simple dual-port mode.
Memory Controller Block

Most Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting a single-chip DRAM (either
DDR, DDR2, DDR3, or LPDDR), and supporting access rates of up to 800 Mb/s.
The MCB has dedicated routing to predefined FPGA I/Os. If the MCB is not used, these I/Os are available as general
purpose FPGA I/Os. The memory controller offers a complete multi-port arbitrated interface to the logic inside the
Spartan-6 FPGA. Commands can be pushed, and data can be pushed to and pulled from independent built-in FIFOs, using
conventional FIFO control signals. The multi-port memory controller can be configured in many ways. An internal 32-, 64-,
or 128-bit data interface provides a simple and reliable interface to the MCB.
The MCB can be connected to 4-, 8-, or 16-bit external DRAM. The MCB, in many applications, provides a faster DRAM
interface compared to traditional internal data buses, which are wider and are clocked at a lower frequency. The FPGA logic
interface can be flexibly configured irrespective of the physical memory device. The MCB functionality is not supported in the
-3N speed grade.
Digital Signal Processing—DSP48A1 Slice

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All
Spartan-6 FPGAs have many dedicated, full-custom, low-power DSP slices, combining high speed with small size, while
retaining system design flexibility.
Each DSP48A1 slice consists of a dedicated 18 × 18 bit two's complement multiplier and a 48-bit accumulator, both capable
of operating at up to 390 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance
speed and efficiency of many applications, even beyond digital signal processing, such as wide dynamic bus shifters,
memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be
used as a synchronous up/down counter. The multiplier can perform barrel shifting.

Input/Output
The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can
comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources User Guide describes
the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,
all other package pins have the same I/O capabilities, constrained only by certain banking rules. All user I/O is bidirectional;
there are no input-only pins.
All I/O pins are organized in banks, with four banks on the smaller devices and six banks on the larger devices. Each bank
has several common VCCO output supply-voltage pins, which also powers certain input buffers. Some single-ended input
buffers require an externally applied reference voltage (VREF). There are several dual-purpose VREF-I/O pins in each bank.
In a given bank, when I/O standard calls for a VREF voltage, each VREF pin in that bank must be connected to the same
voltage rail and can not be used as an I/O pin.
I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards VCCO or Low towards
ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each
I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors,
adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO
Resources User Guide for more details on available options for each I/O standard.
I/O Logic
Input and Output Delay
This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured
as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can
be individually delayed by up to 256 increments (except in the -1L speed grade). This is implemented as IODELAY2. The
identical delay value is available either for data input or output. For a bidirectional data line, the transfer from input to output
delay is automatic. The number of delay steps can be set by configuration and can also be incremented or decremented
while in use.
Because these tap delays vary with supply voltage, process, and temperature, an optional calibration mechanism is built into
each IODELAY2:
• For source synchronous designs where more accuracy is required, the calibration mechanism can (optionally)
determine dynamically how many taps are needed to delay data by one full I/O clock cycle, and then programs the
IODELAY2 with 50% of that value, thus centering the I/O clock in the middle of the data eye.
• A special mode is available only for differential inputs, which uses a phase-detector mechanism to determine whether
the incoming data signal is being accurately sampled in the middle of the eye. The results from the phase-detector logic
can be used to either increment or decrement the input delay, one tap at a time, to ensure error-free operation at very
high bit rates.
ISERDES and OSERDES

Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel
converter) with programmable parallel width of 2, 3, or 4 bits. Where differential inputs are used, the two serializers can be
cascaded to provide parallel widths of 5, 6, 7, or 8 bits. Each output has access to its own serializer (parallel-to-serial
converter) with programmable parallel width of 2, 3, or 4 bits. Two serializers can be cascaded when a differential driver is
used to give access to bus widths of 5, 6, 7, or 8 bits.
When distributing a double data rate clock, all SerDes data is actually clocked in/out at single data rate to eliminate the
possibility of bit errors due to duty cycle distortion. This faster single data rate clock is either derived via frequency
multiplication in a PLL, or doubled locally in each IOB by differentiating both clock edges when the incoming clock uses
double data rate.

Low-Power Gigabit Transceiver

Ultra-fast data transmission between ICs, over the backplane, or over longer distances is becoming increasingly popular and
important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues at these high data rates.
All Spartan-6 LXT devices have 2–8 gigabit transceiver circuits. Each GTP transceiver is a combined transmitter and
receiver capable of operating at data rates up to 3.2 Gb/s. The transmitter and receiver are independent circuits that use
separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become
the bit-serial data clock. Each GTP transceiver has a large number of user-definable features and parameters. All of these
can be defined during device configuration, and many can also be modified during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, or 20. The transmitter
output drives the PC board with a single-channel differential current-mode logic (CML) output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B
algorithm to guarantee a sufficient number of transitions. The bit-serial output signal drives two package pins with
complementary CML signals. This output signal pair has programmable signal swing as well as programmable pre-
emphasis to compensate for PC board losses and other interconnect characteristics.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel
stream of words, each 8, 10, 16, or 20 bits wide. The receiver takes the incoming differential data stream, feeds it through a
programmable equalizer (to compensate for the PC board and other interconnect characteristics), and uses the FREF input
to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ)
encoding and optionally guarantees sufficient data transitions by using the 8B/10B encoding scheme. Parallel data is then
transferred into the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio can be 8, 10, 16, or 20.
Integrated Endpoint Block for PCI Express Designs

The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission
uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.
The PCI Express Base Specification 1.1 defines bit rate of 2.5 Gb/s per lane, per direction (transmit and receive). When
using 8B/10B encoding, this supports a data rate of 2.0 Gb/s per lane.
The Spartan-6 LXT devices include one integrated Endpoint block for PCI Express technology that is compliant with the PCI
Express Base Specification Revision 1.1. This block is highly configurable to system design requirements and operates as
a compliant single lane Endpoint. The integrated Endpoint block interfaces to the GTP transceivers for serialization/de-
serialization, and to block RAMs for data buffering. Combined, these elements implement the physical layer, data link layer,
and transaction layer of the protocol.
Xilinx provides a light-weight (<200 LUT), configurable, easy-to-use LogiCORE™ IP that ties the various building blocks (the
integrated Endpoint block for PCI Express technology, the GTP transceivers, block RAM, and clocking resources) into a
compliant Endpoint solution. The system designer has control over many configurable parameters: maximum payload size,
reference clock frequency, and base address register decoding and filtering.
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm

Spartan-6 FPGA Ordering Information

Table 3 shows the speed and temperature grades available in the different Spartan-6 devices. Some devices might not be
available in every speed and temperature grade.
Table 3: Speed Grade and Temperature Ranges
Speed Grade and Temperature Range
Device Family Commercial (C) Industrial (I)
0°C to +85°C –40°C to +100°C
Spartan-6 LX -3, -3N, -2, -1L -3, -3N, -2, -1L
Spartan-6 LXT -3, -3N, -2 -3, -3N, -2
The Spartan-6 FPGA ordering information shown in Figure 1 applies to all packages, including Pb-Free. Refer to the
Package Marking section of UG385, Spartan-6 FPGA Packaging and Pinouts for a more detailed explanation of the device
markings.
X-Ref Target - Figure 1
Example: XC6SLX100T-2FGG676C
Device Type
Temperature Range:
Speed Grade C = Commercial (Tj = 0°C to +85°C)
(-L1(1), -2, -3, -N3(2))
I = Industrial (Tj = –40°C to +100°C)
Note:
1) -L1 is the ordering code for the lower power, -1L speed grade.
Number of Pins
Not all devices are offered in this version (LX only).
Pb-Free
See the Spartan-6 FPGA data sheet for more information.
2) -N3 is the ordering code for the -3N speed grade, Package Type
which indicates the devices in which MCB functionality is not supported. DS160_01_011311
Figure 1: Spartan-6 FPGA Ordering Information
Revision History
The following table shows the revision history for this document:
Date Version Description of Revisions

02/02/09 1.0 Initial Xilinx release.
05/05/09 1.1 Updated and simplified Designed for low cost, Multi-voltage, multi-standard SelectIO™ interface
banks, and Integrated Memory Controller blocks sections on page 1. Clarified PCI support on page 1is
only for the 33 MHz specification. Revised number of logic cells, slices, and maximum user I/O, and
added number of flip-flops to Table 1. In Table 2, revised user I/O counts, removed the XC6SLX25 in
the CSG225 package and the XC6SLX45T in the FGG676 package, added XC6SLX9 in the FT(G)256
package and XC6SLX45 in the CSG324 package, and added notes. Clerical edits to the following
sections: Dynamic Reconfiguration Port, Readback, CLBs, Slices, and LUTs, Frequency Synthesis,
PLL, Programmable Data Width, and Memory Controller Block. Clarified I/O pin range, VREF banks,
and electrical characteristics in the Input/Output section.
06/24/09 1.2 Updated device/package combinations in Table 1 and Table 2 including adding the XC6SLX75 and
XC6SLX75T devices. Added ordering information and FPGA documentation sections. Removed
partial reconfiguration discussion from the Readback section.
11/05/09 1.3 Updated Figure 1, page 9 to show -4 speed grade. Added 64-bit PCI support on page 1. Updated User
I/O numbers in Table 1and Table 2. Clarifying edits to these sections: Configuration, Digital Signal
Processing—DSP48A1 Slice, Input/Output, and PCI Express documentation.

Date Version Description of Revisions

03/03/10 1.4 Updated the slice counts for the LX25 and LX25T in Table 1. Revised the Dynamic Reconfiguration
Port section. Added to the Spread-Spectrum Clocking section. Changed the PLL VCO maximum
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
of the -4 speed specification. Clarified configurations in the Programmable Data Width section.
Updated Low-Power Gigabit Transceiver operating rate.
08/02/10 1.5 Updated data transfer rate per differential I/O from 1,050 Mb/s to 1,080 Mb/s in Summary of Spartan-6
FPGA Features. Added the -3N speed grade to appropriate section throughout the document,
including Figure 1. Updated category in Table 2 from Size to Body Size. Updated the Configuration
section with SPI and BPI interface information. Removed the Dynamic Reconfiguration Port section.
Updated the operating speed of the DSP48A1 slice multiplier and accumulator to 390 MHz in Digital
Signal Processing—DSP48A1 Slice. Updated Input and Output Delay.
11/05/10 1.6 In Summary of Spartan-6 FPGA Features and in Low-Power Gigabit Transceiver, updated GTP serial
transceiver data rate to 3.2 Gb/s. Updated the notes in Figure 1. Added DS170, XA Spartan-6
Automotive FPGA Family Overview to the Spartan-6 FPGA Documentation.
03/21/11 1.7 Updated from Advance to Preliminary Specification. Removed -4 speed grade from Summary of
Spartan-6 FPGA Features and Figure 1 per XCN11008. Updated Integrated Endpoint Block for PCI
Express Designs and Input and Output Delay.
10/25/11 2.0 Updated from Preliminary Specification to Production Specification. Updated Configuration, including
the range of configuration bits to 3 Mb and 33 Mb, and Input and Output Delay. Updated Spartan-6
FPGA Ordering Information and added Table 3. Added Defense-Grade Spartan-6Q Family Overview
(DS172) to list of documentation.
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You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to
the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to
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for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
Applications: http://www.xilinx.com/warranty.htm#critapps.

Spartan-6 FPGA Documentation

Complete and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx website at
http://www.xilinx.com/support/documentation/spartan-6.htm. In addition to the most recent Spartan-6 Family Overview, the
following files are also available for download:
Spartan-6 FPGA Data Sheet: DC and Switching Spartan-6 FPGA Memory Controller User Guide
Characteristics (DS162) (UG388)
This data sheet contains the DC and Switching This guide describes the Spartan-6 FPGA memory
Characteristic specifications for the Spartan-6 family. controller block, a dedicated, embedded multi-port memory
controller that greatly simplifies interfacing Spartan-6
Spartan-6 FPGA Packaging and Pinout Specifications FPGAs to the most popular memory standards.
(UG385)
Spartan-6 FPGA PCB Design and Pin Planning Guide
These specifications includes the tables for device/package
(UG393)
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal This guide provides information on PCB design for
specifications. Spartan-6 devices, with a focus on strategies for making
design decisions at the PCB and interface level.
Spartan-6 FPGA Configuration Guide (UG380)
Spartan-6 FPGA Power Management User Guide
This all-encompassing configuration guide includes
(UG394)
chapters on configuration interfaces (serial and parallel),
multi-bitstream management, bitstream encryption, This document provides information on the various
boundary-scan and JTAG configuration, and reconfiguration hardware methods of power management in Spartan-6
techniques. FPGAs, primarily focusing on the suspend mode.
Spartan-6 FPGA SelectIO Resources User Guide XA Spartan-6 Automotive FPGA Family Overview
(UG381) (DS170)
This guide describes the SelectIO™ resources available in This overview outlines the features and product selection of
all the Spartan-6 devices. the Xilinx Automotive (XA) Spartan-6 family.
Spartan-6 FPGA Clocking Resources User Guide Defense-Grade Spartan-6Q Family Overview
(UG382) (DS172)
This guide describes the clocking resources available in all This overview outlines the features and product selection of
Spartan-6 devices, including the DCMs and the PLLs. the Defense-Grade Spartan-6Q family.
Spartan-6 FPGA Block RAM Resources User Guide

(UG383)
This guide describes the Spartan-6 device block RAM
capabilities.
Spartan-6 FPGA Configurable Logic Blocks User Guide

(UG384)
This guide describes the capabilities of the configurable
logic blocks (CLB) available in all Spartan-6 devices.
Spartan-6 FPGA GTP Transceivers User Guide (UG386)

This guide describes the GTP transceivers available in all
the Spartan-6 LXT FPGAs.
Spartan-6 FPGA DSP48A1 Slice User Guide (UG389)

This guide describes the architecture of the DSP48A1 slice
in Spartan-6 FPGAs and provides configuration examples.

LTC3419
Dual Monolithic 600mA
Synchronous Step-Down
Regulator
FEATURES DESCRIPTION
n High Efficiency Dual Step-Down Outputs: Up to 96% The LTC®3419 is a dual, 2.25MHz, constant-frequency,
n 600mA Current per Channel at VIN = 3V synchronous step-down DC/DC converter in a tiny
n Only 35μA Quiescent Current During Operation 3mm × 3mm DFN package. 100% duty cycle provides
(Both Channels) low dropout operation, extending battery life in portable
n 2.25MHz Constant-Frequency Operation systems. Low output voltages are supported with the 0.6V
n 2.5V to 5.5V Input Voltage Range feedback reference voltage. Each regulator can supply
n Low Dropout Operation: 100% Duty Cycle 600mA output current.
n No Schottky Diodes Required
n
The input voltage range is 2.5V to 5.5V, making it ideal
Internally Compensated for All Ceramic Capacitors
n
for Li-Ion and USB powered applications. Supply current
Independent Internal Soft-Start for Each Channel
n
during operation is only 35μA and drops to <1μA in
Available in Fixed Output Versions
n
shutdown. A user-selectable mode input allows the user
Current Mode Operation for Excellent Line and Load
to trade off between high efficiency Burst Mode operation
Transient Response
n
and pulse-skipping mode.
0.6V Reference Allows Low Output Voltages
n User-Selectable Burst Mode® Operation An internally set 2.25MHz switching frequency allows the
n Short-Circuit Protected use of tiny surface mount inductors and capacitors. Internal
n Ultralow Shutdown Current: IQ < 1μA soft-start reduces inrush current during start-up. Both
n Available in Small MSOP or 3mm × 3mm DFN-8 outputs are internally compensated to work with ceramic
Packages output capacitors. The LTC3419 is available in a low profile
(0.75mm) 3mm × 3mm DFN package. The LTC3419 is also
available in a fixed output voltage configuration selected
APPLICATIONS via internal resistor dividers (see Table 2).
n Cellular Telephones , LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
n Digital Still Cameras Burst Mode is a registered trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents,
n Wireless and DSL Modems including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131.
n Portable Media Players
n PDAs/Palmtop PCs
TYPICAL APPLICATION Efficiency and Power Loss

vs Output Current
Dual Monolithic Buck Regulator in 8-Lead 3 × 3 DFN 100 10
VIN = 3.6V
90
VIN
2.5V TO 5.5V 80 1
10μF
RUN2 VIN RUN1 70
POWER LOSS (W)
EFFICIENCY (%)
MODE 60 0.1
LTC3419 50
VOUT2 3.3μH 3.3μH VOUT1
1.8V AT SW2 SW1 2.5V AT 40 0.01
600mA 22pF 22pF 600mA
30
20 0.001
VFB2 VFB1 VOUT = 1.2V
118k GND 187k 10 VOUT = 1.8V
10μF 59k 59k 10μF VOUT = 2.5V
0 0.0001
3419 TA01
0.1 1 10 100 1000
OUTPUT CURRENT (mA)
3419 TA01b
3419fa
1
LTC3419
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN) ............................. –0.3 to 6V Peak SW Source and Sink Current (Note 2) .............1.3A
VFB1, VFB2 ........................................ –0.3V to VIN + 0.3V Operating Junction Temperature Range
RUN1, RUN2, MODE ........................ –0.3V to VIN + 0.3V (Note 3) .................................................–40 to 125°C
SW1, SW2 ....................................... –0.3V to VIN + 0.3V Junction Temperature (Note 6) ............................. 125°C
P-Channel SW Source Current (DC) (Note 2).......800mA Storage Temperature Range...................–65°C to 125°C
N-Channel SW Source Current (DC) (Note 2) ......800mA Lead Temperature (Soldering, 10 sec)
MSOP Package ................................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VFB1 1 8 VFB2
VFB1 1 10 VFB2
RUN1 2 7 RUN2 RUN1 2 9 RUN2
9 8 SW2
MODE 3 6 SW2 MODE 3
SW1 4 7 VIN
SW1 4 5 VIN GND 5 6 GND
MS PACKAGE
DD PACKAGE 10-LEAD PLASTIC MSOP
8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 120°C/W
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3419EDD#PBF LTC3419EDD#TRPBF LCQJ 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3419EDD-1#PBF LTC3419EDD-1#TRPBF LCWW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3419IDD#PBF LTC3419IDD#TRPBF LCQJ 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3419IDD-1#PBF LTC3419IDD-1#TRPBF LCWW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3419EMS#PBF LTC3419EMS#TRPBF LTCQK 10-Lead Plastic MSOP –40°C to 125°C
LTC3419EMS-1#PBF LTC3419EMS-1#TRPBF LTCWX 10-Lead Plastic MSOP –40°C to 125°C
LTC3419IMS#PBF LTC3419IMS#TRPBF LTCQK 10-Lead Plastic MSOP –40°C to 125°C
LTC3419IMS-1#PBF LTC3419IMS-1#TRPBF LTCWX 10-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3419fa
2
LTC3419
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN VIN Operating Voltage ● 2.5 5.5 V
VUV VIN Undervoltage Lockout VIN Low to High ● 2.1 2.5 V
IFB Feedback Pin Input Current LTC3419 ● ±30 nA
LTC3419-1 ● 3 5 μA
VFBREG1 Regulated Feedback Voltage (Channel 1) LTC3419E, 0°C < TJ < 85°C 0.590 0.600 0.610 V
LTC3419E, –40°C < TJ < 85°C ● 0.588 0.600 0.612 V
LTC3419E-1, –40°C < TJ < 85°C ● 1.544 1.575 1.606 V
LTC3419I, –40°C < TJ < 125°C ● 0.582 0.6 0.618 V
LTC3419I-1, –40°C < TJ < 125°C ● 1.533 1.575 1.617 V
VFBREG2 Regulated Feedback Voltage (Channel 2) LTC3419E, 0°C < TJ < 85°C 0.590 0.600 0.610 V
LTC3419E, –40°C < TJ < 85°C ● 0.588 0.600 0.612 V
LTC3419E-1, –40°C < TJ < 85°C ● 1.764 1.8 1.836 V
LTC3419I, –40°C < TJ < 125°C ● 0.582 0.6 0.618 V
LTC3419I-1, –40°C < TJ < 125°C ● 1.753 1.8 1.847 V
ΔVLINE REG Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 7) 0.3 0.5 %/V
ΔVLOAD REG Output Voltage Load Regulation ILOAD = 0mA to 600mA (Note 7) 0.5 %
IS Input DC Supply Current
Active Mode (Note 4) VFB1 = VFB2 = 0.95 × VFBREG 500 700 μA
Sleep Mode VFB1 = VFB2 = 1.05 × VFBREG , VIN = 5.5V 35 60 μA
Shutdown RUN1 = RUN2 = 0V, VIN = 5.5V 0.1 1 μA
fOSC Oscillator Frequency VFB = VFBREG ● 1.8 2.25 2.7 MHz
ILIM Peak Switch Current Limit VIN = 3V, VFB < VFBREG , Duty Cycle < 35%
Channel 1 (600mA) 900 1200 mA
Channel 2 (600mA) 900 1200 mA
RDS(ON) Channel 1 (Note 5)
Top Switch On-Resistance VIN = 3.6V, ISW = 100mA 0.4 0.6 Ω
Bottom Switch On-Resistance VIN = 3.6V, ISW = 100mA 0.4 0.6 Ω
Channel 2 (Note 5)
Top Switch On-Resistance VIN = 3.6V, ISW = 100mA 0.4 0.6 Ω
Bottom Switch On-Resistance VIN = 3.6V, ISW = 100mA 0.4 0.6 Ω
ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V 0.01 1 μA
tSOFTSTART Soft-Start Time VFB from 10% to 90% Full Scale 0.1 0.95 1.3 ms
VRUN RUN Threshold High ● 0.4 1 1.2 V
IRUN RUN Leakage Current ● 0.01 1 μA
VMODE MODE Threshold High ● 0.4 1 1.2 V
IMODE MODE Leakage Current ● 0.01 1 μA
VBURST Output Ripple in Burst Mode Operation VOUT = 1.5V, COUT = 10μF 20 mVP-P
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Dynamic supply current is higher due to the internal gate charge
may cause permanent damage to the device. Exposure to any Absolute being delivered at the switching frequency.
Maximum Rating condition for extended periods may affect device Note 5: The DFN switch on-resistance is guaranteed by correlation to
reliability and lifetime. wafer level measurements.
Note 2: Guaranteed by long term current density limitations. Note 6: This IC includes overtemperature protection that is intended
Note 3: The LTC3419E and LTC3419E-1 are guaranteed to meet specified to protect the device during momentary overload conditions. Junction
performance from 0°C to 85°C. Specifications over the –40°C to 125°C temperature will exceed 125°C when overtemperature protection is active.
operating junction temperature range are assured by design, Continuous operation above the specified maximum operating junction
characterization and correlation with statistical process controls. The temperature may impair device reliability.
LTC3419I and LTC3419I-1 are guaranteed to meet specified performance Note 7: The converter is tested in a proprietary test mode that connects
over the full –40°C to 125°C operating junction temperature range. the output of the error amplifier to the SW pin, which is connected to an
external servo loop.
3419fa
3
LTC3419
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 3.6V, unless otherwise noted.
Burst Mode Operation Pulse Skip Mode Operation Efficiency vs Input Voltage
100
IOUT = 100mA
SW SW 90
2V/DIV 2V/DIV
80 IOUT = 1mA
VOUT
EFFICIENCY (%)
50mV/DIV VOUT
50mV/DIV IOUT = 600mA
AC-COUPLED 70 IOUT = 10mA
AC-COUPLED
IL 60
IL
100mA/DIV
100mA/DIV
50
IOUT = 0.1mA
3419 G01 3419 G02
2μs/DIV 5μs/DIV 40
VIN = 3.6V VIN = 3.6V
VOUT = 1.8V
VOUT = 1.8V VOUT = 1.8V 30
ILOAD = 25mA ILOAD = 5mA 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
3419 G03
Reference Voltage Oscillator Frequency Supply Current

vs Temperature vs Temperature vs Temperature
1.5 2.6 55
RUN1 = RUN2 = VIN
ILOAD = 0A
2.5 50
1.0
2.4 VIN = 4.2V 45
SUPPLY CURRENT (μA)

FREQUENCY (MHz)
0.5
VFB (% ERROR)
2.3 40
VIN = 3.6V VIN = 5.5V
0 2.2 35
VIN = 2.7V VIN = 2.7V
2.1 30
–0.5
2.0 25
–1.0
1.9 20
–1.5 1.8 15
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3419 G04 3419 G05 3419 G06
Switch On-Resistance Switch On-Resistance

Switch Leakage vs Input Voltage vs Input Voltage vs Temperature
3.0 0.50 0.6
2.5 0.45
0.5
MAIN SWITCH
LEAKAGE CURRENT (nA)
2.0 0.40
RDS(ON) (Ω)
RDS(ON) (Ω)
MAIN SWITCH 0.4

MAIN SWITCH
1.5 0.35
0.3
1.0 SYNCHRONOUS 0.30 SYNCHRONOUS SWITCH
SWITCH SYNCHRONOUS
SWITCH 0.2
0.5 0.25 VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
0 0.20 0.1
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –50 –25 0 25 50 75 100 125
VIN (V) VIN (V) TEMPERATURE (°C)
3419 G07 3419 G08 3419 G09
3419fa
4
LTC3419
Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current

100 100 100
90 90 90
80 80 80
70 70 70
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
60 60 60
50 50 50
40 40 40
30 30 30
20 20 20
VIN = 2.7V VIN = 2.7V VIN = 2.7V
10 VIN = 3.6V 10 VIN = 3.6V 10 VIN = 3.6V
VOUT = 1.2V VIN = 4.2V VOUT = 1.8V VIN = 4.2V VOUT = 2.5V VIN = 4.2V
0 0 0
0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
3419 G10 3419 G11 3419 G12
Efficiency vs Load Current Load Regulation Load Regulation

100 3.0 2.0
Burst Mode OPERATION VOUT = 1.2V VOUT = 1.8V
90 VOUT = 1.8V
2.5
VOUT = 2.5V 1.5
80
2.0
70
VOUT ERROR (%)
VOUT ERROR (%)

1.0
EFFICIENCY (%)
PULSE SKIP MODE 1.5

60
Burst Mode OPERATION
50 1.0 0.5
40
0.5
30 0
0
20
–0.5
10 –0.5 Burst Mode OPERATION
VOUT = 1.8V PULSE SKIP MODE
0 –1.0 –1.0
0.1 1 10 100 1000 0 100 200 300 400 500 600 0 100 200 300 400 500 600
OUTPUT CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3419 G13 3419 G14 3419 G15
Line Regulation Start-Up from Shutdown Start-Up from Shutdown

0.6
VOUT = 1.8V
ILOAD = 100mA RUN RUN
0.4 2V/DIV 2V/DIV
VOUT ERROR (%)
0.2
VOUT VOUT
1V/DIV 1V/DIV
0
IL ILOAD
–0.2 500mA/DIV 500mA/DIV
3419 G17 3419 G18

–0.4 250μs/DIV 250μs/DIV
VIN = 3.6V VIN = 3.6V
–0.6 VOUT = 1.8V VOUT = 1.8V
2.5 3.0 3.5 4.0 4.5 5.0 5.5 ILOAD = 0A RLOAD = 3Ω
VIN (V)
3419 G16
3419fa
5
LTC3419
Load Step Load Step Load Step
VOUT VOUT VOUT

100mV/DIV 100mV/DIV 100mV/DIV
AC-COUPLED AC-COUPLED AC-COUPLED
IL IL IL
500mA/DIV 500mA/DIV 500mA/DIV
ILOAD ILOAD ILOAD

500mA/DIV 500mA/DIV 500mA/DIV
3419 G19 3419 G20 3419 G21

20μs/DIV 20μs/DIV 20μs/DIV
VIN = 3.6V VIN = 3.6V VIN = 3.6V
VOUT = 1.8V VOUT = 1.8V VOUT = 1.2V
ILOAD = 0A TO 600mA ILOAD = 40mA TO 600mA ILOAD = 40mA TO 600mA
PIN FUNCTIONS (DD/MS)
VFB1 (Pin 1/Pin 1): Regulator 1 Output Feedback. Receives SW2 (Pin 6/Pin 8): Regulator 2 Switch Node Connection
the feedback voltage from the external resistive divider to the Inductor. This pin swings from VIN to GND.
across the regulator 1 output. Nominal voltage for this
RUN2 (Pin 7/Pin 9): Regulator 2 Enable. Forcing this pin
pin is 0.6V.
to VIN enables regulator 2, while forcing it to GND causes
RUN1 (Pin 2/Pin 2): Regulator 1 Enable. Forcing this pin regulator 2 to shut down.
to VIN enables regulator 1, while forcing it to GND causes
regulator 1 to shut down. VFB2 (Pin 8/Pin 10): Regulator 2 Output Feedback. Receives
the feedback voltage from the external resistive divider
MODE (Pin 3/Pin 3): Mode Select Input. To select pulse- across the regulator 2 output. Nominal voltage for this
skipping mode, tie to VIN . Grounding this pin selects Burst pin is 0.6V.
Mode operation. Do not leave this pin floating.
Exposed Pad (Pin 9/NA): Ground. The Exposed Pad must
SW1 (Pin 4/Pin 4): Regulator 1 Switch Node Connection be soldered to PCB for optimal thermal performance.
to the Inductor. This pin swings from VIN to GND.
GND (NA/Pins 5, 6): Ground. Connect to the (–) terminal
VIN (Pin 5/Pin 7): Main Power Supply. Must be closely of COUT, and the (–) terminal of CIN . Pin 5 of the MS
de-coupled to GND. package must be soldered to the PC board for optimal
thermal performance.
3419fa
6
LTC3419
FUNCTIONAL DIAGRAM
REGULATOR 1
MODE 3
BURST
CLAMP
SLOPE 5 VIN
COMP
VFB1 1 – –
ITH SLEEP – +
EA ICOMP
+ VSLEEP +
0.6V BURST
S Q
RS
LATCH
SOFT-START R Q
SWITCHING
LOGIC
AND
BLANKING ANTI
CIRCUIT SHOOT-
THRU 4 SW1
+
IRCMP
–
SHUTDOWN 9 GND
RUN1 2 SLEEP2 SLEEP1

0.6V REF OSC
RUN2 7
OSC
VFB2 8 REGULATOR 2 (IDENTICAL TO REGULATOR 1) 6 SW2
3419 FD
3419fa
7
LTC3419
OPERATION
The LTC3419 uses a constant-frequency, current mode MOSFET on. This cycle repeats at a rate that is dependent
architecture. The operating frequency is set at 2.25MHz. on load demand.
Both channels share the same clock and run in-phase. For applications where low ripple voltage and constant-
The output voltage is set by an external resistor divider frequency operation is a higher priority than light load
returned to the VFB pins. An error amplifier compares the efficiency, pulse-skipping mode can be used by connecting
divided output voltage with a reference voltage of 0.6V and the MODE pin to VIN . In this mode, the peak inductor
regulates the peak inductor current accordingly. current is not fixed, which allows the LTC3419 to switch
at a constant-frequency down to very low currents, where
Main Control Loop it will begin skipping pulses.
During normal operation, the top power switch (P-channel
Dropout Operation
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the reference voltage. The When the input supply voltage decreases toward the
current into the inductor and the load increases until the output voltage the duty cycle increases to 100%, which
peak inductor current (controlled by ITH) is reached. The is the dropout condition. In dropout, the PMOS switch is
RS latch turns off the synchronous switch and energy turned on continuously with the output voltage being equal
stored in the inductor is discharged through the bottom to the input voltage minus the voltage drops across the
switch (N-channel MOSFET) into the load until the next internal P-channel MOSFET and the inductor.
clock cycle begins, or until the inductor current begins to An important design consideration is that the RDS(ON)
reverse (sensed by the IRCMP comparator). of the P-channel switch increases with decreasing input
The peak inductor current is controlled by the internally supply voltage (see Typical Performance Characteristics).
compensated ITH voltage, which is the output of the error Therefore, the user should calculate the worst-case power
amplifier. This amplifier regulates the VFB pin to the internal dissipation when the LTC3419 is used at 100% duty cycle
0.6V reference by adjusting the peak inductor current with low input voltage (see Thermal Considerations in the
accordingly. Applications Information section).
Light Load Operation Soft-Start

There are two modes to control the LTC3419 at light load In order to minimize the inrush current on the input bypass
currents: Burst Mode operation and pulse-skipping mode. capacitor, the LTC3419 slowly ramps up the output voltage
Both automatically transition from continuous operation during start-up. Whenever the RUN1 or RUN2 pin is pulled
to the selected mode when the load current is low. high, the corresponding output will ramp from zero to
full-scale over a time period of approximately 750μs. This
To optimize efficiency, Burst Mode operation can be selected prevents the LTC3419 from having to quickly charge the
by grounding the MODE pin. When the load is relatively output capacitor and thus supplying an excessive amount
light, the peak inductor current (as set by ITH) remains of instantaneous current.
fixed at approximately 60mA and the PMOS switch operates
intermittently based on load demand. By running cycles Short-Circuit Protection
periodically, the switching losses are minimized.
When either regulator output is shorted to ground, the
The duration of each burst event can range from a few corresponding internal N-channel switch is forced on for
cycles at light load to almost continuous cycling with a longer time period for each cycle in order to allow the
short sleep intervals at moderate loads. During the sleep inductor to discharge, thus preventing inductor current
intervals, the load current is being supplied solely from runaway. This technique has the effect of decreasing
the output capacitor. As the output voltage droops, the switching frequency. Once the short is removed, normal
error amplifier output rises above the sleep threshold, operation resumes and the regulator output will return to
signaling the burst comparator to trip and turn the top its nominal voltage.
3419fa
8
LTC3419
APPLICATIONS INFORMATION
A general LTC3419 application circuit is shown in Figure 1. or shielded pot cores in ferrite or permalloy materials are
External component selection is driven by the load small and do not radiate much energy, but generally cost
requirement, and begins with the selection of the more than powdered iron core inductors with similar
inductor L. Once the inductor is chosen, CIN and COUT electrical characteristics. The choice of which style
can be selected. inductor to use often depends more on the price versus
size requirements, and any radiated field/EMI requirements,
Inductor Selection than on what the LTC3419 requires to operate. Table 1
Although the inductor does not influence the operating shows some typical surface mount inductors that work
frequency, the inductor value has a direct effect on ripple well in LTC3419 applications.
current. The inductor ripple current ΔIL decreases with Table 1. Representative Surface Mount Inductors
higher inductance and increases with higher VIN or VOUT : MANU- MAX DC
FACTURER PART NUMBER VALUE CURRENT DCR HEIGHT
V ⎛ V ⎞
ΔIL = OUT • ⎜1− OUT ⎟ (1) Taiyo Yuden CB2016T2R2M 2.2μH 510mA 0.13Ω 1.6mm
fO • L ⎝ VIN ⎠ CB2012T2R2M 2.2μH 530mA 0.33Ω 1.25mm
CB2016T3R3M 3.3μH 410mA 0.27Ω 1.6mm
Accepting larger values of ΔIL allows the use of low Panasonic ELT5KT4R7M 4.7μH 950mA 0.2Ω 1.2mm
inductances, but results in higher output voltage ripple, Sumida CDRH2D18/LD 4.7μH 630mA 0.086Ω 2mm
greater core losses, and lower output current capability. Murata LQH32CN4R7M23 4.7μH 450mA 0.2Ω 2mm
A reasonable starting point for setting ripple current is Taiyo Yuden NR30102R2M 2.2μH 1100mA 0.1Ω 1mm
40% of the maximum output load current. So, for a 600mA NR30104R7M 4.7μH 750mA 0.19Ω 1mm
regulator, ΔIL = 240mA (40% of 600mA). FDK FDKMIPF2520D 4.7μH 1100mA 0.11Ω 1mm
FDKMIPF2520D 3.3μH 1200mA 0.1Ω 1mm
The inductor value will also have an effect on Burst Mode FDKMIPF2520D 2.2μH 1300mA 0.08Ω 1mm
operation. The transition to low current operation begins TDK VLF3010AT4R7- 4.7μH 700mA 0.28Ω 1mm
MR70
when the peak inductor current falls below a level set by VLF3010AT3R3- 3.3μH 870mA 0.17Ω 1mm
the internal burst clamp. Lower inductor values result in MR87
higher ripple current which causes the transition to occur VLF3010AT2R2- 2.2μH 1000mA 0.12Ω 1mm
M1R0
at lower load currents. This causes a dip in efficiency in
the upper range of low current operation. Furthermore, Input Capacitor (CIN) Selection
lower inductance values will cause the bursts to occur
with increased frequency. In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately VOUT / VIN .
Inductor Core Selection To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
Different core materials and shapes will change the size/
RMS current must be used. The maximum RMS capacitor
current and price/current relationship of an inductor. Toroid
current is given by:
VIN
2.5V TO 5.5V VOUT ( VIN − VOUT )
C1
RUN2 VIN RUN1 IRMS ≈ IMAX
MODE VIN
LTC3419
L2 L1
VOUT2
CF2
SW2 SW1
CF1
VOUT1
Where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple cur-
COUT2 R4
VFB2
GND
VFB1
R2 COUT1
rent, IMAX = ILIM – ΔIL /2. This formula has a maximum at
R3 R1
VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case
3419 F01
is commonly used to design because even significant

Figure 1. LTC3419 General Schematic
3419fa
9
LTC3419
deviations do not offer much relief. Note that capacitor However, care must be taken when ceramic capacitors are
manufacturer’s ripple current ratings are often based on used at the input. When a ceramic capacitor is used at the
only 2000 hours lifetime. This makes it advisable to further input and the power is supplied by a wall adapter through
derate the capacitor, or choose a capacitor rated at a higher long wires, a load step at the output can induce ringing at
temperature than required. Several capacitors may also be the input, VIN. At best, this ringing can couple to the output
paralleled to meet the size or height requirements of the and be mistaken as loop instability. At worst, a sudden
design. An additional 0.1μF to 1μF ceramic capacitor is inrush of current through the long wires can potentially
also recommended on VIN for high frequency decoupling cause a voltage spike at VIN, large enough to damage the
when not using an all-ceramic capacitor solution. part. For more information, see Application Note 88.
When choosing the input and output ceramic capacitors,
Output Capacitor (COUT) Selection
choose the X5R or X7R dielectric formulations. These
The selection of COUT is driven by the required effective dielectrics have the best temperature and voltage charac-
series resistance (ESR). Typically, once the ESR requirement teristics of all the ceramics for a given value and size.
for COUT has been met, the RMS current rating generally
far exceeds the IRIPPLE(P-P) requirement. The output ripple Setting the Output Voltage
ΔVOUT is determined by:
The LTC3419 regulates the VFB1 and VFB2 pins to 0.6V
⎛ 1 ⎞ during regulation. Thus, the output voltage is set by a
Δ VOUT ≈ Δ IL ⎜ESR + ⎟ resistive divider according to the following formula:
⎝ 8 fOCOUT ⎠
⎛ R2 ⎞
where fO = operating frequency, COUT = output capacitance VOUT = 0 . 6 V ⎜ 1 + ⎟ (2)
⎝ R1⎠
and ΔIL = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input Keeping the current small (< 10μA) in these resistors
voltage since ΔIL increases with input voltage. maximizes efficiency, but making it too small may allow
If tantalum capacitors are used, it is critical that the capacitors stray capacitance to cause noise problems or reduce the
are surge tested for use in switching power supplies. An phase margin of the error amp loop.
excellent choice is the AVX TPS series of surface mount To improve the frequency response of the main control
tantalum. These are specially constructed and tested for low loop, a feedback capacitor (CF) may also be used. Great
ESR so they give the lowest ESR for a given volume. Other care should be taken to route the VFB line away from noise
capacitor types include Sanyo POSCAP, Kemet T510 and sources, such as the inductor or the SW line.
T495 series, and Sprague 593D and 595D series. Consult
the manufacturer for other specific recommendations. Fixed output versions of the LTC3419 (e.g. LTC3419-1)
include an internal resistive divider, eliminating the need
Using Ceramic Input and Output Capacitors for external resistors. The resistor divider is chosen
such that the VFB input current is approximately 3μA. For
Higher values, lower cost ceramic capacitors are now these versions the VFB pin should be connected directly
becoming available in smaller case sizes. Their high to VOUT. Table 2 lists the fixed output voltages available
ripple current, high voltage rating and low ESR make for the LTC3419.
them ideal for switching regulator applications. Because
the LTC3419 control loop does not depend on the output Table 2. Fixed Output Voltage Versions
capacitor’s ESR for stable operation, ceramic capacitors PART NUMBER VOUT1 VOUT2
can be used freely to achieve very low output ripple and LTC3419 Adjustable Adjustable
small circuit size. LTC3419-1 1.575V 1.8V
3419fa
10
LTC3419
Checking Transient Response It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
The regulator loop response can be checked by looking
produce the most improvement. Percent efficiency can
at the load transient response. Switching regulators
be expressed as:
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an % Efficiency = 100% – (L1 + L2 + L3 + ...)
amount equal to ΔILOAD • ESR, where ESR is the effective where L1, L2, etc., are the individual losses as a percentage
series resistance of COUT. ΔILOAD also begins to charge or of input power.
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value. During Although all dissipative elements in the circuit produce
this recovery time, VOUT can be monitored for overshoot losses, four sources usually account for the losses in
or ringing that would indicate a stability problem. LTC3419 circuits: 1) VIN quiescent current, 2) switching
losses, 3) I2R losses, 4) other system losses.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second 1. The VIN current is the DC supply current given in the
order overshoot/DC ratio cannot be used to determine the Electrical Characteristics which excludes MOSFET
driver and control currents. VIN current results in a
phase margin. In addition, feedback capacitors (CF1 and
small (<0.1%) loss that increases with VIN, even at
CF2) can be added to improve the high frequency response,
no load.
as shown in Figure 1. Capacitor CF provides phase lead by
creating a high frequency zero with R2 which improves 2. The switching current is the sum of the MOSFET driver
the phase margin. and control currents. The MOSFET driver current results
from switching the gate capacitance of the power
The output voltage settling behavior is related to the stability
MOSFETs. Each time a MOSFET gate is switched from
of the closed-loop system and will demonstrate the actual
low to high to low again, a packet of charge dQ moves
overall supply performance. For a detailed explanation of from VIN to ground. The resulting dQ/dt is a current
optimizing the compensation components, including a re- out of VIN that is typically much larger than the DC bias
view of control loop theory, refer to Application Note 76. current. In continuous mode, IGATECHG = fO(QT + QB),
In some applications, a more severe transient can be caused where QT and QB are the gate charges of the internal top
by switching in loads with large (>1μF) input capacitors. The and bottom MOSFET switches. The gate charge losses
discharged input capacitors are effectively put in parallel are proportional to VIN and thus their effects will be
with COUT , causing a rapid drop in VOUT. No regulator can more pronounced at higher supply voltages.
deliver enough current to prevent this problem if the switch 3. I2R losses are calculated from the DC resistances
connecting the load has low resistance and is driven quickly. of the internal switches, RSW , and external inductor,
The solution is to limit the turn-on speed of the load switch RL. In continuous mode, the average output current
driver. A Hot Swap™ controller is designed specifically for flows through inductor L, but is “chopped” between
this purpose and usually incorporates current limiting, the internal top and bottom switches. Thus, the series
short-circuit protection, and soft-starting. resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
Efficiency Considerations (DC) as follows:
The percent efficiency of a switching regulator is equal to RSW = (RDS(ON)TOP) • (DC) + (RDS(ON)BOT) • (1– DC)
the output power divided by the input power times 100%.
Hot Swap is a trademark of Linear Technology Corporation.
3419fa
11
LTC3419
The RDS(ON) for both the top and bottom MOSFETs can be Given that the thermal resistance of a properly soldered
obtained from the Typical Performance Characteristics DFN package is approximately 40°C/W, the junction
curves. Thus, to obtain I2R losses: temperature of an LTC3419 device operating in a 70°C
I2R losses = IOUT2 • (RSW + RL) ambient temperature is approximately:
4. Other “hidden” losses, such as copper trace and TJ = (2 • 0.216W • 40°C/W) + 70°C = 87.3°C
internal battery resistances, can account for additional which is well below the absolute maximum junction
efficiency degradations in portable systems. It is very temperature of 125°C.
important to include these “system” level losses in
the design of a system. The internal battery and fuse PC Board Layout Considerations
resistance losses can be minimized by making sure that When laying out the printed circuit board, the following
CIN has adequate charge storage and very low ESR at checklist should be used to ensure proper operation of the
the switching frequency. Other losses, including diode LTC3419. These items are also illustrated graphically in the
conduction losses during dead-time, and inductor layout diagrams of Figures 2 and 3. Check the following
core losses, generally account for less than 2% total in your layout:
additional loss.
1. Does the capacitor CIN connect to the power VIN (Pin 5)
Thermal Considerations and GND (Pin 9) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
In a majority of applications, the LTC3419 does not
and their drivers.
dissipate much heat due to its high efficiency. In the
unlikely event that the junction temperature somehow 2. Are the respective COUT and L closely connected? The
reaches approximately 150°C, both power switches will be (–) plate of COUT returns current to GND and the (–)
turned off and the SW node will become high impedance. plate of CIN .
The goal of the following thermal analysis is to determine 3. The resistor divider, R1 and R2, must be connected
whether the power dissipated causes enough temperature between the (+) plate of COUT1 and a ground sense line
rise to exceed the maximum junction temperature (125°C) terminated near GND (Pin 9). The feedback signals VFB1
of the part. The temperature rise is given by: and VFB2 should be routed away from noisy components
TRISE = PD • θJA and traces, such as the SW lines (Pins 4 and 6), and
their trace length should be minimized.
Where PD is the power dissipated by the regulator and
θJA is the thermal resistance from the junction of the die 4. Keep sensitive components away from the SW pins, if
to the ambient temperature. The junction temperature, possible. The input capacitor CIN and the resistors R1,
TJ, is given by: R2, R3 and R4 should be routed away from the SW
traces and the inductors.
TJ = TRISE + TAMBIENT
5. A ground plane is preferred, but if not available, keep
As a worst-case example, consider the case when the
the signal and power grounds segregated with small
LTC3419 is in dropout on both channels at an input voltage
signal components returning to the GND pin at a single
of 2.7V with a load current of 600mA and an ambient
point. These ground traces should not share the high
temperature of 70°C. From the Typical Performance
current path of CIN or COUT.
Characteristics graph of Switch Resistance, the RDS(ON)
of the main switch is 0.6Ω. Therefore, power dissipated 6. Flood all unused areas on all layers with copper.
by each channel is: Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
PD = IOUT2 • RDS(ON) = 216mV
connected to VIN or GND.
3419fa
12
LTC3419
VIN
2.5V TO 5.5V
C1
RUN2 VIN RUN1
MODE
L2 LTC3419 L1
VOUT2 SW2 SW1 VOUT1
CF2 CF1
VFB2 VFB1
R4 GND R2
COUT2 R3 R1 COUT1
3419 F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 2. LTC3419 Layout Diagram (See Board Layout Checklist)
CF1 CF2
R2 R1 R3 R4
VOUT1 VOUT2
COUT1 COUT2
VIA TO VIN
VFB1 VFB2
L1 L2
RUN1 RUN2
MODE SW2
SW1 VIN
VIA TO GND
GND
CIN
3419 F03
Figure 3. LTC3419 Suggested Layout
Design Example A 10μF ceramic capacitor should be more than sufficient

As a design example, consider using the LTC3419 in a for this output capacitor. As for the input capacitor, a
portable application with a Li-Ion battery. The battery typical value of CIN = 10μF should suffice, as the source
impedance of a Li-Ion battery is very low.
provides a VIN ranging from 2.8V to 4.2V. The load on
each channel requires a maximum of 600mA in active The feedback resistors program the output voltage. To
mode and 2mA in standby mode. The output voltages are maintain high efficiency at light loads, the current in these
VOUT1 = 2.5V and VOUT2 = 1.8V. resistors should be kept small. Choosing 10μA with the
Start with channel 1. First, calculate the inductor value 0.6V feedback voltage makes R1~60k. A close standard
for about 40% ripple current (240mA in this example) at 1% resistor is 59k. Using Equation 2.
maximum VIN. Using a derivation of Equation 1: ⎛V ⎞
R2 = ⎜ OUT − 1⎟ • R1 = 187k
2 . 5V ⎛ 2 . 5V ⎞ ⎝ 0.6 ⎠
L1 = • ⎜ 1− = 1 . 8 7μH
2 . 25MHz • (240mA) ⎝ 4 . 2V ⎟⎠ An optional 22pF feedback capacitor (CF1) may be used
For the inductor, use the closest standard value of to improve transient response.
2.2μH.
3419fa
13
LTC3419
Using the same analysis for channel 2 (VOUT2 = 1.8V), 100
90
the results are:
80
L2 = 1.9μH 70
EFFICIENCY (%)
60
R3 = 59k 50
40
R4 = 118k 30
20
CF2 = 22pF VIN = 2.7V
10 VIN = 3.6V
VOUT = 1.8V VIN = 4.2V
Figure 4 shows the complete schematic for this example, 0
0.1 1 10 100 1000
along with the efficiency curve and transient response. OUTPUT CURRENT (mA)
100
VIN
2.5V TO 5.5V 90
C1
10μF 80
RUN2 VIN RUN1
MODE 70
EFFICIENCY (%)
L2 L1
LTC3419 60
VOUT2 2.2μH 2.2μH VOUT1
1.8V AT SW2 SW1 2.5V AT 50
600mA CF2, 22pF CF1, 22pF 600mA
40
30
VFB2 VFB1
20
COUT2 R4 R3 GND R1 R2 COUT1 VIN = 2.7V
10μF 118k 59k 59k 187k 10μF 10 VIN = 3.6V
VOUT = 2.5V VIN = 4.2V
3419 F04a 0
0.1 1 10 100 1000
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: TDK VLF3010AT2R2M1RD OUTPUT CURRENT (mA)
3419 F04b
Figure 4a. Design Example Circuit Figure 4b. Efficiency vs Output Current
Load Step Transient Response
VOUT VOUT
100mV/DIV 100mV/DIV
AC-COUPLED AC-COUPLED
IL IL
500mA/DIV 500mA/DIV
ILOAD ILOAD
500mA/DIV 500mA/DIV
3419 F04c1 3419 F04c2

20μs/DIV 20μs/DIV
VIN = 3.6V VIN = 3.6V
VOUT = 1.8V VOUT = 2.5V
ILOAD = 40mA TO 600mA ILOAD = 40mA TO 600mA
Figure 4c. Transient Response
3419fa
14
LTC3419
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 0.38 ± 0.10

TYP
5 8
0.675 ±0.05
3.5 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10

2.15 ±0.05 (2 SIDES) PACKAGE (4 SIDES) (2 SIDES)
OUTLINE
PIN 1
TOP MARK
(NOTE 6) (DD) DFN 1203
4 1
0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 0.50 BSC
BSC 2.38 ±0.10
2.38 ±0.05 (2 SIDES)
0.00 – 0.05
(2 SIDES) BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 5. EXPOSED PAD SHALL BE SOLDER PLATED
2. DRAWING NOT TO SCALE 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
3. ALL DIMENSIONS ARE IN MILLIMETERS ON TOP AND BOTTOM OF PACKAGE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127 3.00 ± 0.102

(.035 ± .005) (.118 ± .004) 0.497 ± 0.076
(NOTE 3) (.0196 ± .003)
10 9 8 7 6
REF
5.23
(.206) 3.20 – 3.45
MIN (.126 – .136)
4.90 ± 0.152 3.00 ± 0.102
(.193 ± .006) (.118 ± .004)
(NOTE 4)
0.305 ± 0.038 0.50

(.0120 ± .0015) (.0197)
TYP BSC 1 2 3 4 5
RECOMMENDED SOLDER PAD LAYOUT
1.10 0.86
DETAIL “A” (.043) (.034)
0.254 DETAIL “A” REF
MAX
(.010) 0.18
0° – 6° TYP
(.007)
GAUGE PLANE SEATING
PLANE 0.17 – 0.27 0.1016 ± 0.0508
0.53 ± 0.152 (.007 – .011) (.004 ± .002)
(.021 ± .006) 0.50
TYP MSOP (MS) 0307 REV E
(.0197)
NOTE: BSC
1. DIMENSIONS IN MILLIMETER/(INCH) 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
2. DRAWING NOT TO SCALE INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 0.102mm (.004") MAX
3419fa
15
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3419
TYPICAL APPLICATIONS
Dual 600mA Buck Converter 1.8V/1.575V Dual 600mA Buck Converter
VIN VIN
2.5V TO 5.5V 2.5V TO 5.5V
C1 C1
10μF RUN2 VIN RUN1 10μF RUN2 VIN RUN1
MODE MODE
L2 L1 L2 L1
3.3μH LTC3419 3.3μH 3.3μH LTC3419-1 3.3μH
VOUT2 VOUT1 VOUT2 VOUT1
1.8V AT SW2 SW1 2.5V AT 1.8V AT SW2 SW1 1.575V AT
600mA CF2, 22pF CF1, 22pF 600mA 600mA 600mA
VFB2 VFB1 VFB2 VFB1

COUT2 R4 R3 GND R1 R2 COUT1 COUT2 GND COUT1
10μF 118k 59k 59k 187k 10μF 10μF 10μF
3419 TA02 3419 TA03
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: TDK VLF3010AT3R3M1RD C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: TDK VLF3010AT3R3M1RD
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3405/LTC3405A 300mA IOUT, 1.5MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA, ISD = <1μA,
Step-Down DC/DC Converters ThinSOTTM Package
LTC3406/LTC3406B 600mA IOUT, 1.5MHz, Synchronous 96% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD = <1μA,
Step-Down DC/DC Converters ThinSOT Package
LTC3407/LTC3407-2 Dual 600mA/800mA IOUT, 1.5MHz/ 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD = <1μA,
2.25MHz, Synchronous Step-Down MS10E and DFN Packages
DC/DC Converters
LTC3409 600mA IOUT, 1.7MHz/2.6MHz, 96% Efficiency, VIN(MIN) = 1.6V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 65μA, ISD = <1μA,
Synchronous Step-Down DC/DC DFN Package
Converter
LTC3410/LTC3410B 300mA IOUT, 2.25MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD = <1μA,
Step-Down DC/DC Converters SC70 Package
LTC3411 1.25A IOUT, 4MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD = <1μA,
Step-Down DC/DC Converter MS10 and DFN Packages
LTC3412 2.5A IOUT 4MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD = <1μA,
Step-Down DC/DC Converter TSSOP-16E Package
LTC3441/LTC3442, 1.2A IOUT 2MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.4V, VIN(MAX) = 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50μA,
LTC3443 Buck-Boost DC/DC Converters ISD = <1μA, DFN Package
LTC3531/LTC3531-3/ 200mA IOUT, 1.5MHz, Synchronous 95% Efficiency, VIN(MIN) = 1.8V, VIN(MAX) = 5.5V, VOUT(MIN): 2V to 5V, IQ = 16μA,
LTC3531-3.3 Buck-Boost DC/DC Converter ISD = <1μA, ThinSOT and DFN Packages
LTC3532 500mA IOUT, 2MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.4V, VIN(MAX) = 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35μA,
Buck-Boost DC/DC Converter ISD = <1μA, MS10 and DFN Packages
LTC3547/LTC3547B Dual 300mA IOUT, 2.25MHz, 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN): 0.6V, IQ = 40μA, ISD = <1μA,
Synchronous Step-Down DC/DC DFN-8 Package
Converters
LTC3548/LTC3548-1/ Dual 400mA and 800mA IOUT, 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN): 0.6V, IQ = 40μA, ISD = <1μA,
LTC3548-2 2.25MHz, Synchronous Step-Down MS10E and DFN Packages
DC/DC Converters
LTC3561 1.25A IOUT, 4MHz, Synchronous 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN): 0.8V, IQ = 240μA, ISD = <1μA,
Step-Down DC/DC Converter DFN Package
ThinSOT™ is a trademark of Linear Technology Corporation.
3419fa
LT 0309 REV A • PRINTED IN USA
16 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Future Technology
Devices International Ltd
FT2232D Dual USB to
Serial UART/FIFO IC
The FT2232D is a dual USB to serial UART or Fully assisted hardware or X-On / X-Off
FIFO interface with the following advanced software handshaking.
features:
UART Interface supports 7/8 bit data, 1/2 stop
Single chip USB to dual channel serial / parallel bits, and Odd/Even/Mark/Space/No Parity.
ports with a variety of configurations.
Operational configuration mode and USB
Entire USB protocol handled on the chip. No
Description strings configurable in external
USB specific firmware programming required.
EEPROM over the USB interface.
Transfer Data Rate 300 to 3 Mbaud.
USB to parallel FIFO transfer data rate up to 1 Low operating and USB suspend current.
megabyte / second.
Multi-Protocol Synchronous Serial Engine Supports bus powered, self powered and high-
(MPSSE) to simplify synchronous serial power bus powered USB configurations.
protocol (USB to JTAG, USB to I2C, USB to UHCI/OHCI/EHCI host controller compatible.
SPI) design.
CPU-style FIFO interface mode simplifies CPU USB 2.0 Full Speed (12Mbits/Second)
interface design. compatible.
MCU host bus emulation mode configuration Extended -40°C to 85°C industrial operating
option. temperature range.
Fast Opto-Isolated serial interface option.
Compact 48-LD Lead Free LQFP package
FTDI‟s royalty-free Virtual Com Port (VCP) and
Direct (D2XX) drivers eliminate the +4.35V to +5.25V single supply operating
requirement for USB driver development in voltage range.
most cases. Dedicated Windows DLLs available for USB to
Highly integrated design includes 3.3V LDO JTAG, USB to SPI, and USB to I2C applications.
regulator for USB I/O, integrated POR function ESD protection for FT2232D IO‟s:
and on chip clock multiplier PLL (6MHz – Human Body Model (HBM) ±2kV,
48MHz). Machine Mode (MM) ±100V,
Asynchronous serial UART interface option with Charge Device Model (CDM) ±500V,
full hardware handshaking and modem Latch-up free..
interface signals.
Enhanced bit-bang Mode interface option with
RD# and WR# strobes.
Configurable I/O drive strength.
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow, G41 1HH, United Kingdom. Scotland Registered Number: SC136640
Copyright © 2010 Future Technology Devices International Limited 1

Version 2.05
1 Typical Applications
USB Audio and Low Bandwidth Video data
USB to Dual Port RS232 Converters
transfer
USB to Dual Port RS422 / RS485 Converters
PDA to USB data transfer
Upgrading Legacy Peripheral Designs to USB
USB Smart Card Readers
USB Instrumentation
USB Instrumentation
USB JTAG Programming
USB Industrial Control
USB to SPI Bus Interfaces
USB MP3 Player Interface
USB Industrial Control
USB FLASH Card Reader / Writers
Field Upgradable USB Products
Set Top Box PC - USB interface
Galvanically Isolated Products with USB
USB Digital Camera Interface
Interface
USB Bar Code Readers
USB to synchronous serial interface
Interfacing MCU / PLD / FPGA based designs to
Cellular and cordless phone USB data
USB
transfer cables and interfaces.
1.0 Driver Support

The FT2232D requires USB drivers (listed below), available free from http://www.ftdichip.com, which
are used to make the FT2232D appear as a virtual COM port (VCP). This then allows the user to
communicate with the USB interface via a standard PC serial emulation port (for example TTY). Another
FTDI USB driver, the D2XX driver, can also be used with application software to directly access the
FT2232D though a DLL.
Royalty free VIRTUAL COM PORT Royalty free D2XX Direct Drivers
(VCP) DRIVERS for... (USB Drivers + DLL S/W Interface)
Windows 98, 98SE, ME, 2000, Server 2003, XP Windows 98, 98SE, ME, 2000, Server 2003, XP
and Server 2008 and Server 2008
Windows XP and XP 64-bit Windows XP and XP 64-bit
Windows Vista and Vista 64-bit Windows Vista and Vista 64-bit
Windows XP Embedded Windows XP Embedded
Windows CE 4.2, 5.0 and 6.0 Windows CE 4.2, 5.0 and 6.0
Mac OS 8/9, OS-X Windows 7 32,64 bit
Windows 7 32,64 bit Linux 2.4 and greater
Linux 2.4 and greater
For driver installation, please refer to the application note AN232B-10.
1.1 Part Numbers

Part Number Package
FT2232D 48 Pin LQFP

Table 1.1 Part Numbers

Version 2.05
1.2 USB Compliant

The FT2232D is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID
(TID) 40680003.

Version 2.05
2 FT2232D Block Diagram
Figure 2.1 FT2232D Block Diagram
For a description of each function please refer to Section 4.1.

Version 2.05
Table of Contents
1 Typical Applications ........................................................................ 2
1.0 Driver Support .................................................................................... 2
1.1 Part Numbers...................................................................................... 2
1.2 USB Compliant .................................................................................... 3
2 FT2232D Block Diagram .................................................................. 4
3 Device Pin Out and Signal Description ............................................ 7
3.0 48-Pin LQFP Package .......................................................................... 7
3.1 Pin Out Description ............................................................................. 8
3.2 Common Pins ...................................................................................... 8
3.3 IO Pin Definitions by Chip Mode .......................................................... 10
3.4 IO Mode Command Hex Values .......................................................... 12
4 Function Description ..................................................................... 13
4.0 Key Features ..................................................................................... 13
4.1 Functional Block Descriptions ........................................................... 15
5 Devices Characteristics and Ratings.............................................. 16
5.0 Absolute Maximum Ratings............................................................... 16
5.1 DC Characteristics............................................................................. 17
5.2 ESD Tolerance ................................................................................... 20
6 USB Power Configurations ............................................................ 21
6.0 USB Bus Powered Configuration ...................................................... 21
6.1 USB Self Powered Configuration ...................................................... 22
6.2 Interfacing to 3.3V Logic ................................................................... 23
6.3 Power Switching Configuration ......................................................... 25
7 Standard Device Configuration Examples ...................................... 27
7.0 Oscillator Configurations .................................................................. 27
7.1 EEPROM Configurations .................................................................... 29
8 Signal Descriptions by IO Mode and Interface Channel
Configurations .................................................................................... 31
8.0 232 UART Interface Mode Signal Descriptions and Interface
Configurations ........................................................................................... 31
8.1 232 UART Mode LED Interface ........................................................... 35
8.2 245 FIFO Interface Mode Signal Descriptions and Interface
Configurations ........................................................................................... 37
8.3 245 FIFO Mode Timing Diagram ........................................................ 38
8.4 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal
Description and Interface Configuration .................................................... 40

Version 2.05
8.5 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal

Descriptions and Interface Configurations ................................................ 42
8.6 MCU Host Bus Emulation Mode Signal Descriptions and Interface
Configuration ............................................................................................. 44
8.7 Fast Opto-Isolated Serial Interface Mode Signal Descriptions and
Interface Configuration ............................................................................. 48
8.8 CPU FIFO Interface Mode Signal Descriptions and Configuration
Examples ................................................................................................... 52
9 Package Parameters ..................................................................... 56
10 Contact Information ................................................................... 57
Appendix A – References ........................................................................... 58
Useful Application Notes and Projects ....................................................... 58
Appendix B - List of Figures and Tables ..................................................... 59
Appendix C - Revision History .................................................................... 61

Version 2.05
3 Device Pin Out and Signal Description

3.0 48-Pin LQFP Package
Figure 3.1 48 pin LQFP Package Pin Out and Schematic Symbol

Version 2.05
3.1 Pin Out Description

This section describes the operation of the FT2232D pins. Common pins are defined in the first section,
and then the I/O pins are defined by chip mode.
Note: The convention used throughout this document for active low signals is the signal name followed
by#
3.2 Common Pins

The operation of the following FT2232D pins do not change regardless of the configured mode:-
Pin No. Name Type Description
7 USBDP I/O USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )
8 USBDM I/O USB Data Signal Minus

Table 3.1.1 USB Interface Group

EECS I/O EEPROM – Chip Select. Tri-State during device reset. **Note 1
48
EESK OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out.
1
**Note 1
EEDATA I/O EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to
Data-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the
2
EEPROM to VCC via a 10K resistor for correct operation. Tri-State during
device reset. **Note 1
Table 3.2.2 EEPROM Interface Group
4 RESET# INPUT Can be used by an external device to reset the FT2232D. If not
required, tie to VCC. **Note 1
5 RSTOUT# OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC
> 3.5V and the internal clock starts up, then clamps it‟s output to the
3.3V output of the internal regulator. Taking RESET# low will also force
RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset.
47 TEST INPUT Puts device into I.C. test mode – must be tied to GND for normal
operation.
41 PWREN# OUTPUT Goes Low after the device is configured via USB, then high during USB
suspend. Can be used to control power to external logic using a P-
Channel Logic Level MOSFET switch. Enable the Interface Pull-Down
Option in EEPROM when using the PWREN# pin in this way.
43 XTIN INPUT Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an
external 6MHz clock if required. Note: Switching threshold of this pin is
VCC/2, so if driving from an external source, the source must be
driving at 5V CMOS level or a.c. coupled to centre around VCC/2.
44 XTOUT OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating
during USB suspend, so take care if using this signal to clock external
logic.
Table 3.3.3 Miscellaneous Signal Group
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.

Version 2.05

6 3V3OUT OUTPUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be
decoupled to GND using a 33nF ceramic capacitor in close proximity to
the device pin. It‟s prime purpose is to provide the internal 3.3V supply
to the USB transceiver cell and the RSTOUT# pin. A small amount of
current (<= 5mA) can be drawn from this pin to power external 3.3V
logic if required.
3, 42 VCC PWR +4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART /
FIFO controller interface pins.
14 VCCIOA PWR +3.0 volt to +5.25 volt VCC to the UART / FIFO A Channel interface pins
10..13, 15..17 and 19..24. When interfacing with 3.3V external logic in a
bus powered design connect VCCIO to a 3.3V supply generated from the
USB bus. When interfacing with 3.3V external logic in a self powered
design connect VCCIO to the 3.3V supply of the external logic.
Otherwise connect to VCC to drive out at 5V CMOS level.
31 VCCIOB PWR +3.0 volt to +5.25 volt VCC to the UART / FIFO B Channel interface pins
26..30, 32..33 and 35..40. When interfacing with 3.3V external logic in a
bus powered design connect VCCIO to a 3.3V supply generated from the
USB bus. When interfacing with 3.3V external logic in a self powered
design connect VCCIO to the 3.3V supply of the external logic.
Otherwise connect to VCC to drive out at 5V CMOS level.
9,18, GND PWR Device - Ground Supply Pins
25, 34
46 AVCC PWR Device - Analog Power Supply for the internal x8 clock multiplier. A low
pass filter consisting of a 470 Ohm series resistor and a 100 nF to GND
should be used on the supply to this pin.
45 AGND PWR Device - Analog Ground Supply for the internal x8 clock multiplier
Table 3.4.4 Power and Ground Group

Version 2.05
3.3 IO Pin Definitions by Chip Mode

The FT2232D will default to dual serial mode (232 UART mode on both channel A and B, if no external
EEPROM is used, or the external EEPROM is blank. The definition of the following pins varies according to
the chip‟s mode:-
Channel A
Pin Definitions by Chip Mode **Note 2
Generic
232 245 Enhanced MPSSE MCU Fast CPU
Pin
Pin# UART FIFO **Note 4 Host Bus Opto- FIFO
name Asynchronous
Mode Emulatio Isolated Interfac
and
n Mode e Mode
Synchronous Serial
**Note 5
Serial
Mode
24 ADBUS0 TXD D0 D0 TCK/SK **Note 3 D0 D0

AD0
23 ADBUS1 RXD D1 D1 TDI/D0 AD1 D1 D1
22 ADBUS2 RTS# D2 D2 TDO/DI AD2 D2 D2
21 ADBUS3 CTS# D3 D3 TMS/CS D3 D3

AD3
20 ADBUS4 DTR# D4 D4 GPIOL0 AD4 D4 D4
19 ADBUS5 DSR# D5 D5 GPIOL1 AD5 D5 D5
17 ADBUS6 DCD# D6 D6 GPIOL2 AD6 D6 D6
16 ADBUS7 RI# D7 D7 GPIOL3 AD7 D7 D7
15 ACBUS0 TXDEN RXF# WR# **Note 6 GPIOH0 I/O0 CS# CS#
13 ACBUS1 SLEEP# TXE# RD# **Note 6 GPIOH1 I/O1 A0 A0
12 ACBUS2 RXLED# RD# WR# **Note 7 GPIOH2 IORDY RD# RD#
24 ADBUS0 TXD D0 D0 TCK/SK **Note 3 D0

AD0
11 ACBUS3 TXLED# WR RD# **Note 7 GPIOH3 OSC WR# WR#
10 SI/WUA SI/WUA SI/WUA SI/WUA **Note 8 **Note 8 **Note 8 **Note 8

Table 3.5.5 Pin Definition by Chip Mode (Channel A)
**Note 2: 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are
enabled in the external EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes,
MPSSE, and MCU Host Bus Emulation modes are enabled using the driver command set bit
mode. See Section 3.3 for details.
**Note 3: Channel A can be configured in another IO mode if channel B is in Fast Opto-
Isolated Serial Mode. If both Channel A and Channel B are in Fast Opto-Isolated Serial Mode all
of the IO will be on Channel B.
**Note 4: MPSSE is Channel A only.
**Note 5: MCU Host Bus Emulation requires both Channels.
**Note 6: The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on
these pins when the main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated
Serial Modes.
these pins when the main Channel mode is 232 UART Mode.

Version 2.05
**Note 8: SI/WU is not available in these modes.
Channel B
Pin Definitions by Chip Mode **Note 2
Generic
232 245 Enhanced MPSSE MCU Fast CPU
Pin
Pin# UART FIFO **Note 4 Host Bus Opto- FIFO
name Asynchronous
Mode Emulatio Isolated Interface
and
n Mode Mode
Synchronous Serial
**Note 5
Serial
Mode
40 BDBUS0 TXD D0 D0 A8 FSDI D0 D0
39 BDBUS1 RXD D1 D1 A9 FSCLK D1 D1
38 BDBUS2 RTS# D2 D2 A10 FSDO D2 D2
37 BDBUS3 CTS# D3 D3 A11 FSCTS D3 D3
36 BDBUS4 DTR# D4 D4 A12 **Note 3 D4 D4
35 BDBUS5 DSR# D5 D5 A13 D5 D5
33 BDBUS6 DCD# D6 D6 A14 D6 D6
32 BDBUS7 RI# D7 D7 A15 D7 D7
30 BCBUS0 TXDEN RXF# WR# **Note 9 CS# CS# CS#
29 BCBUS1 SLEEP# TXE# RD# **Note 9 ALE A0 A0
28 BCBUS2 RXLED# RD# WR# **Note 7 RD# RD# RD#
27 BCBUS3 TXLED# WR RD# **Note 7 WR# WR# WR#
26 SI/WUB SI/WUB SI/WUB SI/WUB **Note 8 **Note 8 SI/WUB **Note 8
40 BDBUS0 TXD D0 D0 A8 FSDI D0

Table 3.6.6 Pin Definition by Chip Mode (Channel B)
**Note 2: 232 UART, 245 FIFO, CPU FIFO Interface, and Fast Opto-Isolated modes are
enabled in the external EEPROM. Enhanced Asynchronous and Synchronous Bit-Bang modes,
MPSSE, and MCU Host Bus Emulation modes are enabled using the driver command set bit
mode. See Section 3.3 for details.
**Note 3: Channel A can be configured in another IO mode if channel B is in Fast Opto-
Isolated Serial Mode. If both Channel A and Channel B are in Fast Opto-Isolated Serial Mode all
of the IO will be on Channel B.
**Note 4: MPSSE is Channel A only.
**Note 5: MCU Host Bus Emulation requires both Channels.
these pins when the main Channel mode is 245 FIFO, CPU FIFO interface, or Fast Opto-Isolated
Serial Modes.
these pins when the main Channel mode is 232 UART Mode.
**Note 8: SI/WU is not available in these modes.
**Note 9: The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these
pins when the main Channel mode is 245 FIFO, CPU FIFO interface. Bit-Bang mode is not available
on Channel B when Fast Opto-Isolated Serial Mode is enabled.

Version 2.05
3.4 IO Mode Command Hex Values

Enhanced Asynchronous and Synchronous Bit-Bang modes, MPSSE, and MCU Host Bus Emulation modes
are enabled using the D2XX driver command FT_SetBitMode. The hex values used with this command to
enable these modes are as follows-
Mode Value (Hex)
Reset the IO bit Mode 0
Asynchronous Bit Bang Mode 1
MPSSE 2
Synchronous Bit bang Mode 4
MCU Host bus Emulation 8
Fast Opto-Isolated Serial Mode 10

Table 3.7.7 IO Mode Command Hex Values
See application note AN2232-02, “Bit Mode Functions for the FT2232D” for more details
and examples.
Note that all other device modes can be enabled in the external EEPROM, and do not require
these values to be configured.
In the case of Fast Opto-Isolated Serial mode sending a value of 10 will hold this device mode in
reset, and sending a value of 0 will release this mode from reset.

Version 2.05
4 Function Description
The FT2232D is a USB to serial UART interface device which incorporates the functionality of two
of FTDI‟s second generation FT232BM and FT245BM chips into a single device. A single downstream
USB port is converted to two IO channels which can each be individually configured as a FT232BM-
style UART interface, or a FT245BM-style FIFO interface, without the need to add a USB hub. In
addition a new high drive level option means that the device UART / FIFO IO pins will drive out at
around three times the normal power level, meaning that the bus can be shared by several devices.
4.0 Key Features

Two Individually Configurable IO Channels: Each of the FT2232D‟s Channels (A and B) can be
individually configured as a FT232BM-style UART interface, or as a FT245BM-style FIFO interface. In addition
these channels can be configured in a number of special IO modes.
Integrated Power-On-Reset (POR) circuit: The device incorporates an internal POR function. A
RESET# pin is available to allow external logic to reset the device where required, however for most
applications this pin can simply be hardwired to Vcc. A RSTOUT# pin is provided in order to allow the new
POR circuit to provide a stable reset to external MCU and other devices.
Integrated RCCLK circuit: Used to ensure that the oscillator and clock multiplier PLL frequency are stable
prior to USB enumeration.
Integrated level converter on UART / FIFO interface and control signals: Each channel of the
FT2232D has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each
channel‟s output voltage drive level to be individually configured. Thus allowing, for example 3.3V logic to
be interfaced to the device without the need for external level converter I.C.‟s.
Improved power management control for high-power USB Bus Powered devices: The PWREN# pin
will become active when the device is enumerated by USB, and be deactivated when the device is in USB
suspend. This can be used to directly drive a transistor or P-Channel MOSFET in applications where power
switching of external circuitry is required. The BM pull down enable feature (configured in the external
EEPROM) is also retained. This will make the device gently pull down on the FIFO / UART IO lines when the
power is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND
when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when
power is restored.
Send Immediate / Wake Up Signal Pin on each channel: There is a Send Immediate / Wake Up
(SI/WU) signal pins on each of the chips channels. These combine two functions on one pin. If USB is in
suspend mode (and remote wakeup is enabled in the EEPROM), strobing this pin low will cause the device
to request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used to wake up the
Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out
over USB on the next Bulk-IN request from the drivers regardless of the packet size. This can be used to
optimise USB transfer speed for some applications.
Low suspend current: The suspend current of the FT2232D is typically under 100 μA (excluding the 1.5K
pull up resistor on USBDP) in USB suspend mode. This allows greater margin for peripherals to meet the
USB Suspend current limit of 500uA.
Programmable Receive Buffer Timeout: The TX buffer timeout is programmable over USB in 1ms
increments from 1ms to 255ms, thus allowing the device to be better optimised for protocols requiring
faster response times from short data packets.
Relaxed VCC Decoupling: The improved level of Vcc decoupling that was incorporated into BM devices
has also been implemented in the FT2232D device.
Baud Rate Pre-Scaler Divisors: The FT2232D (UART mode) baud rate pre-scaler supports division by
(n+0), (n+0.125), (n+0.25), (n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875) where n is an
integer between 2 and 16,384 (214).
Extended EEPROM Support: The FT2232D supports 93C46 (64 x 16 bit), 93C56 (128 x 16 bit), and
93C66 (256 x 16 bit) EEPROMs. The extra space is not used by the device. However it is available for use
by other external MCU / logic whilst the FT2232D is being held in reset. There is now an additional 64 words
of space available (128bytes total) in the user area when a 93C56 or 93C66 is used.
USB 2.0 (full speed option): An EEPROM based option allows the FT2232D to return a USB 2.0 device
descriptor as opposed to USB 1.1. Note: The device would be a USB 2.0 Full Speed device (12Mb/s) as
opposed to a USB 2.0 High Speed device (480Mb/s).

Version 2.05
In addition to the BM chip features, the FT2232D incorporates the following new features and interface
modes:-
Enhanced Asynchronous Bit-Bang Interface: The FT2232D supports FTDI‟s BM chip Bit Bang mode. In
Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel
IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate
controlled by an internal time (equivalent to the baud rate prescaler). With the FT2232D device this mode
has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can
be used to allow external logic to be clocked by accesses to the Bit-Bang IO bus.
Synchronous Bit-Bang Interface: Synchronous Bit-Bang Mode differs from Asynchronous Bit-Bang mode
in that the device is only read when it is written to. Thus making it easier for the controlling program to
measure the response to an output stimulus as the data returned is synchronous to the output data.
High Output Drive Level Capability: The IO interface pins can be made to drive out at three times the
standard drive level thus allowing multiple devices, or devices that require a greater drive strength to be
interfaced to the FT2232D. This option is configured in the external EEPROM, ad can be set individually for
each channel.
Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.): The Multi-Protocol Synchronous
Serial Engine (MPSSE) interface is a new option designed to interface efficiently with synchronous serial
protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry
standards, or proprietary bus protocols. For instance, it is possible to connect one of the FT2232D‟s
channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device
would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC
could use the MPSSE to download configuration data to the FPGA over USB. This data would define the
hardware‟s function on power up. The other FT2232 channel would be available for other devices. This
approach would allow a customer to create a “generic” USB peripheral, whose hardware function can be
defined under control of the application software. The FPGA based hardware could be easily upgraded or
totally changed simply by changing the FPGA configuration data file. (See FTDI‟s MORPH-IC development
module for a practical example, www.morph-ic.com )
MCU Host Bus Emulation: This new mode combines the „A‟ and „B‟ bus interface to make the FT2232D
interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU
families to be directly attached to the FT2232D with IO being performed over USB with the help of MPSSE
interface technology.
CPU-Style FIFO Interface: The CPU style FIFO interface is essentially the same function as the classic
FT245 interface; however the bus signals have been redefined to make them easier to interface to a CPU
bus.
Fast Opto-Isolated Serial Interface: A new proprietary FTDI protocol is designed to allow galvanically
isolated devices to communicate synchronously with the FT2232D using just 4 signal wires (over two dual
opto-isolators), and two power lines. The peripheral circuitry controls the data transfer rate in both
directions, whilst maintaining full data integrity. Maximum USB full speed data rates can be achieved. Both
„A‟ and „B‟ channels can communicate over the same 4 wire interface if desired.

Version 2.05
4.1 Functional Block Descriptions

The following paragraphs detail each function within the FT2232D. Please refer to the block diagram
shown in Figure 2.1.
3.3V LDO Regulator: The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB
transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT
regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to
power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However,
external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power from
the 3V3OUT pin if required
USB Transceiver: The USB Transceiver Cell provides the USB 1.1 or USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential
receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection.
USB DPLL: The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered
clock and data signals to the SIE block.
6MHz Oscillator: The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock
multiplier from an external 6MHz crystal or ceramic resonator.
x8 Clock Multiplier: The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a
48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE): The Serial Interface Engine (SIE) block performs the Parallel to Serial and
Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit
stuffing / un- stuffing and CRC5 / CRC16 generation / checking on the USB data stream.
USB Protocol Engine: The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller
and the commands for controlling the functional parameters of the UART / FIFO controller blocks.
Dual Port TX Buffers (128 bytes): Data from the USB data out endpoint is stored in the Dual Port TX
buffer and removed from the buffer to the transmit register under control of the UART FIFO controller.
Dual Port RX Buffers (384 bytes): Data from the UART / FIFO controller receive register is stored in the
Dual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in
endpoint.
Multi-Purpose UART / FIFO Controllers: The Multi-purpose UART / FIFO controllers handle the transfer
of data between the Dual Port RX and TX buffers and the UART / FIFO transmit and receive registers. When
configured as a UART it performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of
the data on the RS232 (RS422 and RS485) interface. Control signals supported by UART mode include RTS,
CTS, DSR, DTR, DCD and RI. There are also transmitter enable control signal pins (TXDEN) provided to
assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and Xon/Xoff handshaking options are
also supported. Handshaking, where required, is handled in hardware to ensure fast response times. The
UART‟s also supports the RS232 BREAK setting and detection conditions.
Baud Rate Generator: The Baud Rate Generator provides a x16 clock input to the UART‟s from the 48MHz
reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud
rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is
programmable from 183 baud to 3 million baud.
RESET Generator: The Reset Generator Cell provides a reliable power-on reset to the device internal
circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices
to reset the FT2232D, or the FT2232D to reset other devices respectively. During reset, RSTOUT# is driven
low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control
the 1.5K pull-up on USBDP directly where delayed USB enumeration is required. It can also be used to reset
other devices. RSTOUT# will stay high- impedance for approximately 5ms after VCC has risen above 3.5V
AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a
requirement to reset the device from external logic or an external reset generator I.C.
EEPROM Interface: When used without an external EEPROM the FT2232D be configured as a USB to dual
serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows each of the chip‟s channels
to be independently configured as a serial UART (232 mode), or a parallel FIFO (245 mode). The external
EEPROM is used to enable the Fast Opto-Isolated Serial interface mode.
The external EEPROM can also be used to customise the USB VID, PID, Serial Number, Product Description
Strings and Power Descriptor value of the FT2232D for OEM applications. Other parameters controlled by
the EEPROM include Remote Wake Up, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The
EEPROM should be a 16 bit wide
configuration such as a MicroChip 93LC46B or equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to
5.25V. The EEPROM is programmable-on board over USB using a utility program available from FTDI‟s web
site (www.ftdichip. com). This allows a blank part to be soldered onto the PCB and programmed as part
of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT2232D
will default to dual serial ports. The device uses its built-in default VID, PID Product Description and Power
Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor.

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5 Devices Characteristics and Ratings

5.0 Absolute Maximum Ratings
These are absolute maximum ratings for the for the FT2232D device in accordance with the Absolute
Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device.
Parameter Value Unit
Storage Temperature -65°C to 150°C Degrees C
192
Floor Life (Out of Bag) At Factory Ambient
(IPC/JEDEC J-STD-033A MSL Level 3 Hours
(30°C / 60% Relative Humidity)
Compliant)**Note 10
Ambient Temperature (Power Applied) -40°C to 85°C Degrees C
VCC Supply Voltage -0.5 to +6.00 V
DC Input Voltage – USBDP and USBDM -0.5 to +3.8 V
DC Input Voltage – High Impedance

-0.5 to + (VCC +0.5) V
Bidirectional
DC Input Voltage – All Other Inputs -0.5 to + (VCC +0.5) V
DC Output Current – Outputs 24 mA
DC Output Current – Low Impedance

24 mA
Bidirectional
Power Dissipation (VCC = 5.25V) 500 mW
Electrostatic Discharge Voltage (Human

+/- 3000 V
Body Model) (I < 1μA)
Latch Up Current (Vi = +/- 10V maximum,

200 mA
for 10 ms
Table 5.1 Absolute Maximum Ratings
**Note 10 if devices are stored out of the packaging beyond this time limit the devices should be baked
before use. The devices should be ramped up to a temperature of 110oC and baked for 8 to 10 hours.

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5.1 DC Characteristics
DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter Description Minimum Typical Maximum Units Conditions
VCC Operating Supply 4.35 5.0 5.25 V

VCC1
Voltage
VCCIO Operating 3.0 - 5.25 V

VCC2
Supply Voltage
Operating Supply
Icc1 --- 30 --- mA Normal Operation
Current
Operating Supply USB Suspend

Icc2 --- 100 200 μA
Current **Note 11
Table 5.2 Operating Voltage and Current
**Note 11 - Supply current excludes the 200μA nominal drawn by the external pull-up resistor on
USBDP.
Voh Output Voltage High 3.2 4.1 4.9 V I source = 2mA
Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 2mA
Input Switching
Vin 1.3 1.2 1.5 V
Threshold
Input Switching
VHys 50 25 30 mV
Hysteresis
Table 5.3 IO Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) **Note 12
Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA
Input Switching
Vin 1.0 1.2 1.5 V
Threshold
Input Switching
VHys 20 25 30 mV
Hysteresis
Table 5.4 IO Pin Characteristics (VCCIO = 3.0V – 3.6V, Standard Drive Level) **Note 12

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Voh Output Voltage High 3.2 4.1 4.9 V I source
Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 6 mA
Vin Input Switching 1.3 1.6 1.9 V

Threshold
VHys Input Switching 50 55 60 mV

Hysteresis
Table 5.5 IO Pin Characteristics (VCCIO = 5.0V, High Drive Level) **Note 12 and 13

Threshold

Hysteresis
Table 5.6 IO Pin Characteristics (VCCIO = 3.0V -3.6V, High Drive Level) **Note 12 and 13
**Note 12: Inputs have an internal 200K pull-up resistor to VCCIO, which can alternativly be
programmed to pull down using a configuration bit in the external EEPROM.
**Note 13: The high output drive level is configured in the external EEPROM. Each channel
can be configured individually.
Voh Output Voltage High 4.0 - 5.0 V Fosc = 6MHz
Vol Output Voltage Low 0.1 - 1.0 V Fosc = 6MHz

Threshold
Voh Output Voltage High 4.0 - 5.0 V Fosc = 6MHz

Table 5.7 XTIN / XTOUT Pin Characteristics

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Threshold

Hysteresis
Table 5.8 RESET# and TEST EECS, EESK, EEDATA Pin Characteristics **Note 14
**Note 14 - EECS, EESK, EEDATA and RESET# pins have an internal 200K pull-up resistor to VCC
Voh Output Voltage High 3.0 - 3.6 V I source = 2mA
Vol Output Voltage Low 0.3 - 0.6 V I sink = 2mA

Table 5.9 RSTOUT# Pin Characteristics
RI = 1.5kΩ to
I/O Pins Static Output
UVoh 2.8 - 3.6 V 3V3OUT (D+) RI =
(High)
15KΩ to GND (D-)
RI = 1.5kΩ to
I/O Pins Static Output
UVol 0 - 0.3 V 3V3OUT (D+) RI =
(Low)
15kΩ to GND (D-)
Single Ended Rx
UVse 0.8 - 2.0 V
Threshold
Differential Common
UCom 0.8 - 2.5 V
Mode
Differential Input
UVDif 0.2 - - V
Sensitivity
Driver Output
UDrvZ 26 - 44 Ohms
Impedance
Table 5.10 USB I/O Pin (USBDP, USBDM) Characteristics **Note 15
**Note 15 - Driver Output Impedance includes the external 27R series resistors on USBDP and USBDM
pins.

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5.2 ESD Tolerance
ESD protection for FT2232D IO‟s
Parameter Reference Minimum Typical Maximum Units
JEDEC EIA/JESD22-A114-B,
Human Body Model (HBM) ±2kV kV
Class 2
JEDEC EIA/JESD22-A115-A,
Machine Mode (MM) ±100V V
Class A
Charge Device Model JEDEC EIA/ JESD22-C101-D,

±500V V
(CDM) Class-III
Latch-up JESD78, Trigger Class-II ±200mA mA
Table 5.11 ESD Tolerance

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6 USB Power Configurations

The following sections illustrate possible USB power configurations for the FT2232D.
6.0 USB Bus Powered Configuration
Figure 6.1 Bus Powered Configuration

Figure 6.1 illustrates the FT2232D in a typical USB bus powered configuration. A USB Bus
Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as
follows:-
a) On plug-in, the device must draw no more than 100mA
b) On USB Suspend the device must draw no more than 500μA.
c) A High Power USB Bus Powered Device (one that draws more than 100mA) should use the
PWREN# pin to keep the current below 100mA on plug-in and 500μA on USB suspend.
d) A device that consumes more than 100mA cannot be plugged into a USB Bus Powered Hub
e) No device can draw more that 500mA from the USB Bus.
The power descriptor in the EEPROM should be programmed to match the current draw required by the
device. A Ferrite Bead is connected in series with USB power to prevent noise from the device and
associated circuitry (EMI) being radiated down the USB cable to the Host. The value of the Ferrite Bead
depends on the total current required by the circuit - a suitable range of Ferrite Beads is available from
Steward (www.steward.com) for example Steward Part # MI0805K400R-00 also available from DigiKey,
Part # 240-1035-1.

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6.1 USB Self Powered Configuration
Figure 6.2 Self Powered Configuration
Figure 6.2 illustrates the FT2232D in a typical USB self powered configuration. A USB Self
Powered device gets its power from its own POWER SUPPLY and does not draw current from the
USB bus. The basic rules for USB Self power devices are as follows –
a) A Self-Powered device should not force current down the USB bus when the USB
Host or Hub Controller is powered down.
b)A Self Powered Device can take as much current as it likes during normal operation
and USB suspend as it has its own POWER SUPPLY.
c)A Self Powered Device can be used with any USB Host and both Bus and Self
Powered USB Hubs.
The USB power descriptor option in the EEPROM should be programmed to a value of zero (self powered).
To meet requirement a) the 1.5 K pull-up resistors on USBDP is connected to RSTOUT# as per the bus-
power circuit. However, the USB Bus Power is used to control the RESET# Pin of the FT2232D device. When
the USB Host or Hub is powered up RSTOUT# will pull the 1.5K resistor on USBDP to 3.3V, thus identifying
the device as a full speed device to USB. When the USB Host or Hub power is off, RESET# will go low and
the device will be held in reset. As RESET# is low, RSTOUT# will also be low, so no current will be forced
down USBDP via the 1.5K pull-up resistor when the host or hub is powered down. Failure to do this may
cause some USB host or hub controllers to power up erratically. Note: When the FT2232D is in reset, the
I/O interface pins all go tri-state. These pins have internal 200K pull-up resistors to VCCIO, so they will
gently pull high unless driven by some external logic.

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6.2 Interfacing to 3.3V Logic
Figure 6.3 Bus Powered Circuit with 3.3V logic drive and IO supply voltage
Figure 6.3 shows how to configure the FT2232D to interface with 3.3V logic devices. In this example,
a discrete 3.3V regulator is used to supply the 3.3V logic from the USB supply. VCCIOA and VCCIOB
are connected to the output of the 3.3V regulator, which in turn will cause the device interface IO
pins on both channels to drive out at 3.3V level. It is also possible to have one IO interface channel
driving out at 5V level, and the other at 3.3V level. In this case one of the VCCIO pins would be
connected to 5V, and the other connected to 3.3V.
For USB bus powered circuits some considerations have to be taken into account when selecting the
regulator:-
a) The regulator must be capable of sustaining its output voltage with an input voltage of 4.35
volts. A Low Drop Out (LDO) regulator must be selected.
b) The quiescent current of the regulator must be low in order to meet the USB suspend
total current requirement of <= 500μA during USB suspend.
An example of a regulator family that meets these requirements is the MicroChip (Telcom) TC55
Series. These devices can supply up to 250mA current and have a quiescent current of under 1μA.
In some cases, where only a small amount of current is required (< 5mA) , it may be possible to
use the in-built regulator of the FT2232D to supply the 3.3V without any other components being
required. In this case, connect VCCIOA or VCCIOB to the 3V3OUT pin of the FT2232D.
Note: It should be emphasised that the 3.3V supply for VCCIO in a bus powered design with a 3.3V
logic interface should come from an LDO which is supplied by the USB bus, or from the 3V3OUT pin
of the FT232BM, and not from any other source. Please also note that if the SI/WU pins are not
being used they should be pulled up to the same supply as their respective VCCIO pin.

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Figure 6.4 Self Powered Circuit with 3.3V logic drive and IO supply voltage
Figure 6.4 is an example of a FT2232D USB self powered design with 3.3V interface. In this case
the VCCIOA and VCCIOB pins are supplied by an external 3.3V supply in order to make both of the
device‟s IO channels drive out at 3.3V logic level, thus allowing them to be connected to a 3.3V
MCU or other external logic. It is also possible to have one IO interface channel driving out at 5V
level, and the other at 3.3V level. In this case one of the VCCIO pins would be connected to 5V,
and the other connected to 3.3V. A USB self powered design uses its own power supplies, and
does not draw any of its power from the USB bus. In such cases, no special care need be taken to
meet the USB suspend current (0.5 mA) as the device does not get its power from the USB port.
As with bus powered 3.3V interface designs, in some cases, where only a small amount of current
is required (<5mA), it may be possible to use the in-built regulator of the FT2232D to supply the
3.3V without any other components being required. In this case, connect VCCIOA or VCCIOB to
the 3V3OUT pin of the FT2232D. Note that if the SI/WU pins are not being used they should be
pulled up to the same supply as their respective VCCIO pin.

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6.3 Power Switching Configuration
Figure 6.5 Bus Powered Circuit with Power Control
USB Bus powered circuits need to be able to power down in USB suspend mode in order to meet
the <= 500μA total suspend current requirement (including external logic). Some external logic can
power itself down into a low current state by monitoring the PWREN# pin. For external logic that
cannot power itself down in that way, the FT2232D provides a simple but effective way of turning
off power to external circuitry during USB suspend.
Figure 6.5 shows how to use a discrete P-Channel Logic Level MOSFET to control the power to
external logic circuits. A suitable device would be an International Rectifier (www.irf.com)
IRLML6402, or equivalent. It is recommended that a “soft start” circuit consisting of a 1K series
resistor and a 0.1 μF capacitor are used to limit the current surge when the MOSFET turns on.
Without the soft start circuit there is a danger that the transient power surge of the MOSFET turning
on will reset the FT2232D, or the USB host / hub controller. The values used here allow attached
circuitry to power up with a slew rate of ~12.5 V per millisecond, in other words the output voltage
will transition from GND to 5V in approximately 400 microseconds.
Alternatively, a dedicated power switches I.C. with inbuilt “soft-start” can be used instead of a
MOSFET. A suitable power switch I.C. for such an application would be a Micrel (www.micrel.com)
MIC2025-2BM or equivalent. Please note the following points in connection with power controlled
designs: –
a)The logic to be controlled must have its own reset circuitry so that it will automatically reset
itself when power is re-applied on coming out of suspend.
b)Set the Pull-down on Suspend option in the FT2232D‟s EEPROM.
c)For USB high-power bus powered device (one that consumes greater than 100 mA, and up to
500 mA of current from the USB bus), the power consumption of the device should be set in the
max power field in the EEPROM. A high-power bus powered device must use this descriptor in the
EEPROM to inform the system of its power requirements.
d)For 3.3V power controlled circuits the VCCIO pins must not be powered down with the external
circuitry. Either connect the power switch between the output of the 3.3V regulator and the
external 3.3V logic, or if appropriate power the VCCIO pin from the 3V3OUT pin of the FT2232D.

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Figure 6.6 Bus Powered Circuit with Power Control and 3.3V Logic Drive/ IO Supply Voltage
Figure 6.6 is a FT2232D design example which effectively combines the circuits shown in Figures
6.4 and 6.5 to give a USB bus powered design with power switching and 3.3V logic drive level on
both channels. Once again a P-Channel Power MOSFET and soft start circuit are used to control the
power to external logic devices. A 3.3V LDO regulator which is supplied by the USB bus is used to
provide the 3.3V supply for the VCCIO pins, as well as the external logic. If the SI/WU pins are not
being used they should be pulled up to 3.3V.

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7 Standard Device Configuration Examples

7.0 Oscillator Configurations
Figure 7.1 3-Pins Ceramic Resonator Configuration
Figure 7.1 illustrates how to use the FT2232D with a 3-Pin Ceramic Resonator. A suitable part would be a
ceramic resonator from Murata‟s CERALOCK range. (Murata Part Number CSTCR6M00G15), or equivalent.
3-Pin ceramic resonators have the load capacitors built into the resonator so no external loading
capacitors are required. This makes for an economical configuration. The accuracy of this Murata ceramic
resonator is +/- 0.25% and it is specifically designed for USB full speed applications. A 1 MegaOhm
loading resistor across XTIN and XTOUT is recommended in order to guarantee this level of accuracy.
Other ceramic resonators with a lesser degree of accuracy (typically +/- 0.5%) are technically out-with
the USB specification, but it has been calculated that using such a device will work satisfactorily in
practice with a FT2232D design. An example of such a device is Murata‟s CSTLSM00G53.

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Figure 7.2 Crystal or 2-Pin Ceramic Resonator Configuration
Figure 7.2 illustrates how to use the FT2232D with a 6MHz Crystal or 2-Pin Ceramic Resonator. In this
case, these devices do not have in-built loading capacitors so these have to be added between XTIN,
XTOUT and GND as shown. A value of 27pF is shown as the capacitor in the example – this will be good
for many crystals and some resonators but do select the value based on the manufacturers
recommendations wherever possible. If using a crystal, use a parallel cut type. If using a resonator, see
the previous note on frequency accuracy.
It is also possible to use a 6 MHz Oscillator with the FT2232D. In this case the output of the oscillator
would be connected to XTIN, and XTOUT should be left unconnected. The oscillator must have a CMOS
output.

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7.1 EEPROM Configurations
Figure 7.3 EEPROM Configuration
Figure 7.3 illustrates how to connect the FT2232D to the 93C46 (93C56 or 93C66) EEPROM. EECS (pin
48) is directly connected to the chip select (CS) pin of the EEPROM. EESK (pin 1) is directly connected to
the clock (SK) pin of the EEPROM. EEDATA (pin 2) is directly connected to the Data In (Din) pin of the
EEPROM. There is a potential condition whereby both the Data Output (Dout) of the EEPROM can drive
out at the same time as the EEDATA pin of the FT2232D. To prevent potential data clash in this situation,
the Dout of the EEPROM is connected to EEDATA of the FT2232D via a 2.2K resistor.
Following a power-on reset or a USB reset, the FT2232D will scan the EEPROM to find out (a) if an
EEPROM is attached to the Device and (b) if the data in the device is valid. If both of these are the case,
then the FT2232D will use the data in the EEPROM, otherwise it will use its built-in default values and
configuration. The default port configuration of the FT2232D puts both Channel A and Channel B into
serial UART mode.
When a valid command is issued to the EEPROM from the FT2232D, the EEPROM will acknowledge the
command by pulling its Dout pin low. In order to check for this condition, it is necessary to pull Dout high
using a 10K resistor. If the command acknowledge doesn‟t happen then EEDATA will be pulled high by
the 10K resistor during this part of the cycle and the device will detect an invalid command or no EEPROM
present.
There are two varieties of 93C46/56/66 EEPROM‟s on the market – one is configured as being 16 bits
wide, the other is configured as being 8 bits wide. These are available from many sources such as
Microchip, STMicro, ISSI etc. The FT2232D requires EEPROM‟s with a 16-bit wide configuration such as
the Microchip 93LC46B device. The EEPROM must be capable of reading data at a 1Mb clock rate at a
supply voltage of 4.35V to 5.25V. Most available parts are capable of this. Check the manufacturers data
sheet to find out how to connect pins 6 and 7 of the EEPROM. Some devices specify these as no-connect,
others use them for selecting 8 / 16 bit mode or for test functions. Some other parts have their pinout
rotated by 90o so please select the required part and its options carefully.

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It is possible to “share” the EEPROM between the FT2232D and another external device such as an MCU.
However, this can only be done when the FT2232D is in its reset condition as it tri-states its EEPROM
interface at that time. A typical configuration would use four bits of an MCU IO Port. One bit would be
used to hold the FT2232D reset (using RESET#) on power-up, the other three would connect to the
EECS, EESK and EEDATA pins of the FT2232D in order to read / write data to the EEPROM at this time.
Once the MCU has read / written the EEPROM, it would take RESET# high to allow the FT2232D to
configure itself and enumerate over USB.
The external EEPROM can be programmed over USB using utility software provided by FTDI. The external
EEPROM is used to enable 245 FIFO, and Fast Opto-Isolated Serial interface modes on each channel.

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8 Signal Descriptions by IO Mode and Interface Channel

Configurations
8.0 232 UART Interface Mode Signal Descriptions and Interface
Configurations
When either Channel A or Channel B is in 232 UART mode, the IO signal lines are configured as follows:-
Pin# Signal Type Description
Channel A Channel B
24 40 TXD OUTPUT Transmit Asynchronous Data Output
23 39 RXD INPUT Receive Asynchronous Data Input **Note 16
22 38 RTS# OUTPUT Request To Send Control Output / Handshake signal
21 37 CTS# INPUT Clear To Send Control Input / Handshake signal
**Note 16
20 36 DTR# OUTPUT Data Terminal Ready Control Output / Handshake
signal
19 35 DSR# INPUT Data Set Ready Control Input / Handshake signal
**Note 16
17 33 DCD# INPUT Data Carrier Detect Control Input **Note 16
16 32 RI# INPUT Ring Indicator Control Input. When the Remote
Wake up option is enabled in the EEPROM, taking
RI# low can be used to resume the PC USB Host
controller from suspend. **Note 16
15 30 TXDEN OUTPUT Enable Transmit Data for RS485
13 29 SLEEP# OUTPUT Goes low during USB Suspend Mode. Typically used
to power-down an external TTL to RS232 level
converter I.C. in USB to RS232 converter designs.
12 28 RXLED# O.C. LED Drive - Pulses Low when Transmitting Data via
USB.
11 27 TXLED# O.C LED Drive - Pulses Low when Receiving Data via
USB.
10 26 SI/WU INPUT The Send Immediate / WakeUp signal combines
two functions on a single pin. If USB is in suspend
mode (PWREN# = 1) and remote wakeup is
enabled in the EEPROM , strobing this pin low will
cause the device to request a resume on the USB
Bus. Normally, this can be used to wake up the
Host PC.
During normal operation (PWREN# = 0), if this pin
is strobed low any data in the device TX buffer will
be sent out over USB on the next Bulk-IN request
from the drivers regardless of the pending packet
size. This can be used to optimise USB transfer
speed for some applications. Tie this pin to VCCIO if
not used
Table 8.1 232 UART mode the IO signal lines Description
**Note 16: These pins are pulled to up VCCIO via internal 200K resistors during Reset and USB
Suspend mode. These can be programmed to gently pull low during USB suspend (PWREN#
=“1”) by setting this option in the EEPROM.

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Figure 8.1 USB <=> Dual Port RS232 Converter Configuration
Figure 8.1 illustrates how to connect the FT2232D, when both channels A and B are configured as 232-
style UART interfaces, to two TTL – RS232 Level Converter I.C.‟s to make a USB <=> Dual Port RS232
converter using the popular “213” series of TTL to RS232 level converters. These devices have 4
transmitters and 5 receivers in a 28-LD SSOP package and feature an in-built voltage converter to
convert the 5V (nominal) VCC to the +/- 9 volts required by RS232. An important feature of these
devices is the SHDN# pin which can power down the device to a low quiescent current during USB
suspend mode.
The device used in the example above is a Sipex SP213EHCA which is capable of RS232 communication
at up to 500K baud. If a lower baud rate is acceptable, then several pin compatible alternatives are
available such as the Sipex SP213ECA , the Maxim MAX213CAI and the Analog Devices ADM213E, which
are all good for communication at up to 115,200 baud. If a higher baud rate is desired, use a Maxim
MAX3245CAI part which is capable of RS232 communication at rates of up to 1M baud. The MAX3245 is
not pin compatible with the 213 series devices, also its SHDN pin is active high, so connect it to PWREN#
instead of SLEEP#. Dual RS232 level converters such as the Maxim MAX3187 may also be a suitable
alternative.

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Figure 8.2 illustrates how to connect the UART interfaces of the FT2232D to two TTL - RS422 Level
Converter I.C.‟s to make a USB to dual port RS422 converter. There are many such level converter
devices available - this example uses two Sipex SP491 devices which have enables on both their
transmitters and receivers. Because the transmitter enables are active high, they are connected to
the SLEEP# pins.
The receiver enables are active low and are both connected to the PWREN# pin. This ensures that
both the transmitters and receivers are enabled when the device is active, and disabled when the
device is in USB suspend mode. If the design is USB BUS powered, it may be necessary to use a P-
Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to ensure
that the USB standby current of 500μA is met. The SP491 is good for sending and receiving data at
a rate of up to 5M Baud - in this case the maximum rate is limited to 3M Baud by the FT2232D.

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Figure 8.3 illustrates how to connect the UART interfaces of the FT2232D to two TTL – RS485 Level
Converter I.C.‟s to make a USB to dual port RS485 converter. This example uses two Sipex SP491
devices but there are similar parts available from Maxim and Analog Devices amongst others. The SP491
is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and
receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the
UART. The TXDEN pins on the FT2232D are provided for exactly that purpose, and so the transmitter
enables are wired to the TXDEN‟s. The receiver enable is active low, so it is wired to the PWREN# pin to
disable the receiver when in USB suspend mode.
RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two
wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are

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provided to allow the cable to be terminated if the device is physically positioned at either end of the
cable.
In this example the data transmitted by the FT2232D is also received by the device that is transmitting.
This is a common feature of RS485 and requires the application software to remove the transmitted data
from the received data stream. With the FT2232D it is possible to do this entirely in hardware – simply
modify the schematic so that RXD of the FT2232D is the logical OR of the SP481 receiver output with
TXDEN using an HC32 or similar logic gate.
8.1 232 UART Mode LED Interface
Figure 8.4 Dual LED Configuration

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Figure 8.5 Single LED Configuration
When configured in UART mode the FT2232D has two IO pins on each channel dedicated to controlling
LED status indicators, one for transmitted data the other for received data. When data is being
transmitted / received the respective pins drive from tri-state to low in order to provide indication on the
LED‟s of data transfer. A digital one-shot timer is used so that even a small percentage of data transfer is
visible to the end user. Figure 8.4 shows a configuration using two individual LED‟s – one for transmitted
data the other for received data. In Figure 8.5, the transmit and receive LED indicators are wire-OR‟ed
together to give a single LED indicator which indicates any transmit or receive data activity.
Another possibility (not shown here) is to use a 3 pin common anode tri-color LED based on the circuit in
Figure 7.5 to have a single LED that can display activity in a variety of colors depending on the ratio of
transmit activity compared to receive activity.
Note that the LED‟s are connected to the same supply as VCCIO.

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8.2 245 FIFO Interface Mode Signal Descriptions and Interface

Configurations
When either Channel A or Channel B is in 245 FIFO mode, the IO signal lines are configured as follows:-
Channel A Channel B
24 40 D0 I/O FIFO Data Bus Bit 0
Table 8.2 FIFO Data Bus Group **Note 17
Channel A Channel B
15 30 RXF# OUTPUT When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low then high again ** Note 18
13 29 TXE# OUTPUT When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high
then low. ** Note 18
12 28 RD# INPUT Enables Current FIFO Data Byte on D0..D7 when low.
Fetches the next FIFO Data Byte (if available) from the
Receive FIFO Buffer when RD# goes from low to high.
** Note 17
11 27 WR INPUT Writes the Data Byte on the D0..D7 into the Transmit
FIFO Buffer when WR goes from high to low.
** Note 17
10 26 SI/WU INPUT The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM, strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used.
Table 8.3 FIFO Control Interface Group
**Note 17: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
**Note 18: During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K
resistors.

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8.3 245 FIFO Mode Timing Diagram
Figure 8.6 FIFO Read Cycle
Time Description Min Max Unit

T1 RD# Active Pulse 50 ns RD# Active Pulse Width
Width
T2 RD# to RD Pre- 50 + T6 ns RD# to RD Pre-Charge Time
Charge Time
T3 RD# Active to 20 50 ns
Valid Data
**Note 19
T4 Valid Data Hold 0 ns Valid Data Hold Time from RD#
Time from RD# Inactive **Note 19
Inactive
**Note 19
T5 RD# Inactive to 0 25 ns
RXF#
T6 RXF# inactive after 80 ns RXF# inactive after RD# cycle
RD# cycle
Table 8.4 Read Cycle
** Note 19: Load 30 pF at standard drive level. These times will also vary if the high output drive level
is enabled
Figure 8.7 FIFO Write Cycle

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T7 WR Active Pulse 50 ns WR Active Pulse Width
Width
T8 WR to WR Pre- 50 ns WR to WR Pre-Charge Time
Charge Time
T9 Data Setup Time 20 ns Data Setup Time before WR
before WR inactive inactive
T10 Data Hold Time 0 ns Data Hold Time from WR
from WR inactive inactive
T11 WR Inactive to 5 25 ns
TXE#
T12 TXE inactive after 80 ns TXE inactive after WR cycle
WR cycle
Table 8.5 Write Cycle
Figure 8.8 Microprocessor Interface Example

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Figure 8.8 illustrates a typical interface between one of the channels of the FT2232D, configured in 245-
style FIFO interface mode, and a Microcontroller (MCU). Either channel A or B, or both can be configured
in this mode.
This examples uses two IO Ports of the MCU, one port (8 bits) to transfer data to one of the and the
other port (4 / 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes
to the FT2232D as required. Optionally, SI / WU can be connected to another IO pin if either of the
functions of this pin are required. If the SI / WU function is not required, tie this pin to VCCIO. If the MCU
is handling power management functions, then PWREN# should also be connected to an IO pin of the
MCU.
The 8 data bits on IO Port 1 can be shared with other peripherals when the MCU is not accessing the
FT2232D
8.4 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal

Description and Interface Configuration
Bit-bang mode is a special FT2232D device mode that changes the 8 IO lines on either (or both) channels
into an 8 bit bi-directional data bus. The are two types of Bit-bang mode for the FT2232D - Enhanced
Asynchronous Bit-Bang Mode, which is virtually the same as FTDI BM chip-style Bit-Bang mode, with the
addition of Read and Write strobes; and Synchronous Bit-Bang mode, where data is only read from the
device when the device is written to. Bit-Bang mode is enabled by driver command. When either Channel
A or Channel B (or both) have Enhanced Asynchronous Bit-Bang mode, or Synchronous Bit-Bang mode
enabled the IO signal lines are configured as follows :-
Channel A Channel B
24 40 D0 I/O Bit-Bang Data Bus Bit 0
Table 8.6 Bit-Bang Data Bus Group **Note 24
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
Channel A Channel B
15 30 WR# OUTPUT **Note 25
13 29 RD# OUTPUT **Note 25
12 28 WR# INPUT **Note 26
11 27 RD# INPUT **Note 26
10 26 SI/WU INPUT The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM , strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used
Table 8.7 Bit-Bang Control Interface Group

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**Note 25: The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these
pins when the main Channel mode is 245 FIFO, or Fast Opto-Isolated Serial Mode. Bit-Bang mode is not
available on Channel B when Fast Opto-Isolated Serial Mode is enabled.
**Note 26 : The Bit-Bang Mode (synchronous and asynchronous) WR# and RD# strobes are on these
pins when the main Channel mode is set to 232 UART Mode.
Enhanced Asynchronous Bit-Bang Mode

Enhanced Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode, except that the internal
RD# and WR# strobes are now brought out of the device to allow external logic to be clocked by
accesses to the bit-bang IO bus.
On either or both channels any data written to the device in the normal manner will be self clocked onto
the data pins (those which have been configured as outputs). Each pin can be independently set as an
input or an output. The rate that the data is clocked out at is controlled by the baud rate generator.
For the data to change there has to be new data written, and the baud rate clock has to tick. If no new
data is written to the channel, the pins will hold the last value written.
To allow time for the data to be setup and held around the WR# strobe, the baud rate should be less
than 1 MegaBaud.
See the application note AN232B-01, “FT232BM/FT245BM Bit Bang Mode” for more details and a
sample application.
Enabling
Asynchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 1 will
enable it, and a hex value of 0 will reset the device. See application note AN2232-02, “Bit Mode
Functions for the FT2232D” for more details and examples of this.
Synchronous Bit-Bang Mode

With Synchronous Bit-Bang mode data will only be sent out by the FT2232D if there is space in the
device for data to be read from the pins. This Synchronous Bit-Bang mode will read the data bus pins
first, before it sends out the byte that has just been transmitted. It is therefore 1 byte behind the output,
and so to read the inputs for the byte that you have just sent, another byte must be sent.
For example:-
(1) Pins start at 0xFF
Send 0x55, 0xAA
Pins go to 0x55 and then to 0xAA
Data read = 0xFF, 0x55
(2) Pins start at 0xFF
Send 0x55, 0xAA, 0xAA
(Repeat the last byte sent)
Pins go to 0x55 and then to 0xAA
Data read = 0xFF, 0x55, 0xAA
Enabling
Synchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 4 will
Functions for the FT2232D” for more details and examples.

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Figure 8.9 Synchronous Bit Bang Mode Signal Timing
Time Description
t1 Current pin state is read
t2 RD# is set inactive
t3 RD# is set active again, and any pins that are output will change to the new data.
t4 Clock state for data setup
t5 WR# goes active
t6 WR# goes inactive
Table 8.8 Synchronous Bit Bang Mode Signal Timing
The internal RD# and WR# strobes are brought out of the device to allow external logic to be clocked by
accesses to the bit-bang IO bus.
8.5 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal

Descriptions and Interface Configurations
MPSSE Mode is designed to allow the FT2232D to interface efficiently with synchronous serial protocols
such as JTAG and SPI Bus. It can also be used to program SRAM based FPGA‟s over USB. The MPSSE
interface is designed to be flexible so that it can be configured to allow any synchronous serial protocol
(industry standard or proprietary) to be interfaced to the FT2232D. MPSSE is available on channel A only.
MPSSE is fully configurable, and is programmed by sending commands down the data pipe. These can be
sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of
5.6 Mega bits /s.

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When Channel A is configured in MPSSE mode the IO signal lines are configured as follows:-
Channel A only
24 TCK/SK OUTPUT Clock signal Output
23 TDI/D0 OUTPUT Serial Data Out
22 TDO/DI INPUT Serial Data In **Note 27
21 TMS/CS OUTPUT Select Signal Out
20 GPIOL0 I/O General Purpose input / Output **Note 27
15 GPIOH0 I/O General Purpose input / Output **Note 27
Table 8.9 MPSSE Mode Configuration
programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the
EEPROM.
Enabling
MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a
hex value of 0 will reset the device. See application note AN2232-02, “Bit Mode Functions for the
FT2232D” for more details and examples.
The MPSSE command set is fully described in application note AN_108, “Command Processor for
MPSSE and MCU Host Bus Emulation Modes”.
Example project code for the FT2232D that demonstrates how to use the devices Multi-Protocol
Synchronous Serial Engine (MPSSE) to make a USB to SPI bus interface are available from FTDI‟s web
site http://www.ftdichip.com/Projects/MPSSE.htm#SPI
Synchronous Serial Engine (MPSSE) to make a USB to I2C bus interface are available from FTDI‟s web
site http://www.ftdichip.com/Projects/MPSSE.htm#I2C
Synchronous Serial Engine (MPSSE) to make a USB to JTAG bus interface are available from FTDI‟s web
site http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

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8.6 MCU Host Bus Emulation Mode Signal Descriptions and Interface
Configuration
MCU host bus emulation mode uses both of the FT2232D‟s A and B channel interfaces to make the chip
emulate a standard 8048 / 8051 MCU host bus. This allows peripheral devices for these MCU families to
be directly connected to USB via the FT2232D.
The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide upper (extended)
addresses.
There are 4 basic operations:-
1) Read (does not change A15 to A8)
2) Read Extended (changes A15 to A8)
3) Write (does not change A15 to A8)
4) Write Extended (changes A15 to A8)
Enabling
MCU Host Bus Emulation mode is enabled using Set Bit Bang Mode driver command. A hex value of 8 will
Functions for the FT2232D” for more details and examples.
The MCU Host Bus Emulation Mode command set is fully described in application note AN_108,
“Command Processor For MPSSE and MCU Host Bus Emulation Modes”.
When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels work together and
the pins are configured as follows :-
24 AD0 I/O Address / Data Bus Bit 0 **Note 28
15 I/O0 I/O MPSSE mode instructions to set / clear or read the
high byte of data can be used with this pin. **Note
28, **Note 29
13 I/O1 I/O MPSSE mode instructions to set / clear or read the
high byte of data can be used with this pin. In
addition this pin has instructions which will make
the controller wait until it is high, or wait until it is
low. This can be used to connect to an IRQ pin of a
peripheral chip. The FT2232D will wait for the
interrupt, and then read the device, and pass the
answer back to the host PC. I/O1 must be held in
input mode if this option is used. **Note 28,
**Note 29
12 IORDY INPUT Extends the time taken to perform a Read or Write
operation if pulled low. Pull up to Vcc if not being
used.
11 OSC OUTPUT Shows the clock signal that the circuit is using.
40 A8 OUTPUT Extended Address Bus Bit 8
30 CS# OUTPUT Negative pulse to select device during Read or
Write.
29 ALE OUTPUT Positive pulse to latch the address.
28 RD# OUTPUT Negative Read Output.
27 WR# OUTPUT Negative Write Output. (Data is setup before WR#
goes low, and is held after WR# goes high)
Table 8.10 MCU Host Bus Emulation Mode IO Signal Lines Configuration

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**Note 28: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
**Note 29: These instructions are fully described in the application note AN2232L-01 - “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
Figure 8.10 MCU Host Bus Emulation Mode Signal Timing - Write Cycle
Time Description
t1 High address byte is placed on the bus if the extended write is used.
t2 Low address byte is put out.
t3 1 clock period for address is set up.
t4 ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is
low.
t5 ALE goes low to latch address and CS# is set active low.
t6 Data driven onto the bus.
t7 1 clock period for data setup.
t8 WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.
t9 WR# is driven inactive high.
t10 CS# is driven inactive, 1/2 a clock period after WR# goes inactive
t11 Data is held until this point, and may now change
Table 8.11 MCU Host Bus Emulation Mode Signal Timing - Write Cycle

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Figure 8.11 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Time Description
t1 High address byte is placed on the bus if the extended read is used -
otherwise t1 will not occur.
t2 Low address byte is put out.
t3 1 clock period for address set up.
t4 ALE goes high to enable address latch. This will extend to 2 clocks wide if
IORDY is low.
t5 ALE goes low to latch address, and CS# is set active low. This will extend to 3
clocks if IORDY is sampled low. CS# will always drop 1 clock after ALE has
gone high no matter the state of IORDY.
t6 Data is set as input (Hi-Z), and RD# is driven active low.
t7 1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is
sampled low.
t8 RD# is driven inactive high.
t9 CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the
data bus is set back to output.
Table 8.12 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Figure 8.12 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal

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Time Description Min Typical Max Unit
Value
tperiod Clock Period 41.6 83.3 125.0 ns
thigh Clock signal high 20.8 41.6 62.5 ns
time
tlow Clock signal low 20.8 41.6 62.5 ns
time
Table 8.13 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
Figure 8.13 MCU Host Bus Emulation Example - USB <=> CAN Bus Interface
Figure 8.13 shows an example where the FT2232D is used to interface a Philips SJA1000 CAN Bus
Controller to a PC over USB. In this example IORDY is not used and so is pulled up to Vcc. I/O1 is used to
monitor the Interrupt output (INT) of the SJA1000. The MODE pin on the SJA1000 is pulled high to select
Intel mode. See the semiconductors section of the Philips website (www.philips.com) for more details
on the SJA1000 and suitable CAN Bus transceiver devices.

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8.7 Fast Opto-Isolated Serial Interface Mode Signal Descriptions and

Interface Configuration
Fast Opto-Isolated Serial Interface Mode provides a method of communicating with an external device
over USB using 4 wires that can have opto-isolators in their path, thus providing galvanic isolation
between systems. If either channel A or channel B are enabled in fast opto-isolated serial mode then the
pins on channel B are switched to the fast serial interface configuration. The I/O interface for fast serial
mode is always on channel B, even if both channels are being used in this mode. An address bit is used
to determine the source or destination channel of the data. It therefore makes sense to always use at
least channel B or both for fast serial mode, but not A own its own.
When either Channel B or Both Channel A and B are configured in Fast Opto-Isolated Serial Interface
mode following IO signal lines are configured as follows :-
40 FSDI INPUT Fast serial data input **Note 30
39 FSCLK INPUT Clock input to FT2232D chip to clock data in or out.
The external device has to provide a clock signal or
nothing will change on the interface pins. This gives
the external device full control over the interface. It
is designed to be half duplex so that data is only
transferred in one direction at a time. **Note 30
38 FSDO OUTPUT Fast serial data output. Driven low to indicate that
the chip is ready to send data.
37 FSCTS OUTPUT Clear To Send control signal output
26 SI/WU INPUT The Send Immediate / WakeUp signal combines
two functions on a single pin. If USB is in suspend
mode (PWREN# = 1) and remote wakeup is
enabled in the EEPROM , strobing this pin low will
cause the device to request a resume on the USB
Bus. Normally, this can be used to wake up the
Host PC.
During normal operation (PWREN# = 0), if this pin
is strobed low any data in the device TX buffer will
be sent out over USB on the next Bulk-IN request
from the drivers regardless of the pending packet
size. This can be used to optimise USB transfer
speed for some applications. Tie this pin to VCCIO if
not used.
Table 8.14 Fast Opto-Isolated Serial Interface Mode IO Signal Lines Configuration
**Note 30: Pulled up to VCCIO via internal 200K resistors. These pins can be programmed to gently pull
low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
Fast Opto-Isolated serial interface mode is enabled in the external EEPROM.

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Figure 8.14 Fast Opto-Isolated Serial Signal Timing Diagram

t1 FSDO / FSCTS hold 5 - ns
time
t2 FSDO / FSCTS 5 - ns
setup time
t3 FSDI hold time 5 - ns
t4 FSDI setup time 10 - ns
t5 FSCLK low 10 - ns
t6 FSCLK high 10 - ns
Table 8.15 Fast Opto-Isolated Serial Signal Timing Diagram
Outgoing Fast Serial Data

To send fast serial data out of the chip, the external device must clock. If the chip has data ready to
send, it will drive FSDO low to indicate the start bit. It will not do this if it is currently receiving data from
the external device.
Figure 8.15 Fast Opto-Isolated Serial Data Format - Data output from the FT2232D
Notes:-
(i) Start Bit is always 0.
(ii) Data is sent LSB first.
(iii) The source bit (SRCE) indicates which channel the data has come from. A „0‟ means that it
has come from Channel A, a „1‟ means that it has come from Channel B.
(iv) If the target device is unable to accept the data when it detects the start bit, it should stop
the FSCLK until it can accept the data.

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Incoming Fast Serial Data

The external device is allowed to send data into the chip if FSCTS is high. On receipt of a Zero start bit on
FSDI, the chip will drop FSCTS on the next positive clock edge. The data from bits 0 to 7 is then clocked
in (LSB first). The next bit determines where the data will be written to. It can go to either channel A or
to channel B. A „0‟ will send it to channel A, providing channel A is enabled for fast serial mode, otherwise
it will go to channel B. A „1‟ will send it to channel B, providing channel B is enabled for fast serial mode,
otherwise it will go to channel A. (Either channel A, or channel B, or both must be enabled as fast serial
mode or the circuit is disabled).
Figure 8.16 Fast Opto-Isolated Serial Data Format - Data input to the FT2232D
Notes:-
(i) Start Bit is always 0.
(ii) Data is sent LSB first.
(iii) The destination bit (DEST) indicates which channel the data should go to. A „0‟ means that it
should go to channel A, a „1‟ means that it should go to channel B.
(iv) The target device should check CTS is high before it sends data. CTS goes low after data bit
0 (D0) and stays low until the chip can accept more data.
Contention
There is a possibility that contention may occur, where the interface goes from being completely idle to
both sending and receiving at the same clock instance. In this case the chip backs off, and allows the
data from the external device to be received.
Data Format
The data format for either direction is:-
1) Zero Start Bit
2) Data bit 0
3) Data bit 1
4) Data bit 2
5) Data bit 3
6) Data bit 4
7) Data bit 5
8) Data bit 6
9) Data bit 7
10) Source/Destination („0‟ indicates channel A; „1‟ indicates channel B)
Reset / Enable
Fast serial mode is enabled by setting the appropriate bits in the external EEPROM. The fast serial mode
can be held in reset by setting a bit value of 10 using the Set Bit Bang Mode command. While this bit is
set the device is held reset - data can be sent to the device, but it will not be sent out by the device until
the device is enabled again. This is done by sending a bit value of 0 using the set bit mode command.
See application note AN2232L-02, “Bit Mode Functions for the FT2232D” for more details and
examples.

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Figure 8.17 Fast Opto-Isolated Serial Interface Example
In the example shown in figure 8.18 two Agilent HCPL-2430 (see the semiconductor section at
www.agilent.com) high speed opto-couplers are used to optically isolate an external device which
interfaced to USB using the FT2232D. In this example VCC5V is the supply for the FT2232D (bus or self
powered), and VCCE is the supply to the external device.
Care must be taken with the voltage used to power the photoLED‟s. It should be the same supply that
the I/Os are driving to, or the LED‟s may be permanently on. Limiting resistors should be fitted in the
lines that drive the diodes. The outputs of the opto-couplers are open-collector and so need a pullup
resistor.
Testing
Fast serial mode has been tested using an Scenix (Ubicom), SX28 microcontroller (see
www.ubicom.com) which was configured in loopback mode. This was done both with, and without HP
HCPL-2430 opto-isolators in place. The isolators add a considerable delay to the turnaround time seen by
the micro. This was close to 100 nS with the high speed HCPL-2430 device. This is the combined delay of
the clock signal from the microcontroller going through an opto-coupler to the chip, and the data from
the FT2232D chip going through the other opto-coupler back to the microcontroller.

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8.8 CPU FIFO Interface Mode Signal Descriptions and Configuration

Examples
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232D. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0).
When either Channel A or Channel B are in CPU FIFO Interface mode the IO signal lines are configured as
follows:-
Channel A Channel B
Table 8.16 FIFO Data Bus Group **Note 20
Channel A Channel B
15 30 CS# INPUT Chip Select Bit ** Note 20
13 29 A0 INPUT Address Bit ** Note 20
12 28 RD# INPUT Negative read input ** Note 20
11 27 WR# INPUT Negative write input ** Note 20
Table 8.17 FIFO Control Interface Group
programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the
EEPROM
CS# A0 RD# WR#
1 X X X
0 0 Read Data Pipe Write Data Pipe
0 1 Read Status Send Immediate **Note 21
Table 8.18 Chip Select bit and Address bit truth table
Key: X = Not Used; 1 = Signal off; 0 = Signal off
**Note 21: Has to be clocked by USB clock

Data Bit Data Status
bit 0 1 Data Available (=RXF)
bit 1 1 Space Available (=TXE)
bit 2 1 Suspend
bit 3 1 Configured
bit 4 **Note 22 X X
bit 5 **Note 22 X X
bit 6 **Note 22 X X
bit 7 **Note 22 X X
Table 8.19 Status Data bits
Key: X = Not Used; 1 = Signal off; 0 = Signal off

**Note 22: bits 4 to 7 will have arbitrary values when the status is read.

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Figure 8.18 CPU FIFO Interface Mode - Signal Timing

t1 A0 / CS Setup to WR# 15 - ns
t2 Data setup to WR# 15 - ns
t3 WR# Pulse width 20 - ns
t4 A0/CS Hold from WR# 5 - ns
t5 Data hold from WR# 5 - ns
t6 A0/CS Setup to RD# 15 - ns
t7 Data delay from RD# 15 50 ns
**Note 23
t8 A0/CS hold from RD# 5 - ns
t9 Data hold time from RD# 0 30 ns
**Note 23
Table 8.20 CPU FIFO Interface Mode - Signal Timing
**Note 23: For standard output drive level Times may vary if high drive level is enabled

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Figure 8.19 CPU FIFO Single Channel Interface Example 1
Figure 8.20 shows an example where channel A of the FT2232D is used in CPU FIFO mode to interface
with a CPU. To read or write data to or from the CPU to the FT2232D, the FT2232D‟s Chip Select (CS#)
would be set to 0. In order to read the status of the device the Address bit would then be set to 1, and
RD# would be strobed causing the status data to be driven onto D0...D7. If data is available (D0 = 1)
then it can be read by setting A0 to 0, and strobing RD#. If space is available (D1=1) then data can be
written to the FT2232D by setting A0 to 0 and strobing WR#.
When CS# is set to 0 and A0 is set to 1, strobing WR# causes any data in the FT2232D‟s TX buffer to be
sent out over USB on the next Bulk-In request, regardless of the pending packet size.

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Figure 8.20 CPU FIFO Dual Channel Interface Example 2
Figure 8.21 shows an example where both channels A and B of the FT2232D are used in CPU FIFO mode
to interface with a CPU. This configuration gives the CPU access to both of the FT2232D‟s data pipes.

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9 Package Parameters
The FT2232D is supplied in a 48 pin lead (Pb) free LQFP package. This package has a 7mm x 7mm body
(9mm x 9mm including leads) with leads on a 0.5mm pitch. The FT2232D is fully compliant with the
European Union RoHS directive.
The below drawing shows the LQFP-48 package – all dimensions are in millimeters.
XXYY = Date Code (XX = 2 digit week number, YY = 1 or 2 digit year number.
Figure 9.1 48LD Lead Free LQFP Package Dimensions
Tape and reel information is available in the following applications note:

http://www.ftdichip.com/Documents/AppNotes/AN_116_FTDI%20Devices%20Tape%20and%20Reel%20
Dimensions.pdf

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10 Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited

Unit 1, 2 Seaward Place,
Centurion Business Park
Glasgow, G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales) sales1@ftdichip.com

E-mail (Support) support1@ftdichip.com
E-mail (General Enquiries) admin1@ftdichip.com
Web Site URL http://www.ftdichip.com
Web Shop URL http://www.ftdichip.com
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)

2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8751 9737
E-mail (Sales) tw.sales1@ftdichip.com

E-mail (Support) tw.support1@ftdichip.com
E-mail (General Enquiries) tw.admin1@ftdichip.com
Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)

7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales) us.sales@ftdichip.com

E-mail (Support) us.support@ftdichip.com
E-mail (General Enquiries) us.admin@ftdichip.com
Branch Office – ShangHai, China
Future Technology Devices International Limited (China)

Room 408, 317 Xianxia Road,
ChangNing District,
ShangHai, P.R. China
Tel: +86 (21) 62351596

Fax: +86 (21) 62351595
E-Mail (Sales) cn.sales@ftdichip.com

E-mail (Support) cn.support@ftdichip.com
E-Mail (General Enquiries) cn.admin@ftdichip.com
Distributor and Sales Representatives

Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.

Version 2.05
Appendix A – References
AN2232-02, “Bit Mode Functions for the FT2232D”
http://www.ftdichip.com/Documents/AppNotes/AN2232C-02_FT2232CBitMode.pdf
AN232B-01, “FT232BM/FT245BM Bit Bang Mode”

http://www.ftdichip.com/Documents/AppNotes/AN232B-01_BitBang.pdf
AN2232L_108, “Command Processor for MPSSE and MCU Host Bus Emulation Modes”.
http://www.ftdichip.com/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Hos
t_Bus_Emulation_Modes.pdf
Useful Application Notes and Projects
http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf
http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf
http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf
http://www.ftdichip.com/Resources/Utilities/AN_127_User_Guide_For_FT2232HD_Factory%20test%20uti
lity.pdf
http://www.ftdichip.com/Documents/AppNotes/AN_131_FT2232D_H_Fast%20Opto-
Isolated%20Serial%20Interface%20mode.pdf
http://www.ftdichip.com/Documents/AppNotes/AN2232C-02_FT2232CBitMode.pdf
http://www.ftdichip.com/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Hos
t_Bus_Emulation_Modes.pdf
http://www.ftdichip.com/Projects/MPSSE.htm#SPI
http://www.ftdichip.com/Projects/MPSSE.htm#I2C
http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

Version 2.05
Appendix B - List of Figures and Tables

List of Figures
Figure 2.1 FT2232D Block Diagram ................................................................................................. 4
Figure 3.1 48 pin LQFP Package Pin Out and Schematic Symbol.......................................................... 7
Figure 6.1 Bus Powered Configuration ........................................................................................... 21
Figure 6.2 Self Powered Configuration ........................................................................................... 22
Figure 6.3 Bus Powered Circuit with 3.3V logic drive and IO supply voltage.......................................... 23
Figure 6.4 Self Powered Circuit with 3.3V logic drive and IO supply voltage ......................................... 24
Figure 6.5 Bus Powered Circuit with Power Control ........................................................................... 25
Figure 6.6 Bus Powered Circuit with Power Control and 3.3V Logic Drive/ IO Supply Voltage ................ 26
Figure 7.1 3-Pins Ceramic Resonator Configuration ......................................................................... 27
Figure 7.2 Crystal or 2-Pin Ceramic Resonator Configuration ............................................................ 28
Figure 7.3 EEPROM Configuration ................................................................................................. 29
Figure 8.1 USB <=> Dual Port RS232 Converter Configuration ......................................................... 32
Figure 8.4 Dual LED Configuration ................................................................................................ 35
Figure 8.5 Single LED Configuration .............................................................................................. 36
Figure 8.6 FIFO Read Cycle .......................................................................................................... 38
Figure 8.7 FIFO Write Cycle ......................................................................................................... 38
Figure 8.8 Microprocessor Interface Example ................................................................................. 39
Figure 8.9 Synchronous Bit Bang Mode Signal Timing ...................................................................... 42
Figure 8.10 MCU Host Bus Emulation Mode Signal Timing - Write Cycle ............................................. 45
Figure 8.11 MCU Host Bus Emulation Mode Signal Timing - Read Cycle ............................................. 46
Figure 8.12 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal .................................. 46
Figure 8.13 MCU Host Bus Emulation Example - USB <=> CAN Bus Interface .................................... 47
Figure 8.14 Fast Opto-Isolated Serial Signal Timing Diagram ........................................................... 49
Figure 8.15 Fast Opto-Isolated Serial Data Format - Data output from the FT2232D ........................... 49
Figure 8.16 Fast Opto-Isolated Serial Data Format - Data input to the FT2232D ................................. 50
Figure 8.17 Fast Opto-Isolated Serial Interface Example .................................................................. 51
Figure 8.18 CPU FIFO Interface Mode - Signal Timing ...................................................................... 53
Figure 8.19 CPU FIFO Single Channel Interface Example 1 .............................................................. 54
Figure 8.20 CPU FIFO Dual Channel Interface Example 2 ................................................................. 55
Figure 9.1 48LD Lead Free LQFP Package Dimensions ..................................................................... 56

Version 2.05
List of Tables
Table 1.1 Part Numbers ................................................................................................................. 2
Table 3.1.1 USB Interface Group .................................................................................................... 8
Table 3.2.2 EEPROM Interface Group............................................................................................... 8
Table 3.3.3 Miscellaneous Signal Group ........................................................................................... 8
Table 3.4.4 Power and Ground Group .............................................................................................. 9
Table 3.5.5 Pin Definition by Chip Mode (Channel A) ....................................................................... 10
Table 3.6.6 Pin Definition by Chip Mode (Channel B) ....................................................................... 11
Table 3.7.7 IO Mode Command Hex Values ..................................................................................... 12
Table 5.1 Absolute Maximum Ratings ........................................................................................... 16
Table 5.2 Operating Voltage and Current ....................................................................................... 17
Table 5.3 IO Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) **Note 12 .............................. 17
Table 5.4 IO Pin Characteristics (VCCIO = 3.0V – 3.6V, Standard Drive Level) **Note 12 .................... 17
Table 5.5 IO Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) **Note 12 and 13 .................. 18
Table 5.6 IO Pin Characteristics (VCCIO = 3.0V -3.6V, Standard Drive Level) **Note 12 and 13 .......... 18
Table 5.7 XTIN / XTOUT Pin Characteristics ................................................................................... 18
Table 5.8 RESET# and TEST EECS, EESK, EEDATA Pin Characteristics **Note 14 .............................. 19
Table 5.9 RSTOUT# Pin Characteristics......................................................................................... 19
Table 5.10 USB I/O Pin (USBDP, USBDM) Characteristics **Note 15 ................................................ 19
Table 5.11 ESD Tolerance ............................................................................................................ 20
Table 8.1 232 UART mode the IO signal lines Description................................................................ 31
Table 8.2 FIFO Data Bus Group **Note 17 ..................................................................................... 37
Table 8.3 FIFO Control Interface Group ......................................................................................... 37
Table 8.4 Read Cycle ................................................................................................................... 38
Table 8.5 Write Cycle .................................................................................................................. 39
Table 8.6 Bit-Bang Data Bus Group **Note 24 ............................................................................... 40
Table 8.7 Bit-Bang Control Interface Group .................................................................................... 40
Table 8.8 Synchronous Bit Bang Mode Signal Timing ....................................................................... 42
Table 8.9 MPSSE Mode Configuration ............................................................................................ 43
Table 8.10 MCU Host Bus Emulation Mode IO Signal Lines Configuration ........................................... 44
Table 8.11 MCU Host Bus Emulation Mode Signal Timing - Write Cycle .............................................. 45
Table 8.12 MCU Host Bus Emulation Mode Signal Timing - Read Cycle ............................................... 46
Table 8.13 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal.................................... 47
Table 8.14 Fast Opto-Isolated Serial Interface Mode IO Signal Lines Configuration .............................. 48
Table 8.15 Fast Opto-Isolated Serial Signal Timing Diagram ............................................................. 49
Table 8.16 FIFO Data Bus Group **Note 20 ................................................................................... 52
Table 8.17 FIFO Control Interface Group........................................................................................ 52
Table 8.18 Chip Select bit and Address bit truth table ..................................................................... 52
Table 8.19 Status Data bits .......................................................................................................... 52
Table 8.20 CPU FIFO Interface Mode - Signal Timing ....................................................................... 53

Version 2.05
Appendix C - Revision History

Version 0.91 Initial Datasheet Created October 2006
Version 2.00 Contact details edited and Corrected FT2232D features 10/11/09
(Removed reference to Isochronous support)
Added links for sample project code that demonstrate how to use
the devices Multi-Protocol Synchronous Serial Engine (MPSSE)
Added Windows 7 support. Added TID number.
Added apps notes references.
Released on the Web
Version 2.01 Corrected table pin No. on Table 3.1.1 27/01/10

Corrected figure 6.6 label from Self Powered to Bus Powered
Version 2.02 Added ESD specifications 21/05/10

Version 2.03 Edited table 5.2 31/05/10
Version 2.04 Edited table 3.5.5 and 3.5.6 CPU FIFO mode signal names 27/07/10
Added section 1.2 USB compliant
Edited Figure 2.1
Version 2.05 Corrected table 5.5 and 5.6 to show “High Current” 18/04/11
Corrected Section 8.7 title

64Mb: x4, x8, x16 SDRAM
Features
Synchronous DRAM
MT48LC16M4A2 – 4 Meg x 4 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram
Features Options Marking

• PC100- and PC133-compliant • Configurations
• Fully synchronous; all signals registered on positive – 16 Meg x 4 (4 Meg x 4 x 4 banks) 16M4
edge of system clock – 8 Meg x 8 (2 Meg x 8 x 4 banks) 8M8
• Internal pipelined operation; column address can be – 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16
changed every clock cycle • Write recovery (tWR)
• Internal banks for hiding row access/precharge – tWR = “2 CLK”1 A2
• Programmable burst lengths: 1, 2, 4, 8, or full page • Plastic package – OCPL2
• Auto precharge, includes concurrent auto precharge – 54-pin TSOP II (400 mil) TG
and auto refresh modes – 54-pin TSOP II (400 mil) Pb-free, P
• Self refresh modes: standard and low power RoHS-compliant
(not available on AT devices) – 54-ball VFBGA 8mm x 8mm (x16 only) F4
• Refresh – 54-ball VFBGA 8mm x 8mm, Pb-free, B43
– 64ms, 4,096-cycle refresh (15.6µs/row) RoHS-compliant (x16 only)
(commercial, industrial) • Timing (cycle time)
– 16ms, 4,096-cycle refresh (3.9µs/row) – 7.5ns @ CL = 3 (PC133) -75
(automotive) – 7.5ns @ CL = 2 (PC133) -7E
• LVTTL-compatible inputs and outputs – 6ns @ CL = 3 (x16 only) -6
• Single +3.3V ±0.3V power supply • Self refresh
– Standard None
Table 1: Address Table – Low power L
• Operating temperature range
16 Meg x 4 8 Meg x 8 4 Meg x 16
– Commercial (0°C to +70°C) None
Configuration 4 Meg x 4 x 2 Meg x 8 x 1 Meg x 16 x – Industrial (–40°C to +85°C) IT
4 banks 4 banks 4 banks
– Automotive (–40°C to +105°C) AT3
Refresh count 4K 4K 4K • Design revision :G
Row 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)
Notes: 1. Refer to Micron technical note: TN-48-05.
addressing
2. Off-center parting line.
Bank 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
addressing 3. Contact Micron for product availability.
Column 1K (A0–A9) 512 (A0–A8) 256 (A0–A7) Part Number Example:
addressing MT48LC8M8A2TG-75:G
PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_1.fm - Rev. N 12/08 EN 1 ©2000 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
General Description
Table 2: Key Timing Parameters

CL = CAS (READ) latency
Access Time
Speed Grade Clock Frequency CL = 2 CL = 3 Setup Time Hold Time
-6 166 MHz – 5.5ns 1.5ns 1ns
-7E 143 MHz – 5.4ns 1.5ns 0.8ns
-75 133 MHz – 5.4ns 1.5ns 0.8ns
-7E 133 MHz 5.4ns – 1.5ns 0.8ns
-75 100 MHz 6ns – 1.5ns 0.8ns
Table 3: 64Mb SDRAM Part Numbers
Part Numbers Architecture Package

MT48LC16M4A2TG 16 Meg x 4 54-pin TSOP II
MT48LC16M4A2P 16 Meg x 4 54-pin TSOP II
MT48LC4M16A2B41 4 Meg x 16 54-ball VFBGA
MT48LC4M16A2F41 4 Meg x 16 54-ball VFBGA
Notes: 1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp
General Description
The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns
by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns
by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
Automotive Temperature
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed, random-access
operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode
is provided, along with a power-saving, power-down mode. All inputs and outputs are
LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperatures cannot be less than –40°C or greater than 105°C
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
64MSDRAMTOC.fm - Rev. N 12/08 EN 4 ©2000 Micron Technology, Inc. All rights reserved.
List of Figures
List of Figures
Figure 1: 16 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2: 8 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3: 4 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 4: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5: Ball Assignment (Top View, Ball Down) x16, 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 10: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 11: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 12: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 13: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 14: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 15: READ-to-WRITE With Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 16: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 17: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 18: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 19: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 20: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 21: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 22: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 23: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 24: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 25: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 26: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 27: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 28: Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 29: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 30: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 31: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 32: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 35: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 36: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 37: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 38: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 39: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 40: READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 41: READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 42: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 43: Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 44: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 45: READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 46: READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 47: WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 48: WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 49: Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 50: Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 51: Alternating Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 52: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 53: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 54: 54-Pin Plastic TSOP II (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
64MSDRAMLOF.fm - Rev. N 12/08 EN 5 ©2000 Micron Technology, Inc. All rights reserved.
List of Tables
List of Tables
Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3: 64Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 7: Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 9: Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 10: Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 11: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 12: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 13: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 14: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 15: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 16: TSOP Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 17: VFBGA Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .48
Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
64MSDRAMLOT.fm - Rev. N 12/08 EN 6 ©2000 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams

Figure 1: 16 Meg x 4 SDRAM
CKE
CLK
CS# CONTROL
COMMAND
LOGIC
DECODE
WE#
BANK3
CAS# BANK2
RAS# BANK1
REFRESH 12
MODE REGISTER COUNTER
ROW- 12 BANK0
ADDRESS ROW- BANK0
MUX ADDRESS MEMORY 1 1
12 4096
LATCH ARRAY DQM
12 & (4,096 x 1,024 x 4)
DECODER
SENSE AMPLIFIERS DATA

4 OUTPUT
4096 REGISTER
2 I/O GATING 4 DQ0–DQ3

DQM MASK LOGIC
BANK READ DATA LATCH
A0–A11, ADDRESS CONTROL WRITE DRIVERS
BA0, BA1 14
REGISTER LOGIC DATA
2 4 INPUT
1024 REGISTER
(x4)
COLUMN
DECODER
COLUMN-
ADDRESS 10
10 COUNTER/
LATCH
CKE
CLK
CS# CONTROL
COMMAND
LOGIC
DECODE
WE#
BANK3
CAS# BANK2
RAS# BANK1
REFRESH 12
ROW- 12 BANK0
ADDRESS ROW- BANK0
12 4096
LATCH ARRAY DQM
12 & (4,096 x 512 x 8)
DECODER

8 OUTPUT
4096 REGISTER

DQM MASK LOGIC
BA0, BA1 14
REGISTER LOGIC DATA
2 8 INPUT
512 REGISTER
(x8)
COLUMN
DECODER
COLUMN-
ADDRESS 9
9 COUNTER/
LATCH
CKE
CLK
CS# CONTROL
COMMAND
LOGIC
DECODE
WE#
BANK3
CAS# BANK2
RAS# BANK1
REFRESH 12
ROW- 12 BANK0
ADDRESS ROW- BANK0
12 4096
LATCH ARRAY DQML,
12 & DQMH
(4,096 x 256 x 16)
DECODER

16 OUTPUT
4096 REGISTER

DQM MASK LOGIC
BA0, BA1 14
REGISTER LOGIC DATA
2 16 INPUT
256 REGISTER
(x16)
COLUMN
DECODER
COLUMN-
ADDRESS 8
8 COUNTER/
LATCH
Pin/Ball Assignments and Descriptions

Figure 4: Pin Assignment (Top View) 54-Pin TSOP
x4 x8 x16 x16 x8 x4
- - VDD 1 54 Vss - -
NC DQ0 DQ0 2 53 DQ15 DQ7 NC
- - VDDQ 3 52 VssQ - -
NC NC DQ1 4 51 DQ14 NC NC
DQ0 DQ1 DQ2 5 50 DQ13 DQ6 DQ3
- - VssQ 6 49 VDDQ - -
NC DQ2 DQ4 8 47 DQ11 DQ5 NC
- - VDDQ 9 46 VssQ - -
DQ1 DQ3 DQ6 11 44 DQ9 DQ4 DQ2
- - VssQ 12 43 VDDQ - -
- - VDD 14 41 Vss - -
NC NC DQML 15 40 NC - -
- - WE# 16 39 DQMH DQM DQM
- - CAS# 17 38 CLK - -
- - RAS# 18 37 CKE - -
- - CS# 19 36 NC - -
- - BA0 20 35 A11 - -
- - BA1 21 34 A9 - -
- - A10 22 33 A8 - -
- - A0 23 32 A7 - -
- - A1 24 31 A6 - -
- - A2 25 30 A5 - -
- - A3 26 29 A4 - -
- - VDD 27 28 Vss - -
Notes: 1. The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is
same as x16 pin function.
Figure 5: Ball Assignment (Top View, Ball Down) x16, 54-Ball VFBGA
1 2 3 4 5 6 7 8 9
A VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD DQML DQ7
F DQMH CLK CKE CAS# RAS# WE#
G NC/A12 A11 A9 BA0 BA1 CS#
H A8 A7 A6 A0 A1 A10
J VSS A5 A4 A3 A2 VDD
Notes: 1. The balls at A4, A5, and A6 are absent from the physical package. They are included to illus-
trate that rows 4, 5, and 6 exist, but contain no solder balls.
Table 4: Pin/Ball Descriptions
VFBGA
TSOP Pin Ball
Numbers Numbers Symbol Type Description
38 F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37 F3 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE power-down and
SELF REFRESH operation (all banks idle), ACTIVE power-down (row
active in any bank), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19 G9 CS# Input Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH, but READ/WRITE bursts already in progress will
continue and DQM will retain its DQ mask capability while CS#
remains HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
16, 17, 18 F9, F7, F8 WE#, CAS#, Input Command inputs: WE#, CAS#, and RAS# (along with CS#) define the
RAS# command being entered.
39 – x4, x8: Input Input/output mask: DQM is an input mask signal for write accesses and
DQM an output enable signal for read accesses. Input data is masked when
15, 39 E8, F1 x16: DQM is sampled HIGH during a WRITE cycle. The output buffers are
DQML, placed in a High-Z state (two-clock latency) when DQM is sampled
DQMH HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC
and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7 and
DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered
same state when referenced as DQM.
20, 21 G7, G8 BA0, BA1 Input Bank address inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
23–26, H7, H8, J8, A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command
29–34, 22, J7, J3, J2, (row-address A0–A11) and READ/WRITE command (column-address
35 H3, H2, H1, A0–A9 [x4]; A0–A8 [x8]; A0–A7 [x16]; with A10 defining auto
G3, H9, G2 precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a precharge command to
determine whether all banks are to be precharged (A10[HIGH]) or
bank selected by BA0, BA1 (A1[LOW]). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8, A8, B9, B8, DQ0–DQ15 x16: I/O Data input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
10, 11, 13, C9, C8, D9, NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for
42, 44, 45, D8, E9, E1, x4).
47, 48, 50, D2, D1, C2,
51, 53 C1, B2, B1,
A2
2, 5, 8, 11, – DQ0–DQ7 x8: I/O Data input/output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
44, 47, 50,
53
5, 11, 44, – DQ0–DQ3 x4: I/O Data input/output: Data bus for x4.
50
40 E2 NC – No connect: These pins should be left unconnected.
Functional Description
Table 4: Pin/Ball Descriptions
VFBGA
TSOP Pin Ball
Numbers Numbers Symbol Type Description
36 G1 NC – No connect: May be used as address inputs (A12) on the 256Mb and
512Mb devices.
3, 9, 43, 49 A7, B3, C7, VDDQ Supply DQ power: Isolated DQ power on the die for improved noise
D3 immunity.
6, 12, 46, A3, B7, C3, VSSQ Supply DQ ground: Isolated DQ ground on the die for improved noise
52 D7 immunity.
1, 14, 27 A9, E7, J9 VDD Supply Power supply: +3.3V ±0.3V.
28, 41, 54 A1, E3, J1 VSS Supply Ground.
In general, the 64Mb SDRAM (4 Meg x 4 x 4 banks, 2 Meg x 8 x 4 banks, and 1 Meg x 16 x 4
banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the
x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the
x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (x4: A0–A9; x8: A0–A8; x16:
A0–A7) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
After the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
The recommended power-up sequence for SDRAMs:

1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.
All banks will complete their precharge, thereby placing the device in the all banks
idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LOAD MODE REGISTER command,
program the mode register. The mode register is programmed via the MODE REGIS-
TER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is
programmed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Outputs
are guaranteed High-Z after the LOAD MODE REGISTER command is issued. Outputs
should be High-Z already before the LOAD MODE REGISTER command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this point the DRAM is ready for any valid command.
Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CL, an operating mode
and a write burst mode, as shown in Figure 6 on page 15. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CL, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future
use.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length
READ and WRITE accesses to the SDRAM are burst oriented, with the burst length (BL)
being programmable, as shown in Figure 6 on page 15. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. BL = 1, 2, 4, or 8 locations are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for the sequential mode. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states cannot be used because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A9 (x4), A1–A8 (x8) or A1–A7 (x16) when BL = 2; by A2–A9 (x4),
A2–A8 (x8) or A2–A7 (x16) when BL = 4; and by A3–A9 (x4), A3–A8 (x8) or A3–A7 (x16)
when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap within the page if the boundary
is reached.
Figure 6: Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx)
Reserved WB Op Mode CAS Latency BT Burst Length
Program Burst Length

BA0, BA1,
M11, M10 = “0, 0” M2 M1 M0 3=0 M3 = 1
to ensure compatibility
with future devices. 0 0 0 1 1
0 0 1 2 2
M9 Write Burst Mode
0 1 0 4 4
0 Programmed Burst Length
0 1 1 8 8
1 Single Location Access
1 0 0 Reserved Reserved
M8 M7 M6–M0 Operating Mode 1 0 1 Reserved Reserved
0 0 Defined Standard Operation 1 1 0 Reserved Reserved
– – – All other states reserved 1 1 1 Full Page Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 5 on page 16.
Table 5: Burst Definition
Order of Accesses Within a Burst

Burst
Length Starting Column Address Type = Sequential Type = Interleaved
2 A0
0 0-1 0-1
1 1-0 1-0
4 A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full page (y) n = A0–A9/8/7 Cn, Cn + 1, Cn + 2 Not supported
Cn + 3, Cn + 4...
(location 0–y) …Cn - 1, Cn…
Notes: 1. For full-page accesses: y = 1,024 (x4); y = 512 (x8); y = 256 (x16).
2. For BL = 2, A1–A9 (x4), A1–A8 (x8), or A1–A7 (x16) select the block-of-two burst; A0 selects
the starting column within the block.
3. For BL = 4, A2–A9 (x4), A2–A8 (x8), or A2–A7 (x16) select the block-of-four burst; A0–A1
select the starting column within the block.
4. For BL = 8, A3–A9 (x4), A3–A8 (x8), or A3–A7 (x16) select the block-of-eight burst; A0–A2
select the starting column within the block.
5. For a full-page burst, the full row is selected and
6. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the starting column.
7. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
8. For BL = 1, A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the unique column to be accessed,
and mode register bit M3 is ignored.
CAS Latency
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a read command is registered at T0 and the
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 7 on page 17. Table 6 on page 17 indicates the oper-
ating frequencies at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 7: CAS Latency
T0 T1 T2 T3
CLK
COMMAND READ NOP NOP

tLZ tOH
DQ DOUT
tAC
CL = 2
T0 T1 T2 T3 T4
CLK
COMMAND READ NOP NOP NOP

tLZ tOH
DQ DOUT
tAC
CL = 3
DON’T CARE
UNDEFINED
Table 6: CAS Latency
Allowable Operating Frequency (MHz)

Speed CL = 2 CL = 3
-6 – ≤166
-7E ≤133 ≤143
-75 ≤100 ≤133
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode

When M9 = 0, the burst length programmed via M0–M2 applies to both read and write
bursts; when M9 = 1, the programmed burst length applies to read bursts, but write
accesses are single-location (nonburst) accesses.
Commands
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operation” on page 21; these tables provide current state/next state information.
Table 7: Truth Table 1 – Commands and DQM Operation

CKE is HIGH for all commands shown except SELF REFRESH.
Name (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row) L L H H X Bank/row X 2
READ L H L H L/H8 Bank/col X 3
(Select bank and column, and start READ burst)
WRITE L H L L L/H8 Bank/col Valid 3
(Select bank and column, and start WRITE burst)
BURST TERMINATE L H H L X X Active
PRECHARGE L L H L X Code X 4
(Deactivate row in bank or banks)
AUTO REFRESH or SOFT REFRESH L L L H X X X 5, 6
(Enter self refresh mode)
LOAD MODE REGISTER L L L L X Op-code X 1
Write enable/output enable – – – – L – Active 7
Write inhibit/output High-Z – – – – H – High-Z 7
Notes: 1. A0–A11 define the op-code written to the mode register.

2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) provide column address; A10 (HIGH) enables the
auto precharge feature (nonpersistent), while A10 (LOW) disables the auto precharge fea-
ture; BA0, BA1 determine which bank is being read from or written to.
4. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
charged and BA0, BA1 are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The command inhibit function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
Commands
LOAD MODE REGISTER

The mode register is loaded via inputs A0–A11. See mode register heading in “Register
Definition” on page 13. The LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD
is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a precharge command is issued to that bank. A precharge command must
be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 (x4), A0–
A8 (x8), or A0–A7 (x16) selects the starting column location. The value on input A10
determines whether auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected,
the row will remain open for subsequent accesses. Read data appears on the DQs subject
to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was regis-
tered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal
was registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 (x4),
A0–A8 (x8), or A0–A7 (x16) selects the starting column location. The value on input A10
determines whether auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the
DQs is written to the memory array subject to the DQM input logic level appearing coin-
cident with the data. If a given DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank precharge function
described above, without requiring an explicit command. This is accomplished by using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command.
Commands
A precharge of the bank/row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-
sistent in that it is either enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in “Operation” on
page 21.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the Operation section of this data
sheet. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command as shown in the Operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the
64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and indus-
trial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every
15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the refresh
requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms
(commercial and industrial) or 16ms (automotive).
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE
is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
Commands
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR, because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.
Operation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 8).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 9 on page 22, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Commands
Figure 8: Activating a Specific Row in a Specific Bank
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A10, A11 ROW

ADDRESS
BA0, BA1 BANK

ADDRESS
DON’T CARE
Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3
T0 T1 T2 T3
CLK
tCK tCK tCK
COMMAND ACTIVE NOP NOP READ or

WRITE
tRCD (MIN)
tRCD (MIN) +0.5 tCK
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 10 on page 23.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 11 on page 24 shows general
timing for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Commands
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst which is being truncated.
The new READ command should be issued x cycles before the clock edge at which the
last desired data element is valid, where x = CL -1. This is shown in Figure 12 on page 25
for CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architecture. A READ command
can be initiated on any clock cycle following a previous READ command. Full-speed
random read accesses can be performed to the same bank, as shown in Figure 13 on
page 26, or each subsequent READ may be performed to a different bank.
Figure 10: READ Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A9: x4 COLUMN
A0–A8: x8 ADDRESS
A0–A7: x16
A11: x4
A9, A11: x8
A8, A9, A11: x16
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1 BANK

ADDRESS
DON’T CARE
Commands
Figure 11: CAS Latency
T0 T1 T2 T3
CLK
COMMAND READ NOP NOP

tLZ tOH
DQ DOUT
tAC
CL = 2
T0 T1 T2 T3 T4
CLK

tLZ tOH
DQ DOUT
tAC
CL = 3
DON’T CARE
UNDEFINED
Commands
Figure 12: Consecutive READ Bursts
T0 T1 T2 T3 T4 T5 T6
CLK
COMMAND READ NOP NOP NOP READ NOP NOP
X = 1 cycle
BANK, BANK,
ADDRESS COL n COL b
DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b
CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
COMMAND READ NOP NOP NOP READ NOP NOP NOP
X = 2 cycles
BANK, BANK,
ADDRESS COL n COL b
DOUT DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3 b
CAS Latency = 3
TRANSITIONING DATA DON’T CARE
Note: Each READ command may be to any bank. DQM is LOW.
Commands
Figure 13: Random READ Accesses
T0 T1 T2 T3 T4 T5
CLK
COMMAND READ READ READ READ NOP NOP
BANK, BANK, BANK, BANK,

ADDRESS COL n COL a COL x COL m
DOUT DOUT DOUT DOUT

DQ n a x m
CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6
CLK
COMMAND READ READ READ READ NOP NOP NOP

DOUT DOUT DOUT DOUT

DQ n a x m
CAS Latency = 3
Note: Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figures 14 and 15 on
page 27. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in,
then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
Commands
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 14
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 15 shows the case where the additional NOP is
needed.
Figure 14: READ-to-WRITE
T0 T1 T2 T3 T4
CLK
DQM
COMMAND READ NOP NOP NOP WRITE
BANK, BANK,
ADDRESS COL n COL b
tCK
tHZ
DQ DOUT n DIN b
tDS
Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of one is used, then DQM is not required.
Figure 15: READ-to-WRITE With Extra Clock Cycle
T0 T1 T2 T3 T4 T5
CLK
DQM
COMMAND READ NOP NOP NOP NOP WRITE
BANK, BANK,
ADDRESS COL n COL b
tHZ
DQ DOUT n DIN b
tDS
Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
Commands
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL -1. This is shown in Figure 16 for each
possible CL; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL = -1. This is shown in Figure 17 on page 29 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 16: READ-to-PRECHARGE
T0 T1 T2 T3 T4 T5 T6
CLK
COMMAND READ NOP NOP NOP PRECHARGE NOP NOP
X = 1 cycle
BANK,
ADDRESS COL n
DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3
CL = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
COMMAND READ NOP NOP NOP PRECHARGE NOP NOP NOP
X = 2 cycles
BANK,
ADDRESS COL n
DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3
CL = 3
Note: DQM is LOW.
Commands
Figure 17: Terminating a READ Burst
T0 T1 T2 T3 T4 T5 T6 T7
CLK
t RP
BURST
TERMINATE
NOP NOP ACTIVE
X = 1 cycle
BANK a, BANK BANK a,
ADDRESS COL n (a or all) ROW
DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3
CL = 2
T0 T1 T2 T3 T4 T5 T6 T7
CLK
t RP
BURST
TERMINATE
NOP NOP ACTIVE
X = 2 cycles
DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3
CL = 3
Note: DQM is LOW.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z, and any additional input
data will be ignored (see Figure 19 on page 30). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command.
Commands
An example is shown in Figure 20 on page 31. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a prefetch architecture. A WRITE
command can be initiated on any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be performed to the same bank, as
shown in Figure 21 on page 32, or each subsequent WRITE may be performed to a
different bank.
Figure 18: WRITE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A9: x4 COLUMN
A0–A8: x8 ADDRESS
A0–A7: x16
A11: x4
A9, A11: x8
A8, A9, A11: x16
A10
BA0, BA1 BANK

ADDRESS
VALID ADDRESS DON’T CARE
Figure 19: WRITE Burst
T0 T1 T2 T3
CLK
COMMAND WRITE NOP NOP NOP
BANK,
ADDRESS COL n
DIN DIN
DQ n n+1
Note: NOTE: BL = 2. DQM is LOW.
Commands
Figure 20: WRITE-to-WRITE
T0 T1 T2
CLK
COMMAND WRITE NOP WRITE
BANK, BANK,
ADDRESS COL n COL b
DIN DIN DIN

DQ n n+1 b
Note: DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a subsequent READ
command. After the READ command is registered, the data inputs will be ignored, and
writes will not be executed. An example is shown in Figure 22 on page 32. Data n + 1 is
either the last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency. In addition, when
truncating a WRITE burst, the DQM signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the PRECHARGE command. An
example is shown in Figure 23 on page 33. Data n + 1 is either the last of a burst of two or
the last desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Commands
Figure 21: Random WRITE Cycles
T0 T1 T2 T3
CLK
COMMAND WRITE WRITE WRITE WRITE

DIN DIN DIN DIN

DQ n a x m
Note: Each WRITE command may be to any bank. DQM is LOW.
Figure 22: WRITE-to-READ
T0 T1 T2 T3 T4 T5
CLK
COMMAND WRITE NOP READ NOP NOP NOP
BANK, BANK,
ADDRESS COL n COL b
DIN DIN DOUT DOUT

DQ n n+1 b b+1
Note: The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW. CL = 2 for illustration.
Commands
Figure 23: WRITE-to-PRECHARGE
T0 T1 T2 T3 T4 T5 T6
CLK
tWR @ tCLK ≥ 15ns
DQM
t RP
COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE NOP

t WR
DIN DIN
DQ n n+1
tWR = tCLK < 15ns
DQM
t RP
COMMAND WRITE NOP NOP PRECHARGE NOP NOP ACTIVE

t WR
DIN DIN
DQ n n+1
Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 24 on page 34, where data n is
the last desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (Figure 25 on page 34) is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Commands
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (tREF or tREFAT ) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 26 on page 35.
Figure 24: Terminating a WRITE Burst
T0 T1 T2
CLK
BURST NEXT
COMMAND WRITE
TERMINATE COMMAND
BANK, (ADDRESS)
ADDRESS COL n
DIN
DQ (DATA)
n
Note: DQMs are LOW.
Figure 25: PRECHARGE Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A9
All Banks
A10
Bank Selected
BA0,1 BANK
ADDRESS
VALID ADDRESS DON’T CARE
Commands
Figure 26: Power-Down
((
))
CLK ((
))
tCKS > tCKS
CKE ((
))
((
))
COMMAND NOP NOP ACTIVE
((
))
All banks idle tRCD
Input buffers gated off tRAS
tRC
Enter power-down mode. Exit power-down mode.
DON’T CARE
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figures 27 and 28 on page 36.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Commands
Figure 27: Clock Suspend During WRITE Burst
T0 T1 T2 T3 T4 T5
CLK
CKE
INTERNAL
CLOCK
COMMAND NOP WRITE NOP NOP
BANK,
ADDRESS COL n
DIN DIN DIN

DIN n n+1 n+2
Figure 28: Clock Suspend During READ Burst
T0 T1 T2 T3 T4 T5 T6
CLK
CKE
INTERNAL
CLOCK
COMMAND READ NOP NOP NOP NOP NOP
BANK,
ADDRESS COL n
DOUT DOUT DOUT DOUT

DQ n n+1 n+2 n+3
Note: For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
Concurrent Auto Precharge

An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
Commands
READ with Auto Precharge

• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 29 on page 37).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30 on page 38).
WRITE with Auto Precharge

• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31 on page 38).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 32 on page 39).
Figure 29: READ With Auto Precharge Interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
READ - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP
BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
Internal t RP - BANK n tRP - BANK m
States Page Active READ with Burst of 4 Precharge

BANK m
BANK n, BANK m,
ADDRESS COL a COL d
DOUT DOUT DOUT DOUT

DQ a a+1 d d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
Note: DQM is LOW.
Commands
Figure 30: READ With Auto Precharge Interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
READ - AP WRITE - AP
COMMAND BANK n
NOP NOP NOP
BANK m
NOP NOP NOP
Page
BANK n Active
READ with Burst of 4 Interrupt Burst, Precharge Idle
Internal tRP - BANK n t WR - BANK m
States Page Active WRITE with Burst of 4 Write-Back

BANK m
BANK n, BANK m,
ADDRESS COL a COL d
1
DQM
DOUT DIN DIN DIN DIN

DQ a d d+1 d+2 d+3
CAS Latency = 3 (BANK n)

Notes: 1. DQM is HIGH at T2 to prevent DOUT a +1 from contending with DIN d at T4.
Figure 31: WRITE With Auto Precharge Interrupted by a READ
T0 T1 T2 T3 T4 T5 T6 T7
CLK
WRITE - AP READ - AP
COMMAND NOP
BANK n
NOP
BANK m
NOP NOP NOP NOP
BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
tRP - BANK m
States Page Active READ with Burst of 4
BANK m
BANK n, BANK m,
ADDRESS COL a COL d
DIN DIN DOUT DOUT

DQ a a+1 d d+1
CAS Latency = 3 (BANK m)
Notes: 1. DQM is LOW.
Commands
Figure 32: WRITE With Auto Precharge Interrupted by a WRITE
T0 T1 T2 T3 T4 T5 T6 T7
CLK
WRITE - AP WRITE - AP
COMMAND NOP
BANK n
NOP NOP
BANK m
NOP NOP NOP
BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
tRP - BANK n
Internal tWR - BANK n
t WR - BANK m
States Page Active WRITE with Burst of 4 Write-Back
BANK m
BANK n, BANK m,
ADDRESS COL a COL d
DIN DIN DIN DIN DIN DIN DIN

DQ a a+1 a+2 d d+1 d+2 d+3
Notes: 1. DQM is LOW.
Table 8: Truth Table 2 – CKE

Notes 1–4 apply to entire table
CKEn-1 CKEn Current State COMMANDn ACTIONn Notes

L L Power-Down X Maintain power-down
Self refresh X Maintain self refresh
Clock suspend X Maintain clock suspend
L H Power-Down COMMAND INHIBIT or NOP Exit power-down 5
Self refresh COMMAND INHIBIT or NOP Exit self refresh 6
Clock suspend X Exit clock suspend 7
H L All banks idle COMMAND INHIBIT or NOP Power-Down entry
All banks idle AUTO REFRESH Self refresh entry
Reading or writing WRITE or NOP Clock suspend entry
H H See Table 9 on page 40
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
Commands
Table 9: Truth Table 3 – Current State Bank n, Command to Bank n

(Notes 1–6 apply to entire table; notes appear below and on next page)
Current State CS# RAS# CAS# WE# Command (Action) Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (Select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 11
Row active L H L H READ (Select column and start READ burst) 10
L H L L WRITE (Select column and start WRITE burst) 10
L L H L PRECHARGE (Deactivate row in bank or banks) 8
Read L H L H READ (Select column and start new READ burst) 10
(auto L H L L WRITE (Select column and start WRITE burst) 10
precharge L L H L 8
PRECHARGE (Truncate READ burst, start precharge)
disabled)
L H H L BURST TERMINATE 9
Write L H L H READ (Select column and start READ burst) 10
(auto L H L L WRITE (Select column and start new WRITE burst) 10
precharge L L H L 8
PRECHARGE (Truncate WRITE burst, start precharge)
disabled)
L H H L BURST TERMINATE 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 8 on page 39) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank,
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 9 and according to Table 10 on page 42.
Precharging: Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD
is met. After tRCD is met, the bank will be in the row active state.
Read w/auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Write w/auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRC is met. After tRC is met, the SDRAM will be in the all banks idle state.
Commands
Accessing mode Starts with registration of a LOAD MODE REGISTER command and ends
register: when tMRD has been met. After tMRD is met, the SDRAM will be in the all
banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. After tRP is met, all banks will be in the idle state.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
less of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
Commands
Table 10: Truth Table 4 – Current State Bank n, Command to Bank m

(Notes 1–6 apply to entire table; notes appear below and on next page)
Current State CS# RAS# CAS# WE# Command (Action) Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise allowed to bank m
Row L L H H ACTIVE (Select and activate row)
activating, L H L H READ (Select column and start READ burst) 7
active, or L H L L 7
WRITE (Select column and start WRITE burst)
precharging
L L H L PRECHARGE
Read L L H H ACTIVE (Select and activate row)
(auto L H L H READ (Select column and start new READ burst) 7, 10
precharge L H L L 7, 11
disabled)
L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(auto L H L H READ (Select column and start READ burst) 7, 12
precharge L H L L 7, 13
WRITE (Select column and start new WRITE burst)
disabled)
L L H L PRECHARGE 9
Read L L H H ACTIVE (Select and activate row)
(with auto L H L H READ (Select column and start new READ burst) 7, 8, 14
precharge) L H L L 7, 8, 15
L L H L PRECHARGE 9
Write L L H H ACTIVE (Select and activate row)
(with auto L H L H READ (Select column and start READ burst) 7, 8, 16
precharge) L H L L 7, 8, 17
WRITE (Select column and start new WRITE burst)
L L H L PRECHARGE 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 8 on page 39) and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Read w/auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write w/auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
Commands

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent Auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 12 on
page 25).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered
(Figures 14 and 15 on page 27). DQM should be used one clock prior to the WRITE com-
mand to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 22
on page 32), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 20 on page 31). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n
will begin when the READ to bank m is registered (Figure 29 on page 37).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The precharge to
bank n will begin when the WRITE to bank m is registered (Figure 30 on page 38).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins
when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m (Figure 31 on page 38).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is regis-
tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to
bank m (Figure 32 on page 39).
Electrical Specifications
Stresses greater than those listed in Table 11 may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 11: Absolute Maximum Ratings
Parameter Min Max Units

Voltage on VDD, VDDQ supply relative to VSS –1V +4.6 V
Voltage on inputs, NC or I/O pins relative to VSS –1V +4.6 V
Operating temperature °C
TA (commercial) 0 70
TA (industrial) –40 +85
TA (automotive) –40 +105
Storage temperature (plastic) –55 +150 °C
Power dissipation – 1 W
Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Figure 12
on page 45, be maintained to ensure the junction temperature is in the proper operating
range to meet data sheet specifications. An important step in maintaining the proper
junction temperature is using the device’s thermal impedances correctly. The thermal
impedances are listed in Table 13 on page 45 for the applicable die revision and pack-
ages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron tech-
nical note, TN-00-08, “Thermal Applications,” prior to using the thermal impedances
listed in Table 13. To ensure the compatibility of current and future designs, contact
Micron Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device's ambient temperature is
too high, use of forced air and/or heat sinks may be required to satisfy the case tempera-
ture specifications.
Table 12: Temperature Limits
Parameter Symbol Min Max Units Notes

Operating case temperature: TC °C 1, 2, 3, 4
Commercial 0 80
Industrial –40 90
Automotive –40 105
Junction temperature: TJ °C 3
Commercial 0 85
Industrial –40 95
Automotive –40 110
Ambient temperature: TA °C 3, 5
Commercial 0 70
Industrial -40 85
Automotive -40 105
Peak reflow temperature TPEAK – 260 °C
Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top
side of the device, as shown in Figure 33 and Figure 34 on page 46.
2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top center of
the component. This should be done with a 1mm bead of conductive epoxy, as defined by
the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is
touching the case.
5. Operating ambient temperature surrounding the package.
Table 13: Thermal Impedance Simulated Values
θ JA (°C/W) θ JA (°C/W) θ JA (°C/W)

Airflow = Airflow = Airflow =
Die Revision Package Substrate 0m/s 1m/s 2m/s θ JB (°C/W) θ JC (°C/W)
G 54-pin 4-layer 70.5 61.2 57.2 54.6 13.7
TSOP
54-ball 2-layer 80.6 67.7 61.5 46.1 4.9
VFBGA 4-layer 64 57.1 53.5 45.7
Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as
typical.
3. These are estimates; actual results may vary.
Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View
8.00mm
4.00mm
Test point
8.00mm
4.00mm
Table 14: DC Electrical Characteristics and Operating Conditions

Notes 1, 5, 6 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V
Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ 3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 22
Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22
Input leakage current: II –5 5 µA
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
Output leakage current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ IOZ –5 5 µA
Output levels:
Output high voltage (Iout = –4mA) VOH 2.4 – V
Output low voltage (Iout = 4mA) VOL – 0.4 V
Table 15: IDD Specifications and Conditions

Notes 1, 5, 6 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V
Max
Parameter/Condition Symbol -6 -7E -75 Units Notes
Operating current: active mode; IDD1 150 125 115 mA 3, 18, 19,
Burst = 2; READ or WRITE; tRC ≥ tRC (MIN) 32
Standby current: Power-down mode; IDD2 2 2 2 mA 32
All banks idle; CKE = LOW
Standby current: Active mode; IDD3 60 45 45 mA 3, 12, 19,
CKE = HIGH; CS# = HIGH; All banks active after tRCD met; 32
No accesses in progress
Operating current: Burst mode; IDD4 180 150 140 mA 3, 18, 19,
Page burst; READ or WRITE; All banks active 32
Auto refresh current: tRFC = tRFC (MIN) IDD5 250 230 210 mA 3, 12, 18,
CKE = HIGH; CS# = HIGH tRFC = 15.625µs IDD6 3 3 3 19, 32, 33
tRFC = 3.906µs (AT) IDD6 6 6 6
Self refresh current: Standard IDD7 1 1 1 mA 4
CKE ≤ 0.2V Low power (L) 0.5 0.5 0.5
Table 16: TSOP Capacitance

Note 2 applies to entire table; notes appear on pages 50 and 51

Input capacitance: CLK CI1 2.5 3.5 pF 29
Input capacitance: All other input-only pins CI2 2.5 3.8 pF 30
Input/output capacitance: DQs CIO 4.0 6.0 pF 31
Table 17: VFBGA Capacitance

Note 2 applies to entire table; notes appear on pages 50 and 51

Input capacitance: CLK CI1 TBD TBD pF 29
Input capacitance: All other input-only pins CI2 TBD TBD pF 30
Input/output capacitance: DQs CIO TBD TBD pF 31
Table 18: Electrical Characteristics and Recommended AC Operating Conditions

Notes 5, 6, 8, 9, 11, 34 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V
AC Characteristics -6 -7E -75

Parameter Symbol Min Max Min Max Min Max Units Notes
t
Access time from CLK CL = 3 AC(3) – 5.5 – 5.4 5.4 ns 27
(positive edge) tAC(2) – – – 5.4 – 6 ns
CL = 2
t
Address hold time AH 1 – 0.8 – 0.8 – ns
t
Address setup time AS 1.5 – 1.5 – 1.5 – ns
tCH 2.5 – 2.5 – 2.5 – ns
CLK high-level width
t
CLK low-level width CL 2.5 – 2.5 – 2.5 – ns
tCK(3) 6 – 7 – 7.5 – ns 23
Clock cycle time CL = 3
t
CL = 2 CK(2) – – 7.5 – 10 – ns 23
tCKH
CKE hold time 1 – 0.8 – 0.8 – ns
tCKS 1.5 – 1.5 – 1.5 – ns
CKE setup time
tCMH
CS#, RAS#, CAS#, WE#, DQM hold 1 – 0.8 – 0.8 – ns
time
tCMS 1.5 – 1.5 – 1.5 – ns
CS#, RAS#, CAS#, WE#, DQM setup
time
tDH 1 – 0.8 – 0.8 – ns
Data-in hold time
tDS
Data-in setup time 1.5 – 1.5 – 1.5 – ns
tHZ(3)
Data-out High-Z time CL = 3 – 5.5 – 5.4 – 5.4 ns 10
tHZ(2)
CL = 2 – – – 5.4 – 6 ns 10
tLZ 1 – 1 – 1 – ns
Data-out Low-Z time
tOH 2 – 3 – 3 – ns
Data-out hold time (load)
tOHN
Data-out hold time (no load) 1.8 – 1.8 – 1.8 – ns 28
tRAS
ACTIVE-to-PRECHARGE command 42 120,000 37 120,000 44 120,000 ns
tRC
ACTIVE-to-ACTIVE command period 60 – 60 – 66 – ns
tRCD 18 – 15 – 20 – ns
ACTIVE-to-READ or WRITE delay
tREF – 64 – 64 – 64 ms
Refresh period (4,096 rows)
tREF
Refresh period–Automotive AT – 16 – 16 – 16 ms
(4,096 rows)
tRFC 60 – 66 – 66 – ns
AUTO REFRESH period
tRP 18 – 15 – 20 – ns
PRECHARGE command period
t
ACTIVE bank a to ACTIVE bank b RRD 12 – 14 – 15 – ns
command
tT
Transition time 0.3 1.2 0.3 1.2 0.3 1.2 ns 7
tWR 1 CLK – 1 CLK – 1 CLK – – 24
WRITE recovery time
+ 6ns + 7ns + 7.5ns
12 – 14 – 15 – ns 25
tXSR 70 – 67 – 75 – ns 20
Exit SELF REFRESH-to-ACTIVE
command
Table 19: AC Functional Characteristics

Notes 5, 6, 8, 9, 11, 34 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V
Parameter Symbol -6 -7E -75 Units Notes

t t
READ/WRITE command to READ/WRITE command CCD 1 1 1 CK 17
t t
CKE to clock disable or power-down entry mode CKED 1 1 1 CK 14
t t
CKE to clock enable or power-down exit setup mode PED 1 1 1 CK 14
t t
DQM to input data delay DQD 0 0 0 CK 17
tDQM 0 0 0 tCK 17
DQM to data mask during WRITEs
t t
DQM to data High-Z during READs DQZ 2 2 2 CK 17
t t
WRITE command to input data delay DWD 0 0 0 CK 17
t t
Data-in to ACTIVE command DAL 5 4 5 CK 15, 21
t t
Data-in to precharge command DPL 2 2 2 CK 16, 21
tBDL 1 1 1 t
Last data-in to burst stop command CK 17
t t
Last data-in to new READ/WRITE command CDL 1 1 1 CK 17
tRDL 2 2 2 tCK 16, 21
Last data-in to precharge command
tMRD 2 2 2 tCK 26
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
CL = 3 tROH(3) 3 3 3 tCK 17
Data-out to High-Z from precharge command
CL = 2 tROH(2) tCK
– 2 2 17
Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test
biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA
≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive) is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. C timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1 ns, then the timing is ref-
erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. CLK
should always be 1.5V referenced to crossover. Refer to Micron technical note
TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and -7E, tCK = 6ns for -6.
Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns/7ns/7.5ns/
7ns after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns; for -6, CL = 3 and
t
CK = 6ns.
33. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
34. The -6 speed grade does not support CL = 2.
Timing Diagrams
Timing Diagrams
Figure 35: Initialize and Load Mode Register
T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
tCK (( (( tCL ((
CLK )) )) ))
(( (( tCH (( ((
)) )) )) ))
tCKS tCKH
(( (( (( ((
)) )) )) ))
CKE
(( ((
)) ))
tCMS tCMH tCMS tCMH tCMS tCMH
(( (( (( ((
)) )) AUTO )) AUTO )) LOAD MODE
COMMAND NOP PRECHARGE NOP NOP NOP NOP NOP ACTIVE
(( (( REFRESH (( REFRESH (( REGISTER
)) )) )) ))
(( (( (( ((
)) )) )) ))
DQM / ((
(( (( ((
DQML, DQMH )) )) )) ))
tAS tAH
(( (( (( ((
)) )) )) ))
A0–A9, A11 (( (( CODE ROW
(( ((
)) )) )) ))
tAS tAH
(( ALL BANKS (( (( ((
)) )) )) ))
A10 (( (( CODE ROW
(( ((
)) )) )) ))
SINGLE BANK
(( (( (( ((
)) ALL )) )) ))
BA0, BA1 (( BANK
(( BANKS (( ((
)) )) )) ))
(( High-Z ((
DQ
)) ))
T = 100µs
tRP tRFC tRFC tMRD
MIN
Power-up:
VDD and Precharge AUTO REFRESH AUTO REFRESH Program Mode Register 2, 3, 4
CLK stable all banks
DON’T CARE
Notes: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
Timing Diagrams
Figure 36: Power-Down Mode
T0 T1 T2 ((
Tn + 1 Tn + 2
tCK tCL ))
CLK
tCH ((
))
tCKS tCKS
CKE ((
))
tCKS tCKH
tCMS tCMH
((
))
COMMAND PRECHARGE NOP NOP NOP ACTIVE
((
))
((
DQM / ))
DQML, DQMH ((
))
((
))
A0–A9, A11 ROW
((
))
ALL BANKS ((
))
A10 ROW
((
SINGLE BANK ))
tAS tAH
((
))
BA0, BA1 BANK(S) BANK
((
))
High-Z
((
DQ ))
Two clock cycles Input buffers gated off while in
power-down mode
Precharge all All banks idle, enter All banks idle
active banks power-down mode Exit power-down mode
DON’T CARE
Notes: 1. Violating refresh requirements during power-down may result in a loss of data.
Timing Diagrams
Figure 37: Clock Suspend Mode
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCKS tCKH
tCMS tCMH
COMMAND READ NOP NOP NOP NOP NOP WRITE NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 COLUMN m 2 COLUMN e 2
tAS tAH
A10
tAS tAH
BA0, BA1 BANK BANK
tAC
AC tOH tHZ tDS tDH
DQ tLZ
DOUT m DOUT m + 1 DIN e DIN e + 1
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
Timing Diagrams
Figure 38: Auto Refresh Mode
T0 T1 T2 Tn + 1 To + 1
(( tCL ((
CLK )) ))
tCK tCH (( ((
)) ))
(( ((
)) ))
CKE
tCKS tCKH
tCMS tCMH
(( ((
AUTO )) AUTO ))
COMMAND PRECHARGE NOP NOP
REFRESH ( ( NOP REFRESH
NOP
( ( NOP ACTIVE
)) ))
(( ((
DQM / )) ))
DQML, DQMH (( ((
)) ))
(( ((
)) ))
A0–A9, A11 ROW
(( ((
)) ))
ALL BANKS (( ((
)) ))
A10 ROW
(( ((
SINGLE BANK )) ))
tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) BANK
(( ((
)) ))
DQ High-Z (( ((
)) ))
tRP tRFC1 tRFC1
Precharge all
DON’T CARE
active banks
Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not
required.
Timing Diagrams
Figure 39: Self Refresh Mode
T0 T1 T2 ((
Tn + 1 ((
To + 1 To + 2
tCL )) ))
CLK
tCK tCH (( ((
)) ))
tCKS
≥ tRAS(MIN)1
((
))
CKE (( ((
)) ))
tCKS tCKH
tCMS tCMH
(( ((
AUTO )) ) ) or COMMAND AUTO
COMMAND PRECHARGE NOP NOP ( (
REFRESH (( INHIBIT REFRESH
)) ))
(( ((
DQM/ )) ))
DQML, DQMH (( ((
)) ))
(( ((
)) ))
A0–A9, A11
(( ((
)) ))
ALL BANKS (( ((
)) ))
A10
(( ((
SINGLE BANK )) ))
tAS tAH
(( ((
)) ))
BA0, BA1 BANK(S) (( ((
)) ))
High-Z (( ((
DQ )) ))
tRP tXSR2
Precharge all Enter self refresh mode Exit self refresh mode
active banks
(Restart refresh time base)
CLK stable prior to exiting DON’T CARE
self refresh mode
Notes: 1. No maximum time limit for self refresh mode. tRAS(MAX) applies to non-self refresh mode.
2. tXSR
requires minimum of two clocks regardless of frequency and timing.
3. Self refresh mode not supported on automotive temperature (AT) devices.
Timing Diagrams
Figure 40: READ – Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m2 ROW
tAS tAH
ALL BANKS
A10 ROW ROW
tAS tAH DISABLE AUTO PRECHARGE SINGLE BANKS
BA0, BA1 BANK BANK BANK(S) BANK
tAC tAC tAC

tAC tOH tOH tOH tOH
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3

tLZ
tHZ
tRCD CAS Latency tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual”
PRECHARGE.
Timing Diagrams
Figure 41: READ – With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
tAS tAH ENABLE AUTO PRECHARGE
A10 ROW ROW
tAS tAH
BA0, BA1 BANK BANK BANK
tAC tAC tAC

tAC tOH tOH tOH tOH
DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3

tLZ
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 4, and CL = 2.

Timing Diagrams
Figure 42: Single READ – Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP3 PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
tAS tAH
ALL BANKS
A10 ROW ROW
tAS tAH DISABLE AUTO PRECHARGE SINGLE BANKS
BA0, BA1 BANK BANK BANK(S) BANK
tAC tOH
DQ DOUT m
tLZ
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual”
PRECHARGE.
3. PRECHARGE command not allowed or tRAS would be violated.
Timing Diagrams
Figure 43: Single READ – With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP NOP2 NOP2 READ NOP NOP ACTIVE NOP
tCMS tCMH
DQM /
DQML, DQMU
tAS tAH
tAS tAH ENABLE AUTO PRECHARGE
A10 ROW ROW
tAS tAH
tAC
t OH
DQ DOUT m
tRCD CAS Latency tHZ
tRAS tRP
tRC
DON’T CARE
UNDEFINED

2. READ command not allowed or tRAS would be violated.
Timing Diagrams
Figure 44: Alternating Bank Read Accesses
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP ACTIVE NOP READ NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m 2 ROW COLUMN b 2 ROW
tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
A10 ROW ROW ROW
tAS tAH
BA0, BA1 BANK 0 BANK 0 BANK 3 BANK 3 BANK 0
tAC tAC tAC tAC tAC

tAC tOH tOH tOH tOH tOH
DQ DOUT m DOUT m + 1 DOUT m + 2 DOUT m + 3 DOUT b

tLZ
tRCD - BANK 0 CAS Latency - BANK 0 tRP - BANK 0 tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 3 CAS Latency - BANK 3
DON’T CARE
UNDEFINED

Timing Diagrams
Figure 45: READ – Full-Page Burst
T0 T1 T2 T3 T4 T5 T6 ((
Tn + 1 Tn + 2 Tn + 3 Tn + 4
tCL tCK ))
CLK
tCH ((
))
tCKS tCKH
((
CKE ))
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP
((
))
tCMS tCMH
((
DQM / ))
DQML, DQMH ((
))
tAS tAH
((
))
A0–A9, A11 ROW COLUMN m 2 ((
))
tAS tAH
((
))
A10 ROW ((
))
tAS tAH
((
))
BA0, BA1 BANK BANK
((
))
tAC tAC tAC ( ( tAC tAC

tAC tOH tOH tOH ) ) tOH tOH tOH
((
))
DQ DOUT m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m DOUT m+1
((
tLZ ))
tHZ
256 (x16) locations within same row
512 (x8) locations within same row
tRCD CAS Latency 1,024 (x4) locations within same row
Full page completed

DON’T CARE
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command. UNDEFINED
Notes: 1. For this example, CL = 2.

3. Page left open; no tRP.
Timing Diagrams
Figure 46: READ – DQM Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0-A9, A11 ROW COLUMN m 2

tAS tAH
A10 ROW
tAS tAH
BA0, BA1 BANK BANK
tAC
tAC tOH tAC tOH tOH
DQ DOUT m DOUT m + 2 DOUT m + 3

tLZ
tHZ tLZ tHZ
tRCD CAS Latency
DON’T CARE
UNDEFINED

Timing Diagrams
Figure 47: WRITE – Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0-A9, A11 ROW COLUMN m 3 ROW
tAS tAH
ALL BANKS
A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH
BA0, BA1 BANK BANK BANK BANK
tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD t WR 2 tRP
tRAS
tRC
DON’T CARE
Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of
frequency.
Timing Diagrams
Figure 48: WRITE – With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m 2 ROW
tAS tAH
A10 ROW ROW
tAS tAH
tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3

tRCD tWR tRP
tRAS
tRC
DON’T CARE
Notes: 1. For this example, BL = 4.

Timing Diagrams
Figure 49: Single WRITE – Without Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP4 NOP4 PRECHARGE NOP ACTIVE NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m3
tAS tAH
ALL BANKS
A10 ROW ROW

DISABLE AUTO PRECHARGE SINGLE BANK
tAS tAH
BA0, BA1 BANK BANK BANK BANK
tDS tDH
DQ DIN m
tRCD t WR 2 tRP
tRAS
tRC
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of
frequency.
4. PRECHARGE command not allowed or tRAS would be violated.
Timing Diagrams
Figure 50: Single WRITE – With Auto Precharge
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP3 NOP3 NOP3 WRITE NOP NOP NOP ACTIVE NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
tAS tAH
A10 ROW ROW
tAS tAH
tDS tDH
DQ DIN m
tRCD tWR tRP
tRAS
tRC
DON’T CARE

3. WRITE command not allowed or tRAS would be violated.
Timing Diagrams
Figure 51: Alternating Write Accesses
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m 2 ROW COLUMN b 2 ROW
tAS tAH ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
A10 ROW ROW ROW
tAS tAH
BA0, BA1 BANK 0 BANK 0 BANK 1 BANK 1 BANK 0
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3 DIN b DIN b + 1 DIN b + 2 DIN b + 3

tRCD - BANK 0 tWR - BANK 0 tRP - BANK 0 tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD tRCD - BANK 1 tWR - BANK 1
DON’T CARE

Timing Diagrams
Figure 52: WRITE – Full-Page Burst
T0 T1 T2 T3 T4 T5 ((
Tn + 1 Tn + 2 Tn + 3
tCL tCK ))
CLK
tCH ((
))
tCKS tCKH
((
))
CKE
((
))
tCMS tCMH
((
))
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP BURST TERM NOP
((
))
tCMS tCMH
((
DQM / ))
DQML, DQMH ((
))
tAS tAH
((
))
A0–A9, A11 ROW COLUMN m1
((
))
tAS tAH
((
))
A10 ROW ((
))
tAS tAH
((
))
BA0, BA1 BANK BANK
((
))
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
((
))
DQ DIN m DIN m + 1 DIN m + 2 DIN m + 3(( DIN m - 1
))
tRCD
Full-page burst does
256 (x16) locations within same row not self-terminate. Can
512 (x8) locations within same row use BURST TERMINATE
1,024 (x4) locations within same row command to stop.2, 3
Full page completed

DON’T CARE
Notes: 1. x16: A8, A9 and A11 = “Don’t Care”

2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
Timing Diagrams
Figure 53: WRITE – DQM Operation
T0 T1 T2 T3 T4 T5 T6 T7
tCK tCL
CLK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS tAH
A0–A9, A11 ROW COLUMN m 2

tAS tAH
A10 ROW
tAS tAH DISABLE AUTO PRECHARGE
BA0, BA1 BANK BANK
tDS tDH tDS tDH tDS tDH
DQ DIN m DIN m + 2 DIN m + 3
tRCD
DON’T CARE

Package Dimensions
Package Dimensions
Figure 54: 54-Pin Plastic TSOP II (400 mil)
0.10
1.2 MAX
0.375 ±0.075 TYP

PIN #1 ID
0.80 TYP
(FOR REFERENCE
22.22 ±.08 ONLY)
2X R 0.75
2X R 1.00
2X 0.71
PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
PACKAGE WIDTH AND LENGTH DO NOT
INCLUDE MOLD PROTRUSION. ALLOWABLE
2X 0.10 PROTRUSION IS 0.25 PER SIDE.
2.80 GAGE PLANE

10.16 ±0.08
0.25
11.76 ±0.20 +0.10
0.10
-0.05
SEE DETAIL A
+0.03
0.15
-0.02
0.50 ±0.10
0.80
DETAIL A
Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
Package Dimensions
Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm
0.65 ±0.05
SEATING PLANE
C SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2% Ag OR
0.10 C 96.5% Sn, 3% Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS:
54X Ø0.45 ±0.05 Ø0.40
SOLDER BALL SUBSTRATE MATERIAL: PLASTIC LAMINATE
6.40
DIAMETER REFERS MOLD COMPOUND: EPOXY NOVOLAC
TO POST REFLOW 0.80
TYP BALL A1 ID
CONDITION. THE PRE- BALL A1 ID
REFLOW DIAMETER
IS 0.42.
BALL A9 BALL A1
4.00 ±0.05
6.40 CL
8.00 ±0.10
3.20 0.80 TYP
CL
3.20 4.00 ±0.05

1.00 MAX
8.00 ±0.10
Notes: 1. All dimensions in millimeters.

2. Recommended pad = Ø 0.40mm SMD.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
MX25L6445E
MX25L6445E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1736 REV. 1.8, DEC. 26, 2011

1
MX25L6445E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Features ............................................................................................................................... 7
PIN CONFIGURATION................................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM........................................................................................................................................................ 9
DATA PROTECTION................................................................................................................................................... 10
Table 2. Protected Area Sizes........................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................. 11
Memory Organization................................................................................................................................................ 12
Table 4. Memory Organization.......................................................................................................................... 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)......................................................................... 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)........................................... 13
COMMAND DESCRIPTION........................................................................................................................................ 14
Table 5. Command Sets.................................................................................................................................... 14
(1) Write Enable (WREN).................................................................................................................................. 16
(2) Write Disable (WRDI)................................................................................................................................... 16
(3) Read Identification (RDID)........................................................................................................................... 16
(4) Read Status Register (RDSR)..................................................................................................................... 17
(5) Write Status Register (WRSR)..................................................................................................................... 18
Protection Modes.............................................................................................................................................. 18
(6) Read Data Bytes (READ)............................................................................................................................ 19
(7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 19
(8) Fast Double Transfer Rate Read (FASTDTRD)........................................................................................... 19
(9) 2 x I/O Read Mode (2READ)....................................................................................................................... 19
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD).................................................................................. 20
(11) 4 x I/O Read Mode (4READ)...................................................................................................................... 20
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD).................................................................................. 21
(13) Sector Erase (SE)...................................................................................................................................... 21
(14) Block Erase (BE)....................................................................................................................................... 22
(15) Block Erase (BE32K)................................................................................................................................. 22
(16) Chip Erase (CE)......................................................................................................................................... 22
(17) Page Program (PP)................................................................................................................................... 23
(18) 4 x I/O Page Program (4PP)...................................................................................................................... 23
Program/Erase Flow(1) with read array data.................................................................................................... 24
Program/Erase Flow(2) without read array data............................................................................................... 25
(19) Continuously program mode (CP mode)................................................................................................... 26
(20) Deep Power-down (DP)............................................................................................................................. 27
(21) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 27
(22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)........................ 27
Table 6. ID Definitions ...................................................................................................................................... 28
(23) Enter Secured OTP (ENSO)...................................................................................................................... 28
(24) Exit Secured OTP (EXSO)......................................................................................................................... 28
P/N: PM1736 REV. 1.8, DEC. 26, 2011

2
MX25L6445E
(25) Read Security Register (RDSCUR)........................................................................................................... 28

Security Register Definition............................................................................................................................... 29
(26) Write Security Register (WRSCUR)........................................................................................................... 29
(27) Write Protection Selection (WPSEL).......................................................................................................... 30
BP and SRWD if WPSEL=0.............................................................................................................................. 30
The individual block lock mode is effective after setting WPSEL=1.................................................................. 31
WPSEL Flow..................................................................................................................................................... 32
(28) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 33
Block Lock Flow................................................................................................................................................ 33
Block Unlock Flow............................................................................................................................................. 34
(29) Read Block Lock Status (RDBLOCK)........................................................................................................ 35
(30) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 35
(31) Clear SR Fail Flags (CLSR)....................................................................................................................... 35
(32) Enable SO to Output RY/BY# (ESRY)....................................................................................................... 35
(33) Disable SO to Output RY/BY# (DSRY)...................................................................................................... 35
(34) Read SFDP Mode (RDSFDP).................................................................................................................... 36
POWER-ON STATE.................................................................................................................................................... 42
ELECTRICAL SPECIFICATIONS............................................................................................................................... 43
ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 43
Figure 2. Maximum Negative Overshoot Waveform......................................................................................... 43
CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................ 43
Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 43
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 44
Figure 5. OUTPUT LOADING.......................................................................................................................... 44
Table 10. DC CHARACTERISTICS ................................................................................................................. 45
Table 11. AC CHARACTERISTICS................................................................................................................... 46
Timing Analysis......................................................................................................................................................... 48
Figure 6. Serial Input Timing............................................................................................................................. 48
Figure 7. Output Timing..................................................................................................................................... 48
Figure 8. Serial Input Timing for Double Transfer Rate Mode........................................................................... 49
Figure 9. Serial Output Timing for Double Transfer Rate Mode........................................................................ 49
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1................................................ 50
Figure 11. Write Enable (WREN) Sequence (Command 06)............................................................................ 50
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................. 50
Figure 13. Read Identification (RDID) Sequence (Command 9F)..................................................................... 51
Figure 14. Read Status Register (RDSR) Sequence (Command 05)............................................................... 51
Figure 15. Write Status Register (WRSR) Sequence (Command 01).............................................................. 51
Figure 16. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 52
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 52
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D).................................................................. 52
Figure 19. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 53
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD).......................................................... 53
Figure 21. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 54
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 54
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)......................................................... 55
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED).................... 55
P/N: PM1736 REV. 1.8, DEC. 26, 2011

3
MX25L6445E
Figure 25. Sector Erase (SE) Sequence (Command 20)................................................................................. 56

Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)................................................................. 56
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 56
Figure 28. Page Program (PP) Sequence (Command 02).............................................................................. 57
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 57
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD).................. 58
Figure 31. Deep Power-down (DP) Sequence (Command B9)....................................................................... 58
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).
.......................................................................................................................................................................... 59
Figure 33. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 59
Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)...
.......................................................................................................................................................................... 60
Figure 35. Write Protection Selection (WPSEL) Sequence (Command 68)..................................................... 60
Figure 36. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)...................... 61
Figure 37. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................. 61
Figure 38. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)....................................... 61
Figure 39. Power-up Timing.............................................................................................................................. 62
Table 12. Power-Up Timing .............................................................................................................................. 62
INITIAL DELIVERY STATE............................................................................................................................... 62
OPERATING CONDITIONS........................................................................................................................................ 63
Figure 40. AC Timing at Device Power-Up........................................................................................................ 63
Figure 41. Power-Down Sequence................................................................................................................... 64
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 65
DATA RETENTION..................................................................................................................................................... 65
LATCH-UP CHARACTERISTICS............................................................................................................................... 65
ORDERING INFORMATION....................................................................................................................................... 66
PART NAME DESCRIPTION...................................................................................................................................... 67
PACKAGE INFORMATION......................................................................................................................................... 68
REVISION HISTORY ................................................................................................................................................. 71
P/N: PM1736 REV. 1.8, DEC. 26, 2011

4
MX25L6445E
64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/
O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- Fast read (Double Transfer Rate Mode)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) /chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 50uA (max.)
- Deep power down current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
P/N: PM1736 REV. 1.8, DEC. 26, 2011

5
MX25L6445E
• Advanced Security Features

- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
- Additional 4K bits secured OTP for unique identifier
• Auto Erase and Auto Program Algorithms
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state first.)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- REMS, REMS2, REMS4 and REMS4D commands for 1-byte Manufacturer ID and 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• NC/SIO3
- NC pin or serial data Input/Output for 4 x I/O mode
• PACKAGE
- 16-pin SOP (300mil)
- 8-WSON (8 x 6mm)
- 8-pin SOP (200mil)
- All devices are RoHS Compliant
P/N: PM1736 REV. 1.8, DEC. 26, 2011

6
MX25L6445E
GENERAL DESCRIPTION
MX25L6445E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. The MX25L6445E features
a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is ena-
bled by CS# input.
MX25L6445E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the per-
formance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L6445E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Continuously Program mode and erase command are executed on 4K-byte sector, 32K-
byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L6445E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Additional Protection and Security Read Performance

Features
Flexible or
1 I/O DT 2 I/O DT 4 I/O DT
Part Individual block 4K-bit 1 I/O Read 2 I/O Read 4 I/O Read
Read Read Read
Name (or sector) secured OTP (104 MHz) (70 MHz) (70 MHz)
(50 MHz) (50 MHz) (50 MHz)
protection
MX25L6445E V V V V V V V V
Additional
Identifier
Features
RES REMS REMS2 REMS4 REMS4D RDID
Part (command: AB (command: 90 (command: EF (command: DF (command: CF (command: 9F
Name hex) hex) hex) hex) hex) hex)
MX25L6445E 16 (hex) C2 16 (hex) C2 16 (hex) C2 16 (hex) C2 16 (hex) C2 20 17 (hex)
P/N: PM1736 REV. 1.8, DEC. 26, 2011

7
MX25L6445E
PIN CONFIGURATION PIN DESCRIPTION

16-PIN SOP (300mil) SYMBOL DESCRIPTION
NC/SIO3 1 16 SCLK
CS# Chip Select
VCC 2 15 SI/SIO0 Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0
NC 3 14 NC
Input & Output (for 2xI/O or 4xI/O mode)
NC 4 13 NC
NC 5 12 NC Serial Data Output (for 1xI/O)/Serial
NC 6 11 NC SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O
CS# 7 10 GND
SO/SIO1 8 9 WP#/SIO2
mode)
SCLK Clock Input
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
8-PIN SOP (200mil)
mode)
NC pin (Not connect) or Serial Data
CS# 1 VCC NC/SIO3
8 Input & Output (for 4xI/O mode)
SO/SIO1 2 7 NC/SIO3
WP#/SIO2 3 6 SCLK
VCC + 3.3V Power Supply
GND 4 5 SI/SIO0 GND Ground
NC No Connection
8-WSON (8x6mm)
CS# 1 8 VCC
SO/SIO1 2 7 NC/SIO3
WP#/SIO2 3 6 SCLK
GND 4 5 SI/SIO0
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MX25L6445E
BLOCK DIAGRAM
Address
X-Decoder
Generator
Memory Array
Page Buffer
Data
SI/SIO0 Register Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2 Mode State HV
NC/SIO3 Logic Machine Generator
SCLK Clock Generator
Output
SO/SIO1
Buffer
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MX25L6445E
DATA PROTECTION
MX25L6445E is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is-
suing other commands to change data. The WEL bit will return to reset stage under following situations:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection

- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-
ed Area Sizes".

- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD
bit. If the system goes into four I/O mode, the feature of HPM will be disabled.

- MX25L6445E provides individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
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MX25L6445E
Table 2. Protected Area Sizes

Status bit Protection Area
BP3 BP2 BP1 BP0 64Mb
0 0 0 0 0 (none)
0 0 0 1 1 (2 blocks, block 126th-127th)
0 1 0 0 4 (16 blocks, block 112nd-127th)
0 1 1 1 7 (128 blocks, all)
1 0 0 0 8 (128 blocks, all)
1 0 0 1 9 (128 blocks, all)
1 0 1 0 10 (128 blocks, all)
1 0 1 1 11 (128 blocks, all)
1 1 0 0 12 (128 blocks, all)
1 1 0 1 13 (128 blocks, all)
1 1 1 0 14 (128 blocks, all)
1 1 1 1 15 (128 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range Size Standard Factory Lock Customer Lock

xxx000~xxx00F 128-bit ESN (electrical serial number)
Determined by customer
xxx010~xxx1FF 3968-bit N/A
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MX25L6445E
Memory Organization
Table 4. Memory Organization
Block(64K-byte) Block(32K-byte) Sector (4K-byte) Address Range

2047 7FF000h 7FFFFFh
…
255
2040 7F8000h 7F8FFFh individual 16 sectors
127
2039 7F7000h 7F7FFFh lock/unlock unit:4K-byte
254
…
2032 7F0000h 7F0FFFh
2031 7EF000h 7EFFFFh
253
…
2024 7E8000h 7E8FFFh
126
2023 7E7000h 7E7FFFh
252
…
individual block 2016 7E0000h 7E0FFFh
lock/unlock unit:64K-byte
2015 7DF000h 7DFFFFh
251
…
2008 7D8000h 7D8FFFh

125
2007 7D7000h 7D7FFFh
250
…
2000 7D0000h 7D0FFFh
individual block
47 02F000h 02FFFFh
5
…
2 40 028000h 028FFFh
39 027000h 027FFFh
4
…
individual block 32 020000h 020FFFh

31 01F000h 01FFFFh
3
…
24 018000h 018FFFh
1
23 017000h 017FFFh
2
…
16 010000h 010FFFh
15 00F000h 00FFFFh
1
…
8 008000h 008FFFh individual 16 sectors

0 7 007000h 007FFFh lock/unlock unit:4K-byte
0
…
0 000000h 000FFFh
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MX25L6445E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-
tion.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock (SCLK) and
data is shifted out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure
1-1. For high performance (Double Transfer Rate Read serial mode), data is latched on both rising and falling
edge of clock and data shifts out on both rising and falling edge of clock as Figure 1-2.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, 4READ, FAST-
DTRD, 2DTRD, 4DTRD, RDBLOCK, RES, REMS, REMS2, REMS4, and REMS4D the shifted-in instruction se-
quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK,
SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglect-
ed and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1-1. Serial Modes Supported (for Normal Serial mode)

CPOL CPHA shift in shift out
(Serial mode 0) 0 0 SCLK
SI MSB
SO MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode)
data data data data
CPOL CPHA
in in out out
SI MSB
SO
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MX25L6445E
COMMAND DESCRIPTION
Table 5. Command Sets
RDSR WRSR FASTDTRD 4DTRD
COMMAND WREN (write WRDI (write RDID (read 2DTRD (Dual
(read status (write status (fast DT (Quad I/O DT
(byte) enable) disable) identification) I/O DT Read)
register) register) read) Read)
Command
06 04 9F 05 01 0D BD ED
(hex)
Input
Data(8) ADD(12) ADD(6) ADD(3)
Cycles
Dummy
6 6 1+7
Cycles
sets the resets the outputs to read out to write new n bytes read n bytes read n bytes read
(WEL) write (WEL) write JEDEC the values values to out (Double out (Double out (Double
enable latch enable latch ID: 1-byte of the status the status Transfer Transfer Transfer
Action bit bit Manufacturer register register Rate) until Rate) by 2xI/ Rate) by 4xI/
ID & 2-byte CS# goes O until CS# O until CS#
Device ID high goes high goes high
2READ (2
FAST READ 4READ (4 4PP (quad
COMMAND READ (read RDSFDP x I/O read SE (sector BE (block
(fast read x I/O read page
(byte) data) (Read SFDP) command) erase) erase 64KB)
data) command) program)
Note1
Command
03 0B 5A BB EB 38 20 D8
(hex)
Input ADD(6)+
ADD(24) ADD(24) ADD(24) ADD(12) ADD(6) ADD(24) ADD(24)
Cycles Data(512)
Dummy
8 8 4 2+4
Cycles
n bytes read n bytes read Read SFDP n bytes read n bytes read quad input to erase the to erase the
out until CS# out until CS# mode out by 2 x I/ out by 4 x I/ to program selected selected
Action goes high goes high O until CS# O until CS# the selected sector 64KB block
goes high goes high page
CP RDP REMS (read

COMMAND BE 32K (block CE (chip PP (Page (Continuously DP (Deep (Release RES (read electronic
(byte) erase 32KB) erase) program) program power down) from deep electronic ID) manufacturer
mode) power down) & device ID)
Command
52 60 or C7 02 AD B9 AB AB 90
(hex)
Input ADD(24)+ ADD(24)+
ADD(24) ADD(24)
Cycles Data(2048) Data(16)
Dummy
24
Cycles
to erase the to erase to program continously enters deep release from to read out output the
selected whole chip the selected program power down deep power 1-byte Device Manufacturer
32KB block page whole chip, mode down mode ID ID & Device
Action the address is ID
automatically
increase
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MX25L6445E
REMS4D ESRY
REMS2 (read REMS4 (read ENSO (enter EXSO (exit RDSCUR WRSCUR
COMMAND (read ID for (enable SO
ID for 2x I/O ID for 4x I/O secured secured (read security (write security
(byte) 4x I/O DT to output RY/
mode) mode) OTP) OTP) register) register)
mode) BY#)
Command
EF DF CF B1 C1 2B 2F 70
(hex)
Input
ADD(24) ADD(24) ADD(24)
Cycles
Dummy
Cycles
output the output the output the to enter to exit the 4K- to read value to set the to enable SO
Manufacturer Manufact- Manufact- the 4K-bit bit Secured of security lock-down bit to output RY/
ID & Device urer ID & urer ID & Secured OTP OTP mode register as "1" (once BY# during
Action ID device ID Device ID mode lock-down, CP mode
cannot be
updated)
DSRY HPM (High

CLSR (Clear WPSEL (write SBLK (single SBULK RDBLOCK
COMMAND (disable SO Perform- GBLK (gang
SR Fail protection block lock) (single block (block protect
(byte) to output RY/ ance Enable block lock)
Flags) selection) *Note 2 unlock) read)
BY#) Mode)
Command
80 30 A3 68 36 39 3C 7E
(hex)
Input
ADD(24) ADD(24) ADD(24)
Cycles
Dummy
Cycles
to disable SO clear security Quad I/O to enter individual individual read whole chip
to output RY/ register bit 6 high Perform- and enable block (64K- block (64K- individual write protect
BY# during and bit 5 ance mode individal byte) or byte) or block or
CP mode block protect sector (4K- sector sector write
Action
mode byte) write (4K-byte) protect status
protect unprotect
COMMAND GBULK (gang

(byte) block unlock)
Command
98
(hex)
Input
Cycles
Dummy
Cycles
whole
chip
unprotect
Action
Notes:
1. It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden
mode.
2: In individual block write protection mode, all blocks/sectors are locked as defualt.
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MX25L6445E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device con-
tent, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to Figure 12)
The WEL bit is reset by following situations:

- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to Table 6)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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MX25L6445E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 14).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-
ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BP3 BP2 BP1 BP0
SRWD (status QE WEL WIP
(level of (level of (level of (level of
register write (Quad (write enable (write in
protected protected protected protected
protect) Enable) latch) progress bit)
block) block) block) block)
1= Quad 1=write 1=write
1=status
Enable enable operation
register write (note 1) (note 1) (note 1) (note 1)
0=not Quad 0=not write 0=not in write
disable
Enable enable operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
volatile bit volatile bit
bit bit bit bit bit bit
Note: see the Table 2 "Protected Area Size" in page 11.
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MX25L6445E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to Figure 15)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Mode Status register condition WP# and SRWD bit status Memory
Status register can be written
Software protection WP#=1 and SRWD bit=0, or The protected area
in (WEL bit is set to "1") and
mode(SPM) WP#=0 and SRWD bit=0, or cannot
the SRWD, BP0-BP3
WP#=1 and SRWD=1 be program or erase.
bits can be changed
The SRWD, BP0-BP3 of The protected area
Hardware protection
status register bits cannot be WP#=0, SRWD bit=1 cannot
mode (HPM)
changed be program or erase.
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):
Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
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MX25L6445E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. (Please refer to Fig-
ure 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte
address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (Please refer to Figure 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) Fast Double Transfer Rate Read (FASTDTRD)
The FASTDTRD instruction is for doubling reading data out, signals are triggered on both rising and falling edge of
clock. The address is latched on both rising and falling edge of SCLK, and data of each bit shifts out on both rising
and falling edge of SCLK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock, and 2-bit
data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock.
The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single FASTDTRD instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing FASTDTRD instruction is: CS# goes low → sending FASTDTRD instruction code (1bit
per clock) → 3-byte address on SI (2-bit per clock) → 6-dummy clocks (default) on SI → data out on SO (2-bit per
clock) → to end FASTDTRD operation can use CS# to high at any time during data out. (Please refer to Figure 18)
While Program/Erase/Write Status Register cycle is in progress, FASTDTRD instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(9) 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
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19
MX25L6445E
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-
terleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 2 x I/O Read Mode
Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD)
The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The ad-
dress (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on dual
I/O pins) shift out on both rising and falling edge of SCLK at a maximum frequency fT2. The 4-bit address can be
latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock,
the other two bits at falling edge of clock. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest ad-
dress has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as
4-bit instead of previous 1-bit.
The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks on SIO1 & SIO0 → data out inter-
leave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 20 for 2 x I/O Double Transfer Rate Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact
(11) 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol-
lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address in-
terleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 21 for 4 x I/O Read
Mode Timing Waveform).
Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4
READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
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MX25L6445E
P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4Read instruction) → 24-bit ran-
dom access address (Please refer to Figure 22 for 4x I/O Read Enhance Performance Mode timing waveform).
In the performance-enhancing mode (Notes of Figure. 22), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h,
5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer
toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance
mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)
The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on
both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,
and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall-
ing edge of clock. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruc-
tion, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24-
bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → 8 dummy clocks → data out interleave on
SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data
out (Please refer to Figure 23 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).
Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is: CS# goes
low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit
per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#
goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (Please refer to Figure
24 for 4x I/O Double Transfer Rate read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact
(13) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) in-
struction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-
in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (Please refer to Figure 25)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE
timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the
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sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(14) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block (see Table 4) is a valid address for Block
Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI
→ CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE tim-
ing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block
is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change)
and the WEL bit still be reset.
(15) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32). Any address of the block (see Table 4) is a valid address
for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on
SI → CS# goes high. (Please refer to Figure 26)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE tim-
ing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block
is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change)
and the WEL bit still be reset.
(16) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please
refer to Figure 27)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-
ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is
protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
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(17) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,
A7-A0 (the eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0)
are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address
of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the
last 256-byte is programmed at the requested page and previous data will be disregarded. If less than 256 bytes
are sent to the device, the data is programmed at the requested address of the page without effect on other address
of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→
at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 28)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP
timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If
the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(18) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,
and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less
than 20MHz. For system with faster clock, the Quad page program cannot provide more performance, because
the required internal page program time is far more than the time data flows in. Therefore, we suggest that while
executing this command (especially during sending data), user can slow the clock speed down to 20MHz below.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to Figure 29)
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
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MX25L6445E
The Program/Erase function instruction function flow is as follows:

Program/Erase Flow(1) with read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address

(Write erase address)
RDSR command
No
WIP=0?
Yes
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully Program/erase fail
CLSR(30h) command
Program/erase Yes
another block?
*
* Issue RDSR to check BP[3:0].
No
* If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
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Program/Erase Flow(2) without read array data
Start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address

(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSCUR command
Yes
P_FAIL/E_FAIL=1?
No
Program/erase successfully Program/erase fail
CLSR(30h) command
Program/erase Yes
another block?
* Issue RDSR to check BP[3:0].
No * If WPSEL=1, issue RDBLOCK to check the block status.
Program/erase completed
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(19) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unpro-
tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI
pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes
are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to
low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode
word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 30 of CP
mode timing waveform)
Two methods to detect the completion of a program cycle during CP mode:

1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
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(20) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby cur-
rent is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, the device is only in standby mode, not deep power-down mode. It's different from
Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please
refer to Figure 31)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(21) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#)
must remain High for at least tRES2(max), as specified in Table 11. Once in the standby mode, the device waits to
be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-
gram/erase/write cycles in progress. The sequence is shown as Figure 32, 33.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)
The REMS, REMS2, REMS4 and REMS4D instruction provides both the JEDEC assigned Manufacturer ID and the
specific Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "CFh", "DFh" or "EFh" fol-
lowed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and
the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 34.
The Device ID values are listed in table of ID Definitions. If the one-byte address is initially set to 01h, then the De-
vice ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
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Table 6. ID Definitions
Command Type MX25L6445E
manufacturer ID memory type memory density
RDID
C2 20 17
electronic ID
RES
16
manufacturer ID device ID
REMS/REMS2/REMS4/REMS4D
C2 16
(23) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While device is in 4K-bit Secured
OTP mode, main array access is not available. The additional 4K-bit Secured OTP is independent from main array,
and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updat-
ed again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not ac-

ceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands
are valid.
(24) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
(25) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Regis-
ter data out on SO→ CS# goes high.
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be updated any more.
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Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h).
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h).
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
Security Register Definition

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Continuously LDSO
Program (lock-down 4K-bit
WPSEL E_FAIL P_FAIL x x
mode 4K-bit Se- Secured OTP
(CP mode) cured OTP)
0 = not
0=normal 0=normal
0=normal lockdown 0=
Erase Program 0=normal
WP mode 1 = lock- nonfactory
succeed succeed Program
1=individual down lock
1=indicate 1=indicate mode reserved reserved
WP mode (cannot 1 = factory
Erase failed Program 1=CP mode
(default=0) program/ lock
(default=0) failed (default=0)
erase
(default=0)
OTP)
non-volatile non-volatile non-volatile
volatile bit volatile bit volatile bit volatile bit volatile bit
bit bit bit
OTP Read Only Read Only Read Only Read Only Read Only OTP Read Only
(26) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Se-
cured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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(27) Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the indi-
vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on the Security Register bit 7 is checked. If WPSEL=1, all the blocks
and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and
GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed.
BP protection mode, WPSEL=0:

ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:

Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, bit 7 in
the security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-
ods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function flow is as follows:
BP and SRWD if WPSEL=0
WP# pin
BP3 BP2 BP1 BP0 SRWD
64KB
64KB (1) BP3~BP0 is used to define the protection group region.

(The protected area size see Table 2)
(2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this

64KB
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
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The individual block lock mode is effective after setting WPSEL=1
4KB SRAM • Power-Up: All SRAM bits=1 (all blocks are default protected).
4KB SRAM All array cannot be programmed/erased
TOP 4KBx16
Sectors
…
…
• SBLK/SBULK(36h/39h):
4KB SRAM - SBLK(36h): Set SRAM bit=1 (protect): array can not be
SRAM programmed/erased
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
64KB programmed/erased
… - All the top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
SRAM
unprotected with SRAM bits individually by SBLK/SBULK
command set.
…
Uniform
64KB blocks • GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1, the whole chip is
……
protected and cannot be programmed/erased.

- GBULK(98h): Set all SRAM bits=0, the whole chip is
64KB unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of the whole chip can be
protected and unprotected at one time by GBLK/GBULK
4KB SRAM command set.
Bottom
…
4KBx16 • RDBLOCK(3Ch):
…
Sectors - use RDBLOCK mode to check the SRAM bits status after
4KB SRAM SBULK/SBLK/GBULK/GBLK command set.
SBULK / SBLK / GBULK / GBLK / RDBLOCK
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MX25L6445E
WPSEL Flow
start
RDSCUR(2Bh) command
Yes
WPSEL=1?
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
No
WIP=0?
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, … etc).
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32
MX25L6445E
(28) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a spec-
ified block(or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction →
send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Fig-
ure 36)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function flow is as follows:
Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1? WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully Block lock fail
Yes
Lock another block?
No
Block lock completed
P/N: PM1736 REV. 1.8, DEC. 26, 2011

33
MX25L6445E
Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1? WPSEL command
Yes
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
Yes
Unlock another block?
Unlock block completed?
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34
MX25L6445E
(29) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block (or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 ad-
dress bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please
refer to Figure 37)
(30) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →
CS# goes high. (Please refer to Figure 38)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(31) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed be-
fore program/erase another block during programming/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
(32) Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputting the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high.
(33) Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
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MX25L6445E
(34) Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP
operation can use CS# to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
Command 24 BIT ADDRESS
SI 5Ah 23 22 21 3 2 1 0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI 7 6 5 4 3 2 1 0
DATA OUT 1 DATA OUT 2
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB
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MX25L6445E
Table 7. Signature and Parameter Identification Data Values
Add (h) DW Add Data (h/b) Data

Description Comment
(Byte) (Bit) (Note1) (h)
00h 07:00 53h 53h
01h 15:08 46h 46h
SFDP Signature Fixed: 50444653h
02h 23:16 44h 44h
03h 31:24 50h 50h
SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h
SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h
Number of Parameter Headers Start from 00h 06h 23:16 01h 01h
Contains 0xFFh and can never be
Unused 07h 31:24 FFh FFh
changed
00h: it indicates a JEDEC specified
ID number (JEDEC) 08h 07:00 00h 00h
header.
Parameter Table Minor Revision
Start from 0x00h 09h 15:08 00h 00h
Number
Parameter Table Major Revision
Start from 0x01h 0Ah 23:16 01h 01h
Number
Parameter Table Length How many DWORDs in the
0Bh 31:24 09h 09h
(in double word) Parameter table
0Ch 07:00 30h 30h
First address of JEDEC Flash
Parameter Table Pointer (PTP) 0Dh 15:08 00h 00h
Parameter table
0Eh 23:16 00h 00h
Unused 0Fh 31:24 FFh FFh
changed
ID number it indicates Macronix manufacturer
10h 07:00 C2h C2h
(Macronix manufacturer ID) ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length How many DWORDs in the
13h 31:24 04h 04h
(in double word) Parameter table
14h 07:00 60h 60h
First address of Macronix Flash
Parameter Table Pointer (PTP) 15h 15:08 00h 00h
Parameter table
16h 23:16 00h 00h
changed
P/N: PM1736 REV. 1.8, DEC. 26, 2011

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MX25L6445E
Table 8. Parameter Table (0): JEDEC Flash Parameter Tables

Description Comment
00: Reserved, 01: 4KB erase,
Block/Sector Erase sizes 10: Reserved, 01:00 01b
11: not suport 4KB erase
Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b
Write Enable Instruction 0: Nonvolatitle status bit
Requested for Writing to Volatile 1: Volatitle status bit 03 0b
Status Registers (BP status register bit) 30h E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is 04 0b
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused 07:05 111b
changed
4KB Erase Opcode 31h 15:08 20h 20h
(1-1-2) Fast Read (Note2) 0=not support 1=support 16 0b

Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte,
18:17 00b
addressing flash array 10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
0=not support 1=support 19 1b
Clocking
32h B8h
(1-2-2) Fast Read 0=not support 1=support 20 1b
Unused 23 1b
Flash Memory Density 37h:34h 31:00 03FFFFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 0 0100b
states (Note3) Clocks) not support
38h 44h
(1-4-4) Fast Read Number of
000b: Mode Bits not support 07:05 010b
Mode Bits (Note4)
(1-4-4) Fast Read Opcode 39h 15:08 EBh EBh
20:16 0 0000b
states Clocks) not support
3Ah 00h
Mode Bits
(1-1-4) Fast Read Opcode 3Bh 31:24 FFh FFh
P/N: PM1736 REV. 1.8, DEC. 26, 2011

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MX25L6445E

Description Comment
04:00 0 0000b
3Ch 00h
Mode Bits
(1-1-2) Fast Read Opcode 3Dh 15:08 0xFFh 0xFFh
20:16 0 0100b
3Eh 04h
Mode Bits
(1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh
Unused 03:01 111b
40h EEh
Unused 07:05 111b
Unused 43h:41h 31:08 0xFFh 0xFFh
20:16 0 000b
46h 00h
Mode Bits
(2-2-2) Fast Read Opcode 47h 31:24 FFh FFh
20:16 0 0000b
4Ah 00h
Mode Bits
(4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh
Sector/block size = 2^N bytes (Note5)
Sector Type 1 Size 4Ch 07:00 0Ch 0Ch
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode 4Dh 15:08 20h 20h
Sector/block size = 2^N bytes
Sector Type 2 Size 4Eh 23:16 0Fh 0Fh
Sector Type 2 erase Opcode 4Fh 31:24 52h 52h
Sector Type 3 Size 50h 07:00 10h 10h
Sector Type 3 erase Opcode 51h 15:08 D8h D8h
Sector Type 4 Size 52h 23:16 00h 00h
Sector Type 4 erase Opcode 53h 31:24 FFh FFh
P/N: PM1736 REV. 1.8, DEC. 26, 2011

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MX25L6445E
Table 9. Parameter Table (1): Macronix Flash Parameter Tables

Description Comment
2000h=2.000V
07:00 00h 00h
Vcc Supply Maximum Voltage 2700h=2.700V 61h:60h
15:08 36h 36h
3600h=3.600V
1650h=1.650V
2250h=2.250V 23:16 00h 00h
Vcc Supply Minimum Voltage 63h:62h
2350h=2.350V 31:24 27h 27h
2700h=2.700V
HW Reset# pin 0=not support 1=support 00 0b
HW Hold# pin 0=not support 1=support 01 0b

Deep Power Down Mode 0=not support 1=support 02 1b
SW Reset 0=not support 1=support 03 0b
Reset Enable (66h) should be issued 65h:64h 1111 1111b 4FF4h
SW Reset Opcode 11:04
before Reset command (FFh)
Program Suspend/Resume 0=not support 1=support 12 0b
Erase Suspend/Resume 0=not support 1=support 13 0b
Unused 14 1b
Wrap-Around Read mode 0=not support 1=support 15 0b
Wrap-Around Read mode Opcode 66h 23:16 0xFFh 0xFFh
08h:support 8B wrap-around read
16h:8B&16B
Wrap-Around Read data length 67h 31:24 0xFFh 0xFFh
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock 0=not support 1=support 00 1b
Individual block lock bit
0=Volatile 1=Nonvolatile 01 0b
(Volatile/Nonvolatile)
0011 0110b
Individual block lock Opcode 09:02
(36h)
Individual block lock Volatile
0=protect 1=unprotect 10 0b C8D9h
protect bit default protect status
6Bh:68h
Secured OTP 0=not support 1=support 11 1b
Read Lock 0=not support 1=support 12 0b
Permanent Lock 0=not support 1=support 13 0b
Unused 15:14 11b
Unused 31:16 0xFFh 0xFFh
Unused 6Fh:6Ch 31:00 0xFFh 0xFFh
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MX25L6445E
Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh.
P/N: PM1736 REV. 1.8, DEC. 26, 2011

41
MX25L6445E
POWER-ON STATE
The device is at the following states after power-up:

- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
P/N: PM1736 REV. 1.8, DEC. 26, 2011

42
MX25L6445E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING VALUE
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to 4.6V
Applied Output Voltage -0.5V to 4.6V
VCC to Ground Potential -0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 2, 3.
Figure 2. Maximum Negative Overshoot Waveform Figure 3. Maximum Positive Overshoot Waveform
20ns 20ns 20ns
Vss
Vcc + 2.0V
Vss-2.0V
20ns Vcc
20ns 20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter Min. Typ. Max. Unit Conditions

CIN Input Capacitance 10 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V
P/N: PM1736 REV. 1.8, DEC. 26, 2011

43
MX25L6445E
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level Output timing reference level
0.8VCC
0.7VCC AC
Measurement 0.5VCC
0.3VCC Level
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER 2.7K ohm

TEST +3.3V
CL
6.2K ohm DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
P/N: PM1736 REV. 1.8, DEC. 26, 2011

44
MX25L6445E
Table 10. DC CHARACTERISTICS
Symbol Parameter Notes Min. Max. Units Test Conditions

ILI Input Load Current 1 ±2 uA VCC = VCC Max, VIN = VCC or GND
ILO Output Leakage Current 1 ±2 uA VCC = VCC Max, VOUT=VCC or GND
ISB1 VCC Standby Current 1 50 uA VIN = VCC or GND, CS# = VCC
Deep Power-down
ISB2 20 uA VIN = VCC or GND, CS# = VCC
Current
fQ=70MHz (4 x I/O read)
22 mA
SCLK=0.1VCC/0.9VCC, SO=Open
f=104MHz
19 mA
fT=70MHz (2 x I/O read)
ICC1 VCC Read 1 17 mA
f=66MHz
15 mA
f=33MHz,
10 mA
VCC Program Current
ICC2 1 25 mA Program in Progress, CS# = VCC
(PP)
VCC Write Status Program status register in progress,
ICC3 20 mA
Register (WRSR) Current CS#=VCC
VCC Sector Erase
ICC4 1 25 mA Erase in Progress, CS#=VCC
Current (SE)
VCC Chip Erase Current
ICC5 1 20 mA Erase in Progress, CS#=VCC
(CE)
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM1736 REV. 1.8, DEC. 26, 2011

45
MX25L6445E
Table 11. AC CHARACTERISTICS

Symbol Alt. Parameter Min. Typ. Max. Unit
Clock Frequency for the following instructions:
fSCLK fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP, D.C. 104 MHz
WREN, WRDI, RDID, RDSR, WRSR
fRSCLK fR Clock Frequency for READ instructions 50 MHz
fT Clock Frequency for 2READ instructions 70 MHz
VCC=2.7V-3.6V 70 MHz
fQ Clock Frequency for 4READ instructions
VCC=3.0V-3.6V 85 MHz
fTSCLK
fC2 Clock Frequency for FASTDTRD instructions 50 MHz
fT2 Clock Frequency for 2DTRD instructions 50 MHz
fQ2 Clock Frequency for 4DTRD instructions 50 MHz
f4PP Clock Frequency for 4PP (Quad page program) 20 MHz
(1) Fast_Read 4.5 ns
tCH tCLH Clock High Time
Read 9 ns
Fast_Read 4.5 ns
tCL(1) tCLL Clock Low Time
Read 9 ns
tCLCH(2) Clock Rise Time (3) (peak to peak) 0.1 V/ns
tCHCL(2) Clock Fall Time (3) (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH CS# Active Hold Time (relative to SCLK) 5 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns
Read 15 ns
(3)
tSHSL tCSH CS# Deselect Time Write/Erase/
50 ns
Program
(2) VCC=2.7V-3.6V 10 ns
tSHQZ tDIS Output Disable Time
VCC=3.0V-3.6V 8 ns
1 I/O 9 ns
Clock Low to Output Valid Loading: 15pF
tCLQV tV 2 I/O & 4 I/O 9.5 ns
VCC=2.7V~3.6V
Loading: 30pF 2 I/O & 4 I/O 12 ns
Clock Low to Output Valid (DTR mode) 1 I/O, 2 I/O &
tCLQV2 tV2 9.5 ns
VCC=2.7V~3.6V, Loading: 15pF 4 I/O
tCLQX tHO Output Hold Time 2 ns
tWHSL Write Protect Setup Time 20 ns
tSHWL Write Protect Hold Time 100 ns
(2)
tDP CS# High to Deep Power-down Mode 10 us
(2) CS# High to Standby Mode without Electronic Signature
tRES1 100 us
Read
tRES2(2) CS# High to Standby Mode with Electronic Signature Read 100 us
tW Write Status Register Cycle Time 40 100 ms
tBP Byte-Program 9 300 us
tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time (4KB) 60 300 ms
tBE Block Erase Cycle Time (32KB) 0.5 2 s
tBE Block Erase Cycle Time (64KB) 0.7 2 s
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MX25L6445E
Symbol Alt. Parameter Min. Typ. Max. Unit

tCE Chip Erase Cycle Time 50 80 s
tWPS Write Protection Selection Time 1 ms
tWSR Write Security Register Time 1 ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
P/N: PM1736 REV. 1.8, DEC. 26, 2011

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MX25L6445E
Timing Analysis
Figure 6. Serial Input Timing
tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHCL
tCHDX tCLCH
SI MSB LSB
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV tCLQV tCL tSHQZ
tCLQX tCLQX
SO LSB
SI ADDR.LSB IN
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MX25L6445E
Figure 8. Serial Input Timing for Double Transfer Rate Mode
tSHSL
CS#
SCLK
tDVCH tCHCL
tDVCH
tCHDX tCHDX tCLCH
SI MSB LSB
High-Z
SO
Figure 9. Serial Output Timing for Double Transfer Rate Mode
CS#
tCH
SCLK
tCLQV2
tCLQV2 tCLQV2 tCL tSHQZ
tCLQX
tCLQX
SO LSB
SI ADDR.LSB IN
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MX25L6445E
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI 01
High-Z
SO
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 04
High-Z
SO
P/N: PM1736 REV. 1.8, DEC. 26, 2011

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MX25L6445E
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
SCLK
Command
SI 9F
Manufacturer Identification Device Identification

High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0
MSB MSB
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
command
SI 05
Status Register Out

High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
command Status
Register In
SI 01 D7 D6 D5 D4 D3 D2 D1 D0
High-Z MSB
SO
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MX25L6445E
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24 ADD Cycles
SI 03 A23 A22 A21 A3 A2 A1 A0
MSB
Data Out 1 Data Out 2
High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command 24 ADD Cycles 8 Dummy Cycles
SI 0B A23 A22 A21 A3 A2 A1 A0
Data Out 1 Data Out 2

High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)
CS#
0 7 8 19 25 26 27 28 29
SCLK
  
Command 12 ADD Cycles 6 Dummy

Cycles Data Out Data Out
1 2
SI/SIO0 0D A23 A22  A1 A0
SO/SIO1 D7 D6 D5 D4 D3 D2 D1 D0 D7
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MX25L6445E
Figure 19. 2 x I/O Read Mode Sequence (Command BB)
CS#
0 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29
SCLK

Command 12 ADD Cycle 4 dummy Data Out Data Out
cycle 1 2
SI/SIO0 BB(hex) A22 A20  A2 A0 P2 P0 D6 D4 D2 D0 D6 D4
High Impedance
SO/SIO1 A23 A21  A3 A1 P3 P1 D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)
CS#
0 7 8 13 14 19 20 21 22 23
SCLK   
Command 6 ADD Cycles 6 Dummy Data Out Data Out 

Cycles 1 2
SI/SIO0 BD A22 A20  A2 A0 P2 P0 D6 D4 D2 D0 D6 D4 D2 D0 D6
SO/SIO1 A23 A21  A3 A1 P3 P1 D7 D5 D3 D1 D7 D5 D3 D1 D7
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
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MX25L6445E
Figure 21. 4 x I/O Read Mode Sequence (Command EB)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SCLK
Command 6 ADD Cycles 4 dummy Data Data Data

Performance cycles
Enhance
Indicator
Out 1 Out 2 Out 3
(Note1, 2)
SI/SIO0 EB A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4
High Impedance
SO/SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5
High Impedance
WP#/SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6
High Impedance
NC/SIO3 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
CS#
0 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n+1  n+7  n+9  n+13 

SCLK
 
6 ADD Cycles 4 dummy Data Data
Command 6 ADD 4 dummy Data Data Data
Performance cycles Cycles Performance
enhance Out 1 Out 2 enhance cycles Out 1 Out 2 Out 3
indicator (Note) indicator (Note)
SI/SIO0 EB A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 A20  A0 P4 P0 D4 D0 D4 D0 D4
High Impedance
SO/SIO1 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 A21  A1 P5 P1 D5 D1 D5 D1 D5
High Impedance
WP#/SIO2 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 A22  A2 P6 P2 D6 D2 D6 D2 D6
NC/SIO3
High Impedance
A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 A23
 A3 P7 P3 D7 D3 D7 D3 D7
Notes:
1. Performance enhance mode: if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, F0, 0F.
2. Reset the performance enhance mode: if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 55, 00, FF.
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MX25L6445E
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)
CS#
0 7 8 9 10 11 18 19 20
SCLK  
Command 3 ADD Cycles 1 cycle 7 Dummy
cycles
Performance
Enhance Indicator
(Note1,2)
SI/SIO0 ED A20 A16  A4 A0 P4 P0 D4 D0 D4 D0 D4
SO/SIO1 A21 A17  A5 A1 P5 P1 D5 D1 D5 D1 D5
WP#/SIO2 A22 A18  A6 A2 P6 P2 D6 D2 D6 D2 D6
NC/SIO3 A23 A19  A7 A3 P7 P3 D7 D3 D7 D3 D7
Notes:
1. Hi-impedance is inhibited for this clock cycle.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)
CS#
0 7 8 9 10 11 18 19 20
SCLK    
Command 3 ADD Cycles 1 cycle

Performance
7 Dummy Data Out Data Out 3 ADD Cycles 1 cycle
Performance
7 Dummy Data Out Data Out 
enhance cycles 1 2 enhance cycles 1 2
indicator (Note) indicator (Note)
SI/SIO0 ED (hex) A20 A16  A4 A0 P4 P0 D4 D0 D4 D0 A20 A16  A4 A0 P4 P0 D4 D0 D4 D0 D4
SO/SIO1 A21 A17

 A5 A1 P5 P1 D5 D1 D5 D1 A21 A17
 A5 A1 P5 P1 D5 D1 D5 D1 D5
WP#/SIO2 A22 A18  A6 A2 P6 P2 D6 D2 D6 D2 A22 A18  A6 A2 P6 P2 D6 D2 D6 D2 D6
NC/SIO3 A23 A19  A7 A3 P7 P3 D7 D3 D7 D3 A23 A19  A7 A3 P7 P3 D7 D3 D7 D3 D7
Note: Performance enhance, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggle)
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MX25L6445E
Figure 25. Sector Erase (SE) Sequence (Command 20)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
…
SI 20 A23 A22 … A2 A1 A0
MSB
Figure 26. Block Erase (BE/BE32K) Sequence (Command D8/52)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
SI D8/52 A23 A22 A2 A1 A0
MSB
Figure 27. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 60 or C7
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56
MX25L6445E
Figure 28. Page Program (PP) Sequence (Command 02)
CS#
2072
2073
2074
2075
2076
2077
2078
2079
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24 ADD Cycles Data Byte 1 Data Byte 256
SI 02 A23 A22 A21 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB MSB
Figure 29. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 524 525
SCLK

Command 6 ADD cycles Data Data Data
Byte 1 Byte 2 Byte 256
SI/SIO0 38 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0  D4 D0
SO/SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1  D5 D1
WP#/SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2  D6 D2
NC/SIO3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3  D7 D3
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MX25L6445E
Figure 30. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
0 1 6 7 8 9 30 31 31 32 47 48 0 1 6 7 8 20 21 22 23 24 0 7 0 7 8
SCLK
Command
data in Valid data in 04 (hex) 05 (hex)
SI AD (hex) 24-bit address
Byte 0, Byte1 Command (1) Byte n-1, Byte n
high impedance
S0 status (2)
Notes:
(1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command
(05 hex), and RDSCUR command (2B hex).
(2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS#
goes high will return the SO pin to tri-state.
(3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) com-
mand (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP
mode is ended.
Figure 31. Deep Power-down (DP) Sequence (Command B9)
CS#
0 1 2 3 4 5 6 7 tDP
SCLK
Command
SI B9
Stand-by Mode Deep Power-down Mode
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MX25L6445E
Figure 32. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24 ADD Cycles tRES2
SI AB A23 A22 A21 … A3 A2 A1 A0
MSB
Electronic Signature Out
High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0
MSB
Deep Power-down Mode Stand-by Mode
Figure 33. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0 1 2 3 4 5 6 7 tRES1
SCLK
Command
SI AB
High-Z
SO
Deep Power-down Mode Stand-by Mode
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59
MX25L6445E
Figure 34. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI A3 A2 A1 A0
90 A23 A22 A21
Manufacturer ID Device ID
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB MSB MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex) or CF(hex).
Figure 35. Write Protection Selection (WPSEL) Sequence (Command 68)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 68
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MX25L6445E
Figure 36. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 24 Bit Address

Cycles
SI 36/39 A23 A22 A2 A1 A0
MSB
Figure 37. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI 3C A23 A22 A21 A3 A2 A1 A0
MSB Block Protection Lock status out

High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0
MSB
Figure 38. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 7E/98
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MX25L6445E
Figure 39. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL Device is fully accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 12. Power-Up Timing

Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to CS# low 300 us
Note: The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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MX25L6445E
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 40 and Figure 41 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 40. AC Timing at Device Power-Up
VCC(min)
VCC
GND tVR tSHSL
CS#
SCLK
tDVCH tCHCL
tCHDX tCLCH
SI MSB IN LSB IN
High Impedance
SO
Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 20 500000 us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
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63
MX25L6445E
Figure 41. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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64
MX25L6445E
ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ. (1) Max. (2) Unit
Write Status Register Cycle Time 40 100 ms
Sector Erase Time (4KB) 60 300 ms
Block Erase Time (64KB) 0.7 2 s
Block Erase Time (32KB) 0.5 2 s
Chip Erase Time 50 80 s
Byte Program Time (via page program command) 9 300 us
Page Program Time 1.4 5 ms
Erase/Program Cycle 100,000 cycles
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
DATA RETENTION
Parameter Condition Min. Max. Unit
Data retention 55˚C 20 years
LATCH-UP CHARACTERISTICS
Min. Max.
Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax
Input Voltage with respect to GND on SO -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1736 REV. 1.8, DEC. 26, 2011

65
MX25L6445E
ORDERING INFORMATION
CLOCK
PART NO. TEMPERATURE PACKAGE Remark
(MHz)
16-SOP RoHS
MX25L6445EMI-10G 104 -40°C~85°C
(300mil) Compliant
8-SOP RoHS
MX25L6445EM2I-10G 104 -40°C~85°C
(200mil) Compliant
8-WSON RoHS
MX25L6445EZNI-10G 104 -40°C~85°C
(8x6mm) Compliant
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MX25L6445E
PART NAME DESCRIPTION
MX 25 L 6445E M I 10 G
OPTION:
G: RoHS Compliant
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M: 300mil 16-SOP
M2: 200mil 8-SOP
ZN: 8x6mm 8-WSON
DENSITY & MODE:

6445E: 64Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
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67
MX25L6445E
PACKAGE INFORMATION
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68
MX25L6445E
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MX25L6445E
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70
MX25L6445E
REVISION HISTORY
Revision No. Description Page Date

1.0 1. Removed "Preliminary" P5 MAY/19/2009
2. Merge MX25L6445E and MX25L12845E together All
3. Add CFI mode content P37
4. Align waveform format All
5. Modify tCH/tCL value, from rev0.06 tCH/tCL=5.5ns P43,45
to rev1.0 tCH/tCL(FAST_READ/READ)=4.5/9ns
6. Change command table format P15,16
7. Added "DATA RETENTION" Condition P66
8. Modified sector erase time from 90ms to 60ms P5,43,46,
P66
9. Modified 128Mb chip erase time (max) from 512s to 200s P46,66
1.1 1. Added 128M 8-WSON EPN P67 JUL/16/2009
2. Change RDCFI command from A5 to 5A P16,37
1.2 1. Added DMC Code content table P37~39 OCT/21/2009
2. Removed MX25L12845EZNI-10G advanced information remark P69
3. Changed the naming "CFI mode" as "DMC mode" All
1.3 1. Corrected error P8,43,44,54 APR/01/2010
P68
2. Added wording "e.g. Vcc and CS# ramp up simultaneously" P67
3. Modified low active read and standby current consumption P5,43~44,69
and deep power down current consumption
4. Deleted parallel mode condition P43
5. Modified table of "Read DMC mode (RDDMC)" P37~39
6. Added "Input Test Waveforms And Measurement Level" P42
7. Modified tSLCH, tSHCH from 8ns to 5ns P45,47
1.4 1. Removed DMC sequence description & content table P6,14,16,37 JUL/14/2010
2. Revised low active read current spec P5
3. Revised Table 7-1 and Table 7-2 P40-41
1.5 1. Removed MX25L12845E information from the previous combined All AUG/19/2011
version of MX25L6445E/MX25L12845E
2. Modified description for RoHS compliance P6,60,61
3. Revised Figure 18. Fast DT Read (FASTDTRD) Sequence P46,47,49
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence;
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence; and
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance.
4. Corrected ILO TEST CONDITIONS in Table 7 P39
5. Revised Storage Temperature P37
1.6 1. Changed Quad I/O Read Frequency from 80MHz@VCC=3.0V~3.6V P40 SEP/13/2011
to 85MHz@VCC=3.0V~3.6V
1.7 1. Revised the description in The individual block lock mode P31 OCT/05/2011
1.8 1. Modified Input Capacitance P43 DEC/26/2011
2. Modified Figure 41. Power-Down Sequence P64
3. Added Read SFDP (RDSFDP) Mode P6,13,14,
P36~41
4. Changed ordering information format P66
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71
MX25L6445E
Except for customized products which has been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2009~2011. All rights reserved.

Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash,
XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered
trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification
purposes only and may be claimed as the property of the respective companies.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
72

Papilio Pro Datasheet

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Papilio Pro

Papilio Pro - Pin Assignments

64Mbit Macronix MX25L6445 SPI Flash (Datasheet) Device: xc6slx9-2-tqg144 CLK

32Mhz Crystal Oscillator

Papilio Board 18Kbit BRAM Blocks Max SRAM Usable SRAM

Papilio Pro 32 576Kbit (72KByte) 512Kbit (64KByte)

Papilio One 500K 20 360Kbit (45KByte) 320Kbit (40KByte)

Papilio One 250K 12 216Kbit (27KByte) 192Kbit (24KByte)

One of the big improvements with the

The Papilio Pro includes a 64Mbit Micron MT48LC4M16 SDRAM

Hamster's SDRAM Controller

Channel A is connected to the Papilio Pro in an Asynchronous serial UART

Direction (FPGA Arduino Papilio Wing Papilio Pro

FPGA Serial Receive

FPGA Serial Transmit

The 64Mbit Macronix MX25L6445 SPI Flash chip is the largest

Direction (FPGA Arduino Papilio Wing Papilio Pro

FLASH_CS Output SPI Flash Chip Select N/A N/A P38

FLASH_CLK Output SPI Flash Clock N/A N/A P70

SPI Flash Master Out Slave In

SPI Flash Master In Slave Out

The I/O of the Papilio Pro is backwards

The major difference between the Papilio Pro and

The Papilio Pro has a 32Mhz oscillator that can be converted to

Direction (FPGA Arduino Papilio Wing Papilio Pro

Name Direction (FPGA Perspective) Function Arduino Pin Papilio Wing Pin Papilio Pro Pin

JTAG_TMS Input JTAG TMS N/A N/A P107

JTAG_TCK Input JTAG TCK N/A N/A P109

JTAG_SI Input JTAG SI N/A N/A P64

JTAG_SO Output JTAG SO N/A N/A P65

Pressing the reset button will cause the Spartan 6 FPGA to

Name Direction (FPGA Perspective) Function Arduino Pin Papilio Wing Pin Papilio Pro Pin

RESET Input FPGA Reset N/A N/A P37

Name Direction (FPGA Perspective) Function Arduino Pin Papilio Wing Pin Papilio Pro Pin

LED1 Output USER LED1 N/A N/A P112

© Gadget Factory 2009-2013

MT48LC64M4A2 108 129 128

PWRSELECT VCC ADBUS1

IS62WV51216 JTAG_TDO TDI

IO_L44N_GCLK20_3 DQ7 IO_L13P_M1_2

IO_L43N_GCLK22_IRDY2_3 A1 DQ9 IO_L14P_D11_2 SW1

24 DQ11 A4 29 48 DQ12 W1_B15 50 REBOOT B A

Spartan-6 Family Overview

DS160 (v2.0) October 25, 2011 Product Specification

DS160 (v2.0) October 25, 2011 www.xilinx.com

Spartan-6 FPGA Feature Summary

XC6SLX4 3,840 600 4,800 75 8 12 216 2 0 0 0 4 132

DS160 (v2.0) October 25, 2011 www.xilinx.com

Spartan-6 FPGA Device-Package Combinations and Available I/Os

Table 2: Spartan-6 Device-Package Combinations and Maximum Available I/Os

DS160 (v2.0) October 25, 2011 www.xilinx.com

CLBs, Slices, and LUTs

DS160 (v2.0) October 25, 2011 www.xilinx.com

Global Clock Lines

DS160 (v2.0) October 25, 2011 www.xilinx.com

Programmable Data Width

Memory Controller Block

Digital Signal Processing—DSP48A1 Slice

DS160 (v2.0) October 25, 2011 www.xilinx.com

I/O Electrical Characteristics

ISERDES and OSERDES

DS160 (v2.0) October 25, 2011 www.xilinx.com

Low-Power Gigabit Transceiver