VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belagavi, Karnataka-590018

A seminar report on

“Title of the seminar”

Submitted in partial fulfillment of the requirements for the award of degree in

Bachelor of Engineering
in
Electronics and Communication Engineering

Submitted by
Name USN

Under the Guidance of

Guide name

Department of Electronics & Communication Engineering

Government Engineering College, K R Pet-571426
2019-2020
 Department of Technical Education

Government Engineering College

K. R. Pet-571426, Mandya District
Department of Electronics and Communication Engineering

CERTIFICATE
This is to certify that the seminar [8th Semester] entitled “Title of the seminar” carried out

by name (USN), in the fulfillment for the award of Bachelor of Engineering in Electronics and

Communication Engineering of Visvesvaraya Technological University, Belagavi during the year

2019-2020. It is certified that all corrections/suggestions indicated for Internal Assessment have

been incorporated in the report. The seminar report has been approved as it satisfies the academic

requirements in respect of project work prescribed for the said degree.

Signature of Guide Signature of HOD Signature of Principal

 ACKNOWLEDGEMENT
I feel great pleasure in submitting this report “Title of the seminar”. The successful completion of
any task would be incomplete without the mention of people who made it possible and whose
support had been a constant of encouragement which crowned our efforts with success.

I indebted to my guide Dr. Rudrappa K. M, Associate Professor and HOD of Department of

Electronics and Communication Engineering for providing constant inputs and giving feedbacks
without which would not have been possible to complete this project seminar successfully.

I would like sincerely thank to Dr. Rudrappa K. M Associate Professor and Seminar Coordinator,
Department of Electronics and Communication, for providing the necessary resources and
guidelines required to complete this seminar.

I am extremely grateful to Dr. Rudrappa K. M, Associate Professor and HOD, Department of

Electronics and Communication Engineering, for the valuable and timely support throughout the
seminar.

I express my respect and gratitude to our honourable Principal Dr. N.S. Sathisha Government
Engineering College, K R Pet for his motivation and moral support in my academic endeavours.

I also thank my Department faculty, staff members and my parents for their encouragement and
support for this work.

Name

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 CONTENTS

Chapter No. Description Page No.

ACKNOWLEDGEMENTS iii

1 INTRODUCTION 1
1.1 General Introduction 1
1.2 Back ground 4
1.3 Organization of Report 7
2. Title of the chapter 8

3. Title of the chapter 14

3.1 14
3.2 16
3.3 17

4. Title of the chapter 18

4.1 18
4.2 19
4.3 20
4.4 Advantages 21
4.5 Disadvantages 21
4.6 Applications 22
5. CONCLUSION 23
REFERENCES 24

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LIST OF FIGURES
Figure 1.1 Design Areas of Processor 2
Figure 1.2 General Block Diagram of VLIW 3
Figure 2.1 Block Cipher Processing Model 11
Figure 3.1 Cryptographic Processor using AES 18
Figure 3.2 General Structure of AES Algorithm 20

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 LIST OF TABLES

Table 1.1 Main Registers used by the Functional Units 5

Table 1.2 Registers Organized according to the Function 15
Table 2.1 The Operation width and Block length of Block ciphers 20
Table 4.1 AES Encryption Cryptographic Processor 44

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