DE Book Work

Digital Electronics
and Computer Architecture

Lab Workbook
DR. SHARDA VASHISTH

DR. VANDANA KHANNA
School of Engineering & Technology

Department of Electrical, Electronics
and Communication Engineering
Name_____________________________________________________
Roll No.___________________________________________________
Branch____________________________________________________
Batch_____________________________________________________
The NorthCap University

Gurugram, Haryana
ii Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook iii
Published by: PREFACE

School of Engineering and Technology
Department of Electrical, Electronics and Communication Engineering
Digital Electronics and Computer Architecture Lab Workbook is designed to meet the syllabus
requirements of NCU curriculum for B.Tech II and III year students of CSE, IT, B.Sc and Electrical,
Gurugram
Electronics & Communication Engineering branch. The concept of the work book is to give brief and
important information about the experiments to students and provide the space and scope for self-study
• Laboratory Workbook is for Internal Circulation only
so that students can come up with new and creative ideas.
The work book is written on the basis of “teach yourself pattern” and expected that students who
© Copyright Reserved come with proper preparation should be able to perform the experiments without any difficulty. Brief
No part of this Practical Record Book may be reproduced, used, introduction to each experiment with information about self-study material is provided. Sufficient space
stored without prior permission of The NorthCap University. in work book is provided for independent writing of theory, observation, calculation and conclusion.
Fourteen selected experiments are presented in the best suitable fashion and are expected to be “student
friendly”, with an additional two value added experiments. At the start of each experiment a question
bank for preparation and practice is suggested which may be used to test the basic understanding of the
Copying or facilitating copying of lab work comes under students about the experiment. Students are expected to come thoroughly prepared for the lab. Quiz
cheating and is considered as use of unfair means. Students after each experiment will be conducted in the lab. General disciplines, safety guidelines and report
indulging in copying or facilitating copying shall be awarded writing are also discussed.
zero marks for that particular experiment. Frequent cases of The lab work book is an initiative of The NorthCap University, Gurugram for providing quality
copying may lead to disciplinary action. preparation, conduct and record keeping of the experiments. Teacher’s copy of the lab work book is
available as a reference in the lab.
Labs are open up to 7 PM upon request. Students are encouraged We hope that lab work book would be useful to students of CSE, IT, ECE and B.Sc branches and author
to make full use of labs beyond normal lab hours. requests the readers to kindly forward their suggestions / constructive criticism for further improvement
of the work book.
Authors express deep gratitude to Members, Governing Body-NCU for encouragement and motivation.
We are grateful to Director and Vice Chancellor of the University for their encouragement. We are highly
thankful to Dr. Swaran Ahuja, Dean-Academics and Dr. Sharda Vashisth, HOD - EECE for their keen
interest and guidance.
Sixth Edition
January, 2020 Authors
Gurugram
Revised by: January 2020
Dr. Sharda Vashisth
Deepika
Printed by:
ABC PRESS • A-21/12, Naraina Indl. Area, Ph-II, New Delhi - 110 028
Tel: 011-41418676 • E-mail: mailabcpress@gmail.com • Web: abcpress.co.in
iv Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook v
CONTENTS 3.8 Experiment No.- 8 58

Objective: Validate practically and through simulation (a) S-R and D
S.N. Details Page Latches (b) J-K and T flip flops using IC 7476.
No.
3.9 Experiment No.- 9 66
Syllabus: Digital Electronics vi Objective: Validate the operation of universal shift register using
practically and through simulation. Validate the operation of a Ring
Practical Contents vii counter and a Johnson counter
1 Introduction viii 3.10 Experiment No.- 10 74

Objective: Validate the operation of decade counter practically and
2 General Instructions viii through simulation using IC 7490 & drive a seven-segment display using
2.1 General discipline in the lab the same.
2.2 Attendance
2.3 Preparation and Performance 3.11 Experiment No.- 11 81
2.4 Lab Reports Objective: Analyze the characterstics of propagation delay time, fan out
2.5 Evaluation Plan and Noise Margin of the transistor – transistor logic (TTL) family and
Complementary Metal Oxide Semiconductor Logic (CMOS) family.
3 3.1 Experiment No.- 1 1
Objective: Validate practically and through simulation TTL and CMOS 3.12 Experiment No.- 12 91
gates – AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR. Objective: To Recognize various components of personal computer.
3.2 Experiment No.- 2 11 Virtual Lab Experiments

Objective: Design Ex-OR gate using minimum number of universal gates
and validate practically and through simulation its operation. 3.13 Experiment No.- 13 99
Objective: Design of 4 bit Arithmetic Logic Unit (With AND , OR, XOR ,
3.3 Experiment No.- 3 18 ADD Operation)Using Virtual Lab
Objective: Validate practically and through simulation operation of half
Adder and Full Adder. 3.14 Experiment No.- 14 102
Objective: Design and simulate Encoder, Decoder, Multiplexer and
3.4 Experiment No.- 4 25 Demultiplexer.
Objective: Design and realize Binary to Gray code converter using K-map
method and validate its performance practically and through simulation. 3.15 New Experiment (If any) 104
3.5 Experiment No.- 5 33 Project Report 109

Objective: Validate practically the characteristics of seven segment display
4. Notes and Comments 113
using decoder driver IC7447.

Objective: Design and implement 4-bit adder and subtractor using IC7483.

Objective: Validate practically and through simulation the operation of
Multiplexer and Demultiplexer.
vi Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook vii
Department of Electronics and Communication Practical Content

L T P C Type of Course Sl. Title of the Experiment Software/Kit based/ Unit
2 0 3 - Program Core Component based covered
Subject : Digital Electronics 1. Validate practically and through simulation TTL and CMOS gates – Component based, 1
Medium of Code : ECL 255 AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR. supplemented with
Frequency of Offering software simulation
Instruction:
English Only Even Semester 2. Design Ex-OR gate using minimum number of universal gates and Component based, 2
validate practically and through simulation its operation. supplemented with
software simulation
Brief Syllabus: Digital signal, Logic gates, Number system, Error detection and correction codes, Boolean 3. Validate practically and through simulation operation of half Adder Component based, 2
Algebra and Switching functions, Minimization Techniques, Combinational circuits, Logic Modules and their and Full Adder. supplemented with
functions, Sequential circuits and their applications, Digital Logic families, Building blocks of a computer, software simulation
Addressing techniques and registers, Memories, Advances in Technology, Current applications of digital
4. Design and realize Binary to Gray code converter using K-map method Component based, 3
electronics, Simulation Software (ORCAD, Labview), Case studies and analysis of Real time Situations.
and validate its performance practically and through simulation. supplemented with
Course Outcomes (COs) software simulation
Possible usefulness of this course after its completion i.e. how this course will be practically useful to him once 5. Validate practically the characteristics of seven segment display using Component based, 3
it is completed decoder driver IC7447. supplemented with
CO 1 Designing simple digital circuits employing logic gates software simulation
CO 2 Designing any combinational circuit using gates and logic elements like multiplexer, decoder etc.
CO 3 Designing sequential circuits like latches, flip flops, registers and counters. 6. Design and implement 4-bit adder and subtractor using IC7483. Component based, 3
CO 4 Understanding of the various architectural components of a digital computer. supplemented with
CO 5 Describing the different ways of communication between different devices including I/O, memory and software simulation
processor. 7. Validate practically and through simulation the operation of Multiplexer Component based, 3
S.N. Unit Content Lectures and Demultiplexer. supplemented with
software simulation
Introduction
Number systems, Logic Gates , Basics of Logic families: TTL, CMOS, 8. Validate practically and through simulation (a) S-R and D Latches (b) Component based, 4
1. to Digital 6
Boolean algebra, K-maps, Code converters J-K and T flip flops using IC 7476. supplemented with
Electronics
software simulation
Boolean algebra: Basic postulates and fundamental theorems of Boolean
9. Validate the operation of universal shift register using practically and Component based, 4
algebra; Standard representation of logic functions - SOP and POS forms;
Combinational through simulation. Validate the operation of a Ring counter and a supplemented with
2. K-map and QuineMcCluskey tabular methods; code converters: example- 6
Circuits Johnson counter. software simulation
BCD to Gray code converter and vice versa, BCD to Excess-3 Converter
and vice versa; designing of combinational logic circuits 10. Study and simulate the operation of decade counter using IC 7490 & Component based, 4
drive a seven-segment display using the same. supplemented with
Sequential Latches- S-R, J-K, D, T, Race around condition, Flip-flops, Shift registers, software simulation
3. 6
Circuits Asynchronous and synchronous counters, lock out condition.
11. Analyze the characterstics of propagation delay time, fan out and Component based, 5
Building Basic building blocks I/O, memory, ALU, control unit and their Noise Margin of the transistor – transistor logic (TTL) family and supplemented with
Blocks of a interconnections. Instruction word, Instruction execution cycle, control Complementary Metal Oxide Semiconductor Logic (CMOS) family. software simulation
4. 6
Computer registers, controlling of arithmetic operations, branch, skip, jump and shift
System instructions, components of ALU 12. To recognise various components of personal computer Virtual Lab 6
Addressing techniques- direct, immediate addressing, paging, relative, 13. Design of 4bit Airthmatic Logic Unit (with AND, OR, XOR and ADD Virtual Lab 2
Addressing operation.
indirect and indexed addressing, Memory buffer register, accumulators,
5. Techniques and 6
Registers- indexed, general purpose, special purpose. Overflow, carry, 14. Design and Simulate Encoder, Decoder, Multiplexer and Component based, 3
Registers
shift, scratch registers; stack pointers Demultiplexer. supplemented with
software simulation
Main, RAM, static and dynamic, EPROM, EEPROM, Cache and virtual
6. Memory 5 15. Mini Project Component based
memory
Total Lectures 35
viii Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook ix
1. INTRODUCTION 2.2 Attendance

That ‘learning is a continuous process’ cannot be overemphasized. The theoretical knowledge gained • Attendance in the lab class is compulsory.
during lecture sessions need to be strengthened through practical experimentation. Thus practical • As the attendance system is biometric, so late entry in the lab may result in the ‘absent’.
makes an integral part of a learning process.
• Students should not attend a different lab group/section other than the one assigned at the
The purpose of conducting experiments can be stated as follows: beginning of the session.
• To get familiarization with the basic components, devices, electronic instruments, modules, • On account of illness or some family problems, if a student misses his/her lab classes,
kits etc. used for constructing instrumentation circuits. he/she may be assigned a different group to make up the losses in consultation with the
• Circuit drawing using standard symbols as practiced in Engineering and Technology. concerned faculty / lab instructor. Or he/she may work in the lab during spare/extra hours
to complete the experiment. No attendance will be granted for such case.
• Making proper connection in the experimental kits/modules as per the circuit diagram and
connection of appropriate power supply for energizing the circuits. 2.3 Preparation and Performance
• Conducting experiments and writing observation as per the guidelines. • Students should come to the lab thoroughly prepared on the experiments they are assigned
to perform on that day. Brief introduction to each experiment with information about self-
• Verification of theoretical results through graphs or calculations.
study reference is provided in the work book.
• Hands on experience on the experimental setup and software tools.
• Faculty may check their preparation and understanding of the experiments. If not found
2. GENERAL INSTRUCTIONS satisfactory, students may be debarred from doing the experiments
2.1 General discipline in the lab • Students should mention the experiments in index in the sequence of performance.
• Students should come properly dressed and should wear shoes with the rubber sole. • Students should record the experimental results and observation in the lab work book and
get it signed by the instructor/faculty.
• Students must turn up in time and contact concerned faculty for the experiment they are
supposed to perform. • Faculty will conduct a Quiz after each experiment and marks will be awarded for each
quiz in the work book only. Lab work book should be submitted to faculty for evaluation
• Students will not be allowed to enter late in the lab.
after the quiz.
• Students will not leave the class till the period is over.
• Students must bring the lab work book on each practical class with written records of the
• Students should come prepared for their experiment with lab work book. last experiments performed complete in all respect.
• Experimental results should be entered in the lab work book and certified/signed by • Students without lab work book will not be allowed to do the experiments and hence lose
concerned faculty/ lab Instructor. their attendance.
• Students must get the connection of the experimental setup verified before switching on • Each student must write a satisfactory report for each lab experiments.
the power supply.
• Students should complete the experiments on the day allotted for the same.
• After the experiment is over, the experimental kits/modules. DMM and any other tools
• Failure to do so or any absence on that day may result in loosing marks in the continuous
issued for the experiments should be returned to the course instructor.
evaluation process of lab records.
• Students should maintain silence while performing the experiments. Should any necessity
• However, on the genuine ground, alternate times lot may be given to complete the
arises for discussion amongst them, they should discuss with a very low pitch without
experiment.
disturbing the adjacent groups.
2.4 Lab Reports
• Students should not unnecessarily fiddle with the instruments knob or any other pot in the
instruments which may disturb the calibration accuracy, range or zero etc. • Each student is required to write a complete report of the experiment he has performed
and bring to lab class for evaluation in the next working lab. Sufficient space in work book
• Violating the above code of conduct may attract disciplinary action.
is provided for independent writing of theory, observation, calculation and conclusion.
• Damaging lab equipment or removing any component from the lab may invite penalties
• Report should be written very clearly and lab record should be maintained neatly.
and strict disciplinary action.
• Students should follow the Zero tolerance policy for copying / plagiarism. Zero marks
will be awarded if found copied. If caught further, it will lead to disciplinary action.
x Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook xi
• The lab report must contain the following: 3. INDEX RollNo:.......................

1. Each report should include title, apparatus used, circuit / connection diagram, graphs,
equations, calculations, program codes(wherever applicable)etc.
Faculty’s
2. Standard symbols should be used to draw the diagrams. Name of Experiment Date of Total
S.N. Signature
3. Calculations & comparisons with appropriate equations and comments. (In the sequence of performance) Performance Marks (10)
with Date
4. Observation can be included explaining your experience in conducting the
1.
experiments.
5. Comments/notes must be written for further improvement of the lab work book. Sufficient
space is provided at the end of the lab work book. 2.
6. Print out of software/programs and results wherever applicable.

3.
The Students should maintain and preserve the lab work book properly and deposit the same with
the concerned lab in-charge at the end of the semester.
2.5 Evaluation plan for lab work 4.
Marks distribution
Continuous Evaluation (35 Marks) End semester exam 5.
(20 Marks) +
Mini Project (15 Marks) 6.
Each experiment shall be evaluated for 10 marks and End semester practical evaluation
at the end of the semester proportional marks shall be and Mini Project evaluation.
awarded out of 35. 7.
Following is the breakup of 10 marks for each
experiment: 8.
• 4 Marks: Observation & conduct of experiment.
Teacher may ask one or two questions while 9.
checking observations
• 3 Marks: For report writing
• 3 Marks: For the 15 minutes quiz to be 10.
conducted in every lab.
11.
12.
13.
14.
xii Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook 1
Suggested List of Projects Experiment No.: 1

1) Mobile phone detector
2) Visitor counter Date of Performance _________________
3) Traffic light control

4) IR transmitter receiver Objective
Validate practically and through simulation TTL and CMOS gates – AND, OR, NOT, NAND, NOR,
5) Disco lights EX-OR, EX-NOR.
6) Coin toss
Introduction to the experiment
7) Counter to count up to 100 Logic gates are elementary building block of a digital circuit. Most logic gates have two inputs and
8) Game scoring one output. At any given moment, every terminal is in one of the two binary conditions low (0) or
high (1), represented by different voltage levels. There are three types of basic gates i.e. AND, OR
9) Digital pulse counter and NOT. There are two universal gates i.e. NAND and NOR which can be used to realize any digital
10) LED flasher & inverter circuit using only one type of gates, either NAND or NOR. Ex-OR and Ex-NOR are two special
purpose gates. Logic gates are used to design combinational and sequential logic digital circuits.
11) Hello display
All digital circuits belong to one of the digital logic families. A logic family of monolithic digital
12) Clap detector integrated circuit devices is a group of electronic logic gates constructed using one of several
different designs, usually with compatible logic levels and power supply characteristics within a
13) Arduino based car
family. Many logic families were produced as individual components, each containing one or a few
14) Arithmetic and logic unit (ALU) related basic logical functions, which could be used as "building-blocks" to create systems or as so-
called "glue" to interconnect more complex integrated circuits. A "logic family" may also refer to a
15) Digital door lock set of techniques used to implement logic within VLSI integrated circuits such as central processors,
16) Smoke detector memories, or other complex functions. Some such logic families use static techniques to minimize
design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques
17) Christmas fancy lights to minimize size, power consumption, and delay. TTL and CMOS are most popular logic families.
18) LED-based message display In this experiment the students are expected to
19) IR remote switch • Validate the operation of all gates with TTL and CMOS family ICs on breadboard
20) Mobile phone battery charger • Be familiar with ORCAD software and validate the gates through simulation
21) Digital stop watch
Self-Study Material
• Digital Logic and Computer Design by Morris Mano, Pearson
• Fundamentals of Digital Electronics by Anand Kumar, PHI
• lms.ncuindia.edu
• http://nptel.ac.in/courses/117106086/1
• http://etech.atu.edu/student.html
• http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001
Suggested Preparatory Question Bank
Q1. Why are NAND, NOR gates known as universal gates?
Q2. The minimum no. of NAND gates required to implement the Boolean function
A + A B + A B C is equal to ………….
Q3. Obtain logical expression for the following circuit
2 Digital Electronics and Computer Architecture Lab Workbook Digital Electronics and Computer Architecture Lab Workbook 3
Lab Report
(To be completed by next lab turn)
Write the following:

Objective:
Q4. Draw the truth table of coincidence logic gate.

Q5. Make truth table for 3 I/P OR and NAND gates. Apparatus Required
Q6. Is it possible to use a 3 I/P gate as a 2 I/P gate for NAND and NOR gates? If yes, how?
Q7. The number of rows in a truth table of 4 variables is------------ Software Required:
Q8. The no. of 3 I/P NAND gates in a 14-pin IC is--------
Q9. The minimum number of bits required to distinguish 108 distinct objects is------ Procedure
Q10. Why unconnected input of TTL IC is considered high?
Q11. When used with an IC, what does the term "QUAD" indicate?
Q12. Following voltage wave forms are applied at the inputs of 2 input AND gate & OR gate. Plot
the output waveforms of these gates.
1
0
Q13. TTL operates with ________ volt supply.
Q14. A CMOS IC operating from a 3-volt supply will consume ________ power than a TTL IC.
Q15. What does the small bubble on the output of the NAND gate logic symbol mean?
Q16. What are the pin numbers of the outputs of the gates in a 7432 IC?
Q17. What is the circuit number of the IC that contains four two-input AND gates in standard TTL?
Q18. The output of an exclusive-NOR gate is HIGH if ________.
Q19. The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is
HIGH is a(n) ________.
Q20. For the circuit shown below, the output F is given by
3. NOT Gate
Pin Diagrams
1. AND Gate
2. OR Gate
4. NAND Gate
5. NOR Gate
Draw symbols and write logical expression of all the gates.
6. EX- OR Gate
7. EX-NOR Gate
Marks for write-up (Max. Marks 3)

Paste print outs of the Schematic diagram and the required waveforms. Observation Table (Truth Table)
Faculty signature with Date ____________________

Marks for experiment performance (Max. Marks 4) _____________________
Answers to Quiz Experiment No.: 2

Date of Performance _________________
Objective
Design Ex-OR gate using minimum number of universal gates and validate practically and through
simulation its operation.
Exclusive-OR Gates are used mainly to build circuits that perform arithmetic operations and
calculations. Half-Adders and Full adders are built with Ex-OR gates which are the building blocks
for Adders in calculators and computers. One of its most commonly used applications is as a basic
logic comparator which produces a logic “1” output when its two input bits are not equal. Because of
this, the exclusive-OR gate has an inequality status being known as an odd function.
In order to design adders and comparators, XOR gate can be reconstructed directly using AND, OR
and NOT gates. However, this approach requires five gates of three different kinds. An XOR gate
could be made from four NAND or five NOR gates in the configurations shown below. In fact, both
NAND and NOR gates are so-called "universal gates," and any logical function can be constructed
from either NAND logic or NOR logic alone.
In this experiment the students are expected to
• Realize Ex-OR gate using minimum number of NAND gates only / NOR gates only.
• Validate the operation of both the circuits practically and through simulation.
Self-Study Material
1. Digital Logic and Computer Design by Morris Mano, Pearson
2. Fundamentals of Digital Electronics by Anand Kumar, PHI
3. lms.ncuindia.edu
4. http://cs.stackexchange.com/questions/43342/how-to-construct-xor-gate-using-only-4-nand-
gate
5. http://nptel.ac.in/courses/117106086/1
6. http://etech.atu.edu/student.html
7. http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001
Quiz Marks (Max. Marks 3) _____________________

Faculty signature with Date _______________________ Total Marks _______________
Suggested Preparatory Question Bank Lab Report

Q1. Construct AND, OR, NOT gate using NAND gates only. (To be completed by next lab turn)
Q2. Construct AND, OR, NOT gate using NOR gates only.
(
Q3. Write self-dual expression of Boolean relation, AB (C + D) + A + ABC . ) Objective:
Q4. Implement the following function with NAND and NOR logic F = ( A + B) C + D( )
Q5. Make truth table for 3 I/P XOR and XNOR gates.
Q6. Minimize the Boolean function xyz + xy + x Apparatus Required
Q7. Convert the following SOP expression to an equivalent POS expression.
ABC + AB C + ABC + ABC + ABC
Software Required:
Q8 Derive the Boolean expression for the logic circuit shown below:
Procedure
Q9. State Demorgan’s Laws.

Q10. Applying DeMorgan's theorem to the expression ABC , we get ________.
Q11. An AND gate with schematic "bubbles" on its inputs performs the same function as
a(n)________ gate.
Q12. For the SOP expression A B C + A B C + A B C , how many 1s are in the truth table's output
column?
Q13. What is the primary motivation for using Boolean algebra to simplify logic expressions?
Q14. AC + ABC = AC, True or False?
Q15. When grouping cells within a K-map, the cells must be combined in groups of ________.
Q16. Make Ex-NOR gate using minimum no. of NAND gates.
Q17. Make Ex-NOR gate using minimum no. of NOR gates.
Q18. Show analytically realization of Ex-OR gate using 4 NAND gates.
Q19. Show analytically realization of Ex-OR gate using 5 NOR gates.
Q20. A bulb in a staircase has two switches, one switch being at the ground floor and the other one at
the first floor. The bulb can be turned ON and also can be turned OFF by any one of the
switches irrespective of the state of the other switch. The logic of switching of the bulb
resembles to which gate.
Circuit Diagrams Paste print outs of the Schematic diagram and the required waveforms
Ex-OR using 4 NAND gates only.
Ex-OR using 5 NOR gates only.

Observation Table (Truth Table) Answers to quiz
Faculty signature with Date Quiz Marks (Max. Marks 3) _____________________________

Marks for experiment performance (Max. Marks 4)
Faculty signature with Date ____________________ Total Marks _______________________

Experiment No.: 3 Q1 For adding 4-bit numbers we need ……………………. full adders connected in parallel.
Q2 For adding two 8-bit numbers, a parallel binary adder must contain …………………. Full
Date of Performance _________________ adders.
Q3 What changes need to be done in half adder to convert it into half subtractor?
Q4 Why subtractor IC is not available?
Objective Q5 Draw an adder to add two 4 bit Nos.
Validate practically and through simulation operation of half Adder and Full Adder. Q6 Draw circuit of half adder using NAND gates only.
Q7 Draw circuit diagram of full adder using NAND gates only.
Q8 How many minimum number of NAND gates are used in half adder?
Half Adder and Full Adder are the basic building blocks of all adders and subtractors.
Q9 How many minimum number of NAND gates are used in full adder?
Half-Adder: Half adder is a logic circuit that accepts two binary digits on its inputs and produces the Q10 Add two BCD numbers (679+588)10
binary digits on its outputs i.e. a sum bit & a carry bit. Half adder adds two 1-bit numbers. Q11 True or False, A full adder has a carry-in.
Logic Symbol Q12 How many inputs must a full-adder have?
Q13 Convert each of the decimal numbers to two's-complement form and perform the addition in
binary.
i) +13 add -7 ii) –10 add +15
Q14 What is the range of positive numbers when using an eight-bit two's-complement system?
Q15 What are the two types of basic adder circuits?
Full Adder
Q16 Add two hexadecimal numbers. (AB235F + E356AC)16
Full adder is a logic circuit that accepts three inputs and generates two outputs i.e. sum & carry. Q17 Perform octal subtraction. (752 – 376)8
Full adder adds three 1-bit numbers i.e. two new inputs and one carry input from the previous stage.
Q18 True or False, Half-adders can be combined to form a full-adder with no additional gates.
Logic Symbol Q19 Design a Full Adder using 2 Half Adder?
Q20 Half Adder Can Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages

• Design Half Adder and Full Adder circuits.
• Validate the operation of both the circuits practically and through simulation.
Self-Study Material
3. lms.ncuindia.edu
4. http://www.iium.edu.my/ece/laboratory/dld_microp/Experiment_2.pdf
8. http://www.circuitstoday.com/half-adder-and-full-adder
Circuit Diagrams
Lab Report Half Adder Circuit

Objective:
Apparatus Required
Software Required:
Procedure
Full Adder Circuit

Paste print outs of the Schematic diagram and the required waveforms Observation Table (Truth Table)
Half Adder
Full Adder
Faculty signature with Date

Answers to quiz Experiment No.: 4

Objective
Design and realize Binary to Gray code converter using K-map method and validate its
performance practically and through simulation.
BINARY CODE A binary code represents text or computer processor instructions using the binary
number system's two binary digits, 0 and 1. The binary code assigns a bit string to each symbol or
instruction. For example, a binary string of eight binary digits (bits) can represent any of 256 possible
values and can therefore correspond to a variety of different symbols, letters or instructions. Decimal
number can be converted to binary code by dividing it by 2 and keeping the remainder aside and by
taking it from bottom to top.
(34)10 = (100010)2
GRAY CODE after Frank Gray, is a binary numeral system where two successive values differ
in only one bit. The advantage of the Gray code over the straight binary number sequence is
that only one bit in the code group changes ion going from one number to the next.
Conversion from Binary number to gray code

• Design and Realize Binary to Gray code converter using K-map method
• Validate the operation of the circuit practically and through simulation.
Self-Study Material
3. lms.ncuindia.edu
4. http://www.iium.edu.my/ece/laboratory/dld_microp/Experiment_3.pdf
Quiz Marks (Max. Marks 3) _____________________________ 6. http://etech.atu.edu/student.html

Faculty signature with Date ____________________ Total Marks _______________________ 7. http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001
8. http://www.electrical4u.com/gray-code-binary-to-gray-code-and-that-to-binary-conversion/
Suggested Preparatory Question Bank Lab Report

Q1 Write Binary code of (365)10. (To be completed by next lab turn)
Q2 True or false, In a Gray code, each number is 3 greater than the binary representation of that
number. Write the following:
Q3 Convert (59.72)10 to BCD.
Objective:
Q4 Convert (8B3F)16 to binary.
Q5 Which is typically the longest: bit, byte, nibble, word?
Q6 Assign the proper odd parity bit to the code 111001.
Apparatus Required
Q7 Convert the following octal number to decimal (17)8
Q8 How many binary digits are required to count to (100)10?
Software Required:
Q9 When using even parity, where is the parity bit placed?
Q10 What is the difference between binary coding and binary-coded decimal?
Procedure
Q11 Digital electronics is based on the ________ numbering system.
Q12 Is there any meaning of BCD no. 1010 ?
Q13 Why is the Gray code more practical to use when coding the position of a rotating shaft?
Q14 Why is the Gray code important for numbering the cells in K-Map?
Q15 Why is Gray code known as reflected code?
Q16 Write 2-bit Gray code table.
Q17 Write 3-bit Gray code table.
Q18 Convert (110110111)2 into Gray code.
Q19 Convert (100100110)GRAY into binary code.
Q20 Is Gray code weighted?
Table for converting binary code to gray code Circuit Diagram
K-map Simplification
Marks for write-up (Max. Marks 3) _______________________

Paste print outs of the Schematic diagram and the required waveforms Observation Table


Objective
Validate practically the characteristics of seven segment display using decoder driver IC7447.
A standard 7-segment LED display generally has 8 input connections, one for each LED segment and
one that acts as a common terminal for all the internal display segments. Some single displays have
also have an additional input pin to display a decimal point in their lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
1. The Common Cathode Display (CCD) – In the common cathode display, all the cathode
connections of the LED’s are joined together to logic “0” or ground. The individual segments
are illuminated by application of a “HIGH”, logic “1” signal to the individual Anode terminals.
2. The Common Anode Display (CAD) – In the common anode display, all the anode connections
of the LED’s are joined together to logic “1” and the individual segments are illuminated by
connecting the individual Cathode terminals to a “LOW”, logic “0” signal.
• Study the characteristics of decoder IC 7447.
• Validate the operation of the circuit practically.
Self-Study Material
3. lms.ncuindia.edu
4. http://www.electronics-tutorials.ws/combination/comb_6.html
7. http://ece.uncc.edu/sites/ece.uncc.edu/files/media/labs/2255/2-BCD%20to%20seven%20
segment%20decoder.pdf
Q1 What is the function of LT pin?
Q2 What is the function of RBI pin?
Q3 What is the function of BI pin?
Q4 What do you mean by Common anode and common cathode connection?
Q5 Why do we need to perform all the tests before providing all the inputs
Q6 What are 7 segment display? What are its applications?
Quiz Marks (Max. Marks 3) _____________________________
Q7 Portable digital devices, such as watches or solar-powered calculators, use ___ displays
Faculty signature with Date ____________________ Total Marks _______________________ because of their extremely low power consumption.
Q8 The BCD input into the 7447 decoder IC is ___ causing the 7-segment LED display to read Lab Report
decimal ___ (the number 8 on the display is not the correct output and only shows that this is a
7-segment display). (To be completed by next lab turn)

Objective:
Apparatus Required
Software Required:
Procedure
Q9 The seven-segment display (without the use of colored filters) that emits a reddish glow is the
___ type.
Q10 The 7447 IC is a BCD-to-7-segment decoder which can drive LED displays and has active ___
(HIGH, LOW) input with active ___ (HIGH, LOW) outputs.
Pin Diagram
BCD to 7-segment decoder (IC7447)
Q11 BCD to 7 segment is a …………..

Q12 IC of 7 segment display contains……………….LEDs
Q13 What digit would be displayed If LT = 0, RBI = 1 and DCBA = 0011.
Q14 What digit would be displayed If LT = 1, BI = 0 and DCBA = 0010.
Q16 What digit would be displayed If LT = 1, BI = 1 and DCBA = 1001.
Q19 Whether the special pins LT, RBI and BI are active low or active high pins
Table for designing BCD to 7-segment decoder Observation Table
K-Map Simplification
Circuit Diagram


Objective
Design and implement 4-bit adder and subtractor using IC7483.
A binary adder/subtractor is a digital circuit that produces the arithmetic sum or difference of two
binary numbers. A binary adder can be constructed with full adders connected in cascade with the
output carry from each adder connected to the next full adder in the chain. Subtraction of two
numbers (A-B) can be performed by taking 2’s complement of B and adding it with A. Thus binary
adder can be used to perform subtraction of two binary numbers if few changes are made. In case of
binary adder, input carry is set to be 0 and all the input bits are given as it is. Whereas for binary
subtractor, in order to give 2’s complement of B we consider input carry equal to 1 and the bits of B
is complemented which means 1’s complement of B is taken and it is added with 1 to give its 2’s
complement value. The block diagram of 4-bit binary adder/subtractor is as shown in figure. The
circuit performs addition when M = 0 & subtraction when M = 1. IC 7483 is an integrated circuit
which performs addition of two 4-bit binary numbers.
• Design and implement 4-bit adder/subtractor using IC 7483.
• Validate the operation of the circuits practically.
Self-Study Material
3. lms.ncuindia.edu
4. http://www.pradipyadav.com/2012/08/objective-to-design-and-implement-of-
4_18.html#.V3qST_l97IU’
7. https://dca13d00a675f255e4d75145ccca85da6f5067de.googledrive.com/host/
0B3G21MbFQqR7RUxWTWs5a0JJelk/ece/3/DIGITAL%20ELECTRONICS%20
LAB/Ex.7.pdf

Q16 Binary subtraction of a decimal 15 from 43…………………….
Q17 What is the correct output of the adder in the given figure, with the outputs in the order:
Q1 What is meant by adder and subtractor?
Q2 The circuit shown in the figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z
with Y = P  Q  R, Z = RQ + P R + Q P. Name the circuit.
Q18 Subtract the following binary numbers (1101)2 – (0011)2

Q19 Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
Q3 For a 4-bit parallel adder, if the carry-in of the least significant full adder is connected to a Q20 The binary adder circuit is designed to add ________ binary numbers at the same time.
logical HIGH, what will be the result.
Q4 A = (1100)2 and B = (0111)2 are applied as input to 7483 adder. Determine the outputs.
Q5 Solve this BCD problem: 0100 + 0110 =
Q6 What is the principle of look ahead carry?
Q7 What is the effect of fast-look-ahead carry circuits found in most 4-bit full-adder circuits?
Q8 The binary subtraction 0 – 0 =
Q9 How can we make a BCD adder using 4-bit binary adders? Show with the help of block
diagram.
Q10 Adding in binary, a decimal 26 + 27 will produce a sum of:
Q11 One way to make a four-bit adder perform subtraction is by:
Q12 What distinguishes the look-ahead-carry adder?
Q13 What is one disadvantage of the ripple-carry adder?
Q14 How many BCD adders would be required to add the numbers 97310 + 3910?
Q15
Lab Report Pin Diagram

(To be completed by next lab turn) 4-bit Binary Adder(IC 7483)

Objective:
Apparatus Required
Software Required:
Procedure
Circuit Diagram (Adder with 7483 IC) Implement 4 bit adder/subtractor using a control input (Block Diagram)
Circuit Diagram (Subtractor with 7483 IC)

Observation Table Answers to quiz
Faculty signature with Date Quiz Marks (Max. Marks 3) _____________________________

Self-Study Material
Experiment No.: 7 1. Digital Logic and Computer Design by Morris Mano, Pearson
Date of Performance _________________ 3. lms.ncuindia.edu
4. http://site.iugaza.edu.ps/wmousa/files/Lab7_Multiplexers-and-Demultiplexers1.pdf
Objective 5. http://ux.brookdalecc.edu/fac/engtech/andy/engi251/labs/lab10.pdf
Validate practically and through simulation the operation of Multiplexer and Demultiplexer. 6. https://www.unf.edu/~sahuja/cda3101/lab5.PDF
Multiplexers: In electronics, a multiplexer (or mux) is a device that selects one of several analog or
digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n Suggested Preparatory Question Bank
select lines, which are used to select the input line to send to the output. A 2n -to-1 multiplexer sends Q1 For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be
one of 2n input lines to a single output line. LOW. What is the status of the Y output?
Q2 How many data select lines are required for selecting eight inputs?
Q3 The device shown here is most likely a ________.
Demultiplexers: The Demultiplexer is a combinational logic circuit that performs the reverse
operation of Multiplexer. It has only one input, n selectors and 2n outputs. Depending on the
combination of the select lines, one of the outputs will be selected to take the state of the input.
Q4 A decoder can be used as a demultiplexer by

Q5 How many 3-line-to-8-line decoders are required for a 1:32 demultiplexer?
Q6 What is the function of an enable input on a multiplexer chip?

• Study the operation of Multiplexer and Demultiplexer.
• Validate practically and through simulation the operation of the circuit practically.
Q7 The device shown here is most likely a ________. Q12 In the following circuit X is given by
Q8 The logic realized by the circuit shown in figure is

Q13 What are the minimum number of 2 to 1 multiplexers required to generated a 2 input AND gate
and a 2 input EX-OR gate?
Q14 Enable input is also called …………………..
Q15 Two input mux would have……………select lines.
Q16 A combinational circuit that selects one from many inputs is called………………………
Q17 1 to 8 demux would have ………………..input(s).
Q18 In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by
Q9 In the TTL circuit in the figure, S2 to S0 are select lines and X7 to X0 are input lines. S0 and
X0 are LSBs. The output Y is
Q19 How many 1:16 demultiplexers are required to obtain 1:1024 demultiplexers?
Q20 An 8 – to – 1 multiplexer is used to implement a logical function Y as shown in the figure. The
output Y is given by
Q10 Can we use an 8:1 MUX without any additional circuitry to obtain All functions of 3 variables
and some but not all of 4 variables?
Q11 The Boolean function f implemented in the figure using two input multiplexers is

(To be completed by next lab turn) Multiplexer (IC 74151)

Objective:
Apparatus Required
Software Required:
Procedure
Demultiplexer/Decoder (IC 74138)

8:1 Multiplexer circuit diagram Paste print outs of schematic diagram and the required waveforms.
1:8 Demultiplexer circuit diagram


Marks for experiment performance (Max. Marks 4) Faculty signature with Date ____________________ Total Marks _______________________
Q4. What is latch? What is the difference between latch and flip flop?
Experiment No.: 8 Q5. An S-R flip flop can be converted into a T flip flop by connecting __ to Q’ and___ to Q
Q6. How does the JK FF differ from an SR FF in its basic equation?
Date of Performance _________________ Q7. What is the condition on JK FF to work as D FF?
Q8. What is race around condition? How do you eliminate it?
Objective Q9. Mention any two differences between the edge triggering and level triggering.
Validate practically and through simulation (a) S-R and D Latches (b) J-K and T flip flops using IC Q10. Draw a NAND based logic diagram of Master Slave JK FF.
7476. Q11. Convert Transparent flip flop into a JK flip flop.
Introduction to the experiment Q12. Design a JK latch with Preset and Clear options, using NAND gates only.
SR Latch Q13. No. of Flip Flops required for storing n-bit of information is ___________.
Latch is a device, which can store a binary bit indefinitely (as long power is delivered to the circuit), Q14. In a JK flip flop, if J=K=1, its Q output will be _____________when a clock pulse is applied.
until directed by input signal to switch state. Clocked S-R latch can be constructed using either i) two Q15. Preset and clear inputs are used in a flip flop for making Q = __________ and ____________
AND and two NOR gates or ii) using four NAND gates. It has two inputs S(Set) and R (Reset) in respectively.
addition to the clock signal. The outputs are Q and Qbar. Q16. In a T flip flop, the Q output will be ______________when T=0 and clock pulse is applied.
D Latch Q17. Compare combinational circuit and sequential circuit.
If we use only the middle two rows of the characteristics table of the SR Latch, we obtain a D type Q18. What is meant by present state and next state of a sequential circuit?
Latch. It has one input referred to as D input or data input. Q output of D Latch is equal to the input Q19. The present output Qn of an edge triggered JK flip-flop is logic ‘0’. If j = 1, then
applied. Thus, the transfer of data from the input to the output is delayed and hence the name the Qn+1 is_________.
delay Latch.
Q20. Draw the characteristics table and excitation table of T flip flop.
J-K Flip-flop
J-K Flip-flop is probably the most widely used and universal flip-flop. The two indeterminate state in
SR flip-flop are defined in J-k flip-flop.
In a J-K flip-flop if J = K =1, the resulting flip-flop is referred to as a T-type flip-flop. An S-R flip-
flop cannot be converted to a T-type flip-flop, since S = R = 1 is prohibited. T-flip-flop is called a
toggle flip-flop. Since output toggles when T = 1
Asynchronous inputs Preset and CLR over ride synchronous inputs in J-K flip-flop, J is set & K is for
clear, when J=K=1, the F/F switches to its complement state.
Self-Study Material
3. lms.ncuindia.edu
6. https://old.uqu.edu.sa/files2/tiny_mce/plugins/filemanager/files/4281665/digital/
digital_design-__morris_mano-fifth_edition.pdf
Q1. What is sequential circuit? Give some examples.
Q2. Compare Asynchronous and Synchronous sequential logic.
Q3. Make the characteristics table and write the characteristics equation of a D FF.
Lab Report Circuit Diagram SR Latch


Objective:
Apparatus Required
Software Required:
Procedure
Circuit Diagram D Latch
Pin Diagram JK FF (IC7476)

Paste print out of the Schematic diagram and the required waveforms
Marks for write-up (Max. Marks 3) _______________

Observation Table ( Characteristics Table) Answers to quiz
Marks for experiment performance (Max. Marks 4)__________ Quiz Marks (Max. Marks 3) _____________________________
Faculty signature with Date Total Marks Faculty signature with Date ____________________ Total Marks _______________________
Experiment No.: 9 6. http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001
7. https://old.uqu.edu.sa/files2/tiny_mce/plugins/filemanager/files/4281665/digital/digital_design-
Date of Performance _________________ __morris_mano-fifth_edition.pdf
Objective Q1. Define Universal Shift register.
Validate the operation of universal shift register using practically and through simulation. Validate Q2. What is the difference between spacial code and temporal code?
the operation of a Ring counter and a Johnson counter. Q3. Simplest registers only consists of ______________.
Introduction to the experiment Q4. Flip-flops in registers are:
74194 IC Universal shift register is designed to incorporate virtually all of the features a system a. present b. level triggered
designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left- c. edge triggered d. not present
shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. Q5. What type of register would shift a complete binary number in one bit at a time and shift all the
stored bits out one bit at a time?
The 74194 IC contains four edge triggered D type Flip-flops and other combinational logic.
Signals supplied to the Select (S0, S1) inputs determines the type of operation, as shown in the Q6. What is meant by parallel-loading the register?
Function table. Q7. If all inputs are loaded simultaneously and output is loaded bit by bit, then what will be the
mode of operation for a shift register?
The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the
direction Q A toward Q D ) Shift left (in the direction Q D toward Q A ) Inhibit clock (do nothing) Q8. SIPO and SISO stand for ______________________and ______________________.
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode Q9. Twisted ring counter is another name for ____________________counter.
control inputs, S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the
Q10. Purpose of using a shift register is_________________________________.
outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH Q11. If the ring counter and Johnson counter are designed using ‘n’ flip-flops, how many states will
and S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW each counter have?
and S1 is HIGH, data shifts left synchronously and new data is entered at the shift-left serial input. Q12. Design a 3 bit ring counter and find the mod of the designed counter.
Clocking of the flip-flop is inhibited when both mode control inputs are LOW. Q13. Draw the circuit diagram and timing waveforms of a four stage Johnson counter.
Ring Counter Q14. The minimum number of flip flops required to generate a sequence of 9 bits is ¬¬¬¬________.
If the output of the shift register is connected back to its input so that the output from the last flip- Q15. The maximum possible number of states in a clocked sequential circuit having 5 flip flops is
flop, QD becomes the input of the first flip-flop, DA. A closed loop circuit will be formed that ¬__________.
“recirculates” the same bit of DATA around a continuous loop for every state of its sequence, and this Q16. A 4 bit shift register, which shifts 1 bit to the right at every clock pulse, is initialized to values
is the principal operation of a Ring Counter. So a standard shift register can be converted to a ring 1000 for (Q0Q1Q2Q3). The D input is derived from Q0, Q2 and Q3 through two XOR gates as
counter by looping the output back to the input. shown in figure:
Johnson Counter
The Johnson Counter or Twisted Ring Counter, is another shift register with feedback exactly the
same as the standard Ring Counter above, except that this time the inverted output Q of the last flip-
flop is now connected back to the input D of the first flip-flop. The main advantage of this type of
counter is that it only needs half the number of flip-flops compared to the standard ring counter. So an
“n-stage” Johnson counter will circulate a single data bit giving sequence of 2n different states and
can therefore be considered as a “mod-2n counter”.
Self-Study Material
1. Digital Logic and Computer Design by Morris Mano, Pearson a. Write the 4 bit values (Q0Q1Q2Q3) after each clock pulse till the pattern (1000)
2. Fundamentals of Digital Electronics by Anand Kumar, PHI reappears on (Q0Q1Q2Q3).
b. To what values should the shift register be initialized so that the pattern (1001) occurs
3. lms.ncuindia.edu
after the first clock pulse?
Q17. Choose the correct one from among the alternatives A, B, C, D after matching an item from Lab Report
Group 1 with the most appropriate item in Group 2.
Group 1 Group 2
P: Shift Register 1: Frequency division Write the following:
Q: Counter 2: Addressing in memory chips
Objective:
R: Decoder 3: Serial to Parallel data conversion
a. P – 3, Q – 2, R – 1 b. P – 3, Q – 1, R – 2
c. P – 2, Q – 1, R – 3 d. P – 1, Q – 2, R – 2
Q18. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On Apparatus Required
the sixth clock pulse, the sequence is ________.
Q19. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble Software Required:
1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift
register is storing ________.
Procedure
Q20. To operate correctly, starting a ring counter requires:

a. clearing one flip-flop and presetting all the others.
b. clearing all the flip-flops.
c. presetting one flip-flop and clearing all the others.
d. presetting all the flip-flops.
Pin diagram Shift Register (IC 74194) Paste print out of the Schematic diagram and the required waveforms
Circuit Diagram Shift Register
Marks for write-up (Max. Marks 3) _______

Marks for experiment performance (Max. Marks 4)__________

Faculty signature with Date Total Marks Faculty signature with Date ____________________ Total Marks _______________________
Experiment No.: 10 Suggested Preparatory Question Bank

Q1. What is the difference between asynchronous and synchronous counters?
Q2. How many Flip Flops are required to build a binary counter that counts from 0 to 1023.
Date of Performance _________________ Q3. How many flip flops are needed to make a mod-10, mod-16 and mod-32 counter and why?
Q4. Using four cascaded counters with a total of 16 bits, how many states must be deleted to
Objective achieve a modulus of 50,000?
Validate the operation of decade counter practically and through simulation using IC 7490 & drive a Q5. Explain Lock-out condition in counters.
seven-segment display using the same. Q6. Design 4-bit up ripple counter.
Introduction to the experiment Q7. Design mod-5 counter using T flip-flops.
A counter is one of the most useful & versatile subsystem in a digital system. A counter driven by a Q8. When two counters are cascaded, the overall MOD number is equal to the ________ of their
clock can be used to count number of clock cycles. Since the clock pulses occur at regular intervals, individual MOD numbers.
the counter can be used as an instrument for measuring time & therefore period or frequency. Q9. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input
clock frequency is 60 MHz.
The IC 74LS90 is a 4-bit ripple type Decade Counter. It consists of four master/slave J-K flip-flops
which are internally connected to provide a divide-by-two section and a divide-by-five (LS90) Q10. Which segments of a seven-segment display would be required to be active to display the
section. Each section has a separate clock input which initiates state changes of the counter on the decimal digit 2?
HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because Q11. How many flip-flops are required to construct a decade counter?
of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should Q12. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
not be used for clocks or strobes. propagation delay. The total propagation delay (tp(tot)) is ________.
The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input Q13. Three cascaded modulus-5 counters have an overall modulus of ________.
of the device. A gated AND asynchronous Master Reset (MR1 • MR2) is provided on all counters
Q14. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does
which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master
the counter go on the next clock pulse?
Set (MS1 • MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the
outputs to nine (HLLH). Q15. Design a mod-12 synchronous UP counter using D flip flops.
Q16. By default counters are incremented by_________.
Since the output from the divide-by-two section is not internally connected to the succeeding stages,
the devices may be operated in various counting modes. For Decade Counter — The CP1 input must Q17. A ripple counter’s speed is limited by the propagation delay of___________.
be externally connected to the Q0 output. The CP0 input receives the incoming count and a BCD Q18. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple)
count sequence is produced. counters because the¬¬¬_____________________________________.
Self-Study Material Q19. Match the following sequential Circuits with associated functions
1. Digital Logic and Computer Design by Morris Mano, Pearson 1. Counter -------- A. Storage of Program & data in a digital computer
2. Fundamentals of Digital Electronics by Anand Kumar, PHI 2. Register -------- B. Generation of timing variables to sequence the digital system operations
3. Memory --------- C. Design of Sequential Circuits
3. lms.ncuindia.edu
Codes:
a. 1-A , 2-B , 3-C
5. http://etech.atu.edu/student.html b. 1-C , 2-B , 3-A
6. http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001 c. 1-C , 2-A , 3-B
7. https://old.uqu.edu.sa/files2/tiny_mce/plugins/filemanager/files/4281665/digital/digital_design- d. 1-B , 2-C , 3-A
__morris_mano-fifth_edition.pdf Q20. The terminal count of a modulus-11 binary counter is ________.
8. https://www.seattleu.edu/media/college-of-science-and-engineering/files/departments/electrical
andcomputerengineering/74ls90092e.pdf
Lab Report Pin diagram Decade counter (IC 7490)


Objective:
Apparatus Required
Software Required:
Procedure
Circuit diagram Decade counter (IC 7490)

Paste print out of the Schematic diagram and the required waveforms Observation Table


Objective
Analyze the characterstics of propagation delay time, fan out and Noise Margin of the transistor –
transistor logic (TTL) family and Complementary Metal Oxide Semiconductor Logic (CMOS)
family.
Logic gates are classified not only by their logical functions, but also by their logical families. In any
implementation of a digital system, an understanding of a logic element's physical capabilities and
limitations, determined by its logic family, are critical to proper operation.
The logic family refers to the general physical realization of a logical element, such as the TTL,
emitter-coupled logic (ECL), or complementary metal-oxide semiconductor (CMOS) logic families.
Within each logic family are one or more logic series that have distinctive characteristics, relative to
other series within the same logic family. For example, in the TTL logic family, there are several
logic series: the 74 standard, 74L low-power, 74H high-speed, 74S standard Schottky, 74LS low-
power Schottky series, and 74ALS advanced low-power Schottky series.
TTL FAMILY
The TTL family was the most widely used logic family for several years, characterized by its
relatively high speed operation. However, it has now been largely replaced by CMOS logic. The
physical representation of the binary logic states in these families are high and low voltages.
Assuming positive logic, in the 74LS TTl family LOW (L) voltages in the range 0 V to 0.8 V are
considered to be logic 0, and HIGH (H) voltages in the range 2.0 V to 5.5 V are considered to be
logic 1.
CMOS FAMILY
CMOS logic is exemplified by its extremely low power consumption and high noise immunity.
Hence, it is prevalently used in devices demanding low power dissipation, such as digital
wristwatches and other battery powered devices, or in devices operated in noisy environments, such
as industrial plants. A wide variety of CMOS logic devices in the 4000 series are available.
Unlike TTL logic, CMOS logic requires two supply voltages, VDD and VSS. In typical logical designs,
VDD ranges from +3 V to +16 V. The other supply, VSS, is normally grounded. Also, the physical
representation of the binary states in CMOS logic is not entirely compatible with TTL logic. As a
consequence of CMOS's extremely high input impedance, the logic levels in CMOS systems are
essentially VDD and ground. If, for example, a 5 volt power supply is used, LOW typically ranges
from 0 to 0.01 V and HIGH from 4.99 to 5.0 V for CMOS outputs.
Self-Study Material
Quiz Marks (Max. Marks 3) _____________________________ 2. Fundamentals of Digital Electronics by Anand Kumar, PHI
Faculty signature with Date ____________________ Total Marks _______________________ 3. lms.ncuindia.edu
5. http://basicelectronics.iitkgp.ernet.in/view2.php?link=T004&courseId=C001 Lab Report
6. https://old.uqu.edu.sa/files2/tiny_mce/plugins/filemanager/files/4281665/digital/digital_design-
__morris_mano-fifth_edition.pdf
Suggested Preparatory Question Bank Write the following:
Q1. The full forms of the abbreviations TTL and CMOS in reference to logic families are Objective:
______________________________________________________________________.
Q2. As compared to TTL, ECL has_______________________________________.
Q3. As compared to TTL, CMOS logic has______________________________.
Apparatus Required
Q4. Which logic family has the highest power dissipation per gate
a. ECL b. TTL c. CMOS d. PMOS
Q5. Advanced low power schottky is a part of Software Required:
a. ECL family b. CMOS family c. TTL family d. None of the above
Q6. The time needed for an output to change as the result of an input change is known as Procedure
___________________________.
Q7. A TTL totem pole circuit is designed so that the output transistors are
__________________________.
Q8. Low power consumption achieved by CMOS circuits is due to which construction
characteristic?
Q9. What is the standard TTL noise margin?
Q10. The problem of interfacing IC logic families that have different supply voltages (VCCs) can be
solved by using a_____________________________________.
Q11. What is meant by the fan-out of a logic gate?
Q12. The noise immunity of CMOS gates is typically ___________ of the supply voltage.
Q13. What is meant by the rise time of a waveform?
Q14. What is the cause of storage time in a bipolar transistor?
Q15. If power dissipation and propagation delay in a logic circuit are estimated to be 55mW and
20ns respectively, what will be its figure of merit?
Q16. Suppose that the digital IC family has a fan out of 6. It implies that the gate can supply the
current to _______ of same family.
Q17. Which type of unipolar logic family exhibits its usability for the applications requiring low
power consumption?
Q18. Which among the bipolar logic families is specifically adopted for high speed applications?
Q19. Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and
ICCL = 23 mA. What is the power dissipation for the chip?
Q20. The term buffer/driver signifies the ability to provide low output currents to drive light loads.
True/False.
Marks for write-up (Max. Marks 3) ______________

Observations II. Voltage Transfer Curve

1. CMOS Operation a) Plot the voltage transfer curves of both the TTL & CMOS gates as determined in lab.
a) Complete the voltage level table from the results determined in the lab for a CMOS
CD4001 integrated circuit:
b) What is the resulting truth table assuming positive logic? What logic function has been
realized?
c) What is the resulting truth table assuming negative logic? What logic function is realized
in this case?
b) On the plot s above illustrate graphically the procedure for determining the gates'
threshold voltages. What are the resulting threshold voltages?
c) Illustrate graphically the procedure for deter mining VIL and VIH for a TTL gate. What
are the DC0 and DC1 noise margins for this gate? Show how they were determined.
III. Rise and Fall Times V. Propagation Delay

a) On the graph below, plot both output waveforms resulting when a 307.2 kHz square a) Plot the output waveforms observed in part E of this experiment to determine the
wave is applied to a CMOS gate and a TTL gate. propagation delay through CMOS gates.
b) Which device family for this device, TTL or CMOS, has the faster rise and fall times?
IV. Noise Margin
a) What is the DC0 noise margin measured for the CMOS gate?
b) As a result of this measurement and the results in II c) for determining the noise margin
of TTL devices, which device family would be the best candidate to use in designing
digital circuits for an electrically "noisy" environment?
b) What is the resulting average propagation delay per gate? Indicate how it was
determined. Compare it with the average propagation delay of a TTL gate (e.g., a
74LS04 inverter) as listed in a TTL data sheet.
b) If this degradation of the power supply is left unchecked in large circuits, circuit
VI. Capacitive Loading operation can become impaired. The many gate outputs switching at any moment will all,
for a brief moment, attempt to draw huge amounts of current simultaneously. The power
a) Graph the two output waveforms obtained in Part F below: supply may not be able to satisfy this sudden demand for current. How can this problem
be circumvented?
VIII. Summary
Write a concise description of the device characteristics measured for TTL and CMOS logic in
this experiment. Contrast the measurements for TTL with those made for CMOS. From this
comparison, determine which design criteria would favor the use of TTL logic and which
would favor the use of CMOS.
Effects of Capacitive Loading

b) What effect does capacitive loading have on the rise and fall times of gate outputs?
Calculate the rise and falls times with and without capacitive loading.
VII. Current Spiking
a) Graph the gate output and voltage supply waveforms obtained in Part G.
Marks for experiment performance (Max. Marks 4)__________

Current Spiking
Faculty signature with Date_________________ Total Marks ____________


Objective
To Recognize various components of personal computer.
Introduction to the Experiment
Computers come in all types and sizes. there are basically two main sizes of Computer
1. Portable
2. Desktop
The Portable Computer Comes in various Sizes and called as laptops , notebooks and hand held
computers. these generally denotes different sizes , the laptop being the largest and hand held is the
smallest size. this document mainly talks about the desktop computer although portable computer
issues are also discussed in various areas.
Computer Components:
The basic components are defined as follow
1. Case with hardware inside:
a) a power supply comes with the case but this component is mentioned separately but this
component is mentioned separately since there are various types of power supplies . the one you
should get defined on the requirements of the system. this will be discussed in more detail later.
Motherboard: This is where the core component of computer resides which are listed below . also
the support card for video , sound , networking and are mounted to this board.
Microprocessor: this is the brain of the computer . it performs commands and instructions and
controls the operation of the computer.
Diagram of Motherboard:

MEMORY: the RAM in your system is mounted on the motherboard. this is memory that must be 5 FDD
powered on to retain its contents.
6 DVD
HARD DISK DRIVES: this is where your files are permanently stored
7 TFT/CRT
CU: It is the unit which controls the flow of information through the processor and coordinate the
activities the activities of other unit which are within it. 8 Keyboard
So it is the brain within the brain as it controls what happens inside the 9 Mouse
Processor. It generate timing signal and control signal for well coordination. 10 UPS
MEMORY UNIT: 11 Cabinet

It stores the information by providing facility to the CPU actively by providing necessary data to CPU. 12 Speaker
Memory units are of two types:
1. Primary memory Self Study Material
2. Secondary memory 1. Computer Architecture and Organisation by Morris Mano , Pearson
Primary Memory : It is also of two types 2. Computer Organisation and Architecture by Stallings
RAM: It can be randomly accessed. Memory is temporarily used because when the power goes off , all 3. Computer Architecture and Organisation by John P Hayes
the data stored in it are erased. So it is volatile in nature. It can be read and the data can be written into Quiz:
it.
http://cse.iitkgp.ac.in/~chitta/coldvl/memory.html
ROM: It is also randomly accessed. It is only read memory unit .It is non-volatile in nature It can be
read only but datas can’t be written into it Suggested Preparatory Question Bank
1. Explain Motherboard in Personal Computer?
ALU:- It performs arithmetic operation like addition, subtraction etc and logical operation like
AND,OR,NAND etc. It works in electronic speed but the device attached to it works in low speed. 2. Devices that accepts data from outside computer and transfer into CPU are called
That’s why processor can handle all the peripheral devices at a time. 3. Define Central Processing Unit (CPU)?
CU: It is the unit which controls the flow of information through the processor and coordinate the 4. Name the Devices which are used to receive data from central processing unit?
activities the activities of other unit which are within it. So, it is the brain within the brain as it controls 5. What are some common input devices for a computer system?
what happens inside the processor. 6. Explain the Function of ALU?
Keyboard: It is a primary input device of the PC similar to type writer. 7. Define the Output Devices of Personal Computer?
Mouse: It is used to point to the desired position in the computer. It is also an input device. 8. Write the Function of Hard Disk Drives in personal Computer?
UPS : It is the device that produce supply to the PC. 9. Write the Differences Between the primary and Secondary Memory?
10. Define HDD and FDD in Personal Computer?
UPS: It is the device that produce supply to the PC.
11. Notebook PCs fall into a category of devices called?
Speaker: It is an output device through which CPU can produce sound for the user.
12. How you divide a hard disk into tracks?
Observation Table: 13. Define all the physical parts of computer?
S.no Name of Name of Capacity/ Interface 14. Explain the Graphical User Interface in personal computer?
Component Manufacturer Frequency
15. Explain the difference between volatile and non volatile memory?
1 Processor
2 Motherboard
3 RAM
4 HDD


Objective:
Apparatus Required
Software Required:
Procedure
Circuit Diagram

Paste print outs of schematic diagram and the required waveforms. Observation Table


Objective
Design of 4 bit Arithmetic Logic Unit (With AND , OR, XOR , ADD Operation) Using Virtual Lab.
1. Start the simulator as directed. This simulator supports 5-valued logic.
2. To design the circuit we need 4 1-bit ALU, 11 Bit switch (to give input, which will toggle its
value with a double click), 5 Bit displays (for seeing output), wires .
3. The pin configuration of a component is shown whenever the mouse is hovered on any canned
component of the palette. Pin numbering starts from 1 and from the bottom left corner
(indicating with the circle) and increases anticlockwise.
4. For 1-bit ALU input A0 is in pin-9,B0 is in pin-10, C0 is in pin-11 (this is input carry), for
selection of operation, S0 is in pin-12, S1 is in pin-13, output F is in pin-8 and output carry is
pin-7
5. Click on the 1-bit ALU component (in the Other Component drawer in the pallet) and then
click on the position of the editor window where you want to add the component (no drag and
drop, simple click will serve the purpose), likewise add 3 more 1-bit ALU (from the Other
Component drawer in the pallet), 11 Bit switches and 5 Bit Displays (from Display and Input
drawer of the pallet ,if it is not seen scroll down in the drawer), 3 digital display and 1 bit
Displays (from Display and Input drawer of the pallet ,if it is not seen scroll down in the
drawer)
6. To connect any two components select the Connection menu of Palette, and then click on the
Source terminal and click on the target terminal. According to the circuit diagram connect all
the components. Connect the Bit switches with the inputs and Bit displays component with the
outputs. After the connection is over click the selection tool in the pallete.
7. See the output, in the screenshot diagram we have given the value of S1 S0=11 which will
perform add operation and two number input as A0 A1 A2 A3=0010 and B0 B1 B2 B3=0100
so get output F0 F1 F2 F3=0110 as sum and 0 as carry which is indeed an add operation .you
can also use many other combination of different values and check the result. The operations
are implemented using the truth table for 4 bit ALU given in the theory.
Circuit Diagram:

Components : Answers to quiz

To build any 4 bit ALU, we need :
1. AND gate, OR gate, XOR gate
2. Full Adder,
3. 4-to-1 MUX
4. Wires to connect.
In case of counters the number of flip-flops depends on the number of different states in the counter
Self Study Material:
1. Digital Logic and Computer Design - M. Morris Mano. Pearson Education - Prentice Hall.
2. Computer Architecture and Organization - John P. Hayes
3. Digital Principles Foundation of Circuit Design and Application - Arun Kumar Singh. New
Age Publishers.
4. The Art of Electronics - Paul Horowitz and Winfield Hill (1989). Cambridge University Press
5. Modern Dictionary of Electronics - Rudolf F. Graf (1999). Newnes
Quiz:
http://cse.iitkgp.ac.in/~chitta/coldvl/alu.html
Experiment:
http://cse.iitkgp.ac.in/~chitta/coldvl/alu.html
Suggested Preparatory Question Bank:
1. What ALU stands for ?
2. How a computer stores binary numbers?
3. Define Logic gates ?
4. How 3 is represented in a computer?
5. Define Transistor switches?
6. The differences between NOT, OR, AND, and XOR logic gates?
7. How logic gates make it possible to perform arithmetic operations?
8. What does a computer use to store binary numbers?
9. What is a logic gate?
10. How an ALU Works?
11. Explain bitwise operators in ALU?
12. Name the ‘heart’ of the processor which performs many different operations ?
13. Explain Boolean operators in personal computer?
14. How many units of ALU in pc?
15. Explain difference between combinational and sequential logic circuit?

Experiment No.: 14 Answers to quiz
Objective
Design and simulate Encoder, Decoder, Multiplexer and Demultiplexer.
Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit
that converts coded inputs into coded outputs, where the input and output codes are different e.g. n-
to-2n , binary-coded decimal decoders. Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address decoding.
Encoder
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on output N
lines. If a device output code has fewer bits than the input code has, the device is usually called an
encoder.
Multiplexer
In electronics, a multiplexer or mux is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines,
which are used to select which input line to send to the output. An electronic multiplexer can be
considered as a multiple-input, single-output switch i.e. digitally controlled multi-position switch.
The digital code applied at the select inputs determines which data inputs will be switched to output.
Demultiplexer
A demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-
output-lines, which is connected to the single input. A multiplexer is often used with a
complementary demultiplexer on the receiving end. A demultiplexer is a single-input, multiple-output
switch. Demultiplexers take one data input and a number of selection inputs, and they have several
outputs. They forward the data input to one of the outputs depending on the values of the selection
inputs.
Procedure:
1. Log onto vlab.co.in.
2. Go to link: http://hecoep.vlabs.ac.in/List%20of%20experiments.html?domain=Electronicsand
Communications
3. Go to experiment 5 (Design and Simulation of Decoders, Encoders, Multiplexer and
Demultiplexer).
4. Follow the instructions and perform the experiment. Quiz Marks (Max. Marks 3) _____________________________
5. After performing experiment, do the Post Test.
New Experiment (If any) Student’s Work Area
Objective
Student’s Work Area Student’s Work Area

Student’s Work Area Project Report

Project Report Project Report

Project Report Notes/Comments

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116 Digital Electronics and Computer Architecture Lab Workbook
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Signature of Student: ___________________

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Digital Electronics

and Computer Architecture

DR. SHARDA VASHISTH

School of Engineering & Technology

The NorthCap University

Published by: PREFACE

CONTENTS 3.8 Experiment No.- 8 58

1 Introduction viii 3.10 Experiment No.- 10 74

3.2 Experiment No.- 2 11 Virtual Lab Experiments

3.5 Experiment No.- 5 33 Project Report 109

3.6 Experiment No.- 6 39

3.7 Experiment No.- 7 48

Department of Electronics and Communication Practical Content

1. INTRODUCTION 2.2 Attendance

• The lab report must contain the following: 3. INDEX RollNo:.......................

6. Print out of software/programs and results wherever applicable.

Suggested List of Projects Experiment No.: 1

3) Traffic light control

Write the following:

Q4. Draw the truth table of coincidence logic gate.

Marks for write-up (Max. Marks 3)

Faculty signature with Date ____________________

Answers to Quiz Experiment No.: 2

Quiz Marks (Max. Marks 3) _____________________

Suggested Preparatory Question Bank Lab Report

Q9. State Demorgan’s Laws.

Ex-OR using 5 NOR gates only.

Marks for write-up (Max. Marks 3)

Observation Table (Truth Table) Answers to quiz

Faculty signature with Date Quiz Marks (Max. Marks 3) _____________________________

Suggested Preparatory Question Bank

In this experiment the students are expected to

Write the following:

Full Adder Circuit

Marks for write-up (Max. Marks 3)

Faculty signature with Date

Answers to quiz Experiment No.: 4

In this experiment the students are expected to

Quiz Marks (Max. Marks 3) _____________________________ 6. http://etech.atu.edu/student.html

Suggested Preparatory Question Bank Lab Report

Table for converting binary code to gray code Circuit Diagram

Marks for write-up (Max. Marks 3) _______________________

Faculty signature with Date

Marks for experiment performance (Max. Marks 4)

Answers to quiz Experiment No.: 5

Write the following:

Q11 BCD to 7 segment is a …………..

Table for designing BCD to 7-segment decoder Observation Table

Faculty signature with Date

Marks for write-up (Max. Marks 3)

Answers to quiz Experiment No.: 6

Quiz Marks (Max. Marks 3) _____________________________

Faculty signature with Date ____________________ Total Marks _______________________

Q18 Subtract the following binary numbers (1101)2 – (0011)2

Lab Report Pin Diagram

Write the following:

Circuit Diagram (Subtractor with 7483 IC)

Marks for write-up (Max. Marks 3)

Observation Table Answers to quiz

Faculty signature with Date Quiz Marks (Max. Marks 3) _____________________________

Marks for experiment performance (Max. Marks 4)

Q4 A decoder can be used as a demultiplexer by

In this experiment the students are expected to

Faculty signature with Date Total Marks ___

Faculty signature with Date_____ Total Marks