University of Baghdad

College of Engineering
Department of Computer

Effect of Sampling Frequency

On The Steady-State Error
Of Discrete-Time Systems

By the undergraduate student:

Ghadeer Hayder Abood

Submitted to:
Dr. Omar Abdulwahhab

2020
 Abstract

The impact of sampling frequency on the absolute and relative stability of the closed-

loop system ought to be explored. This report will explore the effect of sample

frequency on the steady-state error of discrete-time systems after modifying each of

discrete-time signal, sampling process and steady-state error, also, calculate it.

Introduction

A feedback control system is profitable since it gives the engineer the ability to alter

the transitory reaction. In expansion, the affectability of the system and the impact

of unsettling influences can be diminished essentially.[1]

Discrete-Time Systems And Sample Process

the digital signal is discrete in both time and amplitude. For changing a signal from

continuous-time to discrete-time, a process called sampling is utilized. The esteem

of the signal is measured at certain intervals in time. Each estimation is alluded to as

a sample. (The analogue signal is also quantized in amplitude, but that process is

ignored in this demonstration(.

A linear, time-invariant, single-input, single-output (SISO) plant a computerized

dynamic controller has been planned so that the comparing discrete-time linear

feedback control system will fulfil specific indicated steady-state error criteria.

Comparing to the over-idealized direct framework, the computerized

implementation of the energetic controller will result in a nonlinear feedback control

system. Within the display note, we examine to what degree the resulting nonlinear

digital criticism control framework fulfils the steady-state error criteria of the first

idealized linear model input control framework. We consider advanced controller

executions that utilize fixed-point arithmetic or floating-point arithmetic. We assume

designs which are well scaled, i.e., we don't address overflow nonlinearities in digital

controllers.[2]

Steady-State Error

A steady-state error is characterized as the contrast between the required value and

the genuine value of a system when the response has reached a steady state. We will

calculate the steady-state error of the system utilizing the final value theorem. This

theorem is given for the unit feedback system in Fig.1 as

Fig.1. Unit feedback system. [3]

we must look at and compare the final steady-state error for an open-loop and a

closed-loop system. The steady-state error is the error after the transitory response

has rotted, taking off as it were the ceaseless response. The error of the open-loop

system shown in Figure 2.

Fig.2. An open-loop system with a disturbance input, T(s). (a) Signal-flow graph,

(b) Block diagram.

when T(s) = 0. Figure.3 shows the closed-loop system. When T(i(s) = 0 and N(s) =

0, and we let H(s) = 1,

Figure 3. A closed-loop control system. (a) Signal-flow graph, (b) Block diagram.

But To calculate the steady-state error, we use the final-value theorem as we

mentioned above. [1]

Effect of sampling frequency on the steady-state error

making the sampling period smaller permits the basic gain to be bigger, i.e., the

greatest passable gain can be made bigger by expanding the sampling frequency

/rate. It appears from the illustration that damping proportion decreases with the

decrease in T. Still, one ought to take note that the damping ratio of the closed-loop
poles of a digital control system demonstrates the relative stability as it were in case

the examining frequency is adequately high (8 to 10 times). In case it isn't the case,

the forecast of overshoot from the damping ratio will be incorrect, and in practice,

the overshoot will be much higher than the anticipated one. Next, we may explore

the effect of T on the steady-state error. Let us take a settled gain K = 2. When T =

0.5 sec.

It is a second-order system, and velocity error constant will be a non zero finite

quantity.

When T = 1 sec. and K = 2

When T = 2 sec. and K = 2

[4]

Conclusion

In case the signals at one or more points of a system can alter as it were at discrete

values of time, the system is known as a ‘‘discrete’’ or ‘‘sampled-data’’ system.

Such systems, for the most part, contain components working on continuous signals,

components operating on discrete signals, devices for changing continuous to

discrete data (as a rule known as samplers), and devices for changing discrete to

continuous data (ordinarily known as hold circuits). The sampling operations are

regularly periodic but may be arbitrary. Thus, expanding the examining period

(decreasing sampling frequency) has an antagonistic effect on the steady-state error

as well.
Refrences

[1] R. B. Richard Dorf, Modern Control Systems, TWELFTH ED. .

[2] A. J. A. F. R. K. MILLER, A. N. MICHEL, “Quantizer Effects on Steady-State

Error Specifications of Digital Feedback Control Systems R.,” vol. 34, no. 6,

pp. 651–654, 1989.

[3] C. Of and D. Current, Control of direct current motors 2, no. Dc. 2017.

[4] D. Control, “Module 5 : Design of Sampled Data Control Systems Lecture

Note 1,” vol. 0, pp. 1–6.