5592
10, OCTOBER 2014
Multilevel Direct Power Control—A Generalized
Approach for Grid-Tied Multilevel
Converter Applications
Sebastian Rivera, Student Member, IEEE, Samir Kouro, Member, IEEE, Bin Wu, Fellow, IEEE,
Salvador Alepuz, Senior Member, IEEE, Mariusz Malinowski, Member, IEEE, Patricio Cortes, Member, IEEE,
and Jose Rodriguez, Fellow, IEEE
Abstract—This paper presents a generalized multilevel direct
power control (ML-DPC) scheme for grid-connected multilevel
power converters. The proposed method extends the original DPC
operating principle by considering only the closest subset of two-
level voltage vectors to the present switching state. The implemen-
tation of this principle requires the power derivatives for feedback,
which can present numerical problems when applied experimen-
tally, mainly due to high measurement noise sensitivity. Therefore,
a derivative estimator is proposed based on the converter–grid
model in the synchronous reference frame. In addition, a virtual
flux observer is developed to achieve synchronization and improve
robustness in the presence of grid voltage harmonics. The pro-
posed method is applicable to any multilevel converter topology of
any number of levels. In this paper, simulations and experimental
results are presented for a seven-level cascaded H-bridge converter.
Index Terms—Direct power control (DPC), grid connection,
multilevel converters.
I. INTRODUCTION
NDUSTRIAL processes have increased substantially their
I size and capacity over the last years. This has been caused
mainly by economies of scale, and the constant search to in-
crease the production levels and efficiency. This has resulted in
higher power ratings for the power converters and electric drives
applications. Currently, multilevel converters have become a
mature technology and are widespread found in medium-voltage
and high-power industrial processes [1]. Renewable energy con-
Manuscript received February 22, 2013; revised July 1, 2013 and October
31, 2013; accepted November 9, 2013. Date of current version May 30, 2014.
This work was supported by SERC Chile (CONICYT/ FONDAP/15110019), by
CCTVal (FB0821), and by Fondecyt 1131041. Recommended for publication
by Associate Editor J. Liu.
S. Rivera and B. Wu are with the Department of Electrical and Com-
puter Engineering, Ryerson University, Toronto ON M5B 2K3 Canada (e-mail:
srivera@ee.ryerson.ca; bwu@ee.ryerson.ca).
S. Kouro, P. Cortes, and J. Rodriguez are with the Department of Electronic
Engineering, Universidad Tecnica Federico Santa Maria, 1680 Valparaiso, Chile
(e-mail: samir.kouro@usm.cl; patricio.cortes@usm.cl; jrp@usm.cl).
S. Alepuz is with the Mataró School of Technology (Tecnocampus Mataró-
Maresme), Technical University of Catalonia, 08302 Mataró (Barcelona), Spain
(e-mail: alepuz@eupmt.es).
M. Malinowski is with the Institute of Control and Industrial Electronics,
Warsaw University of Technology, 00-661 Warsaw, Poland (e-mail: malin@
isep.pw.edu.pl).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2294711
0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.
version systems are also reaching higher power levels and are
now in the multimegawatt range [2]. Therefore, the use of multi-
level converters as grid interface has become increasingly attrac-
tive for these applications [3], in order to meet higher efficiency
requirements, more demanding grid codes for both wind and so-
lar photovoltaic (PV) systems to provide support for the power
network, and the continuous increase in their size and power
capacity.
The permanent magnet synchronous generator-based wind
energy conversion systems (WECS) using fully rated power
converter has become the state-of-the-art solution for large size
multimegawatt wind turbines. Currently, commercially avail-
able turbines reach up to 7.5 MW [4], putting the traditional
two-level voltage source converter (2L-VSC) to its limits. In
fact, the industrial solution is to parallel several converters to
reach the power rating, without any additional benefit in terms
of power quality and efficiency. Therefore, there is a growing
search for new multilevel converter-based configurations for
grid connection of WECS [5], [6].
On the other hand, photovoltaic (PV) energy conversion sys-
tems have shown a clear trend to increase their capacity up to
large-scale PV plants over the last years. Cumulative worldwide
installed capacity has reached 70 GW as of 2011; equivalent to a
fourth of the wind energy cumulative installed capacity [7]. This
has been mainly driven by the reduction of PV module cost, feed-
in-tariff incentives, environmental concerns, and higher costs of
fossil fuels. Utility scale PV systems are a reality and currently
there are over 50 PV plants over 30 MW worldwide, being the
largest one in operation located in Yuma County, AZ, USA, with
a nominal capacity of 250 MW [8]. These systems are interfaced
to the grid mostly using the centralized or multistring configu-
rations with 2L-VSC [9]. Hence, to reach the total capacity of a
power plant, several converters are needed, presenting the same
challenges as in wind power applications. Therefore, multilevel
grid-tied converters have also been proposed for PV applica-
tions [10], [11]. It is important to note that insulation ratings
of standard commercial PV modules are currently of 1000 V,
which limits the dc-link capacitor voltages of the multilevel
converter, preventing connection to medium voltage grids, and
therefore may require an additional dc–dc stage with high fre-
quency galvanic isolation and voltage boost capability as in [11],
or the use of a larger number of cells per phase (in the case of
multicell converters) to overcome this limitation. Nevertheless,
multilevel converters have already been used commercially for
RIVERA et al.: MULTILEVEL DIRECT POWER CONTROL
low-voltage grid-connected PV systems [9], [12], [13], where
the voltage insulation limitation is not a problem, due to their
power quality and efficiency.
Not only renewable energy power conversion systems re-
quire high power rates at the grid side, but also several high-
performance adjustable speed drive applications with regener-
ative operating conditions, such as train traction and downhill
conveyors, require fully rated high power active front end rec-
tifiers at the grid side, to enable an energy path back to the grid
during regenerative braking [14].
As for the control of grid-connected converters, there are
basically two control methods applied to the conventional 2L-
VSC: voltage-oriented control (VOC) [15], which is based in
the use of linear controllers and a modulation stage; and the
direct power control (DPC) [16], which directly uses the infor-
mation provided by the nonlinear hysteresis controllers to select
the voltage vector to be applied by the converter. These methods
provide a high dynamic performance beside the generation of
high-quality signals with a reduced harmonic content. VOC fea-
tures a modulation stage, which allows a good harmonic profile
in the steady state, but is limited in dynamic performance by the
response and robustness of the linear controllers. On the other
hand, DPC presents faster dynamics because of the nonlinear
nature of the controllers, with the disadvantage of larger ripples
in the power signals, and variable switching frequency. Inde-
pendently from the control scheme, the 2L-VSC will inherently
produce large dv/dts, poor power quality, and require higher
switching frequencies, compared to multilevel converters.
For multilevel converters VOC has no conceptual difference,
and can be easily extended since it only requires a change in
the modulation stage, which has to be modified to the suitable
multilevel modulation for the topology and application [17]. For
DPC however, the implementation is not straightforward, since
it is conceptually based on the relationship between a certain
voltage vector of the two-level converter and their direct influ-
ence on the active and reactive power. Since the possible vectors
generated by a multilevel converter increases overproportionally
to the number of levels, it becomes infeasible to apply the same
conceptual basis for the extension. Despite this fact, DPC has
been adapted to certain multilevel topologies [18]–[20]. How-
ever, these methods are applied to a specific converter, or for a
given number of levels, like the three-level neutral point clamped
(NPC) [18], [19], and the five-level active NPC [20].
This paper provides a generalized scheme for multilevel DPC
(ML-DPC) for grid-tied converters, regardless the topology or
the number of levels. The operating principle is based in the use
of hexagonal subspaces analogously to the direct torque control
(DTC) extension in [21]. This approach serves two purposes: re-
duce multiple level steps in the voltage waveform, hence dv/dts,
and simplify the vector selection to the traditional DPC. This
method retains the attractive features of classic DPC: fast hys-
teresis active and reactive power controllers, no need of linear
PI power controllers and modulation stage. It also overcomes
some of the main drawbacks of two-level DPC: large power rip-
ple due to the hysteresis controller. In addition, in this proposal
the concept of virtual fluxes presented in [22] is considered, in
5593
Fig. 1. Space vector equivalent circuit of a grid-connected multilevel
converter.
order to mitigate the effects of harmonic content usually present
in grid voltages.
In order to validate the proposed method, a seven-level Cas-
caded H-Bridge converter is used for both simulation and ex-
perimental results. The selection of this topology is based on its
potential for medium-voltage high-power grid connected appli-
cations. Recently, it has been proposed for traction drives [23],
PV energy conversion systems [11], [24], [25], wind energy [26],
reactive compensation [27], distributed generation [28], and
HVdc transmission [29], among others.
II. TWO-LEVEL VIRTUAL FLUX DIRECT POWER CONTROL
As in classic DTC, which regulates directly the torque and
flux of an inverter fed induction machine using a switching
table, it is possible to extend the same principle and control the
active and reactive power of a grid-tied converter. This scheme is
called direct power control (DPC) [16]. The performance of this
method can be improved by using the virtual flux concept [22],
obtaining the virtual flux direct power control (VFDPC).
This analogy can be illustrated by using the vector equivalent
circuit of the grid interfacing converter, shown in Fig. 1. If the
grid is seen as a virtual AC machine, whose line-to-line voltages
are induced by a virtual air gap, then the integration of the grid
voltage vector leads to a virtual flux vector Ψs . In the same
way, the integration of the converter voltage leads to a converter
virtual flux vector Ψc , i. e.,
 
Ψs = vs dt and Ψc = vc dt (1)
where vs and vc represent the grid and converter voltage vectors,
respectively.
On the other hand, the expression for active power is given
by
3
P = Re {vs i∗s } . (2)
2
By writing the grid voltage in terms of its virtual flux, replac-
ing the grid current by (Ψs − Ψc )/Ls , neglecting the voltage
drop across the resistor Rs , and using the synchronous dq ref-
erence frame (synchronized with Ψs ), the active power can be
expressed as a function of the virtual fluxes as
3ωs
P = Re {jΨs (Ψs − Ψc )∗ } . (3)
2Ls
This can be expressed in terms of its synchronous rotating frame
flux components (Ψs = ψsd + jψsq and Ψc = ψcd + jψcq )
yields to
3ωs
P =− ψsd ψcq . (4)
2Ls
5594
Fig. 2. Sectors division of the Stationary Frame for VF-DPC.
In the same way the reactive power can be expressed by
3ωs
Q= Im {jΨs (Ψs − Ψc )∗ } (5)
2Ls
repeating the previous analysis leads to
3ωs
Q=− ψsd (ψsd − ψcd ). (6)
2Ls
Then, as the virtual grid flux magnitude is constant, due to the
fact that the grid voltage amplitude does not vary under normal
operating conditions, from (4) and (6) it can be observed that the
term 1.5 ωs ψsd becomes a constant, and therefore the changes
in both active and reactive powers are proportional to each of
the synchronous components of Ψc , hence
ΔP ∝ −Δψcq and ΔQ ∝ −Δψcd . (7)
Furthermore, the discretization of (1) using the forward Euler
approximation and a sample period Ts , the relation between the
converter flux and its voltage becomes
Ψkc +1 = Ψkc + vck Ts ⇒ ΔΨkc +1 = vck Ts . (8)
To generate the switching table, the influence of each voltage
vector must be studied. To do so, the stationary frame will be
divided into 12 sectors as shown in Fig. 2, and the synchronous
frame is aligned with Ψs . The angular position of the grid flux
vector θs determines the operating sector. Using the example
given in Fig. 2 for sector 5 and the previous analysis, it can be
seen that the application of v3 will result in the increase of both
converter flux components ψcd and ψcq , which according to (7)
would reduce Q and P , respectively. Hence, if hP and hQ are the
outputs of the hysteresis controllers for P and Q, the choice of
v3 will be suitable for (hP , hQ ) = (0, 0) in sector 5. Extending
this concept through all sectors and possible combinations of
active and reactive power hysteresis controllers, the Table I is
generated.
Note that the zero voltage vectors v0 and v7 are also consid-
ered, since they both produce a lag between Ψc and Ψs (which
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014
TABLE I
VOLTAGE VECTOR SELECTION FOR CLASSIC DPC
Fig. 3. Classic two-level VF-DPC control diagram.
keeps rotating at ωs along with the synchronous frame), produc-
ing the increase of both P and Q. Since both vectors generate
the same voltage, they are alternated in order to distribute evenly
the usage of the switches of the converter.
The VFDPC scheme for a 2L-VSC is shown in Fig. 3. It can
be seen that the dc-link voltage vdc is controlled by a linear
PI controller, which provides the reference for the active power
P ∗ , while the reactive power reference Q∗ is set to zero for
unity power factor operation. Both powers are estimated from
measurements feedback, and as mentioned previously are con-
trolled with hysteresis comparators. Their outputs hP and hQ
along with θs are used to access the voltage vector lookup ta-
ble. Finally the table delivers the gating signals to generate the
selected voltage vector.
Unfortunately, this operating principle cannot be extended
directly to multilevel converters, because the increase of vectors
disables the direct link between the hysteresis controllers output
and the influence of each vector over P and Q. Therefore, a new
vector selection lookup table with the influence of each new vec-
tor needs to be developed, which is complex and increasingly
difficult for more levels. In addition, the traditional hysteresis
controller cannot be used to access those new entries to the
table. Therefore, particular adaptations have been proposed for
a given converter and number of levels [18]–[20]. Neverthe-
less, the growing number of multilevel converter topologies [3],
with different number of voltage levels, and their use in grid-
tied applications, has motivated the search for a more general
approach.
III. MULTILEVEL DIRECT POWER CONTROL
A. Multilevel Generalization of DPC Concept
The previous section establishes that it is possible to control
the active and reactive powers by using the voltage vectors gen-
erated by the converter. This concept is also valid for the vectors
generated by a multilevel converter. However, to determine the
RIVERA et al.: MULTILEVEL DIRECT POWER CONTROL
Fig. 4. Space vectors generated by a generic multilevel converter, and the
two-level Δ vectors closest to v ck .
influence of each one over P and Q for a particular sector, and
with the use of such simple controller as the hysteresis compara-
tor is not feasible. This selection, can be simplified by limiting
the vector selection to the closest vectors to the one previously
applied.
This approach not only reduces the complexity of the prob-
lem, but it also reduces the amplitudes of the dv/dts, and the
number of commutations to only one per vector change. Fig. 4
shows this concept for a generic multilevel converter, where
at t = k an arbitrary vector vck is shown with the surrounding
closest vectors. The difference between these vectors and vck
are the delta (Δ) vectors (Δvc1,...,6 ). In summary, the control
logic will be similar to classic DPC, with the difference that
now the lookup table will select Δvc instead of vc . Therefore,
their influence over P and Q needs to be studied. This can be
achieved by differentiating the power expressions (4) and (6),
which yields to
dP 3ωs dψcq dQ 3ωs dψcd
=− ψsd and =− ψsd . (9)
dt 2Ls dt dt 2Ls dt
This reflects that the changes in Ṗ and Q̇ are proportional to
the changes in ψ̇cq and ψ̇cd respectively, i. e.,
ΔṖ ∝ −Δψ̇cq and ΔQ̇ ∝ −Δψ̇cd . (10)
On the other hand, based on (1), the converter flux relates to
the applied voltage vector by
Ψ̇c = vc ⇒ ΔΨ̇c = Δvc . (11)
This equation is important as it highlights that the relation
between the change in the applied vector (Δvc ) and the slopes
of the active and reactive power (Ṗ and Q̇ respectively) is equiv-
alent to the relation observed between vc and the power signals
P and Q. For this reason, a similar operating principle of classic
DPC can be applied to multilevel converters. Note however, that
this yields to the Δ vector selection lookup given in Table II and
not the complete vector.
It is worth mentioning that in this approach is not suitable
to use the delta zero voltage vectors (Δvc0 and Δvc7 ). The
reason is that in classic DPC such selection means that vc = 0
and, according to (8), Ψkc +1 = Ψkc , causing an increase in the
active and reactive power. In the proposed ML-DPC scheme
5595
TABLE II
Δ VOLTAGE VECTOR SELECTION IN THE PROPOSED ML-DPC
instead, such selection does not necessarily means that vc = 0
and, according to
Ψkc +1 = Ψkc + vck −1 Ts + Δvck Ts (12)
the converter flux maintains its previous rate of change and
generally in the next sample period Ψkc +1 = Ψkc . This is why
the delta zero vectors are replaced by delta active vectors.
According to Table II, this scheme only selects the variation
for the voltage vector Δvck . Therefore, in order to generate the
corresponding voltage vector vck the delta component needs to
be added to the previously generated vector
vck = vck −1 + Δvck . (13)
Note that this criterion might suggest the notion that the dy-
namic response of the system will be reduced, as the vector
selection possibilities have been limited. However, the system
dynamics are mostly dominated by the outer voltage loop, which
due to its linear nature, it always offers a slower response than
the internal nonlinear DPC loop. In addition, this effect is negli-
gible when using higher sampling rates in the proposed scheme.
It is worth noticing, that the proposed vector selection technique
preserves the basic operating principle of classic DPC, by di-
rectly generating the selected space vector without modulation
or any type of duty cycle calculation.
The proposed scheme implies the control of Ṗ and Q̇, and
considering the behavior of the active and reactive powers in
steady state, the use of hysteresis comparators is no longer
needed. Instead, simple comparators are used to regulate the
derivatives of the power signals. Therefore, the control signals
generated by the comparators are renamed to cP and cQ as listed
in Table II.
The proposed control scheme is illustrated in Fig. 5. It is
possible to find some similarities with conventional DPC: a dc-
link voltage outer control loop (which varies depending on the
converter topology) provides the reference for the active power
P ∗ , while Q∗ is set arbitrarily depending on the application
requirements (for example reactive power compensation, unity
power factor, etc.).
Using these signals, the references for the power derivatives
are computed using the Euler forward approximation and the
notion of dead beat control according to
P ∗k − P k Q∗k − Qk
Ṗ ∗k = , Q̇∗k = (14)
Ts Ts
5596 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014

Fig. 5. Control scheme for the proposed virtual flux based ML-VFDPC.

Considering that the grid voltage vector is a sinusoidal signal

with frequency ωs a valid state space representation is
 
k +1
cos(ωs Ts ) sin(ωs Ts )/ωs
x = xk (15)
−ωs sin(ωs Ts ) cos(ωs Ts )
vsk = [ 0 1 ] xk . (16)
From (15), it can be seen that this representation leads to a
Fig. 6. Control scheme for the power derivatives. state vector xk comprised by both the grid voltage and virtual
flux components and, as the system is observable, is possible to
generate a gain J to estimate it using
and then compared with the estimated slopes (their obtention x̂k +1 = Φx̂k + J(vsk − Cx̂k ). (17)
will be described in the following section). These error signals
This leads to an estimation of Ψs without phase or ampli-
are fed to simple comparators, and its outputs are used to access
tude errors, and more importantly without using an integrator,
the lookup table along with the sector information, as it is de-
avoiding all its drawbacks.
tailed in Fig. 6. This selection of Δvc is used to synthesize the
For the power derivatives observer, consider the vector equiv-
required voltage vector according to (13) by the converter. The
alent shown in Fig. 1 and applying Kirchhoff voltage law holds
estimation of the virtual fluxes is obtained using the generated
voltage and the current measurements. Then, the angle θs is dis
vs = vc + Rs is + Ls (18)
extracted using a PLL, to determine the sector of the system. dt
2
Note that v̄dc has been considered for the control in the outer clearing the current derivative, replacing the grid voltage in
voltage loop (instead of v̄dc ), since by definition active power terms of Ψs and separating into its synchronous components
is proportional to the square of the dc-link voltage. In this way, leads to
there is a linear relation between the output of the PI controller  
disd 1 dψsd
(P ∗ ) and its input (v̄dc error). This simplifies the design of the PI = − ωs ψsq − vcd − Rs isd + ωs Ls isq
dt Ls dt
controller and improves its robustness. Finally, the estimation
of the power derivatives is done using the virtual fluxes and the (19)
measured currents with an observer.  
disq 1 dψsq
= + ωs ψsd − vcq − Rs isq − ωs Ls isd .
dt Ls dt

B. Ψs , Ṗ , and Q̇ Observers (20)

The presence of power derivatives imposes a challenge for Under the assumption that the grid virtual flux is sinusoidal,
the practical implementation of the proposed ML-VFDPC ap- it can be shown that the powers are proportional to each one of
proach. This is because the presence of measurement noise in is synchronous components. Extending this idea to the power
the signals used for the power estimation, which along with the derivatives, an estimator for these variables is given by
high-pass nature of the derivators can make the practical im- dP 3ωs
plementation unfeasible. To avoid this situation the proposed = ψsd (ωs ψsd − vcq − Rs isq − ωs Ls isd ) (21)
dt 2Ls
scheme will use an observer for Ṗ and Q̇. In addition, the esti-
dQ 3ωs
mation of Ψs using the conventional approaches leads to phase = ψsd (−ωs ψsq − vcd − Rs isd + ωs Ls isq ) .
errors in the synchronization of the system. A novel virtual flux dt 2Ls
observer is also proposed. (22)
RIVERA et al.: MULTILEVEL DIRECT POWER CONTROL 5597

This way of obtaining Ṗ and Q̇ is feasible in practice, as

no real derivations are performed. It is important to note that
the approximation made does not imply a sensitivity to distur-
bances in the supply voltage. This is due the low-pass nature
of the virtual flux observer, which attenuates dramatically the
effect of harmonics in the estimations of both powers and its
derivatives, improving the system performance when operating
with polluted grids.
Note that the flux observer block of Fig. 5 is given by (17).
In addition, the power and derivatives block shown in Fig. 5 is
composed by (4) and (6) to compute the powers, and (21) and
(22) for its derivatives.
Fig. 7. Power circuit of grid connected 7L-CHB and experimental prototype.
C. DC-Link Voltage Control
TABLE III
The generalized DPC method discussed in this paper depends SIMULATION AND EXPERIMENTAL PARAMETERS
on the voltage space vectors generated by the multilevel con-
verter, and is therefore independent on the topology (only the
switching table is modified with the corresponding switching
states). However, like with VOC, the outer dc-link voltage con-
trol loop is used to control the total average dc-link voltage of the
converter through the active power with a single PI controller.
Hence, depending on the topology and the number of individual
dc-link capacitors, an additional dc-link voltage balance scheme
is necessary. This issue is inherent to all grid-connected mul-
tilevel converters for both VOC and DPC schemes, since the
total dc-link is composed by more than one capacitor. This has
been addressed in previous works for the NPC [18], [30]–[32],
flying capacitor [33], CHB [11], [34], and MMC [35], [36],
to name a few. Note that in the case of VOC, a modulation
the individual dc-link capacitors of the converter, similar to the
stage is used, most commonly multilevel carrier-based PWM or
methods presented in [37] and [38].
multilevel SVM, in which case the balancing mechanism must
be added to the modulation stage. This is particularly difficult
in carrier-based PWM methods since the gating signals result IV. SIMULATION RESULTS
from direct comparison of references with triangular carriers, The performance of the scheme will be tested on a seven-
making the use of converter switching state redundancies not level CHB, as shown in Fig. 7, both in steady state and in
straightforward, for which PI controlled offsets are used to con- several dynamic scenarios faced by a grid-tied converter, which
trol the unbalance instead, which can lead to saturation of the are described as follows:
modulation stage. In SVM-based methods and the vector selec- 1) step change vdc ∗ ;
tion strategy of the proposed multilevel DPC scheme, redundant 2) step change Q∗ (both positive and negative values);
space vectors and switching states can be selected in the gate 3) load impact (both passive and active values).
signal sequence generation to balance capacitor voltages. How- However, considering that one critical aspect of the proposed
ever, this becomes increasingly complex when the number of method is the correct estimation of the power derivatives, and its
voltage levels in higher, since the number of possible redun- robustness to measurement noise, white noise has been added to
dancies increases overproportionally. Therefore, these solutions the current sensors (equivalent to 200 mA). In addition, to make
are only practical up to a certain number of voltage levels, usu- the scenario more realistic, the grid voltage has been distorted
ally below 13 (six-series-connected cells in cascaded H-bridge by adding the fifth and seventh harmonics, to challenge the
converters). performance of the proposed flux observer.
In this study, the experimental validation is performed using The distortion added to the grid voltage corresponds to a 4%
a three-cell per phase (seven-level) CHB. Hence, the outer dc- and 2% for the fifth and seventh harmonics, respectively, in order
link voltage control loop provides the total reference for the to emulate the laboratory grid voltage. The main simulation
active power, through the regulation of the average of the DC parameters are presented in Table III. All the simulations were
voltages, as shown in Fig. 5. However, the total power must made using MATLAB/Simulink and PSIM.
be shared among all cells in proportion to their deviation of To test the dynamic and steady-state performance of the pro-
their individual dc-link voltage. To achieve this the voltage- posed control method, three-step changes are performed: first in
level redundant switching state or redundant space vectors are the dc voltage reference and two successive step changes to the
used together with the sign of the grid current to properly control reactive power reference. All power cells of the converter start
5598
Fig. 8. Simulated ML-VFDPC dynamic performance for case I: (a) Active and reactive power, (b) grid currents and phase a grid voltage, (c) converter phase
voltage, (d) converter line-to-line voltage, and (e) total dc-link voltage phase a.
at vdc ∗ = 0.29 pu (total dc-link voltage is 0.87 pu), operating at
unity power factor Q∗ = 0 pu. At t = 0.52 s, the reference for
the dc-link voltages is changed to 0.33 pu (total dc-link voltage
is 1pu), forcing a total increase in the active power of 0.25 pu
reaching the rated operation condition. Then at t = 0.58 s, the
reference for reactive power is changed to Q∗ = −0.4 pu, and
the system begins to operate with capacitive (leading) power
factor. Finally, at t = 0.64 s the reference for reactive power is
changed to Q∗ = 0.4 pu, changing the operation to inductive
(lagging) power factor. The results are presented in Fig. 8.
Fig. 8 confirms the performance of the method. By study-
ing the power signals in Fig. 8(a), the method offers a fast
and smooth response to the different reference changes. This
confirms the previous statements that the limitation to act just
with the closest vectors does not reduce the dynamic response,
since the nonlinear controller of DPC is significantly faster than
the external linear control loop. Fig. 8(a), shows the differ-
ence between the inner and outer loops, as the active power
responds almost instantly reaching its saturation level until the
dc-link voltages get closer to its new value. Note that, despite
the changes involved in P , the reactive power is not disturbed
at all, confirming the decoupling of the proposed ML-VFDPC
method. This is confirmed later, when the active power does
not modify its reference tracking, while the reference for Q
is changed. Is important to highlight that both powers remain
controlled and offer a proper track for its references, despite
the presence of measurement noise in the current measurement,
confirming the immunity to high frequency disturbances of the
power derivative estimator.
Both, active and reactive power show extremely low ripple
compared to the classic two-level DPC schemes, due the higher
quality signals provided by the use of a multilevel converter as
a grid interface.
The currents, as shown in Fig. 8(b), present a highly sinusoidal
waveform during the whole simulation, despite the presence
of harmonic distortion in the grid voltage, thus validating the
proposed flux observer. Also, it can be seen that until t = 0.58 s
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014
the grid currents are kept in phase with the grid voltage, showing
that the observer does not introduce the phase error.
Then, the voltages generated by the converter, it can be seen
in Fig. 8 that present seven levels clearly defined, and a si-
nusoidal waveform, this implies that the balancing mechanism
for the cells provides a good balance. The equivalent switch-
ing frequency for the semiconductor devices is 830 Hz, which
enables the use of the proposed method in high-power applica-
tions. Fig. 8 shows the sinusoidal behavior of the line-to-line
voltage.
Finally, the dc-link voltage response presents a smooth and
good regulation, as shown in Fig. 8(e), and due the fast dynamic
offered by the inner nonlinear loop, it is not disturbed by the
changes in the power factor value.
Then, to fully validate the range of operation of the proposed
scheme, a second dynamic test is performed, involving load
impacts. The cells begin operating at half-load capacity and
with vdc ∗ = 0.33 pu, with unity power factor. At t = 1.56 s,
a 100% passive load impact is performed, doubling the active
power consumption. Finally at 1.62 s, an active load is connected
to each cell of the converter, reversing the power flow of the
system. The results are shown in Fig. 9.
The waveforms obtained for active and reactive power show
a good decoupling, and despite the dynamic changes the vari-
ables remain separately controlled. As for the load impacts, the
system presents a smooth and soft response, driven mainly by
the voltage controller. No large overshoots or oscillation can
be observed during the transient as the system reaches its new
operation point. This situation is plotted in Fig. 9(a).
As for the input currents of Fig. 9(b), they remain to be
highly sinusoidal, and during the whole experiment they remain
in phase with the grid voltage. After the load impact, they double
its amplitude to reach 1pu and operate under rated condition,
and after t = 1.62 s they change its phase in πrad changing
the power factor as the power flow has been reversed, and now
the system injects power into the grid. Despite the change in
the power flow, the currents keep its sinusoidal waveform and
RIVERA et al.: MULTILEVEL DIRECT POWER CONTROL
Fig. 9. Simulated ML-VFDPC dynamic performance for case II: (a) Active and reactive power, (b) grid currents and phase a grid voltage, (c) converter phase
voltage, (d) converter line-to-line voltage, and (e) total dc-link voltage phase a.
reduced distortion values. In addition, they are not altered by
the grid distortion as in the previous cases.
The converter voltages do not change dramatically in com-
parison with the previous case, as can be seen in Fig. 9(c) and
(d).
Finally, Fig. 9(e) shows that the dc-link voltage remains con-
trolled, and properly tracking its reference, experiencing just
small deviations at the impact instants, but the fast dynamic of
the DPC loop quickly drives the voltage back to its reference.
After t = 1.56, the voltage increases its ripple as a consequence
of the higher current demanded by the load.
The results validate four-quadrant operation of the proposed
ML-VFDPC scheme.
V. EXPERIMENTAL RESULTS
The final step in this proposal is to implement the method
in a real system. In order to validate these results, a 5-kW
7L-CHB prototype was built. This setup consists of a trans-
former, an L filter, and an IGBT-based rectifier converter, as
shown in Fig. 7. Because of hardware limitations, the actual
value for the input filter has been increased to 0.24 pu (10 mH).
The control scheme is implemented in a dSPACE R
1103 which
generates the gating pattern for the IGBTs based in the measure-
ments and estimations, and then sends it to a Xilinx Spartan-3
FPGA in order to generate the gating signals and deadtimes
for the devices. The following results were obtained using a
sampling frequency of 10 kHz.
However, due to hardware limitations, only the first dynamic
test is performed in the experiment. Using the parameters pre-
sented in Table III, the control scheme is applied to the seven-
level CHB active rectifier system.
A. Dynamic Response
The results are shown in Fig. 10, it can be seen that despite
the small degradation in the quality signals, due to the initial
assumptions and nonmodeled dynamics, the response of the
5599
drive is very close to the simulation results. The power signals in
Fig. 10(a) offers a fast response to the changes in the references
and despite the presence of grid voltage harmonics, they remain
constant at its commands. The measurement noise has not major
influence on the input signals quality and the system is able to
operate normally in the different values of power factor, always
with sinusoidal input currents, as it is confirmed by Fig. 10(b).
Note that, the power signals are estimated using the virtual
fluxes, not the grid voltages, and because of this the current
lacks the harmonic components present in the voltage. The real
input powers presents a small oscillation in the sixth harmonics
due the presence of both fifth and seventh components.
As for the converter voltages of Fig. 10(c) and (d), there
are no big differences with the previous cases, and present the
characteristic steeped waveform with clearly defined levels, due
to the correct balance of each one of the converter cells.
Finally, the dc voltage response is presented in Fig. 10(e), and
as it was expected that the use of a cascaded control architecture
allows us to compensate quickly the disturbances using a fast
inner loop (in this case the power controllers) in order to avoid
their reflection on the outer loop controlled variable.
In order to highlight the proper performance of the cell rota-
tion mechanism, Fig. 11 presents the dc voltages of each one of
the H-bridge cells, and it can be seen that they remain perfectly
balanced during the entire experiment. However, as the balanc-
ing mechanism is only providing the same usage for each one of
the cells, it will only keep the cells balanced while they have the
same load, and if it is not the case, another balancing algorithm
must be implemented.
B. Steady-State Analysis
The experimental results in the steady state for the rated load
condition are presented in Fig. 12. The wave forms obtained
allow us to confirm the correct performance of the proposed
flux observer, as the current and voltage are synchronized with-
out phase error, as presented in Fig. 12(a), allowing the proper
5600
Fig. 10. Experimental ML-VFDPC dynamic performance: (a) Active and reactive power; (b) grid currents and phase a grid voltage, (c) converter phase voltage,
(d) converter line-to-line voltage, and (e) total dc-link voltage phase a.
Fig. 11. Experimental ML-VFDPC dc-link voltages: (a) Phase a; (b) Phase b;
(c) Phase c.
Fig. 12. Experimental ML-VFDPC: (a) Phase a input current and grid voltage;
(b) Converter phase voltage; (c) Line-to-line voltage.
control of the input powers. Also, the method allows the gen-
eration of high quality currents, with reduced distortion values,
which in this case reach 4.3%.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014
Fig. 13. Experimental ML-VFDPC harmonic content: (a) Grid voltage, and
(b) input current.
Note that, this high quality is obtained using a reduced switch-
ing frequency, as it can be seen in the converter voltages shown
in Fig. 12(b) and (c). In this case, the equivalent switching fre-
quency of each device reaches 830 Hz, which enables the use
of the proposed DPC mechanism for high-power applications
without compromising the efficiency of the drive.
Finally, the harmonic content of the input signals is presented
in Fig. 13. This shows the capacity of the scheme to provide high
quality powers even in the presence of a distorted grid voltage.
Fig. 13(b) confirms the reduced harmonic distortion of isa , and
compared with the requirements imposed by the IEEE 519 Std,
it is possible to observe that the amplitude of the components
are within the established limits (denoted by the gray area).
It is confirmed that the presence of the fifth and seventh
harmonics are not dominant in the input current, despite their
strong presence in the grid voltage, due the use of virtual fluxes
in the estimations.
In addition, the presence of even order harmonics, due the
lack of half-wave symmetry in the generated gating patterns,
appears as an important issue and suggest that the switching
strategy can be further improved. This can also be observed in
the variable switching pattern exhibited in Fig. 12, since there is
no modulation stage leading to a variable switching frequency,
RIVERA et al.: MULTILEVEL DIRECT POWER CONTROL
Fig. 14. Dynamic performance comparison: (a) VOC, and (b) ML-VFDPC.
Fig. 15. Converter voltage waveform in the steady state: (a) VOC, and
(b) ML-VFDPC.
as in classic DPC. This issue can be addressed by including
an additional optimization stage that imposes a fixed switching
frequency, in a similar way as introduced for the generalized
multilevel DTC [21].
VI. COMPARISON WITH VOC
The proposed ML-VFDPC is compared to classic VOC
through simulation to replicate exact operating conditions. In or-
der to keep the comparison fair, the VOC switching frequency
has been selected in order to match the equivalent switching
frequency of ML-VFDPC. Phase-shifted PWM has been used
for the CHB modulation in the VOC scheme. The carrier fre-
quency has been set to obtain an output frequency of 2100 Hz.
In addition, the same grid pollution has been considered. The
implemented VOC scheme considers decoupling terms for the
d and q synchronous reference frame. The comparison includes
both, dynamic performance under case study 1 and also steady-
state operation.
A. Dynamic Response Analysis
The results are presented in Figs. 14–16. Case study I is simu-
lated using VOC in order to compare the dynamic performance
of both methods, which are illustrated in Fig. 16. The results for
VOC, shown in Fig. 14(a), exhibit a lower ripple in the power
signals, due its PWM switching pattern that reduces harmonic
content in the grid current. However, there are still evidences
of coupling between P and Q, and the transient response ex-
hibits considerable overshoot and has some minor oscillations
increasing the settling time. In addition the presence of the grid
voltage harmonic content results in a low frequency power pul-
sation. Due to the linearity of the PI controllers all these effects
5601
Fig. 16. Current waveform and harmonic content comparison: (a) VOC;
(b) ML-VFDPC.
may vary across the dynamic operating range, in effect the result
shown for rated conditions is among the best outcomes, since
the PI were designed around this operating point.
The proposed method exhibits a faster response without over-
shoot, oscillations and dynamic coupling of P and Q. It comes
at expense of larger ripples in the power signals, as it can be
appreciated in Fig. 14(b). This is due to the variable switching
frequency of the DPC operating principle. Note that compared
to VOC, active and reactive power have lower pulsations as they
are directly controlled.
B. Steady-State Analysis
The stead-state converter output voltage waveforms operating
at rated conditions are shown for both methods in Fig. 15. Since
the switching frequency of the PS-PWM carrier signals has been
set to be equal to the average device switching frequency ob-
tained with the proposed methods, both voltages are comparable
in quality. In fact they exhibit very similar THD. The main dif-
ference is in the switching pattern, which is symmetric in the
case of VOC and variable in the case of ML-VFDPC.
A better source of comparison are the grid currents shown
in Fig. 16, since the low-pass nature of the grid filter in-
ductance eliminates the high-frequency switching harmonics.
VOC produces slightly better grid current waveforms due to
the fixed switching frequency of the modulation stage, reduc-
ing the current THD. Despite the variable switching frequency,
ML-VFDPC also produces high-quality currents due to the in-
herent power quality of multilevel converters, which is a clear
advantage over classic two-level DPC. In addition, the variable
switching frequency, which is traditionally seen as a disadvan-
tage, has a positive effect on grid code compliance, since the
switching harmonic content is distributed across the frequency
spectrum, reducing individual harmonic component amplitudes.
5602
In this way, the grid current harmonics are almost completely be-
low the grid code limit. In contrast the modulation stage of VOC
concentrates the switching content in few harmonics which in
turn have larger amplitude, surpassing the grid code limit.
VII. CONCLUSION
A generalized multilevel virtual flux DPC method has been
proposed. The control scheme was validated using a 5-kW
7L-CHB prototype both in simulation and practical implemen-
tation. The method is based on the voltage space vector offered
by the converter rather than its topology, therefore the principle
can be extended to any multilevel voltage source topology. This
enables the use of DPC for existing grid connected multilevel
applications and those to come.
As the multilevel represents a richer actuator than the con-
ventional 2L-VSC, because of the larger number of vectors
available, it is possible to improve the power quality and also
reduce the switching frequency of the semiconductor devices.
As a consequence, the active and reactive power regulation is
smoother and its ripples are substantially reduced.
The use of the grid virtual flux approach instead of direct grid
voltage measurement, improves the results for systems con-
nected to polluted grids. In addition, the implementation chal-
lenges associated with derivatives have been overcome using a
derivative observer whose robustness has been tested in simula-
tion adding measurement noise and by experimental validation
with real measurement system.
The low harmonic distortion obtained in the current and its
grid code compliance allows the use of multilevel converters
and the proposed ML-VFDPC to connect the megawatt range
renewable energy conversion systems to the distribution grid,
introducing power quality and quality improvements compares
with the conventional DPC schemes.
Despite the initial idea, the limitation to act only on the closest
vectors of the converter does not reduce the dynamic response
of the system, as this is mainly influenced by the outer voltage
loop, which will be always slower than the nonlinear controller
used in DPC.
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Sebastian Rivera (S’11) was born in Valparaiso,
Chile, in 1986. He received the bachelor’s and M.Sc.
degrees in electronics engineering from Universidad
Técnica Federico Santa Marı́a, Valparaı́so, in 2007
and 2011, respectively. In 2011, he received a schol-
arship from the Chilean National Commission for
Scientific and Technological Research for his Ph.D.
He is currently working toward the Ph.D. degree in
electrical and computer engineering at Ryerson Uni-
versity, Toronto, ON, Canada.
His research interests include multilevel convert-
ers, renewable energy conversion systems, and charging architectures for plug-in
electric vehicles.
Samir Kouro (S’04–M’08) received the M.Sc.
and Ph.D. degrees in electronics engineering from
the Universidad Tecnica Federico Santa Maria
(UTFSM), Valparaı́so, Chile, in 2004 and 2008,
respectively.
In 2004, he joined the Electronics Engineering
Department, UTFSM, as a Research Assistant, and
became an Associated Researcher in 2008 and Re-
search Academic in 2011. From 2009 to 2011, he was
a Postdoctoral Fellow in the Department of Electri-
cal and Computer Engineering, Ryerson University,
Toronto, Canada. He is a Principal Investigator of the Solar Energy Research
Center (SERC Chile). He has coauthored one book, three book chapters and
more than 70 refereed journal and conference papers. His research interests
include power electronics, control, and renewable energy power conversion
systems (photovoltaic and wind).
Dr. Kouro has served as Chair of 11 special sessions in conferences and
served as a Guest Editor of a Special Section in the IEEE TRANSACTIONS ON
INDUSTRIAL ELECTRONICS and one in the IEEE TRANSACTIONS ON POWER
ELECTRONICS. He received the IEEE Power Electronics Society Richard M.
Bass Outstanding Young Power Electronics Engineer Award in 2012, the IEEE
Industry Applications Magazine 1st prize paper award of 2012, the IEEE Trans-
actions on Industrial Electronics Best Paper Award of 2011, the IEEE Industrial
Electronics Magazine Best Paper Award of 2008.
5603
Bin Wu (S’89–M’92–SM’99–F’08) received the
Ph.D. degree in electrical and computer engineering
from the University of Toronto, Toronto, ON, Canada,
in 1993.
After being with Rockwell Automation Canada,
he joined Ryerson University, Toronto, where he is
currently a Professor and NSERC/Rockwell Indus-
trial Research Chair in Power Electronics and Elec-
tric Drives. He has published more than 300 tech-
nical papers, authored/coauthored two Wiley-IEEE
Press books, and holds more than 20 issued/pending
patents in the area of power electronics, electric drives, and renewable energy
systems.
Dr. Wu received the Gold Medal of the Governor General of Canada, the
Premier’s Research Excellence Award, Ryerson Distinguished Scholar Award,
and the NSERC Synergy Award for Innovation. He is a Fellow of Engineering
Institute of Canada and Canadian Academy of Engineering.
Salvador Alepuz (S’98–M’03–SM’12) was born in
Barcelona, Spain. He received the M.Sc. and Ph.D de-
grees in electrical and electronic engineering from the
Technical University of Catalonia (UPC), Barcelona,
Spain, in 1993, and 2004, respectively.
Since 1994, he has been an Associate Professor
at the Mataro School of Technology, UPC, Tecno-
campus Mataro-Maresme, Mataro, Barcelona. From
2006 to 2007, he was with the Departamento de Elec-
tronica, Universidad Tecnica Federico Santa Maria,
Chile, as a Postdoctoral Research. In 2009, he was a
Visiting Researcher for three months at the Electrical and Computer Engineer-
ing Department, Ryerson University, Toronto, Canada. His research interests
include multilevel conversion and ac power conversion applied to renewable
energy systems.
Mariusz Malinowski (S’99–M’03–SM’08) received
the M.Sc.E.E. and Ph.D. degrees in electrical en-
gineering (with awards) from the Institute of Con-
trol and Industrial Electronics, Warsaw University of
Technology (WUT), Warsaw, Poland, in 1997 and
2001, respectively.
He was a Visiting Scholar with Aalborg Univer-
sity, Aalborg, Denmark; the University of Nevada,
Reno; the Technical University of Berlin, Berlin,
Germany; and the ETH Zurich, Switzerland. He
was also a Visiting Professor with the Universi-
dad Tecnica Federico Santa Maria, Valparaı́so, Chile; the University of
Cergy-Pontoise, Cergy-Pontoise, France; and the École Nationale Supérieure
d’Électronique, d’Électrotechnique, d’Informatique, d’Hydraulique, et des
Télécommunications-Laplace, Toulouse, France. He is currently with the In-
stitute of Control and Industrial Electronics, WUT. He has authored more than
100 technical papers. He is the holder of three implemented patents. His current
research interests include the control and the modulation of pulse width modu-
lation rectifiers, multilevel converters, and active filters, and power-generation
systems based on renewable energies.
Dr. Malinowski is an active member of the IEEE Industrial Electronics
Society (IES) and the IEEE Poland Section. Within the IES, he was responsi-
ble for student activities (2005–2009). He is an Associate Editor for the IEEE
TRANSACTIONS ON INDUSTRIAL ELECTRONICS, the IEEE TRANSACTIONS ON
POWER ELECTRONICS, and the Past Editor in Chief for the IEEE INDUSTRIAL
ELECTRONICS MAGAZINE (2010–2012). He received the Siemens Prize (2002
and 2007), the WUT President Prize (2001, 2005, 2007, 2009, and 2011), a
paper award at the Industrial Electronics Conference 2000 and European Power
Electronics-Power Electronics and Motion Control 2004, and the Polish Min-
ister of Science and Higher Education Awards (2003 and 2008). His industry
application received many awards and medals, e.g., the Innovation Exhibition
in Geneva (2006) and the Exhibition in Brussels ”Eureco” (2006). He received
IEEE IES David Irwin Early Career Award for ”Outstanding research and de-
velopment of modulation and control for industrial electronics converters” in
2011.
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Patricio Cortes (S’05–M’08) received the Engi-
neer and M.Sc. degrees in electronic engineering
from the Universidad Tecnica Federico Santa Maria
(UTFSM), Valparaiso, Chile, in 2004, and the Ph.D.
degree from the same university in 2008. He also re-
ceived the Industrial Design degree from the Pontif-
ical Catholic University of ValparaÌso in 2006. From
2008 to 2012, he was a Research Associate at the
Electronics Engineering Department, UTFSM. Since
2012 he is a Postdoctoral Researcher at the Power
Electronic Systems Laboratory, Swiss Federal Insti-
tute of Technology (ETH) Zurich. His main research interests include modeling
and control of power converters. He received the Best Paper Award from the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS in 2007.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014
Jose Rodriguez (M’81–SM’94–F10) received the
Engineer degree in electrical engineering from the
Universidad Federico Santa Maria (UTFSM), Val-
paraiso, Chile, in 1977, and the Dr.-Ing. degree in
electrical engineering from the University of Erlan-
gen, Erlangen, Germany, in 1985.
He has been with the Department of Electronics
Engineering, University Federico Santa Maria, Val-
paraı́so, since 1977, where he is currently Full Pro-
fessor and Rector. He has coauthored more than 350
journal and conference papers. His main research in-
terests include multilevel inverters, new converter topologies, control of power
converters, and adjustable-speed drives. Dr. Rodriguez is an Associate Editor of
the IEEE TRANSACTIONS ON POWER ELECTRONICS, INDUSTRIAL ELECTRONICS,
AND INDUSTRIAL INFORMATICS. He has received 5 Best Paper Awards from
different IEEE Journals. He is a Fellow of the Chilean Academy of Engineering
.