COMPUTER ORGANIZATION AND ARCHITECTURES(ECE3004)

DIGITAL ASSIGNMENT – 1

Submitted by:
KULDEEP SAI
17BEC0752
C2+TC2

1Q) Compare the characteristics of Arduino and Raspberry Pi in a neat tabular column.
ANS)
Definition:
ARDUINO- It is a microcontroller which is just a normal part of the computer. It can be used
to run a single program code again and again.
RASBERRY PI - A mini-computer with its own Raspberry OS capable of handling multiple
programs at a time.

ARDUINO RASPBERRY PI
Battery it can be powered with a battery It Is quite difficult to power using a
Support pack battery pack
Onboard It provides the onboard storage It doesn’t have an onboard storage
Storage facility in place, it rather depends on
the SD card based storage
No. of USB It has just 1 USB port . It has 4 USB ports .
ports
Processor The processor here is from AVR The processor here is from ARM
family. family.
Connectivity It requires integration of external It can be easily connected with the
hardware to establish a internet by making use of Ethernet
connection with the internet. This port and Wi-Fi dongles.
hardware is handled properly
using the code.
Languages Its own language Arduino, C or C+ Python,C,C++ and Ruby .
supported +.
Cost Low cost. Quite expensive.
2Q) Compare the characteristics of 8051 and PIC16F.

8051 PIC16F
ALU Size 8 Bits 8 Bits
Architecture CISC RISC
Clock Speed 12 MHz 20 MHz

Number of Instructions 256 35

Immediate Addressing
Immediate Addressing Mode
Mode
Register Addressing Mode
Register Operand
Direct Addressing Mode Addressing Mode
Register Indirect Addressing Memory Operand
Mode Addressing Mode
Indexed Addressing Mode Direct Addressing Mode
Supported Addressing Modes Implied Addressing Mode Indirect Addressing Mode

Inbuilt peripherals like ADC

or DAC Nil 1 ADC module

Number of timers 2x16-bit 2x8 Bit, 1x 16 Bit

5 interrupt
Interrupts signals(INT0,TFO,INT1,TF1,RI/T1) 15 Interrupt Signals

Supports RTC using I2C

Real-Time clocks Supports RTC using I2C protocol protocol
RAM,ROM 128 Bytes,4KB 368 Bytes, 14KB
1xDataBus(8-Bit),
1xDataBus(8bit), 1xProgram Code Bus(14
System BUS 1xAddress Bus(16 bit) Bit)

I/O Ports 4x8 Bit Bidirectional pins 5x8 Bit Bidirectional

Supports full duplex UART

Serial Port Communication Supporta USART

Operating Voltage 2-5.5 volts 2-5.5 volts

3Q) Describe in detail the various benchmark procedures used in the EEMBC for processor
performance analysis.

ANS)
EEMBC develops performance benchmarks for the hardware and software used in
autonomous driving, mobile imaging, the Internet of Things, mobile devices, and many
other applications
The various EEMBC benchmarks are

ULPMark , IoTMark , SecureMark , MLMark , ADASMark , CoreMark , CoreMark-PRO ,

FPMark , MultiBench , AndEBench-PRO , BrowsingBench ,AutoBench , DENBench ,
Networking , OABench , TeleBench.

Benchmarks can be grouped into the following categories:

 Ultra-Low Power and Internet of Things

 Heterogeneous Compute
 Single-core Processor Performance
 Multi-core Processor Performance
 Phone and Tablet

Ultra-Low Power (ULP) and Internet of Things:-

The ULP subcommittee focuses on power and energy. The scores associated with the
benchmarks are derived from measurements taking using the STMicroelectronics
PowerShield.

ULPMark: In 2014, the ULP team introduced the ULPmark-CoreProfile (or -CP for short).
The benchmark runs an active workload for a period of time, then goes to sleep. The energy
measurement during the duty cycle reflects a real-life test of embedded low power beyond
a simple sleep number. The ULPMark-PeripheralProfile (or -PP for short) launched in 2016
examines the energy cost of four peripherals: real-time clock, pulse-width modulation,
analog-to-digital conversion, and SPI communication.

It is EEMBC's first active-power benchmark

IoTMark: IoTMark builds on ULPMark by adding a sensor emulation module (the IO

Manager) and a radio gateway emulator (the Radio Manager). The execution profile
incorporates the types of behavior an IoT edge node would perform. The first benchmark in
this series, IoTMark-BLE, uses a Bluetooth Low Energy (BLE) radio as the gateway and an I2C
device as the sensor.
Heterogeneous Compute:-

EEMBC's original benchmarks focused on single core 8- and 16-bit embedded processors.
These benchmarks aren't suitable for todays mixed-core heterogeneous platforms deployed
for high-performance computation. The benchmarks in this category differ from single-core
or symmetric multi-core performance benchmarks EEMBC has developed in the past, in that
they provide more sophisticated frameworks for assymmetric compute.

ADASMark: ADASMark focuses benchmarking a typical vision pipeline that may be used
in advanced driver-assistance systems (ADAS) platforms. Built on OpenCL, the pipeline may
be distributed among CPUs, GPUs and DSPs.

MLMark: Machine Learning on the edge has become a reality. This benchmark strives
to categories and analyze several broad classes of popular ML neural networks on
embedded edge-compute platforms.

Single-core Processor Performance

The original EEMBC benchmarks, these suites are still in popular use today for compiler
testing, regressions in new embedded core RTL, and academic analysis.

CoreMark: A simple, yet sophisticated test of the functionality of a processor core; it

produces a single-number score allowing users to make quick comparisons between
processors.

OABench (Office Automation): This benchmark approximates office automation tasks

performed by processors in printers, plotters, and other office automation systems that
handle text and image processing tasks.

Symmetric Multi-core Processor Performance:-

Our multicore suites are built on the multi-instance test harness (MITH) which exploits the
POSIX pthreads interace for testing both context- and worker-level parallelism.

AutoBench -2.0: The original AutoBench benchmark is back in parallel form, with more
workloads consistenting on aggregated tasks (combinations of AutoBench-1.1 kernels) that
reflect the increase in compute demand of automotive electronic control units (ECU).

MultiBench: To analyze worker-level parallelism in addition to context-level, MultiBench

contains integer workloads that scale in both directions.
4Q) Describe the architecture and special features of the Qualcomm Snapdragon 855
Mobile Platform and Snapdragon X50 5G modem.
ANS)

Architecture and special features:

The Qualcomm Snapdragon 855 Mobile Platform is a top of the line cell phone and tablet
SoC that Qualcomm declared in December 2018. The SoC incorporates a quick 'Prime Core'
that tickers up to 2.84 GHz and three further quick ARM Cortex-A76 execution centers,
which can reach up to 2.42 GHz. These are supplemented by four force sparing ARM Cortex-
A55 centers that clock up to a limit of 1.8 GHz. The higher 'Prime Core' clock speed ought to
give altogether preferable single center execution over the Snapdragon 845.The new SoC
ought to have up to 45% quicker single-center execution and 35% multi-center execution
than its antecedent.

The SoC additionally incorporates the new X24 LTE modem that Qualcomm guarantees will
convey up to 2 Gbit/s most extreme download speed over LTE Cat.20 and up to 316 Mbit/s
transfer speeds. The Snapdragon 855 can be designed with the organization's new X50 5G
modem as well.

Qualcomm has likewise improved the coordinated Wi-Fi modem, which is Wi-Fi 6-prepared,
has 8x8 Sounding and supports up to 802.11 ay Wi-Fi. The Wi-Fi modem can use the 60 GHz
mmWave band for up to 10 Gbit/s web speeds.The Hexagon 690 DSP has experienced the
most corrections of that which Qualcomm has incorporated into the Snapdragon 855. The
new DSP joins a neural handling unit (NPU) with committed Tensor-centers that can execute
up to 7 trillion tasks for every second related to the CPU and GPU.

The built-in memory controller supports up to 16 GB LPDDR4x RAM (4 x 16-bit). Moreover,

the Adreno 640 has 50% more compute units (ALUs) than the Adreno 630.

Qualcomm will maker the Snapdragon 855 at the Taiwan Semiconductor Manufacturing
Company (TSMC) utilizing a 7 nm FinFET process.
The change to 7 nm assembling should make the SD855 20% more effective than the
SD845. Qualcomm has not formally declared the warm structure power (TDP) of the SD855,
however we speculate that the SoC will arrive at a limit of 5 W and will average around 3.5
W under burden.
The world's first Computer Vision (CV) ISP conveying 4K HDR video catch with Portrait Mode
and world's first to catch HDR10+ video.
Snapdragon X50 5G modem:

Supporting up to 5 gigabits per second download speeds, the Snapdragon X50 5G Modem-
RF System can provide a vastly more immediate connection between the user and the
cloud, opening up the possibilities of an entirely new generation of applications and
services.
The Snapdragon X50 5G Modem-RF System, matched with up to 4 QTM052 mmWave
reception apparatus modules, bolsters propelled portability highlights including shaft
framing, bar directing and pillar following which are built to improve mmWave signal range
and inclusion, making versatile mmwave practical and prepared for enormous scope
commercialization.
The Snapdragon X50 5G Modem-RF System is intended to help the up and coming age of
cell phones. At the point when combined with a Snapdragon processor with a coordinated
Gigabit class LTE modem, the total Snapdragon X50 5G stage can give multi-mode 4G/5G
ability through double network. In fixed remote applications, the Snapdragon X50 5G
Modem-RF System can supplant fiber-to-the-home (FTTH) establishments with remote 5G
associations.

Specifications:

5G Technology: 5G NR
5G Spectrum: mmWave, sub-6 GHz
5G Modes: TDD, NSA (non-standalone)
5G mmWave specs: 800 MHz bandwidth, 8 carriers, 2x2 MIMO
5G sub-6 GHz specs: 100 MHz bandwidth, 4x4 MIMO
mmWave Features: Dual-layer polarization in downlink and uplink, Beam forming, Beam
steering, Beam tracking
5G Peak Download Speed: 5 Gbps
5G SIM: 5G Dual SIM support