PROJECT

GSM BASED VOTTING MACHINE SYSTEM

Submitted by: mentor:

 Introduction

IN THIS PROJECT WE SHOW THE NEW IDEA AND CONCEPT IN VOTING MACHINE. WITH THE HELP OF
THIS CONCEPT ANY VOTER CAST HIS VOTE FROM ANY PLACE WITH ANY PHONE.
TO ACTIVATE THIS SYSTEM IN REAL LIFE, WE MUST ISSUE ONE UNIQUE ID NUMBER TO EACH VOTER.
FIRST OF ALL PERSON DIAL THE NUMBER, AND PRESS THE HASH BUTTON FROM MOBILE OR LANDLINE.
AS VOTER PRESS THE HASH BUTTON, VOICE RESPONSE SYSTEM RESPOND WITH PREDEFINED MESSAGE
ON THE PHONE. WITH THE HELP OF VOICE COMMAND SYSTEM VOTER ENTER ITS UNIQUE ID AND
SYSTEM COMPARE THE ID WITH DATA BASE. IF THE DATA BASE IS EQUIPPED WITH THIS ID THE SYSTEM
DEMAND A PASSWORD. VOTER ENTER THE PASSWORD AND SYSTEM COMPARE THE PASSWORD. IF THE
PASSWORD IS OK THEN VOTER CAST A VOTE BY PRESSING A SWITCH OPTION.AS THE VOTER CAST THE
VOTE , CAST VOTE IS SAVE IN THE EXTERNAL MEMORY FOR STORAGE. AT THE RECEIVER END WE CHECK
THE TOTAL VOTE AND INDIVIDUAL VOTE BY PRESSING A SWITCH
.
COMPONENTS USED:

Step down Transformer 220 volt to 9 volt AC. 750 ma current.

We use transformer to step down the 220 volt ac into 9 volt ac .

Diode == in 4007.
In this project we use total two diodes to convert AC into DC. As a full wave rectifier we must require a
centre tap Transformer with two diode as a rectifier. Output of the rectifier is further converted in
smooth dc with the help of capacitor filter. Capacitor converts the pulsating dc into smooth DC with the
help of charging and Discharging effect.
IC 7805.
IC 7805 regulator provide a regulated DC output from 9 volt AC. IC 7805 provide a constant 5 volt DC.

IC 8870:-- IC 8870 is a DTMF decode and provide a 4 bit output and connected to the controller
directly. Pin no 11,12,13,14 is connected to the pin no 14,15,16,17 of the controller. Pin no 15 of the
8870 is acknowledgement pin. Whenever 8870 decode the data then pin no 15 goes high and at this
time, this data is connected to the pin no 13 via NPN transistor.

IC 89S52:--
IC 89s52 is 40 Pin IC and family member of the 8051 controller. Pin no 40 of the controller is connected
to the positive 5 volt supply. Pin no 18 and 19 is connected to the external crystal oscillator to set a
machine cycle of the controller. Pin no 9 is reset pin and connected to external RC circuit to provide a
power reset automatically. All the manual switch is connected to the pin no 5,6,7,8,10,11,12 of the
controller to use as a manual check voting switch to check the total vote, individual vote for 4
candidate , memory clear password
.
IC 74154: IC 74154 is 4 bit to 16 pin decoder and use to extend the controller pins. IC 74154 is a 4 to
16 decoder and connected to the voice processor circuit. Output from the IC 74154 is connected to the
voice processor for voice response system
LCD : in this project we use 2 by 16 character to display all the message related to voting machine.

There is total 8 data lines for the data and 3 control line for the control bits.Pin no 39 to 32 is connected

to the 8 data lines and pin no 26,27,28 is connected to the RS,RW and Enable pin of the LCD display
Components used:

STEP DOWN TRANSFORMER

Step down transformer from 220 volt Ac to 9-0-9 ac. We use step down transformer to step down the

voltage from 220 to 9 volt ac. This AC is further connected to the rectifier circuit for AC to DC conversion.

Transformer current rating is 750 ma .

DIODE.

In this project we use IN 4007 diode as a rectifier. IN 4007 is special diode to convert the AC into DC

In this project we use two diode as a rectifier. Here we use full wave

rectifier. Output of rectifier is pulsating DC. To convert the pulsating dc

into smooth dc we use Electrolytic capacitor as a main filter. Capacitor

converts the pulsating dc into smooth dc and this DC is connected to the Regulator circuit for Regulated

5 volt DC.
Pin no 40 of the controller is connected to the positive supply. Pin no 20 is connected to the

ground. Pin no 9 is connected to external resistor capacitor to provide a automatic reset option
when power is on.
Reset Circuitry:

Pin no 9 of the controller is connected to the reset circuit. On the circuit we connect one resistor

and capacitor circuit to provide a reset option when power is on

As soon as you give the power supply the 8051 doesn’t

start. You need to restart for the microcontroller to start.

Restarting the microcontroller is nothing but giving a Logic

1 to the reset pin at least for the 2 clock pulses. So it is

good to go for a small circuit which can provide the 2 clock

pulses as soon as the microcontroller is powered.

This is not a big circuit we are just using a capacitor to charge the microcontroller and again

discharging via resistor.

Crystals

Pin no 18 and 19 is connected to external crystal oscillator to provide a clock to the circuit.

Crystals provide the synchronization of the internal function and to the

peripherals. Whenever ever we are using crystals we need to put the
capacitor behind it to make it free from noises. It is good to go for a 33pf
capacitor.

We can also resonators instead of costly crystal which are low cost and external capacitor can

be avoided.

But the frequency of the resonators varies a lot. And it is strictly not advised when used for

communications projects.
How is this time then calculated?
The speed with which a microcontroller executes instructions is determined by what is known as

the crystal speed. A crystal is a component connected externally to the microcontroller. The

crystal has different values, and some of the used values are 6MHZ, 10MHZ, and 11.059 MHz

etc.

Thus a 10MHZ crystal would pulse at the rate of 10,000,000 times per second.

The time is calculated using the formula

No of cycles per second = Crystal frequency in HZ / 12.

For a 10MHZ crystal the number of cycles would be,

10,000,000/12=833333.33333 cycles.

This means that in one second, the microcontroller would execute 833333.33333 cycles.
PIN NO 1 VSS GROUND

PIN NO 2 VCC +5 V SUPPY.

PIN NO 3 VEE POWER SUPPLY TO CONTRAST CONTROL

PIN NO 4 RS RS = 0 TO SELECT
1.1 VOTING
Voting is a method for a group such as a meeting or an electorate to make a decision or to
express an opinion often following discussions or debates.
1.1.1 Voting Techniques
In India all earlier elections be it state elections or centre elections a voter used to cast his/her
vote to his/her favorite candidate by putting the stamp against his/her name and then folding the ballot
paper as per a prescribed method before putting it in the Ballot box. This is a long, time-consuming
process and very much prone to errors.
This method wanted voters to be skilled voters to know how to put a stamp, and methodical
folding of ballot paper. Millions of paper would be printed and heavy ballot boxes would be loaded and
unloaded to and from ballot office to polling station. All this continued till election scene was completely
changed by electronic voting machine. No more ballot paper, ballot boxes, stamping, etc. all this
condensed into a simple box called ballot unit of the electronic voting machine.

1.1.2 Electronic Voting Machine

The complete EVM consists mainly of two units - (a) Control Unit and (b) Balloting Unit with
cable for connecting it with Control unit. A Balloting Unit caters up-to 16 candidates. Four Balloting Units
linked together catering in all to 64 candidates can be used with one control unit. The control unit is
kept with the Presiding Officer and the Balloting Unit is used by the voter for polling.
The Balloting Unit of EVM is a small Box-like device, on top of which each candidate and his/her
election symbol is listed like a big ballot paper. Against each candidate's name, a red LED and a blue
button is provided. The voter polls his vote by pressing the blue button against the name of his desired
candidate.
1.1.3 Tele voting Machine
Tele-voting is a method of decision making and opinion polling conducted by telephone. TVM
has the major unit i.e. control unit. And the heart of the machine is a microcontroller which controls all
the ICs and components connected to it. It can cater large number of candidates and even further its
capacity can be increased by interfacing it with 8255.
In this a voter calls up the number with which the machine is connected and the system
automatically activates and the voice message already stored on voice processor chip gets played and on
following the voice script voter casts his vote by pressing the respective key of his phone. And the vote
cast gets stored in flash memory instantly. All vote cast can be checked later with the help of couple of
switches and LCD display. Reset keys are also provided to reset the machine for next time.

1.2 ADVANTAGES OF TVM

The TVMs have following advantages:
 Elimination of polling queues.
 Can be interfaced with PC to generate back-ups
 The saving of considerable printing stationery and transport of large
volumes of electoral material,
 Easy transportation, storage, and maintenance,
 No invalid votes,
 Reduction in polling time.
 Easy and accurate counting without any mischief at the counting centre
 Eco-friendly.

1.3 COMPARE A ND CONTRAST: PAPER VOTING, EVM and TVM

We have so far discussed three different voting systems. These systems are
being used or considered obsolete because of certain positive and negative points.
These are summarized as follows:

Device type
Ballot paper : Papers and boxes
EVM : Embedded system with Assembly code
TVM : Embedded system with Assembly code

Visual Output
Ballot paper : Stamp on paper
EVM : Single LED against each candidate's name
TVM : LCD screen and one LED

Security Issues
Ballot paper : No security provided by the system, neither during polling nor
during voting.
EVM : During polling, a facility is provided to seal the machine in case
of booth capturing. No further voting can be done afterwards.
TVM : machine is disconnected from the telephone line. No more calls
can be received afterward.

Power Supply
Ballot paper : No power supply required.
EVM : 6V alkaline batteries or electricity.
TVM : Electricity and supply from exchange.

Capacity
Ballot paper : As much a ballot box can hold.
EVM : 3840 Votes.
TVM : Depends on the size of flash memory attached.

1.4 EXISTING SYSTEM

But this electronic voting machine has its disadvantages too. These areas of deficiency are not much
of a concern to a layman, but for an intelligent voter this must be eliminated for a secure election. The
few technical disadvantages are given as:
 Microprocessor based design, which requires a no. of supporting components like memory,
peripheral interface, etc.
 Long polling queues at the centre.
 Existing system costs around 12000 INR(300$)
1.5 PROPOSED SYSTEM
All these faults motivated us to make this enhanced version of EVM. The faults which are eliminated
are summarized as follows:
 Microcontroller replaced microprocessor, which made the EVM closer to real time operation
making it faster, more reliable and unique.
 More user friendly and interactive LCD display
 Proposed Module costs around Rs 2000.
 Elimination of polling queues had been the major factor.
 Voting machine with voice response method
 Voting with unique id system
 Unique id + password system
 Voter once cast the vote, not possible to cast the vote again
 CHAPTER 2
POWER SUPPLY

2.1 INTRODUCTION

These days almost all the electronic equipments include a circuit that converts AC supply into DC
supply. The part of equipment that converts AC into DC is known as AC to DC converter. In general, at
the input of the power supply is a transformer. It is followed by a rectifier, a smoothing filter and then by
a voltage regulator circuit.

2.2 COMPONENTS OF POWER SUPPLY

Power supply consists of four components:-

(i) Step-Down Transformer

(ii) Rectifier
(iii) Filter
(iv) Voltage Regulator

Block diagram of such a supply is shown below:-

TRANSFORMER RECTIFIER FILTER VOLTAGE REGULATOR

Fig. 2.1 Block diagram

2.2.1 Step Down Transformer

A transformer in which the output (secondary) voltage is less than the input (primary) voltage is
called step down transformer. Alternating current is passed through the primary coil which creates the
changing magnetic field in iron core. The changing magnetic field then induces alternating current of
the same frequency in the secondary coil (the output). A step down transformer has more turns of wire
on the primary coil than in secondary coil which makes a smaller induced voltage in the secondary coil.

The transformer equation relates the number of turns of wire to the difference in voltage
between the primary and secondary coils.

Vp
/Vs = Np/Ns ...(2.1)

Vp is the voltage in the primary coil.

Vs is the voltage in the secondary coil.

Np is the number of turns of wire on the primary coil.

Ns is the number of turns of wire on the secondary coil.

2.2.2 Rectifier

Rectifier is defined as an electronic device used for converting A.C voltage into unidirectional
voltage. A rectifier utilizes unidirectional conduction device like P-N junction diode.

There are three types of rectifier:-

a. Half wave rectifier.

b. Full wave center tap rectifier.
c. Full wave bridge rectifier.

2.2.3 Filter

The output from any of the rectifier circuits is not purely D.C but also has some A.C components,
called ripples, along it. Therefore such supply is not useful for driving sophisticated electronic
devices/circuits. Hence, it becomes essential to reduce the ripples from the pulsating D.C supply
available from rectifier circuits to the minimum. This is achieved by using a filter or smoothing circuit
which removes the A.C components and allows only the D.C component to reach the load. A filter circuit
should be placed between the rectifier and the load.

2.2.4 Voltage Regulator

 Voltage Regulator (regulator), usually having three legs, converts varying input voltage and
produces a constant regulated output voltage.
7805 voltage regulator has three pins:-
a. Input:- For 7805 the rectified and filtered voltage coming at this pin must be between 8 to 18V in
order to get stable 5V DC output at the output pin.

INPUT 7805
OUTPUT

GND

Fig. 2.2 Pin configuration

b. Ground:- This pin is connected to the ground of the circuit to which this 5V DC supply is provided.

c. Output:- If the input voltage at input pin is between 8-18V then at the output pin a stable 5V DC
voltage will be available.

7805 can give +5V output at about 150 mA current, but it can be increased to 1A when good cooling is
added to 7805 regulator chip.

2.3 5V DC POWER SUPPLY USING FULL WAVE CENTER TAP RECTIFIER

The transformer supplies the source voltage for two diode rectifiers, D1 and D2. This
transformer has a center-tapped, low-voltage secondary winding that is divided into two equal parts
(W1 and W2). W1 provides the source voltage for D1, and W2 provides the source voltage for D2. The
connections to the diodes are arranged so that the diodes conduct on alternate half cycles. When the
center tap is grounded, the voltages at the opposite ends of the secondary windings are 180 degrees
out of phase with each other. Thus, when the voltage at point A is positive with respect to ground, the
voltage at point B is negative with respect to ground. Let's examine the operation of the circuit during
one complete cycle.

During the first half cycle (indicated by the solid arrows), the anode of D1 is positive with
respect to ground and the anode of D2 is negative. As shown, current flows from ground (center tap)
to point A, through diode D1 to point B and to point D. When D1 conducts, it acts like a closed switch
so that the positive half cycle is felt across the load (R L).
 During the second half cycle (indicated by the dotted lines), the polarity of the applied voltage
has reversed. Now the anode of D2 is positive with respect to ground and the anode of D1 is negative.
Now only D2 can conduct. Current now flows, as shown, from point C to point B through diode D2 then
to point F and back to point D.

Now during both the cycles the capacitor C1 quickly charges to the peak voltage but when the
input voltage becomes less than peak voltage the capacitor discharges through load resistance and
loses charge. But because of large load resistance the discharging time is large and hence capacitor
does not have sufficient time to discharge appreciably. Due to this the capacitor maintains a
sufficiently large voltage across the load.

Fig. 2.3 Centre-tap full-wave rectifier

The voltage across the capacitor is applied to 7805 voltage regulator which provides a constant
5V D.C. voltage at its output.
Fig. 2.4 Output waveforms of centre-tap full-wave rectifier

Fig. 2.5 Output waveform of voltage regulator.

CHAPTER 3
AUDIO RECORD AND PLAYBACK
3.1 INTRODUCTION
In Tele Voting Machine project we required that a pre-recorded message should be played when
the call is made to the number connected to the voting circuit. For this we are using APR 9600 single
chip audio recording and play back device.

3.2 APR 9600

3.2.1 Features

• Single-chip, high-quality voice recording & playback solution

- No external ICs required
- Minimum external components
• Non-volatile Flash memory technology
- No battery backup required
• User-Selectable messaging options
- Random access of multiple fixed-duration messages
- Sequential access of multiple variable-duration messages
• User-friendly, easy-to-use operation
- Programming & development systems not required
- Level-activated recording & edge-activated play back switches
• Low power consumption
- Operating current: 25 mA typical
- Standby current: 1 uA typical
- Automatic power-down
• Chip Enable pin for simple message expansion.

3.2.2 Pin Configuration

 Fig. 3.1 Pin configuration

Table 3.1 Pin Description

PIN NAME PIN NO. FUNCTIONALITY

Message 1: This pin forces a jump to message 1 for either

recording or playback.
/M1_Messsage 1

PIN NAME PIN NO. FUNCTIONALITY

/M2_Next Message 2: This pin forces a jump to message 2 for either

Message recording or playback.
2

Message 3: This pin forces a jump to message 3 for either

recording or playback
/M3 3 Message 3
 Message 4: This pin forces a jump to message 4 for either
recording or playback
/M4 4

Message 5: This pin forces a jump to message 5 for either

recording or playback.
/M5 5

Message 6: This pin forces a jump to message 6 for either

recording or playback.
/M6 6

Oscillator Resistor: this input allows an external resistor to be

connected to the tank circuit
OscR 7
of the internal oscillator

Message 7: This pin forces a jump to message 7 for either

recording or playback.
/M7_END 8

Message 8: This pin forces a jump to message 8 for either

recording or playback
/M8_Option 9

PIN NAME PIN NO. FUNCTIONALITY

This pin indicates that the device is currently busy performing

internal functions and
/Busy 10
can neither record nor playback at the current time

If this pin is pulled high Beep is enabled. If this pin is pulled

low beep is disabled
BE 11

Digital GND Connection: Connect to system ground.

VSSD 12

Analog GND Connection: Connect system ground

VSSA 13
 Positive Output for Speaker Connection: Should be connected
to the positive terminal of the output speaker. Total output
power is.1 W into 16 ohms. Do not use speaker loads lower
SP+ 14 than 8 ohms or device damage may result

Negative Output for Speaker Connection: Should be

connected to the negative terminal of the output speaker
SP- 15

PIN NAME PIN NO. FUNCTIONALITY

Analog Positive Power Supply: This connection supplies

power for on-chip analog circuitry. Should be connected to
the positive supply rail as outlined in the reference
VCCA 16 schematics

Microphone Input: Should be connected to the microphone

input as outlined in the reference schematic
MicIn 17

Microphone GND Reference: Should be connected to the

microphone input as outlined in the reference schematics
MicRef 18

Automatic Gain Control Attack Time: The time constant of the

RC network connected to this input determines the AGC
attack time. The attack time is defined as the delay present
before the AGC circuit begins to adjust gain. The values
shown in the reference schematics have been optimized for
AGC 19
voice applications.
 Analog In: This pin must be connected to Ana_Out through a
0.1µF Capacitor
Ana_In 20

PIN NAME PIN NO. FUNCTIONALITY

Analog Out: This pin must be connected to Ana_In through a

0.1µF Capacitor.
Ana_Out 21

This pin indicates programming of each individual recording

segment. The falling edge represents the beginning of the
/Strobe 22
sector. The rising edge indicates that the sector is half full.

Chip Select: A low level on this pin enables the device for
operation. Toggling this pin also resets several message
/CE 23
management features

Mode Select1: This pin in conjunction with MSEL2 and

/M8_Option sets record and playback operating mode.
MSEL1 24

Mode Select2: This pin in conjunction with MSEL1 and

/M8_Option sets record and playback operating mode.
MSEL2 25

External Clock: This clock can be used instead of the internal-

clock for greater programming control and accuracy.
ExtClk 26

PIN NAME PIN NO. FUNCTIONALITY

Record Enable: this pin controls whether the device is in

write or read mode. Logic level high is read.
 /RE 27

Digital Positive Power Supply: This connection supplies power

for on-chip digital circuitry.
VCCD 28

3.3 RECORDING OF AUDIO MESSAGE

On power up, the device is ready to record or play back, in any of the enabled message
segments. To record, /CE must be set low to enable the device and /RE must be set low to enable
recording. You initiate recording by applying a low level on the message trigger pin that represents the
message segment you intend to use. The message trigger pins are labeled /M1_Message - /M8_Option
on pins 1-9 (excluding pin 7) for message segments 1-8 respectively.
When actual recording begins the device responds with a single beep (if the BE pin is high to
enable the beep tone) at the speaker outputs to indicate that it has started recording. Recording
continues as long as the message pin stays low. The rising edge of the same message trigger pin during
record stops the recording operation (indicated with a single beep).

If the message trigger pin is held low beyond the end of the maximum allocated duration
recording stops automatically (indicated with two beeps), regardless of the state of the message trigger
pin. The chip then enters low-power mode until the message trigger pin returns high. After the message
trigger pin returns to high, the chip enters standby mode. Any subsequent high to low transition on the
same message trigger pin will initiate recording from the beginning of the same message segment. The
entire previous message is then overwritten by the new message, regardless of the duration of the new
message. Transitions on any other message trigger pin or the /RE pin during the record operation are
ignored until after the device enters standby mode.

3.4 PLAY BACK OF RECORDED AUDIO MESSAGE

On power up, the device is ready to record or playback, in any of the enabled message
segments. To playback, /CE must be set low to enable the device and /RE must be set high to disable
recording & enable playback. You initiate playback by applying a high to low edge on the message
trigger pin that representing the message segment you intend to playback. Playback will continue until
the end of the message is reached. If a high to low edge occurs on the same message trigger pin during
playback, playback of the current message stops immediately.
If a different message trigger pin pulses during playback, playback of the current message stops
immediately (indicated by one beep) and playback of the new message segment begins. A delay equal to
8,400 cycles of the sample clock will be encountered before the device starts playing the new message.
If a message trigger pin is held low, the selected message is played back repeatedly as long as the trigger
pin stays low. A period of silence, of the duration equal to 8,400 cycles of the sampling clock, will be
inserted during looping as an indicator to the user of the transition between the end and the beginning
of the message.
 CHAPTER 5
DTMF RECEIVER

5.1 INTRODUCTION
DTMF stands for Dual Tone Multi Frequency. In TVM we are required to convey the information
of phone key pressed by the voter to the microcontroller for further processing. DTMF receiver converts
the analog signal to digital signal that could be fed to the microcontroller through BCD decoder. In this
project we have used HT9170 series of DTMF receiver.

5.2 GENERAL DESCRIPTION

The HT9170 series are Dual Tone Multi Frequency (DTMF) receivers integrated with digital
decoder and band-split filter functions. The HT9170D type supply power-down mode and inhibit mode
operations. It uses the digital counting techniques to detect and decode all the 16 DTMF tone pairs into
a 4-bit code output. Highly accurate switched capacitor filters are employed to divide tone (DTMF)
signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the
need for pre-filtering.

5.2.1 Features
 Operating voltage: 2.5V~5.5V
 Minimal external components
 No external filter is required
 Low standby current (on power down mode)
 Excellent performance
 Tristate data output for µC interface
 3.58MHz crystal or ceramic resonator
 1633Hz can be inhibited by the INH pin
 HT9170D: 18-pin SOP package
5.2.2 Pin Configuration

Fig. 5.1 Pin configuration

Table 5.1 Pin Description

Pin Name I/O Internal Connection Description

VP I OPERATIONAL AMPLIFIER Operational amplifier non-inverting input

VN I Operational amplifier inverting input

GS O Operational amplifier output terminal

 VREF O VREF Reference voltage output, normally VDD/2

X1 I The system oscillator consists of an

inverter, a bias resistor and the necessary
OSCILLATOR
load capacitor on chip. A standard
3.579545MHz crystal connected to X1 and
X2 O
X2 terminals implements the oscillator
function.

PWDN I CMOS IN Active high. This enables the device to go

into power down mode and inhibits the
Pull-low
oscillator.

Pin Name I/O Internal Connection Description

INH I CMOS IN Logic high. This inhibits the detection of

tones representing characters A, B, C and
Pull-low
D. This pin input is internally pulled down.

VSS --- --------- Negative power supply

OE I CMOS IN D0~D3 output enable, high active

Pull-high

D0-D3 O CMOS OUT Receiving data output terminals

Tristate OE=_H_: Output enable

OE=_L_: High impedance

DV O CMOS OUT Data valid output When the chip receives

a valid tone (DTMF) signal, the DV goes
high; otherwise it remains low.

EST O CMOS OUT Early steering output (see Functional

Description)

RT/GT I/O CMOS IN/OUT Tone acquisition time and release time can
be set through connection with external
 resistor

Pin Name I/O Internal Connection Description

VDD --- ----------- Positive power supply, 2.5V~5.5V for

normal operation

DVB O CMOS OUT One-shot type data valid output, normal

high, when the chip receives a valid time
(DTMF) signal, the DVB goes low for 10ms.

5.3 FUNCTIONAL DESCRIPTION

The HT9170 series tone decoders consist of three band pass filters and two digital decode
circuits to convert a tone (DTMF) signal into digital code output. The pre-filter is a band rejection filter
which reduces the dialing tone from 350Hz to 400Hz. The low group filter filters low group frequency
signal output whereas the high group filter filters high group frequency signal output. When each signal
amplitude at the output exceeds the specified level, it is transferred to full swing logic signal. When
input signals are recognized to be effective, DV becomes high, and the correct tone code (DTMF) digit is
transferred.

When one of the telephone set's buttons is pressed two tones are produced: One signifying the
row and the other the column. The frequencies are chosen thus that they don't contain harmonic
frequencies of each other. Normal human speech doesn't contain mixed frequencies that are stable for
a significant duration.

Table 5.2 Dual Tone Multi Frequencies

1 2 3 A 697

4 5 6 B 770

7 8 9 C 852
 0 * # D 941

1209 1336 1477 1633 Hz

When the voltage of RT/GT changes from 0 to VTRT (2.35V for 5V supply), the input signal is
effective and the correct code will be created by the code detector. After D0~D3 are completely latched,
DV output becomes high. When the voltage of RT/GT falls down from VDD to VTRT (i.e.., when there is
no input tone), DV output becomes low, and D0~D3 keeps data until a next valid tone input is produced.

CHAPTER 6
BCD TO DECIMAL DECODER

6.1 INTRODUCTION
In TVM project DTMF output is fed to microcontroller through BCD to Decimal Decoder. For this
we selected DM74154 4-to-16 line decoder. It is 24 pin IC with 4 input lines and 16 output lines. In this
project we have used only 4 output line to cast vote to 4 different candidates.

6.2 General Description

BCD to Decimal Decoder utilizes TTL circuitry to decode four binary-coded inputs into one of
sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The de-
multiplexing function is performed by using the 4 input lines to address the output line, passing data
from one of the strobe inputs with the other strobe input low. When either strobe input is high, all
outputs are high. These de-multiplexers are ideally suited for implementing high-performance memory
decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line
effects and thereby simplify system design.

6.2.1 Features

 Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs

 Performs the de-multiplexing function by distributing data from one input
line to any one of 16 outputs
 Input clamping diodes simplify system design
 High fan-out, low-impedance, totem-pole outputs
 Typical propagation delay
3 levels of logic 19 ns
Strobe 18 ns

 Typical power dissipation 170 mW

 Alternate Military/Aerospace device (54154) is available. Contact a National
Semiconductor Sales Office/Distributor for specifications.

6.2.2 Pin Configuration

 Fig. 6.1 Pin configuration

6.2.3 Logic Diagram

 Fig. 6.2 Logic diagram

6.2.4 FUNCTION TABLE

Table 6.1
H=High Level, L=Low Level, X=Don’t Care.

CHAPTER 7
MICROCONTROLLER 89S52
7.1 INTRODUCTION

The AT89S52 is a low-power, high-performance CMOS 8-bit

microcontroller with 8K bytes of in-system programmable Flash memory. The
device is manufactured using Atmel’s high-density nonvolatile memory
technology and is compatible with the industry- standard 80C51 instruction set and
pin out. The on-chip Flash allows the program memory to be reprogrammed in-
system or by a conventional nonvolatile memory programmer. By combining a
versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the
Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible
and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash,

256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex serial
port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed
with static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port, and Interrupt system to continue functioning.
The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next interrupt or hardware reset.

7.2 FEATURES

– Compatible with MCS-51® Products

– 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
– 4.0V to 5.5V Operating Range
 – Fully Static Operation: 0 Hz to 33 MHz
– Three-level Program Memory Lock
– 256 x 8-bit Internal RAM
– 32 Programmable I/O Lines
– Three 16-bit Timer/Counters
– Eight Interrupt Sources
– Full Duplex UART Serial Channel
– Low-power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– Watchdog Timer
– Dual Data Pointer
– Power-off Flag
– Fast Programming Time
– Flexible ISP Programming (Byte and Page Mode)

7.3 BLOCK DIAGRAM

 Figure 7.1

7.4 PIN DESCRIPTION

 Figure 7.2

VCC Supply voltage.

GND Ground.
Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 can also be configured to be the multiplexed low-order
address/data bus during accesses to external program and data memory. In this mode,
 P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming
and outputs the code bytes during program verification. External pull-ups are required
during program verification.

Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table. Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port
2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses. In this application,
Port 2 uses strong internal pull-ups when emitting 1s.

Table 7.1 Alternate Functions of Port1

Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
 by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL) because of the pull-ups. Port 3
receives some control signals for Flash programming and verification. Port 3 also serves
the functions of various special features of the AT89S52, as shown in the following table.

Table 7.2 Alternate Functions of Port3

RST Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives high for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the
default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG)
during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external data memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit
set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external
execution mode.
PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the
AT89S52 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory.

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for Internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2 Output from the inverting oscillator amplifier.

7.5 MEMORY ORGANISATION

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes
each of external Program and Data Memory can be addressed.

7.5.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the
AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to
internal memory and fetches to addresses 2000H through FFFFH are to external memory.

7.5.2 Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. This means that the upper 128 bytes have the same
addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an
internal location above address 7FH, the address mode used in the instruction specifies whether the
CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing
access the SFR space. For example, the following direct addressing instruction accesses the SFR at
location 0A0H (which is P2).

EXAMPLE: MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following
indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather
than P2 (whose address is 0A0H).
EXAMPLE: MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are
available as stack space.

7.6 FUNCTIONAL DESCRIPTION

The function of the pins of microcontroller AT89S52 used in the TELEVOTING MACHINE can be
described as follows:

– Pin no 1,2,3,4 of PORT 1 are connected to get the vote data input from 74154 (BCD to DECIMAL
decoder) for four different candidates.
– Pin no 5,6,7,8 are connected to four push-button switches to check the vote data casted for
individual candidate.
– Pin no 9 is connected to the reset button to reset the microcontroller automatically when we
switch on the power. It is a Power on reset.
– Pin no 10 of PORT 3 is connected to a push-button switch to check the total vote caste for all the
candidates.
– Pin no 11 and 12 of PORT 3 are connected to two push-button switches (R-1 and R-2) to reset or
clear all the vote data. To reset the data firstly we will press the R-1 button then press the R-2
button and again press the R-1 button. Then all the vote data has to be cleared from the
AT24c02 flash memory.
– Crystal is connected to the pin no 18(XTAL 1) and pin no 19(XTAL 2) providing 11.0592 MHz
frequency.
– Pin no 20 is connected to the ground (GND).
– Pin no 21 and 22 of PORT 2 are connected to pin no 5(SDA- serial data) and pin no 6 (SCL- serial
clock input) of AT24c02 flash memory.
– Pin no 26, 27, 28 of PORT 2 are connected to the pin no 4, 5, 6 of LCD display. Pin no 26 is
connected to RS (register select), pin no 27 is connected to R/W (read/write select) and pin no
28 is connected to En(chip enable signal) of LCD.
– Pin no 31( EA/Vpp) should be strapped to VCC for internal program executions, this pin also
receives the 12-volt programming enable voltage (VPP) during flash programming.
– Pin no 32 – 39 of PORT 0 are connected to the DB0-DB7 (8-bit) data lines of LCD display.
– Pin no 40 is connected to the positive supply (Vcc).

CHAPTER 8
LIQUID CRYSTAL DISPLAY

8.1 INTRODUCTION
 Figure 8.FFFF
FIG. 8.1
Liquid Crystal Display also called as LCD is very helpful in providing user interface as well as for
debugging purpose. The most common type of LCD controller is HITACHI 44780 which provides a simple
interface between the controller & an LCD. These LCD's are very simple to interface with the controller
as well as are cost effective.
The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16 characters), 2x16
(Double Line & 16 character per line) & 4x20 (four lines & Twenty characters per line).
The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on data lines
depends on the mode of operation. If operated in 8-bit mode then 8 data lines + 3 control lines i.e. total
11 lines are required. And if operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are
required. How do we decide which mode to use? It’s simple if you have sufficient data lines you can go
for 8 bit mode & if there is a time constrain i.e. display should be faster then we have to use 8-bit mode
because basically 4-bit mode takes twice as more time as compared to 8-bit mode.

8.2 PIN DESCRIPTION

Figure 8.2
Table 8.1 Pin Description of LCD

 Pin  Symbol Function

 1  Vss  Ground

 2  Vdd  Supply Voltage

 Pin  Symbol Function

 3  Vo  Contrast Setting

 4  RS  Register Select

 5  R/W  Read/Write Select

 6  En  Chip Enable Signal

 7-14  DB0-DB7  Data Lines

 15  A/Vee  Gnd for the backlight

 16  K  Vcc for backlight

1.RS(Register Select)
When RS is low (0), the data is to be treated as a command. When RS is high (1), the data being sent
is considered as text data which should be displayed on the screen.

2. R/W(Read/Write)
When R/W is low (0), the information on the data bus is being written to the LCD. When RW is high (1),
the program is effectively reading from the LCD. Most of the times there is no need to read from the LCD
so this line can directly be connected to GND thus saving one controller line.

3. E(enable)
The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW signal is required to
latch the data. The LCD interprets and executes our command at the instant the EN line is brought low.
If you never bring EN low, your instruction will never be executed.

4. D0-D7
The 8 bit data pins D0-D7 are used to send information to the LCD or read the contents of the LCD’s
internal registers. .To display any character on LCD micro controller has to send its ASCII value to the
data bus of LCD. For e.g. to display 'AB' microcontroller has to send two hex bytes 41h and 42h
respectively LCD display used here is having 16x2 size. It means 2 lines each with 16 characters.
In 4-bit mode the data is sent in nibbles, first we send the higher nibble and then the lower nibble. To
enable the 4-bit mode of LCD, we need to follow special sequence of initialization that tells the LCD
controller that user has selected 4-bit mode of operation. We call this special sequence as resetting the
LCD. Following is the reset sequence of LCD.
 Wait for about 20mS
 Send the first init value (0x30)
 Wait for about 10mS
 Send second init value (0x30)
 Wait for about 1mS
 Send third init value (0x30)
 Wait for 1mS
 Select bus width (0x30 - for 8-bit and 0x20 for 4-bit)
 Wait for 1mS
8.3 LCD CONNECTIONS IN 4-BIT MODE
 Figure 8.3
Sending data/command in 4-bit Mode
The common steps are:
 Mask lower 4-bits
 Send to the LCD port
 Send enable signal
 Mask higher 4-bits
 Send to LCD port
 Send enable signal

8.4 FUNCTIONAL DESCRIPTION

8.4.1 Writing and reading the data from the LCD

Writing data to the LCD is done in several steps:
1) Set R/W bit to low
2) Set RS bit to logic 0 or 1 (instruction or character)
3) Set data to data lines (if it is writing)
4) Set E line to high
5) Set E line to low

Read data from data lines (if it is reading):

 1) Set R/W bit to high
2) Set RS bit to logic 0 or 1 (instruction or character)
3) Set data to data lines (if it is writing)
4) Set E line to high
5) Set E line to low

EXAMPLE:

Fig. 8.4

8.5 LCD COMMAND CODES

1. CLEAR DISPLAY SCREEN
2. RETURN HOME
4 DECREMENT CURSOR ( SHIFT CURSOR TO LEFT)
5 SHIFT DISPLAY RIGHT.
6. INCREMENT CURSOR ( SHIFT CURSOR TO RIGHT)
7. SHIFT DISPLAY LEFT
8. DISPLAY OFF, CURSOR OFF
A DISPLAY OFF CURSOR ON
C DISPLAY ON CURSOR OFF
E DISPLAY ON CURSOR BLINKING
F. DISPLAY ON CURSOR BLINKING.
10. SHIFT CURSOR POSITION TO LEFT
14. SHIFT CURSOR POSITION TO RIGHT
18. SHIFT THE ENTIRE DISPLAY TO THE LEFT
1C SHIFT THE ENTIRE DISPLAY TO THE RIGHT
80 FORCE CURSOR TO BEGINNING OF IST LINE
C0 FORCE CURSOR TO BEGINNING OF 2ND LINE
38 2 LINES AND 5 X 7 MATRIX

8.5.1 Checking the busy status of LCD

The code to check the status of LCD whether it is busy or not is as follows:
WAIT_LCD:
SETB EN ;Start LCD command
CLR RS ;It's a command
SETB RW ;It's a read command
MOV DATA, #0FFh ;Set all pins to FF initially
MOV A,DATA ;Read the return value
JB ACC.7,WAIT_LCD ;If bit 7 high, LCD still busy
CLR EN ;Finish the command
CLR RW ;Turn off RW for future commands
RET

Thus, our standard practice will be to send an instruction to the LCD and then call our WAIT_LCD
routine to wait until the instruction is completely executed by the LCD. This will assure that our program
gives the LCD the time it needs to execute instructions and also makes our program compatible with any
LCD, regardless of how fast or slow it is.

8.5.2 Initializing the LCD

The code to initialize the LCD is as follows:
INIT_LCD:
SETB EN
CLR RS
MOV DATA, #38h
CLR EN
LCALL WAIT_LCD
SETB EN
CLR RS
MOV DATA, #0Eh
CLR EN
LCALL WAIT_LCD
SETB EN
CLR RS
MOV DATA, #06h
CLR EN
LCALL WAIT_LCD
RET
Having executed this code the LCD will be fully initialized and ready for us to send display data
to it.

8.5.3 Clearing the display

The code to clear the LCD display is as follows:
CLEAR_LCD:
SETB EN
CLR RS
MOV DATA,#01h
CLR EN
LCALL WAIT_LCD
RET
we may clear the LCD at any time by simply executing an LCALL CLEAR_LCD.

8.5.4 Writing text to the LCD

The code to write any text to the LCD is as follows:
WRITE_TEXT:
 SETB EN
SETB RS
MOV DATA,A
CLR EN
LCALL WAIT_LCD
RET

The WRITE_TEXT routine that we just wrote will send the character in the accumulator to the
LCD which will, in turn, display it. Thus to display text on the LCD all we need to do is load the
accumulator with the byte to display and make a call to this routine.

CHAPTER 9
 AT24c02 FLASH MEMORY

9.1 INTRODUCTION
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically
erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words
of 8 bits each. The device is optimized for use in many industrial and commercial applications where low
power and low voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-
saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23
(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-
wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.

9.2 FEATURES
 Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
 Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
 Two-wire Serial Interface
 Schmitt Trigger, Filtered Inputs for Noise Suppression
 Bidirectional Data Transfer Protocol
 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
 Write Protect Pin for Hardware Data Protection
 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
 Partial Page Writes Allowed
 Self-timed Write Cycle (5 ms max)
 High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
9.3 BLOCK DIAGRAM

Fi
g. 9.1

9.4 PIN DESCRIPTION

 Figure 9.2

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard
wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single
bus system (device addressing is discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices
may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may
be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to
ground. The AT24C16A does not use the device address pins, which limits the number of devices on a
single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.

Table 9.1 Pin Description of Flash Memory

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware
data protection. The Write Protect pin allows normal Read/Write operations when connected to ground
(GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and
operates as shown in table 9.2

Table 9.2 Status of Write Protect pin

9.5 MEMORY ORGANISATION

AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-
bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-
bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-
bit data word address for random word addressing.
AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a
10-bit data word address for random word addressing.
AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires
an 11-bit data word address for random word addressing.

9.6 DEVICE OPERATION

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on
the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will
indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode.
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during
the ninth clock cycle.
STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2- wire part can be
reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

CHAPTER 10
PROJECT DESCRIPTION

10.1 CIRCUIT DIAGRAM

 Figure 10.1
10.2 FLOWCHART
The flowchart depicts the working of the project.

START

INITIALISE THE LCD

DISPLAY INITIAL MESSAGE

VOTING MACHINE
IGIT - VOTING

CHECK THE STATUS OF P3.3

IS P3.3= 0

NO

YES
DISPLAY THE MESSAGE
CAST THE VOTE

PROVIDE A DELAY OF 20s.

1
 Figure 10.2

CHECK THE STATUS OF P1.0

IS P1.0 = 0

NO 3

YES
GET THE NO. OF VOTES FOR CANDIDATE 1 FROM MEMORY.

INCREMENT THE NO. OF VOTES BY 1.

STORE THE NO. OF VOTES FOR CANDIDATE 1 INTO MEMORY.

DISPLAY ON LCD
VOTE CASTED

2
 Figure 10.2 Contd…

CHECK THE STATUS OF P1.1

IS P1.1 = 0

NO
4

YES

GET THE NO. OF VOTES FOR CANDIDATE 2 FROM MEMORY.

INCREMENT THE NO. OF VOTES BY 1.

STORE THE NO. OF VOTES FOR CANDIDATE 2 INTO MEMORY.

DISPLAY ON LCD
VOTE CASTED

2
 Figure 10.2 Contd…

CHECK THE STATUS OF P1.2

IS P1.2 = 0
NO
5

YES
GET THE NO. OF VOTES FOR CANDIDATE 3 FROM MEMORY.

INCREMENT THE NO. OF VOTES BY 1.

STORE THE NO. OF VOTES FOR CANDIDATE 3 INTO MEMORY.

DISPLAY ON LCD
VOTE CASTED

2
 Figure 10.2 Contd…

CHECK THE STATUS OF P1.3

IS P1.3 = 0

NO 2

YES
GET THE NO. OF VOTES FOR CANDIDATE 4 FROM MEMORY.

INCREMENT THE NO. OF VOTES BY 1.

STORE THE NO. OF VOTES FOR CANDIDATE 4 INTO MEMORY.

DISPLAY ON LCD
VOTE CASTED

2
 Figure 10.2 Contd…

CHECK THE STATUS OF P1.4 IS P1.4 = 0

NO

YES
GET THE NO. OF VOTES FOR CANDIDATE 1 FROM MEMORY.

DISPLAY ON LCD

CHECK THE STATUS OF P1.5

IS P1.5 = 0
NO 6

YES
GET THE NO. OF VOTES FOR CANDIDATE 2 FROM MEMORY.

DISPLAY ON LCD

6
 Figure 10.2 Contd…

CHECK THE STATUS OF P1.6 IS P1.6 = 0

NO

YES

GET THE NO. OF VOTES FOR CANDIDATE 3 FROM MEMORY.

DISPLAY ON LCD

CHECK THE STATUS OF P1.7

IS P1.7 = 0

NO 7

YES

YES
GET THE NO. OF VOTES FOR CANDIDATE 4 FROM MEMORY.

DISPLAY ON LCD

Figure 10.2 Contd…

 7

CHECK THE STATUS OF P3.0 IS P3.0 = 0

NO

YES
GET THE TOTAL NO. OF VOTES FROM MEMORY.

DISPLAY ON LCD

CHECK THE STATUS OF P3.1

IS P3.1 = 0

A
NO

8YES

Figure 10.2 Contd…

 8

CHECK THE STATUS OF P3.2

IS P3.2 = 0

NO
A

YES
CHECK THE STATUS OF P3.1
IS P3.1 = 0

MAKE TOTAL NO. OF VOTES TO ZERO AND STORE IT IN THE MEMORY

DISPLAY ON LCD ALL CLEARED

Figure 10.2 Contd…

 10.2.1 Flow Chart for Phone Ring Sensor Circuit

START

WHEN CALLL IS MADE TO CAST THE VOTE . THE FIRST RING SEND A LOW SIGNAL TO P3.3.

THE 2ND RING CAUSES THE APR 9600 TO PLAY AUDIO MESSAGE.

ONNECTS 220Ω RESISTANCE ACROSS TELEPHONE LINE THAT DISCONNECTS THE RINGER FROM TELEPHONE LINE IN THE EXCHAN

THE VOTER CAST THE VOTE AFTER LISTENING THE AUDIO MESSAGE.

Figure 10.3
THE CALL IS DISCONNECTED AFTER 1.5 MINUTE .TURNED ON.
10.4 ASSEMBLY CODE

Program code is to be written

STOPin the asm code and after this, the code is
converted into hex code using Keil µ vision3 and transfer onto the blank chip
AT89s52 microcontroller with the help of programmer kit SPIPGM37.
 The program code of TELEVOTING MACHINE using AT89s52
microcontroller chip is as follows:
LCD_RS EQU P2.5
LCD_RW EQU P2.6
LCD_ENEQU P2.7
SDA EQU P2.1
SCL EQU P2.0
KEY 0 EQU P1.0
KEY1 EQU P1.1
KEY 2 EQU P1.2
KEY 3 EQU P1.3
KEY4 EQU P1.4
KEY 5 EQU P1.5
KEY 6 EQU P1.6
KEY 7 EQU P1.7
KEY 8 EQU P3.0
KEY 9 EQU P3.1
KEY 10 EQU P3.2
KEY 11 EQU P3.3

ORG 0000H
LJMP MAIN

ORG 0003H
RETI
;ljmp ex0_isr

ORG 000BH
RETI
;ljmp tim0_isr
ORG 0013H
RETI
;ljmp ex1_isr
ORG 001BH
RETI
;ljmp tim1_isr

ORG 0023H
RETI
;ljmp ser_isr

MAIN:
LCALL DELAY41
LCALL DELAY41
LCALL DELAY41
 LCALL DELAY41
LCALL DELAY41
LCALL DELAY41
MOV 129 , # 040H
MOV 137 , # 00H
MOV 136 , # 00H
MOV 168 , # 00H
MOV 184 , # 00H
MOV 152 , # 00H

MOV 128 , # 0FFH

MOV 144 , # 0FFH
MOV 160 , # 0FFH
MOV 176, # 0FFH
CLR WP
LCALL DELAY41
CLR LCD_RS
CLR LCD_RW
CLR LCD_EN
CLR LED
SETB SDA
SETB SCL

MAIN1:
MOV A , # 0
MOV 45 , A
MOV A, #00H
CALL READ_RANDOM
JC MAIN1
MOV 34 , A

MAIN2:
MOV A , # 1
MOV 45 , A
MOV A, #00H
CALL READ_RANDOM
JC MAIN2
MOV 35 , A

MAIN3:
MOV A , # 2
MOV 45 , A
MOV A, #00H
CALL READ_RANDOM
JC MAIN3
MOV 36 , A

MAIN4:
 MOV A, # 3
MOV 45, A
MOV , #00H
CALL READ_RANDOM
JC MAIN4
MOV 37 , A

MAIN5:
MOV A , # 4
MOV 45 , A
MOV A, #00H
CALL READ_RANDOM
JC MAIN5
MOV 38 , A

MAIN6:
MOV A , # 5
MOV 45 , A
MOV A, #00H
CALL READ_RANDOM
JC MAIN6
MOV 39 , A

MAIN7:
MOV A , # 6
MOV 45 , A
MOV A,#00H
CALL READ_RANDOM
JC MAIN7
MOV 40 , A

MAIN8:
MOV A , # 7
MOV 45 , A
MOV A,#00H
CALL READ_RANDOM
JC MAIN8
MOV 41, A

MAIN9:
MOV A, # 8
MOV 45, A
MOV A, #00H
CALL READ_RANDOM
JC MAIN9
MOV 42, A

MAIN10:
 MOV A, # 9
MOV 45, A
MOV A, #00H
CALL READ_RANDOM
JC MAIN10
MOV 43, A
SETB WP
CLR RST_FLG
CLR CLR_FLG1
CLR CLR_FLG2

;Initialize LCD

MOV 128, # 038H

LCALL COMMAND_BYTE
LCALL DELAY41
MOV 128, # 038H
LCALL COMMAND_BYTE
LCALL DELAY1
MOV 128, # 038H
LCALL COMMAND_BYTE
LCALL DELAY1
MOV 128, # 038H
LCALL COMMAND_BYTE ;1/16 duty, 5x7 char
LCALL DELAY1
MOV 128, # 008H
LCALL COMMAND_BYTE
LCALL DELAY1
MOV 128, # 00CH
LCALL COMMAND_BYTE
LCALL DELAY1
MOV 128, # 006H
LCALL COMMAND_BYTE
LCALL DELAY1
LCALL DISPLAY

MAIN_LP1:
LCALL DELAY41
JB KEY0,NXT_KEY1
LJMP ACT_KEY0

NXT_KEY1:
JB KEY1,NXT_KEY2
LJMP ACT_KEY1

NXT_KEY2:
JB KEY2,NXT_KEY3
LJMP ACT_KEY2
NXT_KEY3:
JB KEY3,NXT_KEY4
LJMP ACT_KEY3

NXT_KEY4:
JB KEY4,NXT_KEY5
LJMP ACT_KEY4

NXT_KEY5:
JB KEY5,NXT_KEY6
LJMP ACT_KEY5

NXT_KEY6:
JB KEY6,NXT_KEY7
LJMP ACT_KEY6

NXT_KEY7:
JB KEY7,NXT_KEY8
LJMP ACT_KEY7

NXT_KEY8:
JB KEY8,NXT_KEY9
LJMP ACT_KEY8
NXT_KEY9:
JB KEY9,NXT_KEY10
LJMP ACT_KEY9

NXT_KEY10:
JB KEY10,NXT_KEY11
LJMP ACT_KEY10

NXT_KEY11:
JB KEY11,NXT_KEY12
LJMP ACT_KEY11

NXT_KEY12:
LJMP MAIN_LP1

ACT_KEY1:
CLR CLR_FLG1
CLR CLR_FLG2
MOV 33, # '1'
JB RST_FLG,INC_CNT1
JMP EXIT_KEY1

INC_CNT1:
MOV A , 34
 ADD A, #01H
DA A
MOV 34 , A
MOV A , 35
ADDC A, #00H
DA A
MOV 35 , A
MOV A , 42
ADDA, #01H
DA A
MOV 42 , A
MOV A , 43
ADDC A, #00H
DAA
MOV 43 , A
CLR RST_FLG
LCALL VOTE_CASTED
LCAL SAVE_DATA

EXIT_KEY1:
LJMP MAIN_LP1

ACT_KEY2:
CLR CLR_FLG1
CLR CLR_FLG2
MOV 33 , # '2'
JB RST_FLG,INC_CNT2
JMP EXIT_KEY2

INC_CNT2:
MOV A , 36
ADD A, #01H
DAA
MOV 36 , A
MOV A , 37
ADDC A, #00H
DAA
MOV 37 , A
MOV A , 42
ADD A, #01H
DA A
MOV 42 , A
MOV A , 43
ADDC A, #00H
DA A
MOV 43 , A
CLR RST_FLG
LCALL VOTE_CASTED
 LCALL SAVE_DATA

EXIT_KEY2:
LJMP MAIN_LP1

ACT_KEY3:
CLR CLR_FLG1
CLR CLR_FLG2
MOV 33 , # '3'
JB RST_FLG,INC_CNT3
JMP EXIT_KEY3

INC_CNT3:

MOV A , 38
ADD A, #01H
DA A
MOV 38 , A
MOV A , 39
ADDC A, #00H
DA A
MOV 39 , A
MOV A , 42
ADD A, #01H
DA A
MOV 42 , A
MOV A , 43
ADDC A, #00H
DA A
MOV 43 , A
CLR RST_FLG
LCALL VOTE_CASTED
LCALL SAVE_DATA

EXIT_KEY3:

LJMP MAIN_LP1

ACT_KEY4:
CLR CLR_FLG1
CLR CLR_FLG2
MOV 33 , # '4'
JB RST_FLG,INC_CNT4
JMP EXIT_KEY4

INC_CNT4:
MOV A , 40
ADD A, #01H
 DA A
MOV 40 , A
MOV A , 41
ADDC A, #00H
DA A
MOV 41 , A
MOV A , 42
ADD A, #01H
DA A
MOV 42 , A
MOV A , 43
ADDC A, #00H
DA A
MOV 43 , A
CLR RST_FLG
LCALL VOTE_CASTED
LCALL SAVE_DATA

EXIT_KEY4:
LJMP MAIN_LP1

;key to see total vote casted for candidate-1

ACT_KEY5:
CLR CLR_FLG1
CLR CLR_FLG2
LCALL DISP_CNT1
MOV 33 , # '5'
LJMP MAIN_LP1

;key to see total vote casted for candidate-2

ACT_KEY6:
CLR CLR_FLG1
CLR CLR_FLG2
LCALL DISP_CNT2
MOV 33 , # '6'
LJMP MAIN_LP1
;key to see total vote casted for candidate-3

ACT_KEY7:
CLR CLR_FLG1
CLR CLR_FLG2
LCALL DISP_CNT3
MOV 33 , # '7'
LJMP MAIN_LP1

;key to see total vote casted for candidate-4

ACT_KEY8:
CLR CLR_FLG1
CLR CLR_FLG2
LCALL DISP_CNT4
MOV 33 , # '8'
LJMP MAIN_LP1

;key to see total number of vote casted

ACT_KEY9:
CLR CLR_FLG1
CLR CLR_FLG2
LCALL DISP_TOTAL
MOV 33, # '9'
LJMP MAIN_LP1

;key to reset all counters

ACT_KEY0:
JNB CLR_FLG2,SKP_ACT0
LCALL CLR_CNTRS
LCALL SAVE_DATA
CLR CLR_FLG1
CLR CLR_FLG2
SJMP EXIT_ACT0

SKP_ACT0:
SETB CLR_FLG1
MOV 33 , # '0'

EXIT_ACT0:
LJMP MAIN_LP1

;key to reset all counters

ACT_KEY10:
JNB CLR_FLG1,EXIT_ACT10
SETB CLR_FLG2
MOV 33 , # 'a'

EXIT_ACT10:
LJMP MAIN_LP1

;reset key for enabling new vote casting

ACT_KEY11:
CLR CLR_FLG1
 CLR CLR_FLG2
MOV 33 , # 62H
SETB RST_FLG
LCALL CAST_VOTE
LJMP MAIN_LP1

DISP_TOTAL:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_TOTAL
LCALL WRITE_MSG
MOV 128 , # 0C6H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV A , 43
ANL A,#0F0H
SWAP A
ADD A,#30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 43
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 42
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 42
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
RET

DISP_CNT1:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_CNT1
LCALL WRITE_MSG
MOV 128 , # 0C6H
LCALL COMMAND_BYTE
LCALL DELAY41
 MOV A , 35
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 35
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 34
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 34
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
RET

DISP_CNT2:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_CNT2
LCALL WRITE_MSG
MOV 128 , # 0C6H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV A , 37
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 37
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 36
ANL A, #0F0H
SWAP A
 ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 36
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
RET

DISP_CNT3:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_CNT3
LCALL WRITE_MSG
MOV 128 , # 0C6H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV A , 39
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 39
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 38
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 38
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
RET

DISP_CNT4:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_CNT4
 LCALL WRITE_MSG
MOV 128 , # 0C6H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV A , 41
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 41
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 40
ANL A, #0F0H
SWAP A
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
MOV A , 40
ANL A, #0FH
ADD A, #30H
MOV 128 , A
LCALL DATA_BYTE
RET

CLR_CNTRS:
MOV A, #00H
MOV 34 , A
MOV 35 , A
MOV 36 , A
MOV 37 , A
MOV 38 , A
MOV 39 , A
MOV 40 , A
MOV 41 , A
MOV 42 , A
MOV 43 , A
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG_CLR
LCALL WRITE_MSG
RET

VOTE_CASTED:
 MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG4
LCALL WRITE_MSG
CLR LED
RET

CAST_VOTE:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
MOV DPTR,#MSG3
LCALL WRITE_MSG
SETB LED
RET

CLR_LCD:
MOV 128 , # 001H
LCALL COMMAND_BYTE
LCALL DELAY41
RET

DISPLAY:
MOV 128 , # 080H
LCALL COMMAND_BYTE
LCALL DELAY1
MOV DPTR,#MSG1
LCALL WRITE_MSG
MOV 128 , # 0C0H
LCALL COMMAND_BYTE
LCALL DELAY1
MOV DPTR,#MSG2
LCALL WRITE_MSG
SETB LED
RET

WRITE_MSG:
MOV A, #00H
MOVC A, @A+DPTR
CJNE A, #'$',WRITE_CONT
RET

WRITE_CONT:
MOV 128 , A
LCALL DATA_BYTE
INC DPTR
LJMP WRITE_MSG
COMMAND_BYTE:
CLR LCD_RS
LJMP CMD10

DATA_BYTE:
SETB LCD_RS
NOP

CMD10:
CLR LCD_RW
NOP
SETB LCD_EN
NOP
CLR LCD_EN
RET

DELAY1:
MOV R0, #00H

DELAY10:
DJNZ R0, DELAY10
RET

DELAY41:
MOV R0, #00H
MOV R1, #0FH

DLP410:
DJNZ R0, DLP410
DJNZ R1, DLP410
RET

SAVE_DATA:
CLR WP
LCALL DELAY41

SAVE1:
MOV A , 34
MOV 44 , A
MOV A , # 0
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE1

SAVE2:
LCALL DELAY41
 MOV A , 35
MOV 44 , A
MOV A , # 1
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE2

SAVE3:
LCALL DELAY41
MOV A , 36
MOV 44 , A
MOV A , # 2
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE3

SAVE4:
LCALL DELAY41
MOV A , 37
MOV 44 , A
MOV A , # 3
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE4

SAVE5:
LCALL DELAY41
MOV A , 38
MOV 44 , A
MOV A , # 4
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE5

SAVE6:
LCALL DELAY41
MOV A , 39
MOV 44 , A
MOV A , # 5
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE6
SAVE7:
LCALL DELAY41
MOV A , 40
MOV 44 , A
MOV A , # 6
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE7

SAVE8:
LCALL DELAY41
MOV A , 41
MOV 44 , A
MOV A , # 7
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE8

SAVE9:
LCALL DELAY41
MOV A , 42
MOV 44 , A
MOV A , # 8
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE9

SAVE10:
LCALL DELAY41
MOV A , 43
MOV 44 , A
MOV A , # 9
MOV 45 , A
MOV A, #00H
LCALL WRITE_BYTE
JC SAVE10
LCALL DELAY41
SETB WP
RET

WRITE_BYTE:
; AT24Cxx Byte Write function.
; Called with programmable address in A, byte address in
; register ADDR_LO, data in register ZDATA.
; Does not wait for write cycle to complete.
; Returns CY set to indicate that the bus is not available
; or that the addressed device failed to acknowledge.
; Destroys A.

LCALL START
JC X49 ; abort if bus not available
RL A ; programmable address to bits 3:1
ORL A , # 160
CLR ACC.0 ; specify write operation
LCALL SHOUT ; send device address
JC X48 ; abort if no acknowledge
MOV A , 45
LCALL SHOUT
JC X48 ; abort if no acknowledge
MOV A , 44
LCALL SHOUT ; send data
JC X48 ; abort if no acknowledge
CLR C
; clear error flag
X48:
LCALL STOP
X49:
RET

READ_CURRENT:

; AT24Cxx Current Address Read function.

; Called with programmable address in A. Returns data in A.
; Returns CY set to indicate that the bus is not available
; or that the addressed device failed to acknowledge.

LCALL START
JC X45 ; abort if bus not available
RL A ; programmable address to bits 3:1
ORL A , # 160
SETB ACC.0 ; specify read operation
LCALL SHOUT ; send device address
JC X44 ; abort if no acknowledge
LCALL SHIN ; receive data byte
LCALL NAK ; do not acknowledge byte
CLR C ; clear error flag

X44:
LCALL STOP
X45:
RET

READ_RANDOM:

; AT24Cxx Random Read function.

; Called with programmable address in A, byte address in
; register ADDR_LO. Returns data in A.
; Returns CY set to indicate that the bus is not available
; or that the addressed device failed to acknowledge.

PUSH 240
MOV 240 , A

; Send dummy write command to set internal address.

LCALL START
JC X47 ; abort if bus not available
RL A ; programmable address to bits 3:1
ORL A , # 160
CLR ACC.0 ; specify write operation
LCALL SHOUT ; send device address
JC X46 ; abort if no acknowledge
MOV A , 45
LCALL SHOUT
JC X46 ; abort if no acknowledge

; Call Current Address Read function.

MOV A , 240
LCALL READ_CURRENT
JMP X47 ; exit

X46:
LCALL STOP

X47:
POP 240
RET

START:
; Send START, defined as high-to-low SDA with SCL high.
; Return with SCL, SDA low.
; Returns CY set if bus is not available.

SETB SDA
 SETB SCL
NOP
NOP
NOP
NOP
NOP

; Verify bus available.

JNB SDA, X40 ; jump if not high

JNB SCL, X40 ; jump if not high
NOP
NOP
NOP
NOP
NOP ; enforce setup delay and cycle delay
CLR SDA
NOP
NOP
NOP
NOP
NOP
CLR SCL
NOP
NOP
NOP
NOP
NOP
CLR C ; clear error flag
JMP X41

X40:
SETB C ; set error flag

X41:
RET

STOP:
; Send STOP, defined as low-to-high SDA with SCL high.
; SCL expected low on entry. Return with SCL, SDA high.

CLR SDA
NOP ; enforce SCL low and data setup
NOP
NOP
NOP
NOP
 NOP
SETB SCL
NOP ; enforce setup delay
NOP
NOP
NOP
NOP
SETB SDA
NOP
NOP
NOP
NOP
NOP
RET

SHOUT:
; Shift out a byte to the AT24Cxx, most significant bit first.
; SCL, SDA expected low on entry. Return with SCL low.
; Called with data to send in A.
; Returns CY set to indicate failure by slave to acknowledge.
; Destroys A.

PUSH 240
MOV 240 , # 8

X42:
RLC A ; move bit into CY
MOV SDA, C ; output bit
NOP ; enforce SCL low and data setup
NOP
NOP
NOP
NOP
SETB SCL ; raise clock
NOP ; enforce SCL high
NOP
NOP
NOP
NOP
CLR SCL ; drop clock
DJNZ 240 , X42
SETB SDA ; release SDA for ACK
NOP ; enforce SCL low and tAA
NOP
NOP
NOP
NOP
 SETB SCL ; raise ACK clock
NOP ; enforce SCL high
NOP
NOP
NOP
NOP
MOV C, SDA ; get ACK bit
CLR SCL ; drop ACK clock
NOP
NOP
NOP
NOP
NOP
POP 240
RET

SHIN:
; Shift in a byte from the AT24Cxx, most significant bit first.
; SCL expected low on entry. Return with SCL low.
; Returns received data byte in A.

PUSH 240
MOV 240 , # 8

X43:
SETB SDA ; make SDA an input
NOP ; enforce SCL low and data setup
NOP
NOP
NOP
NOP
SETB SCL ; raise clock
NOP ; enforce SCL high
NOP
NOP
NOP
NOP
MOV C, SDA ; input bit
RLC A ; move bit into byte
CLR SCL ; drop clock
NOP
NOP
NOP
NOP
NOP
DJNZ 240 , X43
NOP
NOP
 NOP
NOP
NOP
POP 240
RET

ACK:
; Clock out an acknowledge bit (low).
; SCL expected low on entry. Return with SCL, SDA low.

CLR SDA ; ACK bit

NOP ; enforce SCL low and data setup
NOP
NOP
NOP
NOP
SETB SCL ; raise clock
NOP ; enforce SCL high
NOP
NOP
NOP
NOP
CLR SCL ; drop clock
NOP
NOP
NOP
NOP
NOP
RET

NAK:
; Clock out a negative acknowledge bit (high).
; SCL expected low on entry. Return with SCL low, SDA high.

SETB SDA ; NAK bit

NOP ; enforce SCL low and data setup
NOP
NOP
NOP
NOP
SETB SCL ; raise clock
NOP ; enforce SCL high
NOP
NOP
NOP
NOP
CLR SCL ; drop clock
 NOP
NOP
NOP
NOP
NOP
RET

MSG1:
DB ' VOTING-MACHINE$'

MSG2:
DB 'IGIT VOTING $'

MSG3:
DB '*CAST THE VOTE*$'

MSG4:
DB '**VOTE CASTED**$'

MSG_CLR:
DB '**All Cleared**$'

MSG_CNT1:
DB 'CANDIDATE 1$'

MSG_CNT2:
DB 'CANDIDATE 2$'

MSG_CNT3:
DB 'CANDIDATE 3$'

MSG_CNT4:
DB 'CANDIDATE 4$'

MSG_TOTAL:
DB 'Total Vote Cast$'
END

10.5 LIST OF COMPONENTS

Table 10.1 List of Components

S.NO. LIST OF COMPONENTS QUANTITY

1 220V, 50HZ, 9V-0-9V CENTRE TAP TRANSFORMER 1
2 7805 VOLTAGE REGULATOR 2
3 LIQUID CRYSTAL DISPLAY 1
 4 8Ω LOUD SPEAKER 1
5 CONDENSER MICROPHONE 1
6 89S52 MICROCONTROLLER 1
7 817 OPTOCOUPLER 1
8 555 TIMER 1
9 4017 DECADE COUNTER 1
S.NO. LIST OF COMPONENTS QUANTITY
10 APR 9600 1
11 9170 DTMF RECEIVER 1
12 74154 1
4LINE TO 16LINE DECODER
13 24C02 EEPROM 1
14 LED 7
15 IN4148 DIODE 1
16 IN 4007 DIODE 3
16 12V RELAY 1
17 1000µF,16V ELECTROLYTIC CAPACITOR 2
18 470Ω RESISTOR 3
19 LED 7
20 PUSH BUTTON SWITCH 11
21 BAND SWITCH 1
22 10KΩ RESISTOR 5
23 4.7KΩ RESISTOR 4
24 10µF,100V ELECTROLYTIC CAPACITOR 1
25 22KΩ RESISTOR 2
26 100KΩ RESISTOR 9
27 3.58 MHZ CRYSTAL OSCILLATOR 1
28 0.1µF CERAMIC CAPACITOR 4
29 330KΩ RESISTOR 1
S.NO. LIST OF COMPONENTS QUANTITY
30 1KΩ RESISTOR 8
31 27µF CERAMIC CAPACITOR 2
32 .01µF POLYSTER CAPACITOR 3
33 10µF,50V ELECTROLYTIC CAPACITOR 1
34 0.01µF CERAMIC CAPACITOR 1
35 100Ω RESISTOR 1
36 270Ω RESISTOR 1
37 33KΩ RESISTOR 1
38 BC558 PNP TRANSISTOR 2
39 220KΩ RESISTOR 1
40 22µF CERAMIC CAPACITOR 1
41 BC 548 NPN TRANSISTOR 5
42 11.0592MHZ CRYSTAL OSCILLATOR 1
 CHAPTER 11
RESULTS AND CONCLUSION

The complete system (including all the hardware components and software routines) is working
as per the initial specifications and requirements of our project. Because of the creative nature of the
design, and due to lack of time some features could not be fine-tuned and are not working properly. So
certain aspects of the system can be modified as operational experience is gained with it.

 Initially the landline section in the circuit got hanged after 3 rings & the circuit to automatic
switch on the landline section does not work properly as the electromagnetic relay connected
earlier consumes more current when circuit is powered on therefore, a remedy to this problem
is that we have used reed relay which has low switch & voltage ratings, capable of faster
switching speeds and mainly used for temporarily storing information in telephone exchanges.

 Also, the voice processor section having APR9600 chip got hanged due to reverse current flow in
that section. To avoid this we have connected an op-amp 714 to compensate for the same.

As the users work with the system, they develop various new ideas for the
development and enhancement of the circuit.
 CHAPTER 12
APPLICATIONS

 The practical relevance of this project is that it can be used in TV reality shows where viewers
can vote to any participant of their choice.

 Further this project can be used practically in various types of selection & voting schemes to be
held in schools and colleges for the selection for different posts such as union president or
others.

CHAPTER 13
FUTURE SCOPE
 Number of candidates could be increased by using other microcontroller or an 8255 IC.

 It could be interfaced with printer to get the hard copy of the result almost instantly from the
machine itself.

 It could also be interfaced with the personal computer and result could be stored in the central
server and its backup could be taken on the other backend servers.

 On adding security and verification features it can be used for central elections and replace the
existing machines.

 On adding the feature of negative voting we can give people one more choice of reducing the votes
of misappropriate candidate.