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Abstract—In this paper, the performance assessment of three kinds of undesirable perturbations are common in industry line
software single-phase phase-locked loop (PLL) algorithms is car- voltages. These disturbances and their effects on industrial pow-
ried out by means of dynamic analysis and experimental results. er equipment are currently subjects of research [12]–[15].
Several line disturbances such as phase-angle jump, voltage sag,
frequency step, and harmonics are generated by a DSP together The picture sketched above shows that the development of
with a D/A converter and applied to each PLL. The actual minus robust synchronizing algorithms is needed in order to meet the
the estimated phase-angle values are displayed, providing a refined growing performance requirements of modern UPSs and other
method for performance evaluation and comparison. Guidelines grid-connected equipment. The figures of merit of a PLL are the
for parameters adjustments are also presented. In addition, prac- steady state phase-angle error, speed of response to phase, fre-
tical implementation issues such as computational delay effects,
ride-through, and computational load are addressed. The devel- quency and voltage amplitude disturbances, harmonic rejection
oped models proved to accurately represent the PLLs under real and line unbalance rejection in case of three-phase systems.
test conditions. In recent years, several PLL algorithms with different char-
Index Terms—Mathematical modeling, phase-locked loops acteristics have been developed and presented in the literature
(PLLs), uninterruptible power systems (UPSs). [1]–[11]. However, it is often difficult to recognize their exact
behavior and to compare their performances because the results
are not presented in a quite satisfactory way, i.e., usually in
I. I NTRODUCTION
the form of sawtooth or sine waves that represent the real and
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2924 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008
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SANTOS FILHO et al.: COMPARISON OF THREE SINGLE-PHASE PLL ALGORITHMS FOR UPS APPLICATIONS 2925
2
φ̂(s) ∼ skp + ki
d vd − sinτd θ̂ − sin θ̂τdcos θ̂ vd
sin θ̂
τd = kv 3 2
(17)
= + cos θ̂ vα . φ(s) 2τ s + s + skv kp + kv ki
dt vq vq
2
− sin θ̂τqcos θ̂ − cosτq θ̂ τq
(10) where kv is the static PD gain = V .
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2926 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008
V V Â
ed = sin(θ̂ − θ) + sin(θ + θ̂) − sin 2θ̂. (21)
2 2 2
V
ed ∼
= (φ̂ − φ). (22)
Fig. 5. Single-phase EPLL. 2
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SANTOS FILHO et al.: COMPARISON OF THREE SINGLE-PHASE PLL ALGORITHMS FOR UPS APPLICATIONS 2927
estimated phase-angle θ̂ were subtracted to allow comparison, Fig. 8. Switch is needed to assure correct free-running in abnormal line
performance evaluation, and model validation based on the conditions.
phase-angle error. The host PC was used to select and to issue
preprogrammed line disturbances. Moreover, the PC was also
with the help of Lissajous (XY) scope plots. This error could
used to select the output signal to come from one of the D/A
converter channels, while the other channel was kept dedicated be compensated by adding the value 2π/N to θ̂ before feeding
to the emulated line signal. it back, as shown in Fig. 7. This correction term would need
A sampling frequency of 30 720 Hz was used. This ap- to vary according to the input frequency. Nevertheless, it yields
parently high value is a consequence of the bandwidth re- satisfactory correction for a range in input frequency variation
quirements of the UPS output voltage control loop rather than of ±15%.
the PLL bandwidth requirements. The system A/D conversion Another important and essential PLL feature for UPS ap-
time and D/A update time are negligible when compared plications is the ride-through capability, i.e., the PLL output
to sample time. The discretization process has minor effects signal must remain running in the case of unacceptable line
in the above modeling provided that sampling frequency is conditions or even in the case of line outage, because this
more than ten times the PLL bandwidth. Nevertheless, the signal is usually the reference for the UPS inverter control
implementation of low cutoff frequency filters at high sam- section. The usual implementation of PLL algorithms found
pling rates leads to numeric representation problems, even in the literature does not inherently provide the ride-through
when using 32-b word length. The fourth-order Butterworth feature since the PI controller will try to follow the reference
filter for the pPLL has been implemented with the help of even when the line voltage is in an undefined, abnormal con-
the Texas Instruments 32-b filter library, which performs the dition, or when it is out of PLL lock range. A line quality
filtering through cascaded second-order sections, reducing nu- algorithm that continuously inspects the line voltage shall turn
meric problems. In addition, it is written in assembly language a switch in abnormal line situations, so that the PLL output
optimized to take full advantage of DSP architecture. The Q20 remains on its nominal condition, as depicted in Fig. 8. This
fixed point base was employed for overall calculations, while algorithm must have adequate hysteresis margins and timings
the Q30 base was used for filter calculations. The trapezoidal in order to avoid unstable behavior near established quality
method was used to implement the integrations because it thresholds. In this paper, the adopted quality criterion was the
yields exact phase equivalence when discretizing continuous range (−20%, +15%) for the input rms line voltage. Further
systems. discussion of line quality criteria is beyond the scope of this
A computational delay of one sampling time occurs in the paper.
control loop. This delay has negligible effect on stability, since
the closed-loop poles are at low frequency, very far from B. Experimental Results for the pPLL
Nyquist frequency. However, a steady state error of 2π/N
radians in estimated angle (where N is the number of samples Figs. 9 and 10 show the phase-angle error θ − θ̂ and esti-
per fundamental period) occurs due to this one sample time mated frequency ω̂ responses to a 40◦ phase-angle jump and
delay. In the performed experiments N was equal to 512 at to a frequency step of +5 Hz in input voltage, respectively. It
the nominal frequency of 60 Hz, resulting in 0.7◦ steady state can be seen the good agreement between predicted and actual
error. Such quite small error value could only be confirmed results. The oscillations in the variables are not predicted by the
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2928 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008
Fig. 9. pPLL response to a phase-angle jump of 40◦ . Top: phase-angle error. Bottom: estimated frequency.
Fig. 10. pPLL response to a frequency step from 60 to 65 Hz. Top: phase-angle error. Bottom: estimated frequency.
Fig. 11. pPLL response to 15% third harmonic injection in input voltage. Top: Fig. 12. pPLL response to a voltage sag of 30% in input voltage. Top: phase-
phase-angle error. Bottom: input signal to the PLL (0.3 per unit/div). angle error. Bottom: input signal to the PLL (0.3 per unit/div).
model since it is an approximation that describes the relation Fig. 11 shows the response to 15% third harmonic injection.
between estimated angle and input phase difference. The pPLL As shown, the pPLL is almost insensitive to harmonics. Fig. 12
locks to the new condition with zero steady-state error within shows the voltage sag test response, where it can be seen the
about seven cycles (120 ms) in both tests. pPLL low sensitivity to input signal amplitude variations.
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SANTOS FILHO et al.: COMPARISON OF THREE SINGLE-PHASE PLL ALGORITHMS FOR UPS APPLICATIONS 2929
Fig. 13. parkPLL response to a phase-angle jump of 40◦ . Top: phase-angle error. Bottom: estimated frequency.
Fig. 14. parkPLL response to a frequency step from 60 to 65 Hz. Top: phase-angle error. Bottom: estimated frequency.
Fig. 15. parkPLL response to 15% third harmonic injection in input voltage. Fig. 16. parkPLL response to a voltage sag of 30% in input voltage.
Top: phase-angle error. Bottom: input signal to the PLL (0.3 per unit/div). Top: phase-angle error. Bottom: input signal to the PLL (0.3 per unit/div).
C. Experimental Results for the parkPLL tests. It can be seen the good agreement of predicted and actual
results.
Fig. 13 shows the parkPLL response to a 40◦ phase-angle In Fig. 14, the parkPLL locks to the new frequency quickly
jump. The settling time is about three cycles (50 ms) in both with zero steady-state error after a frequency step of +5 Hz
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2930 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008
Fig. 17. EPLL response to a phase-angle jump of 40◦ . Top: phase-angle error. Bottom: estimated frequency.
Fig. 18. EPLL response to a frequency step from 60 to 65 Hz. Top: phase-angle error. Bottom: estimated frequency.
Fig. 19. EPLL response to 15% third harmonic injection in input voltage. Fig. 20. EPLL response to a voltage sag of 30% in input voltage. Top: phase-
Top: phase-angle error. Bottom: input signal to the PLL (0.3 per unit/div). angle error. Bottom: input signal to the PLL (0.3 per unit/div).
in input voltage. Fig. 15 shows the response to 15% third D. Experimental Results for the EPLL
harmonic injection, where an oscillation of about 3◦ peak-to-
peak in steady state is noticeable. Fig. 16 shows the response to Fig. 17 shows the response to a 40◦ phase-angle jump in
30% voltage sag. The phase-angle error is still small, although input voltage. The settling time is about three cycles (40 ms)
it is higher than the pPLL error to the same test. for both tests. Fig. 18 shows the response to a frequency
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SANTOS FILHO et al.: COMPARISON OF THREE SINGLE-PHASE PLL ALGORITHMS FOR UPS APPLICATIONS 2931
R EFERENCES
[1] L. G. B. Rolim et al., “Analysis and software implementation of a robust
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[2] V. Kaura and V. Blasko, “Operation of a phase locked loop system under
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[3] S. A. O. Silva et al., “A three-phase line-interactive UPS system im-
plementation with series-parallel active power-line conditioning capabili-
step of +5 Hz. The PLL locks to the new frequency quickly ties,” in Conf. Rec. IEEE IAS Annu. Meeting, 2001, pp. 2389–2396.
with zero steady state error. The third harmonic injection led [4] M. Aredes et al., “Control strategies for series and shunt active filters,” in
Proc. IEEE Power Tech Conf., 2003, pp. 1–6.
to about 5◦ peak-to-peak error in steady state, as shown in [5] S. M. Silva et al., “Performance evaluation of PLL algorithms for single
Fig. 19. The response to 30% voltage sag is shown in Fig. 20. phase grid-connected systems,” in Conf. Rec. IEEE IAS Annu. Meeting,
This result has been confirmed by floating point simulation in 2004, pp. 2259–2263.
[6] L. N. Arruda et al., “PLL structures for utility connected systems,” in
MATLAB. Conf. Rec. IEEE IAS Annu. Meeting, 2001, pp. 2655–2660.
[7] S. M. Deckmann, F. P. Marafão, and M. S. de Pádua, “Single and three-
phase digital PLL structures based on instantaneous power theory,” in
E. Results Summary Proc. 7th COBEP, Fortaleza, Brazil, Sep. 2003. CD ROM.
[8] M. Karimi-Ghartemani and M. R. Iravani, “A method for synchroniza-
Table I presents a summary of the main time response tion of power electronic converters in polluted and variable-frequency
parameters and other characteristics found in the experimental environments,” IEEE Trans. Power Syst., vol. 19, no. 3, pp. 1263–1270,
results for the PLLs. Aug. 2004.
[9] M. Karimi-Ghartemani and M. R. Iravani, “A new phase-locked loop
(PLL) system,” in Proc. IEEE MWSCAS, 2001, pp. 421–424.
[10] A. V. Timbus, R. Teodorescu, F. Blaabjerg, and M. Liserre, “Synchroniza-
IV. C ONCLUDING R EMARKS tion methods for three phase distributed power generation systems. An
overview and evaluation,” in Proc. IEEE PESC, 2005, pp. 2474–2481.
Three simple different single-phase PLL structures have been [11] B. Han and B. Bae, “Novel phase-locked loop using adaptive linear com-
analyzed and their experimental results have been objectively biner,” IEEE Trans. Power Del., vol. 21, no. 1, pp. 513–514, Jan. 2006.
presented by true phase-angle error data. Schemes for avoiding [12] K. Pietilainen, L. Harnefors, A. Petersson, and H.-P. Nee, “DC-link stabi-
lization and voltage sag ride-through of inverter drives,” IEEE Trans. Ind.
unpredictable PLL behavior under abnormal line conditions and Electron., vol. 53, no. 4, pp. 1261–1268, Jun. 2006.
also to compensate for computational delay effect on steady [13] D. M. Vilathgamuwa, P. C. Loh, and Y. Li, “Protection of microgrids
state phase-angle error have been proposed. during utility voltage sags,” IEEE Trans. Ind. Electron., vol. 53, no. 5,
pp. 1427–1436, Oct. 2006.
The developed models led to results with good agreement [14] J. M. Guerrero, L. G. Vicuna, and J. Uceda, “Uninterruptible power supply
with experimental data. The modeling error for the parkPLL systems provide protection,” IEEE Ind. Electron. Mag., vol. 1, no. 1,
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[15] M. H. J. Bollen, Understanding Power Quality Problems: Voltage Sags
could only predict the averaged evolution of the estimated and Interruptions. Piscataway, NJ: IEEE Press, 2000.
frequencies of the parkPLL and EPLL. The difference between
predicted and actual phase-angle error also decreases when
closed-loop bandwidths of these PLLs are reduced.
The dynamic analysis showed that the EPLL has the fastest
PD, but its output signal highly oscillates at second harmonic
during transient conditions, therefore some filtering may be
required at this frequency depending on the application. The
parkPLL PD has an inherent filtering, but its output also oscil- Rubens M. Santos Filho was born in Belo
Horizonte, Brazil, in 1972. He received the M.S.
lates at second harmonic during transient conditions. The speed degree in electrical engineering from the Universi-
of response of these two PLLs to input angle disturbances can dade Federal de Minas Gerais, Belo Horizonte, in
be increased at the cost of lower harmonic rejection. On the 1998, where he is currently working toward the Ph.D.
degree.
other hand, the pPLL bandwidth can be extended at the cost of Since 1997, he has been with the Centro Federal
higher filter order. It is worth to notice that the static PD gain in de Educação Tecnológica de Minas Gerais, Belo
all three structures depends on input signal amplitude V . Horizonte, where he is an Assistant Professor. His
research interests include control of switching power
The proposed method for designing the pPLL filter allowed converters, digital signal processing, uninterruptible
the extension of its bandwidth when compared to usual low- power systems, and power electronics.
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2932 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008
Paulo F. Seixas was born in Belo Horizonte, Brazil, Leonardo A. B. Torres was born in Belo Horizonte,
in 1957. He received the B.S. and M.S. degrees in Brazil, in 1975. He received the B.Sc. and Ph.D. de-
electrical engineering from the Universidade Federal grees in electrical engineering from the Universidade
de Minas Gerais, Belo Horizonte, in 1980 and 1983, Federal de Minas Gerais (UFMG), Belo Horizonte,
respectively, and the Ph.D. degree from the Insti- in 1997 and 2001, respectively. His thesis was on
tute National Polytechnique de Toulouse, Toulouse, control and synchronization of chaotic oscillators.
France, in 1988. Since 2002, he has been with the Departamento
Since 1980, he has been with the Departamento de Engenharia Eletrônica, UFMG, as an Associate
de Engenharia Eletrônica, Universidade Federal de Professor, where he is currently conducting research
Minas Gerais, where he is an Associate Professor of on autonomous vehicles development, nonlinear sys-
electrical engineering. His research interests include tems analysis and control, and dynamical systems
electrical machines and drives, power electronics, and digital signal processing. synchronization.
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