P R O D U C T   D ATA S H E E T

L-EDIT for PHYSICAL Design

Product Benefits
• Support today’s demanding IC
designs with physical design
tools that maximize efficiency.
• Speed up design cycles with
built-in productivity tools.
• Control every aspect of the
editing process.
• Work on laptops for anytime,
anywhere use and access.
• Save time with a solution which is
easy to set up, manage and use.
• Reduce CAD managers’
support burden for your
physical design tools.
• Integrate with third-party tools
and legacy data through support
for industry standard formats.
• Benefit from flexible
licensing options.
Speeding Concept to Silicon
Product Features
• Complete hierarchical physical
layout including all-angle and In today’s analog design world, speed is using foundry-provided files directly,
curved polygons. more important than ever. To compete allowing you to avoid having to set up
• Fast rendering. in a high-efficiency, high-productivity technology information manually. Once
• Import Cadence® Virtuoso®
marketplace, you need a toolset that you’ve begun using L-Edit, the CAD
technology and display files. has proven its ability to accelerate support burden for your physical design
the design cycles of commercially tools will be reduced, enabling you to
• Object snapping (gravity).
successful projects. focus on other mission critical tasks.
• Interactive (real-time) DRC.
• Schematic Driven Layout (SDL) Tanner EDA’s L-Edit™ meets your needs Create layout with precision
that uses netlist files in T-Spice™, by combining the fastest rendering
HSPICE®, PSpice®, structural available with powerful features L-Edit gives you greater precision
Verilog, or CDL formats. that exceed the needs of the most by enabling you to perform complex
• Easy to configure layout demanding user. This leading analog/ Boolean and derived layer operations
generators for the most mixed signal IC design tool for the PC with polygons of arbitrary shape and
common devices. platform enables you to get started curvature. Perform AND, OR, XOR,
• Automatically create with minimal training. You can draw Subtract, Grow, and Shrink on groups
parameterized cells from layout. and edit quickly, with fewer keystrokes of objects. You can display coordinate
• Node highlighting. and mouse clicks than other layout and distance values in any technology
tools. Using powerful features such unit, and automatically add guard rings
• LVS comparison.
as interactive DRC, object snapping, around any shape. Further increase your
• Standard cell place and route (SPR). productivity by mapping multiple layout
and alignment, you can work more
• Powerful UPI lets you create efficiently to save time and money. functions to a single keystroke.
macros to automate common tasks.
• Multiple language support L-Edit increases your productivity by • Perform complete hierarchical
including English, Japanese, enabling you to import Cadence® physical layout with all-angle and
Simplified and Traditional Virtuoso® technology and display curved polygons on an unlimited
Chinese, German, Italian, files for quick setup. Save time by number of layers.
and Russian

“Tanner Tools provide a complete,
easy-to-use, solution for ASIC and
MEMS designers at a reasonable
price. The Windows-based system
enables interactive web-based
design reviews that are trivial to
set up. The GUI enables any EE to
use it without formal instruction,
and the design kit allows for rapid
realization of mixed-signal ASICs.
This first time user was able to pick
up the tool, design a mixed-signal
circuit of about 4000 transistors,
and tape it out in five months.
Since the chip worked exactly as
simulated—and desired—on the
first try, I obviously think very
highly of Tanner and its tools.”
—Mark Zdeblick, Ph.D.
Chief Technology Officer simple toolkit for creating T-Cell code.
Proteus Biomedical
• Use orthogonal, 45°, all-angle, and • Easily replace instances of one cell
curved drawing modes. with another cell, at the current level
or throughout the design.
• View your design with the fastest
rendering on the market. • Maximize IP reuse or partition your
design for multiple designers with
• Use a command line interface for L-Edit’s multiple library support
run-time automation. (XrefCells).
L-Edit schematic driven layout (SDL)
Gain complete control over editing
provides capabilities that enable you to:
L-Edit gives you the flexibility and
• Read in a netlist and automatically
control you need to master the editing
generate parameterized cells and
process. You can dramatically streamline
instance them into your design.
the process by editing the properties of
• Display flylines allowing you to multiple objects simultaneously. With
place your blocks to minimize L-Edit you can instantly push down the
routing congestion. hierarchy to any object, making it easy
to edit edges, corners, and arcs. You
• Mark existing geometry as part of a can quickly stretch or shrink multiple
specific net allowing selection and edges to make room for more layout.
rip-up of geometry by net.
• Change the current drawing layer
• Perform engineering change orders directly from the layout using the
(ECO) and highlight differences in virtual layer palette.
the netlists.
• Perform unlimited undo and
• Use netlist files in T-Spice™, redo operations.
HSPICE®, PSpice®, structural
Verilog, or CDL formats. • Perform all-angle rotate, flip, merge,
nibble, and slice operations.
L-Edit also supports parameterized cells
called T-Cells™. With T-Cells, you can • Speed drawing and editing by
create versatile source cells that consist snapping the cursor to object
of user-defined input parameters and vertices, edges, midpoints, center
layout-generating code. T-Cells extend points, and instances.
traditional geometry cells to include
• Perform one-click horizontal or vertical
the flexibility and automation of L-Edit’s
object alignment, equally space objects,
user-programmable interface (UPI).
or tile objects horizontally, vertically,
or in a 2D array.
L-Comp™, a set of high-level
composition functions, provides a
• Specify a reference point for editing
operations such as object rotation,
Use L-Comp to efficiently create, place,
flip, move, or instance placement
and align cell instances in a design.
using the base point feature.
Navigate efficiently
Work in a versatile environment
L-Edit provides a built-in Design
Save time and money with L-Edit’s
Navigator that enables you to:
ease-of-use benefits:
• Efficiently traverse design hierarchy
• Delivers powerful features from an
with top-down and bottom-up
affordable, customizable, easy-to-
hierarchical view, non-instanced cells
manage tool.
view, or view cells sorted by their
modified date. • Offers a short learning curve.
• Drag and drop cells into layout from • Enables you to import and export
library files, other design files, or the GDS, DXF, and CIF file formats.
current design database.
• Provides multi-language menus
• View layout details down to any level (English, Japanese, Simplified and
of the hierarchy. Traditional Chinese, German, Italian,
and Russian).
• Lock and unlock cells to protect the
design from any changes.
• Customize and filter the Layer Palette
to show only layers used in the file,
current cell, or cell and its hierarchy
allowing you to finish your layout faster.
• Enables you to easily cut and paste
layout into your documentation flow.
Generate layout for
parameterized devices
L-Edit’s DevGen feature provides layout
generators for most common devices.
It is easy to configure for any process
to help ensure DRC correct layout.
Devices include Capacitor Generator,
Inductor Generator, Resistor Generator,
and MOSFET Generator. For specialized
devices, use L-Edit’s automatic layout
to T-Cell generator to quickly complete
your T-Cell library.
Create UPI macros
L-Edit’s powerful user programmable
interface (UPI) allows you to create
macros that automate layout
manipulations, geometric synthesis,
batch verification, and advanced
analysis. You can further increase your
productivity by mapping multiple layout
functions to a single keystroke. UPI
macros are written in C/C++ language
and can be executed with L-Edit’s built-
in interpreter or compiled as a DLL.
Speed layout with standard
cell place and route
L-Edit standard cell place and route
(SPR) performs place and route,
padframe generation, and pad
routing. To minimize total area, a built-
in placement and routing optimizer
automatically reduces net length and the
number of vias. L-Edit SPR includes:
• Three-layer channel routing.
• Cell clustering options.
• Specification of critical nets.
• Global signal routing for clock nets.
• Back annotation with SDF.
• EDIF input.
Further streamline verification
with Interactive DRC
L-Edit Interactive DRC displays
violations in real time while you edit
your layout, helping you create
compact, error-free layouts the first
time. Interactive DRC simultaneously
checks for violations between objects
in the same cell and down through the
cell hierarchy.
Correct layout as you go
L-Edit Node Highlighting offers
node highlighting for connectivity
visualization so you can quickly find
and fix LVS problems.
• Point to an object in the layout,
regardless of hierarchy, and display
Additional
all the geometry connected to it
Productivity Features
based on a set of connectivity rules.
· Cross-section viewer.
• Highlight discrepancies between the
· Layout vs Layout comparison.
schematic netlist and the extracted
netlist in the layout. · Area calculator.
· PostScript mask export for
• View multiple nodes in different colors. high resolution transparency
MEMS masks.
• Track down shorts and opens.
· Pad I/O cross reference for easy
• Improve design productivity generation of bonding reports.
significantly during LVS. · High-resolution plotter support
with the same rendering scheme
Verify complex designs with DRC used in L-Edit, including legends,
rulers, and headers.
L-Edit DRC™ is a high performance, all-
· Populate wafers with maximum
angle, hierarchical design rule checker. number of die and label all dies
Setting up rules is configurable for any on a wafer with WaferTools.
technology, with a graphical interface · CurveTools add chamfers and
for easy setup. Hierarchical error output fillets quickly to your layout.
displays your errors at the level of the It adds fillets of equal width to
hierarchy where they occur, and the wires and processes multiple
edges as a single edge when
error navigator opens the cell and zooms
working with curved objects
automatically to the location of the error. that have been converted to
Your productivity improves via speedy all-angle objects.
runtimes and quick location of errors. · LayerFill easily adds dummy
fills to your layout to meet
L-Edit DRC features include:
density requirements of
deep submicron designs.
• Support for an unlimited number of
width, spacing, surround, enclose, · MaskBias performs easy mask
resizing on a layer by layer basis
extension, overlap, not exist, and
which is great for designs that
density rules. are 65nm or below.
• High performance all-angle Boolean
and Select layer generation.
• Flag offgrid vertices, self-intersecting
polygons, all-angle edges, and
polygons with more than a specific
number of vertices.
• Full chip and local region DRC.
• Import of Calibre® DRC results for
browsing in L-Edit.
• Seamless integration into the
layout environment using the
DRC Error Navigator.
• See the DRC status (pass/fail/needed)
of each cell.
Integrated Verification Error
Navigator allows you to:
• Navigate instantly down the independently for different device
hierarchy to locate errors.
• View errors grouped by rule or by cell.
• See rule distance and Physical Design Group Leader
actual violation distance.
• View errors in the top cell or in capacitors that exceed user-supplied
the cell where the error occurred.
• Mark or remove errors • Removal of user-specified device models
that have been fixed.
Extract SPICE netlists
L-Edit Extract™ generates a SPICE
netlist from L-Edit layout for LVS
comparison or for post-layout simulation
with T-Spice. It extracts active and
passive devices and user-definable
subcircuits, with support for orthogonal,
45°, all-angle, and curved layout. To aid
in verification against the schematic,
L-Edit enables you to zoom or click in
the layout to display a specific node or
element. For increased accuracy, you
can extract parasitic node capacitances,
including fringing effects.
You can extract the most common
device parameters, including:
• MOSFET width, length, matching formats or hierarchy to be
source/drain area, and perimeter.
• Areas of diodes, BJTs, model definitions, in capacitor (C) and
MESFETs, and JFETs.
• Capacitance and resistance.
• Subcircuit extraction for functional
blocks with user parameters.
Compare layout to schematic
L-Edit layout versus schematic (LVS)
accurately and efficiently compares two
SPICE netlists to determine whether they
contain equivalent circuit descriptions.
LVS can use topological information,
parametric values, and geometric values
to compare netlists according to your
specifications. The program quickly
traces element and node mismatches
back to their origins, pinpointing
irresolvable nodes and devices using
fragmented class reporting.
LVS offers a full range of pre-processing
options to optimize netlists for
comparison, including:
• Merging of parallel or series
devices, where options can be set
types and for specific device models.
• Elimination of shorted and
disconnected (open) devices.
• Elimination of parasitic resistors and
min/max thresholds.
so that the nodes spanned by their
terminals can be shorted or opened.
• Omission of user-selected device
parameters from the compared netlists.
• Checking for soft-connections.
• Supporting asymmetrical MOSFETs
with user-defined pin swapping.
• Matching device parameter values,
which are crucial for analog design.
• Specifying pre- and post-iteration
matches to speed the comparison
process.
LVS reads netlist files in T-Spice,
HSPICE, PSpice, or CDL formats, with
support for all device types and key
parameters. Input netlists do not need
compared. LVS supports length and
width parameters, with accompanying
resistor (R) device statements.
Zip through LVS with cross-probing
from SPICE and LVS results to layout
or schematic and with enhanced
navigation of SPICE files.
Benefit from flexible licensing
When you purchase a new design tool,
licensing options can greatly affect
your total cost of ownership. L-Edit is
available in node-locked and networked
configurations offering you the most
flexible licensing possible. With a single
solution, L-Edit will work whenever and
wherever meeting the design needs
of your main workgroup and remote
workers. If you offshore design projects,
L-Edit does not have geographic
restriction on its licenses, thus, lowering
your total cost of ownership.
“We like the usability performance
and extendibility of the Tanner
Tools. The industry perception is
that PC based tools are not suitable
for ‘real’ chip development.100
Million CSR Bluetooth chips later,
we disagree."
—Paul Egan
CSR plc
“Calient Optical uses Tanner
EDA exclusively for layout of all
its product designs. It provides
a good balance of performance
and ease of use, while continuing
improvements in its software
constantly add value to its line
of products. One critical aspect
of its capabilities is its ability to
handle large, complex projects,
as Calient Optical’s designs can
include more than 30 layers and
millions of objects.”
—John M. Chong
Director of Engineering
Calient Optical Components
Corporate Headquarters
825 South Myrtle Avenue
Monrovia, CA 91016-3424 USA
Tel: +1-626-471-9700
Toll Free: 877-325-2223
Fax: +1-626-471-9800
Email: sales@tanner.com
Web: www.tannereda.com
Tanner Research Japan K.K.
Burex Kojimachi 6F
3-5-2 Kojimachi, Chiyoda-ku,
Tokyo 102-0083
Japan
Tel: +81 (03) -3239-2840
Fax: +81 (03) -3239-2860
Email: sales.jp@tanner.com
Web: www.tanner.jp
Tanner Research Taiwan, Inc.
6F.-8, No. 8, Ziqiang S. Road
Jhubei City
Hsinchu County, 302, Taiwan
Tel:
Fax:
Email: sales.tw@tanner.com
Web: www.tanner.com.tw
© 2008 Tanner Research. All rights reserved.
All other company and/or product names are
the property of their respective owners.