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Design And Layout Of 2KB SRAM Memory For 180nm Technology

Industrial Training Report

Submitted By

Pramod M (05EC78)


October 2008

Department of Electronics and Communication Engineering

National Institute of Technology Karnataka

Design And Layout Of 2KB SRAM Memory
For 180nm Technology

Pramod M & Minkle Eldho Paul

June 2008

1 Department of Electronics and Communication,National Institute of Technol-

ogy Karnataka

This report details the training in the area of Mixed Signal Design at Sankalp
Semiconductor,Hubli. The training involved lectures on Mixed Signal Design
flow and basic circuit theory including operation on MOSFETs.This report
contains the implementation of SRAM memory in 180nm technology and
the issues involved in layout design.The memory is implemented using Ca-
dence tools namely Schematic-Composer,Virtuso,Assura.The access time for
memory is intended to be within 20ns.

We would like to thank Mr.Vivek G Pawar,CEO,Sankalp Semiconductor

Pvt. Ltd. for accommodating us for the training. We thank Dr. Sri-
pathi Acharya for his support and our special thanks to Prof. P Sub-
banna Bhat for guiding us through the project. We would like to ex-
tend our gratitude to Prabhat Agarwal, Venkatesh Puttur, Ajit.S, Damodar
Charate,Vidyasagar T for their support and guidance in layout design. We
thank Department of Electronics and Communication,BVBCET for provid-
ing us lab facility for working on the project.


1 Introduction 3

2 Mixed Signal Design flow 4

3 Project Definition 6

4 Memory Architecture 7

5 Design of Individual Modules 8

5.1 Bit Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Write Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Column Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Row Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 2KB SRAM Memory 23

7 Conclusion 24

Chapter 1


The Semiconductor industry tries to catchup with Moore’s law by scaling the
size of the devices. Reduction in the size of the device guarantees reduction
of its parasitic capacitances but,the parasitics of the metal interconnect be-
comes dominant and the leakage current of the device becomes significantly
large.A well designed layout of chip ensures better performance.

In a typical CMOS chip, nearly 90% of the chip area is occupuied by dig-
ital circuits whereas only around 10% is occupied by analog.As more and
more discrete components get intergrated into the chip, its important that
the interface between them is well defined. As an example consider a mo-
bile phone that can play FM and mp3 and record videos. This requies a
separate RF module for FM reception,an mp3 decoder, DSP processor for
video compression, a memory module to store the video, power management
unit to signal sleep and wake cycle and most importantly the RF module for
high frequncy telephone signal tranception. All these modules if integrated
on a PCB requires a lot of area and the mobile becomes clumsy and power
hungy. Integrating all the modules on a single chip saves power and hence
it becomes compact and reliable.This nessasiates a robust analog design
for the chip that can sense the analog world and process them digitally and
provide the results back to environment.

Chapter 2

Mixed Signal Design flow

In the design of a Analog MOS chip the following steps are involved [1].
1. System Specification: The system requirements are defined in this
stage by specifying quantities like power consumption, interface signals,
frequency of operation, input and output relationship,technology for
fabrication,supply voltage etc. are specified. Certain quantities may
be more specific to a particular design like for an op amp quantities
like slew rate,bandwidth etc.
2. Architecture: The complete architecture of the design is specified,
in this stage of top down design the specifications of the individual
modules in the whole system is defined.Multiple architectures undergo
a system simulation and the most optimal design is chosen.
3. Circuit Design: Circuits for each of the modules are designed and
simulated for different process corners to meet the specifications.These
corners are :
(a) Process Corner: During the fabrication of the chip, there will be
process variation across the wafer and across the chip. Due to
these variations devices may have different threshold voltages,this
affects the speed of the device.The circuit must satisfy the specifi-
cations even with these variations.So all the pmos are assumed to
be fast and the nmos to be slow and the simulation is done with
this assumption and for other permutations also.
(b) Temperature variations: The design has to be robust to tempera-
ture variations in the range of −40◦ C to 125◦ C.

(c) Power Supply variations: The circuit must be able to reject the
noise in the power supply and tolerate a variation ±10%.

4. Layout: The circuit is laid out for a given technology and a Design
Rule Check (DRC) and Layout vs Schematic (LVS) is performed. Once
the layout is extracted for parasitics,this netlist is simulated and con-
formed with the specifications(Back annotation).

5. Fabrication: The chip is fabricated and the prototype chip of the

design is obtained.

6. Characterization: The fabricated chip is ccharacterizedfor its perfor-

mance for all parameter variations.

7. Production and Testing: If the prototype meets the specifications

and if its feasible for mass production then multiple masks are manu-
factured and the chips are mass produced.At this stage the testing of
the chips is minimal as compared to the ccharacterization stage.

After each of the steps simulations are performed to ensure the specifica-
tions are not violated. If the design deviates from the specifications the cycle
restarts from the previous steps.

Chapter 3

Project Definition

The following are the specifications for 2KB SRAM memory to be designed
with 180nm technology.

1. Access time tA (time to access the data after providing valid address )

2. Average power consumption of the chip: 50mW

3. Capacitance of Bit lines : 1pF

4. Size of the memory: 2KBytes

5. Power supply : 1.8V ± 10%.

Chapter 4

Memory Architecture

Since there are 2KBytes of memory locations to be aaccessedthe number of

address lines are log2 211 = 11 ie. A0 to A10 . This is divide into 8 blocks of
128 × 16 bit cells each.The ddiagrammaticrepresentation [2] of the memory
is show in fig 4.This figure also includes the different modules required for
the memory which will be detailed in the next chapter.

Figure 4.1: Sample architecture of memory:Courtesy [2]

Chapter 5

Design of Individual Modules

The SRAM memory will include the following blocks which will be detailed
in the subsequent sections [3].
1. Bit Cell: This is the basic storage element in the memory.

2. Precharge Circuit: Ensure a reliable read operation.

3. Sense Amplifier: Amplifies the difference between the bit and bit lines
thereby reducing tread .

4. Write Circuit: Selectively discharges either bit or bit line for writing

5. Column Decoder: Selects one of the 16 columns of the bit cells ⇒ 4:16

6. Row Decoder: Selects one of the 128 rows of bit cells ⇒ 7:128 Decoder.

7. Column Mux: Bidirectional Mux as indicated by the column decoder.

5.1 Bit Cell

The sschematicof the bit cell is show in the figure 5.1 . It is the basic memory
storing element composed of two back to back inverter. Reducing the area of
the bit cell is crucial since the array of bit cells(128×128) occupies the major
portion of the chip area. The sizing of the transistors becomes important
which prevent a read operation from changing the state of the cell.

Figure 5.1: Schematic of the bit cell

The figure 5.1 shows the layout of the bit cell using 180nm technology.The
dimensions of the bit cell is 3.6µm × 4.55µm.The supply to the bit cell is by
M etal1 and runs horizontally whereas the ground lines uses M etal2 and runs
vertically.The extracted netlist contained around 208 parasitic capacitors.
The cell is designed ssymmetricallyso that the cells can be arrayed.
The simulation of the read and write operation is shown in figures 5.1
and 5.1 respectively.

5.2 Precharge
The precharge circuit is used to charge the bit and bit bar lines to the supply
voltage before a read or write operation. The load capacitance of the seen by
the precharge circuit is the large pparasiticcapacitance of the bit and bit bar

Figure 5.2: Layout of the bit cell

lines. This circuit uses a large pmos ttransistorof width 12µm and it is enable
by EN signal.The figure 5.2 shows the schematic.
The layout of the precharge ccircuitis shown in figure 5.2. The Metal 1
at the ccenterand at the extremes is connected to Vdd and the pmos source
is connected to the bit and bit bar lines.

5.3 Sense Amplifier

The sense amplifier is similar to the bit cell with some slight alterations to
the circuit. The pass transistor uses a pmos instead of a nmos and it is
controlled by the OE signal. The sense amplifier is enabled by a nmos at the
source of the inverter nmos pair as shown in the figure 5.3. The schematic

Figure 5.3: Simulation of Bit cell read operation

for the corresponding layout is shown in figure 5.3. As mentioned earlier

the size of the pmos is made large so as to increase the inverter tthreshold
After extracting the layout of the sense amplifier for segments of length 1µm
the total number of capacitors were 346 each within 0.1fF. The simulation
of the sense amplifier is shown in figure 5.3.The differential input at sense
amplifier was 20mV siting on a common mode voltage of 1.79V, when the
sense amplifier is enable this small difference eventually grows and the back
to back inverter pair latch on to stable state,ie. If the bit line has large value
compared to the bit then the Data will be latched to 1.8V and Data to 0V.

5.4 Write Circuit

This circuit selectively discharges either the bit or bit line depending on
the CE and W E signals.The schematic of the circuit is shown in figure
5.4.The corresponding layout is show in figure 5.4. The number of parasitic
capacitances for this layout is around 709 capacitors each not more than

Figure 5.4: Simulation of bit cell write operation

5.5 Column Decoder

This is similar to a 4:16 decoder with all the outputs Nanded with inverted
CE signal. This decoder produces a 1.8V at all its outputs when it is inactive
and when activated all outputs except the one indicated by the address is
grounded.This module uses two 3:8 decoders and a set of 16 nand gates as
shown if figure 5.5.The layout and the simulation of the extracted netlist is
shown in figure 5.5 and 5.5 respectively.

5.6 Row Decoder

This is a 7:128 decoder that selects one of the 128 columns as indicated by the
address line A0 to A6 and the CE signals.It consists of two sets of eight 3:8
decoders each and a set is enabled by another 3:8 decoder. The schematic of
the 3:8 decoder and the 7:128 decoder is shown in figure 5.6. The simulation
of the extracted netlist of the 7:128 decoder is shown if figure 5.6

Figure 5.5: Schematic of the precharge circuit

Figure 5.6: Layout of the precharge circuit

Figure 5.7: Schematic of Sense amplifier

Figure 5.8: Layout of Sense amplifier

Figure 5.9: Simulation of extracted netlist of Sense amplifier

Figure 5.10: Schematic of Write Circuit

Figure 5.11: Layout of Write circuit

Figure 5.12: Schematic of Column Decoder

Figure 5.13: Layout of Column Decoder

Figure 5.14: Simulation of extracted netlist of Column Decoder

Figure 5.15: Schematic of 3:8 deoderdecoderayout of 7:128 decoder

Figure 5.16: Simulation of extracted netlist of 7:128 decoder

Chapter 6

2KB SRAM Memory

The complete layout of the Memory is shown in figure 7. In this diagram

the individual blocks described above are shown in the memory layout. The
memory occupies 598µm × 745µm which is less than 1mm2 .The simulation
of the whole schematic takes around 3700 seconds(little more than an hour)
since the number of nets is around 38,000.

Chapter 7


In conclusion a 2KB SRAM was designed with 180nm technology to oper-

ate at 50MHz. Each of the individual modules in the memory was layed
laidnd extracted for parasitics and simulated to meet the specifications.The
extracted netlist of the modules had parasitic capacitances not more that

Figure 7.1: Layout of 2KB SRAM


[1] Ken Kundert ”Principles of Top-Down Mixed-Signal Design” Designers

Guide Consulting, Inc.

[2] CY7C1049CV33 512K × 8 Static RAM, Cypress Semiconductor Corpo-


[3] Sourabh Khire, Gopikrishna Srinivasan, and Narayanan Terizhandur


[4] http://www.cedcc.psu.edu/khanjan/vssram.htm