Dataflow Modelling: University of Perpetual Help System DALTA

University of Perpetual Help System DALTA
Alabang-Zapote Road, Las Piñas City
College of Engineering
55072 Tuesday 12:00-3:00PM 255-B
Section Day Time Room
CpE 424L-3: Advanced Logic Circuits Design Laboratory
Machine Problem No. 6

DATAFLOW MODELLING
February 28,2019 March 7, 2019

Date Performed Date Submitted
Bautista, Dan Marlo S.

BSCpE / 4th Year
Engr. Cyd Laurence B. Santos, CpE

Instructor
Alabang
-Zapote Road, Pamplona 3, Las Piñas City,
CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGNLABORATORY
Metro Manila 1740, PHILIPPINES
www.perpetualdalta.edu.ph • +63(02)
-06-39
871
Machine Problem 7
VERILOG HDL FOR COMBINATIONAL CIRCUITS
I. OBJECTIVES
1. To demonstrate the function of a combinational circuit.
2. To design a program of a combinational circuit using Verilog Hardware Description

Language.
3. To create a Verilog HDL program for combinational circuits.
II. EQUIPMENT / MATERIALS
1. Icarus Verilog Hardware Description Language
2. Computer System
3. cmd Application
Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 1
ENGR. JENNELYN PEREZ-CABALE

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III. DISCUSSION
The module is the basic building block for modelling hardware with the Verilog HDL.
The logic of a module can be described in any one (or a combination) of the following
modelling styles:
• Gate-level modelling using instantiations of predefined and user-defined

primitive gates.
• Dataflow modelling using continuous assignment statements with the keyword
assign.
• Behavioural modelling using procedural assignment statements with the keyword
always.
Gate-level (structural) modelling describes a circuit by specifying its gates and how
they are connected with each other. Dataflow modelling is used mostly for describing
the Boolean equations of combinational logic. Behavioural modelling that is used to
describe combinational and sequential circuits at a higher level of abstraction.
Combinational logic can be designed with truth tables, Boolean equations, and
schematics; Verilog has a construct corresponding to each of these classical” approaches
to design: user-defined primitives, continuous assignments, and primitives. There is one
other modelling style, called switch-level modelling.
It is sometimes used in the simulation of MOS transistor circuit models, but not in logic
synthesis.

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IV. ACTIVITY
1. Write the HDL gate level description of the given combinational circuit.
2. Write an HDL dataflow modelling of a four-bit comparator with a six-bit output Y

[5:0]. Bit 5 of Y is for “equals,” bit 4 for “not equal to,” bit 3 for “greater than,” bit 2
for “less than,” bit 1 for “greater than or equal,” and bit 0 for “less than or equal to.”
V. SOURCE CODE
Experiment7a
module experiment7a(X, F1, F2);
input [0:3]X;
output F1, F2;
// A=0, B=1, C=2, D=3
assign F1 = ((~X[1]&X[2])|(~X[3]))+(~((~X[1]&X[2])|(~X[3])));

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assign F2 = ((~X[1]&X[2])|(~X[3]));
endmodule
module experiment7a_tb;
reg [0:3]X;
wire F1, F2;
experiment7a E(X, F1, F2);
initial
begin
$dumpfile("experiment7a.vcd");
$dumpvars(0,E);
$display ("------------------------------------");
$display (" BAUTISTA, DAN MARLO S. ");
$display ("------------------------------------");
$display ("| INPUTS | OUTPUT |");
$display ("------------------------------------");

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$display ("| ABCD | F1 | F2 |");
$display ("------------------------------------");
$monitor ("| %b | %b | %b |", X, F1, F2);
X=4'b0000;
repeat(15)
#1 X=X+4'b0001;
//$finish;
end
endmodule
Experiment7b
module experiment7b (A,B,Y);
input [3:0] A,B;
output [5:0] Y;
assign Y[5]=(A==B);

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assign Y[4]=(A!=B);
assign Y[3]=(A>B);
assign Y[2]=(A<B);
assign Y[1]=(A>=B);
assign Y[0]=(A<=B);
endmodule
module tb_experiment7b;
reg [3:0]A,B;
wire[5:0]Y;
experiment7b N(A,B,Y);
initial
begin
$dumpfile ("experiment7b.vcd");
$dumpvars;
$display("|
===============================================================
==========|");

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$display ("| INPUT ||| OUTPUT |");
$display("|
===============================================================
==========|");
$display ("| A | B ||| Y6 | Y5 | Y4 | Y3 | Y2 | Y1 |");
$monitor ("| %b | %b ||| %b | %b | %b | %b | %b | %b

| ", A,B,Y[5],Y[4], Y[3],Y[2],Y[1],Y[0]);
#0 A=0; B=0;
#5 A=0; B=1;
#5 A=1; B=0;
#5 A=1; B=1;
#40
$finish;
end
endmodule

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VI. PRINTED OUTPUT

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VII.
OBSERVATION
Combinational logic circuits in Verilog can be done using gate-level model. The format is
the same as the activity 5 where the Boolean expression of the circuit is used as the input
for the output. For the second exercise, dataflow model is used to get for the output of the
given combinational circuit. The different outputs are defined using different conditions
like equal, not equal, less than or equal, greater than or equal, less than, and greater than.
The output for dataflow is displayed as the binary of TRUE or FALSE.
VIII. CONCLUSION
Getting the output of a combinational logic circuit can be done in multiple ways, two of
which is using gate-level model and dataflow model. In conclusion, the three objectives
in this activity were met as the Verilog hardware descriptive language is capable of doing
combinational circuit analysis with multiple outputs.

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CpE 424L-3 – ADVANCED LOGIC CIRCUIT & DESIGN

LABORATORY
Name of Student : ______________________________________________

Student Number : ______________________________________________
Case No./ Title : ______________________________________________
Year and Section : ______________________________________________
RUBRICS FOR LABORATORY REPORT

Highly Below Not
Exceptional Satisfactory
Criteria Satisfactory Satisfactory Satisfactory Score
(5) (4) (3) (2) (1)
Follows the Follows the Follows the Does not Does not
given format given format given format follow the follow the
TITLE PAGE
and is written and is written but the given format given format
correctly and correctly information is but the and the
(X2)
neatly incorrect information is information is
correct incorrect
All machine All machine 75% of the 50% of the 25% of the
problems have problems have machine machine machine
been answered been answered problems have problems have problems have
completely. The completely. The been answered been answered been answered
HANDS-ON code is running code is running properly. The properly. The properly. The
ACTIVITY / executing / executing code is code is code is
(CO1 & CO2) efficiently. correctly. running / running / running /
Proper coding Proper coding executing executing executing
(X8) techniques techniques correctly. correctly. correctly.
were applied were applied Proper coding There is no There is no
with but techniques proper coding proper coding
were techniques techniques
Date of Revision: Date of Effectivity: Endorsed by: Noted by: Approved by:
January 2017 June 2017 Shiella Marie Garcia Joel R. Palacol CQI Lorena C. Ilagan
Department Chair Officer College Dean
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minimal with long applied but applied, with applied, with

number of lines number of lines with long long number of long number of
and with and no number of lines lines and no lines and no
aesthetic aesthetic and no aesthetic aesthetic
presentation presentation aesthetic presentation presentation
presentation
All required All required 75% of the 50% of the 25% of the
SOURCE source code source code required source required source required source
CODE is printed, is printed and code code code
(CO1 & CO2) readable, well readable is printed and is printed is printed
presented, and readable
(X2) neat.
All required All required 75% of the 50% of the 25% of the
output is output is required output required output required output
PRINTED printed, printed, is printed and is printed is printed
OUTPUT readable, well readable and readable
(CO1 & CO2) presented, neat well presented
and with
pleasing
(X2)
designs.
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The student The student The student The student The student
was able to was able to was able to was not able to was not able to
identify and identify and identify the discuss clearly discuss the
explain the explain the keywords and the keywords, developed
keywords, keywords, and statements used and statements program.
statements and statements used
OBSERVATIO in the used in the
values used in in the
N the developme developme nt of developme nt of developme nt
(CO2) nt of the codes. the codes. Very the program the program.
Very clear, but with
clear, complete and insufficient
(X2)
complete straight to the support
and with point.
sufficient
support.
The student The student The student The student The student
was able to was able to was able to was able to was not able to
attain all the attain all the attain 75% of attain 50% of attain any
objectives. objectives. the objective the objectives objectives.
CONCLUSION Discussed Very clear and
(CO3) and is written and is not Conclusions
with clarity, complete.
well. written well. were not
complete, is
(X2) written well.
written well
and with
sufficient
support.
The laboratory The laboratory The laboratory The laboratory The laboratory
report follows report follows report follows report does not report does not
APPEARANCE follow the
AND the given the given the given follow the
format, format, format but is given format given format.
PRESENTATI and
O N OF complete, complete and not organized Untidy and
is not
LABORATORY organized and organized. and with with incomplete
organized and
REPORT neatly incomplete contents.
have
presented. contents.
incomplete
(X2) contents.
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TOTAL
SCORE
Comment(s):
______________________________________________________________________________
______________________________________________________________________________
ENGR. JENNELYN P. CABALE

_______________________________________ ________________ Name of Faculty and Signature
Date

Dataflow Modelling: University of Perpetual Help System DALTA

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University of Perpetual Help System DALTA

Alabang-Zapote Road, Las Piñas City

55072 Tuesday 12:00-3:00PM 255-B

Section Day Time Room

CpE 424L-3: Advanced Logic Circuits Design Laboratory

Machine Problem No. 6

February 28,2019 March 7, 2019

Bautista, Dan Marlo S.

Engr. Cyd Laurence B. Santos, CpE

VERILOG HDL FOR COMBINATIONAL CIRCUITS

1. To demonstrate the function of a combinational circuit.

2. To design a program of a combinational circuit using Verilog Hardware Description

3. To create a Verilog HDL program for combinational circuits.

II. EQUIPMENT / MATERIALS

1. Icarus Verilog Hardware Description Language

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 1

ENGR. JENNELYN PEREZ-CABALE

• Gate-level modelling using instantiations of predefined and user-defined

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 2

ENGR. JENNELYN PEREZ-CABALE

2. Write an HDL dataflow modelling of a four-bit comparator with a six-bit output Y

module experiment7a(X, F1, F2);

output F1, F2;

// A=0, B=1, C=2, D=3

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 3

ENGR. JENNELYN PEREZ-CABALE

wire F1, F2;

experiment7a E(X, F1, F2);

$display (" BAUTISTA, DAN MARLO S. ");

$display ("| INPUTS | OUTPUT |");

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 4

ENGR. JENNELYN PEREZ-CABALE

$display ("| ABCD | F1 | F2 |");

$monitor ("| %b | %b | %b |", X, F1, F2);

module experiment7b (A,B,Y);

input [3:0] A,B;

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 5

ENGR. JENNELYN PEREZ-CABALE

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 6

ENGR. JENNELYN PEREZ-CABALE

$display ("| INPUT ||| OUTPUT |");

$display ("| A | B ||| Y6 | Y5 | Y4 | Y3 | Y2 | Y1 |");

$monitor ("| %b | %b ||| %b | %b | %b | %b | %b | %b

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 7

ENGR. JENNELYN PEREZ-CABALE

VI. PRINTED OUTPUT

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 8

ENGR. JENNELYN PEREZ-CABALE

Machine Problem 15: VERILOG HDL FOR COMBINATIONAL CIRCUITS 9

ENGR. JENNELYN PEREZ-CABALE

CpE 424L-3 – ADVANCED LOGIC CIRCUIT & DESIGN

Name of Student : ______________________________________________

RUBRICS FOR LABORATORY REPORT

minimal with long applied but applied, with applied, with

ENGR. JENNELYN P. CABALE

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