EE 577A Fall 2020

Akhilesh Jaiswal TA: Marzieh Vaeztourshizi

Lab 1 Part 1

Score: /100

Student ID: Name:

Assigned: Thursday August 27th

Due: Friday Sept 4th, at 11:59pm. No late submissions are allowed.

In Lab1 Part 1 you can discuss your ideas, algorithms, etc. with your colleagues. However, you
should submit your own implementation. You are NOT allowed to copy your code from others.
This means you should not discuss or present your actual code. You can refer to online
resources but be careful about citing them.

The objective of this assignment is to help you learn scripting, which is used in industry and
academia for various simulation and automation steps of design and verification. You will use
either Perl or Python for any EE577A scripting. Perl/Python scripting will be an important
part of your final project and future lab assignments and may also appear as part of your
exams.

1) (40 pts) Following is a paragraph [ISCA, 2018] introducing the concept of memory wall
bottleneck and in-memory computing. (Note: Mitigation of Memory Wall Bottleneck
through in-memory or processing in memory (PIM) computing techniques are currently an
area of intense research investigation within the VLSI community).

In the last two decades, the number of processor cores per chip has steadily increased while memory
latency has remained relatively constant. This has lead to the so-called memory wall [1] where
memory bandwidth and memory energy have come to dominate computation bandwidth and energy.
With the advent of data-intensive system, this problem is further exacerbated and as a result, today
a large fraction of energy is spent in moving data back-and-forth between memory and compute
units. At the same time, neural computing and other data intensive computing applications have
emerged as increasingly popular applications domains, exposing much higher levels of data
parallelism. In this paper, we exploit both these synergistic trends by opportunistically leveraging
the huge caches present in modern processors to perform massively parallel processing for neural
computing. Traditionally, researchers have attempted to address the memory wall by building a deep
memory hierarchy. Another solution is to move compute closer to memory, which is often referred
to as processing-in-memory (PIM). Past PIM [2]–[4] solutions tried to move computing logic near
DRAM by integrating DRAM with a logic die using 3D stacking [5]–[7]. This helps reduce latency
and increase bandwidth, however, the functionality and design of DRAM itself remains unchanged.
Also, this approach adds substantial cost to the overall system as each DRAM die needs to be
augmented with a separate logic die. Integrating computation on the DRAM die itself is difficult
since the DRAM process is not optimized for logic computation. In this paper, we instead completely

EE577A Lab 1 – Part I Fall 2020 1

eliminate the line that distinguishes memory from compute units. Similar to the human brain, which
does not separate these two functionalities distinctly, we perform computation directly on the bit
lines of the memory itself, keeping data in-place. This eliminates data movement and hence
significantly improves energy efficiency and performance. Furthermore, we take advantage of the
fact that over 70% of silicon in today’s processor dies simply stores and provides data retrieval;
harnessing this area by re-purposing it to perform computation can lead to massively parallel
processing.

a) Write a Python or Perl script (lab1p1_1.py or lab1p1_1.pl) that reads the above sample
paragraph through an input text file text_in.txt. The file may include special characters
and numbers.

Your script then writes every word in text_in.txt into an output file text_out1.txt
with the following requirement:

For each sentence, starting from the first sentence in text_in.txt, if the word ‘THE’ (case-
insensitive) occurs even number of times you should rewrite the words in the paragraph with
all the words staring with – ‘a,e,i,o,u’ in UPPER CASE. All other words should be in lower
case. If the word ‘THE’ does not occur in a sentence, then you should still rewrite the words
in the paragraph with all the words staring with – ‘a,e,i,o,u’ in UPPER CASE. All other words
should be in lower case.

If, however, the number of occurrences of the word ‘THE’ (case-insensitive) is odd then
sentence should be written as it is in the text_in.txt file.

Each sentence should start from a new line. Each sentence in text_out1.txt should end
by mentioning the number of occurrences of the word ‘THE’ in round parenthesis.

For example,

In the last two decades, the number of processor cores per chip has steadily increased while
memory latency has remained relatively constant. This has lead to the so-called memory wall
[1] where memory bandwidth and memory energy have come to dominate computation
bandwidth and energy.

The first sentence has even number of word ‘THE’ and second sentence has odd number of
occurrences for the word ‘THE’. Therefore, the output should look like:

IN the last two decades, the number OF processor cores per chip has steadily INCREASED
while memory latency has remained relatively constant (2).
This has lead to the so-called memory wall [1] where memory bandwidth and memory
energy have come to dominate computation bandwidth and energy (1).

Note, your code should function properly even if the contents in text_in.txt is
changed.

EE577A Lab 1 – Part I 2

Fall 2020
 2) (60 pts) Below are the equations for Subthreshold and Saturation Current for a long
channel MOSFET, ignoring the channel length modulation effect. In this part, we
would analyze the effect of process induced variations on the distribution of
Subthreshold and ON current of a MOSFET. (Note: The behavior of a circuit due to
process induced variations is a key aspect to be taken into consideration while
designing and optimizing a circuit.)

Subthreshold Current

Saturation Current

Assume VDD = 1.2V, VT = 0.48V, μecox, = 90μA/V2, I0 = 10e-6A, n = 1.5, W/L =1

Write a Perl/Python script (lab1p1_2.py or lab1p1_2.pl) to do the following:

1. Generate 1000 samples from a gaussian distribution with mean 480mV and standard
deviation of 5%.
2. For each generated sample VT (among the 1000 samples), calculate the corresponding
Subthreshold and ON Current.
3. Generate a file variation_analysis.txt containing 4 columns as shown below, fist
column contains the Sample Number, second column enumerates the value of V T, third
column represents the calculated Subthreshold Current and fourth column represents the ON
Current values.
4. The final row should contain the ratio of Imax/Imin of the values in columns 3 and 4.

Sample Number VT Value (mV) Subthreshold Current ON Current (uA)

(uA)
1 480 . .
2 . . .
. . . .
Imax/Imin - . .

Based on this exercise could you guess why process variations have more pronounced effect
on subthreshold behavior as compared to saturation (or ON) behavior of the transistor?
Answer this question in the pdf file (see Submission Guidelines).

EE577A Lab 1 – Part I 3

Fall 2020
 Submission Guidelines

Briefly explain your algorithms, ideas, comments in a pdf file. Name your pdf file
based on the following format:
“yourfirstname_yourlastname_studentID_Lab1_Part1.pdf”.
Provide a readme.txt including any facts you think the grader should know to run and
assess your work. This includes references: e.g.: in my Python code, lines 5-38, are
indirectly (or mention, if directly) inspired by the code (lines numbers ….) in www…….

Submit your lab1p1_1.py or lab1p1_1.pl and lab1p1_2.py or lab1p1_2.pl

scripts as well as your generated text_out1.txt, variation_analysis.txt
files.

Submit through D2L->Assignments->Lab1Part1 Submission. Multiple submissions are

allowed, and the latest submission will be graded.

EE577A Lab 1 – Part I 4

Fall 2020