Tutorial-6

1. Design an 8-Bit register circuit with the following specifications.—SHIFTER CIRCUIT

a. At positive edge of input line reset, the register loads the value 00000000.
b. If the reset is low, value in (i-1)th Bit of the register is loaded into the ith Bit of the
register for i=1 to i=7. The value in the input line Seq-In is loaded into the 0th Bit
of the register and value in the 7 th Bit of the register is sent as output from line
Seq-Out.
c. Step b is repeated at each edge of the clock.
Figure given below, illustrates the block diagram of the circuit.

reset

Seq-Out
7 6 5 4 3 2 1 0
Seq-In
8 Bit Register (Memory)

Clock

2. Design an 8-Bit register circuit with the following specifications.—LEFT and RIGHT
SHIFTER
a. At positive edge of input line reset, the register loads the value 00000000.
b. If the reset is low,
i. If input line Lt_Shift is high, the value in (i-1)th Bit of the register is loaded
into the ith Bit of the register for i=1 to i=7. The value in the input line Seq-
In is loaded into the 0th Bit of the register.
ii. If input line Rt_Shift is high, the value in ith Bit of the register is loaded
into the (i-1)th Bit of the register for i=7 to i=1. The value in the input line
Seq-In is loaded into the 7th Bit of the register.
iii. For all other cases, the value of the register is freezes.
c. Step b is repeated at each edge of the clock.
The output of the circuit is the values of the register.
Lt_shift Rt_shift

reset

Seq-In

7 6 5 4 3 2 1 0

8 Bit Register (Memory)

Clock
8 Bit output
Register Value
 3. Design an 8-Bit register circuit with the following specifications.—PARALLEL LOAD
and Left SHIFTER
a. If input line parallelload is high, the register loads the value from input bus
parallelinput.
b. If the parallelload is low,
The value in (i-1)th Bit of the register is loaded into the ith Bit of the register
for i=1 to i=7. The value in the input line Seq-In is loaded into the 0th Bit of
the register and value in the 7th Bit of the register is sent as output from
line Seq-Out.
c. Step a is repeated at each edge of the clock.

parallelload

7 6 5 4 3 2 1 0
Seq-In
8 Bit Register (Memory)

Clock
8 Bit input
parallelinput
Seq-Out