Information of the Toshiba 8X series CPU

Note –
- this information is individual information, (Inc.) all inquiry to Toshiba and
(Inc.) the Toyota Motor Corporation and the like is prohibited. In addition, it
does not owe all responsibility concerning the accident damage trouble
which derives from this information.

The Toshiba 8X series micro controller besides the fact that it was used, as
custom CPU of the Toyota car ECU has the instruction set which is similar to
6800 systems CPU as well.

1. Pin arrangement
The typical package is 64 pins wide DIP package. There are also those of 42 pin
DIP types in the series.

2. Operational mode
With the operational mode of 7 types, MODE7 and MODE2 can be selected with
the I/E pin of the chip. Movement to other modes during program operating does
by operating the OMODE register.

Mode MD2 MD1 MD0 ROM RAM Interruption Remark

 vector
Single chip
7 1 1 1 Inside Inside Inside
mode
As for access to
Port B register as
for external
treatment Port A
6 1 1 0 Inside Inside Inside only the Output
setting bit part of
DDRA address
output

5 1 0 1 Inside Inside Inside Ditto

Single chip static
4 1 0 0 Invalidity Inside Inside test mode

Port A, B
register
3 0 1 1 Outside Outside Outside
external
treatment

2 0 1 0 Outside Inside Outside 〃

1 0 0 1 Inside Inside Outside 〃

0 0 0 0 Inside Inside Inside 〃

3. Memory map
With built-in ROM 12KB and built-in RAM 384byte, short story low ル it is
possible on & off and external memory reference of ROM RAM with operational
mode to do. 0xffde-0xffff is the vector Mode 7 area, reset
vector 0xfffe (MSB), 0xffff (LSB) 0x0000 contents are set
by PC at the time of CPU reset and 0x0030
0x0040 I/O Area
execution is
started.
Unused
The internal
RAM
I/O area
0x01c0
mode 2

External Unused
memory
0x0000 Built-in 0xd000
0x0030
0x0040
RAM
0x0100
The
internal
ROM

0xffde
Vector
area
0xffff
 External
memory
vector
area

0xffff
0xffde

4. I/O register
Memory address 0x0000- 0x002f, the I/O register for peripheral interface is done
mapping. When CPU is operated with the external mode of MODE2 and the like,
because PORT A and PORT B in the one for external memory bus the allotment
and others れ る, it is use failure. When the same port at the time of external
mode is used, if PORT A/PORT B and the equivalent I/O circuit are increased
outside, it is possible to operate same as the time of single chip,

I/O register summary

Address Abbreviation Function
Port A Input/output direction
0x00 DDRA
appointment
Port B Input/output direction
0x01 DDRB
appointment
0x02 WDC Watchdog timer
0x03 TIMER3 Timer LSB (bit0-Bit2)
0x04 TIMER Timerー MSB(bit11～bit18)
0x05 TIMERL Timerー LSB(bit3～bit10)
0x06 SIDR(S ODR) Serial data
 0x07 SMRC/S IR Serial controller
0x08 CPR0 Timer comparison＃０ MSB
0x09 CPR0L Timer comparison＃０ LSB
0x0a CPR1 Timer comparison＃１ MSB
0x0b CPR1L Timer comparison＃１ LSB
0x0c CPR2 Timer comparison＃２ MSB

0x0d CPR2L
Timer comparison ＃２ LSB
0x0e CPR3 Timer comparison ＃３ MSB
0x0f CPR3L Timer comparison ＃３ LSB
0x10 ASR0P ASR0↑􀀀 Edge counter value MSB
0x11 ASR0PL ASR0↑􀀀 Edge counter value LSB
0x12 ASR0N ASR0↓􀀀 Edge counter value MSB
0x13 ASR0NL ASR0↓􀀀 Edge counter value LSB
0x14 ASR1P ASR1↑􀀀 Edge counter value MSB
0x15 ASR1PL ASR1↑􀀀 Edge counter value LSB
0x16 ASR1N ASR1↓􀀀 Edge counter value MSB
0x17 ASR1NL ASR1↓􀀀 Edge counter value LSB
0x18 ASR2 ASR2 Edge counter value MSB
0x19 ASR2L ASR2 Edge counter value LSB
0x1a ASR3 ASR3 Edge counter value MSB
0x1b ASR3L ASR3 Edge counter value LSB
0x1c - Unused

0x1d - Unused
0x27 DOM DOUT Control
0x1e - Unused
0x28 PORTC Port C data
Operation PODTD/
Port D data - ASR
0x29
0x1f OMODE mode ASRIN input data
appointment 0x2a RAMST Built-in RAM status
0x20 PORTA Port A data Serial status data
0x2b SSD
0x21 PORTAL Port A latch register
0x22 PORTB Port B data Interruption required
0x2c IRQL
0x23 PBCS
Port B flag MSB
control Interruption required
0x2d IRQLL
0x24 TAIT
Timer ASR flag LSB
control Interruption mask
0x25 LDOUT LDOUT 0x2e IMASK
MSB
0x26 DOUT DOUT data Interruption mask
0x2f IMASKL
LSB

5. Operator cord/code
It has the instruction set which is similar to 6800 series, but both operator
cord/code order it is not identical. Addressing mode almost is identical to 68
systems.

Contents of CCR
register.
7 6 5 4 3 2 1 0
- - H I N Z V C

CCR flag
Flag Explanation
H The half carry
from bit.3
I Interruption
mask
N Negative
Z Zero
V Overflow
C Carry

Register Explanation
name
A 8bit アキュームレータ
B 〃
Higher rank the 16bit
D
register which designates
A and subordinate
position as B
X 16bit Index register
Y 16bit Index register
SP 16bit Stack pointer
PC 16bit Program counter
CCR 8bit Condition register

命令 ニモニック 動作式
加算 ADD op.1 = op.1 + op.2
op.1 = op.1 + op.2 +
キャリア付加算 ADDC
C
減算 SUB op.1 = op.1 – op.2
op.1 = op.1 – op.2 –
キャリア付減算 SUBC
C
乗算 MUL Acc.D = Acc.A * op.2
Acc.A < op.2なら、
商 = Acc.B, 余 = Acc.A,
除算 DIV C = 0
Acc.A >= op.2なら
 無動作、C = 1
インクリメント INC op.1 = op.1 + 1

デクリメント DEC op.1 = op.1 – 1

クリア CLR op.1 = 0

２ の補数 NEG op.1 = ~op.1 + 1

右シフト SHR 0→ [op.1] →C

算術右シフト SHRA [op.1]→C

左シフト SHL C←[op.1]←0

右ローテート RORC C→[op.1]→C

左ローテート ROLC C←[op.1]←C

比較 CMP op.1 – op.2

論理積 AND op.1 = Op.1∧op.2

論理和 OR op.1 = op.1∨op.2

排他的論理和 XOR op.1 = op.1∀op.2

ビット比較 CMPB op.1∧op.2

ゼロと比較 CMPZ op.1 – 0

割込禁止 DI I = 0

V フラグのクリア CLRV V =0

キャリークリア CLRB C = 0

ビットクリア CLRB bit.X = 0

割込許可 EI I = 1
V フラグのセット SETV V = 1
キャリーセット SETC C = 1
ビットセット SETB bit.X = 1
ビットテスト分岐 TBBS bit.X = 1なら分岐
ビットテスト分岐 TBBC bit.X = 0なら分岐
ビットテスト＆ セット TBS bit.X = 1 なら、Bit.X =
1
BCD 変換 ADJ op.1 = BCD[op.1]
レジスタ転送 LD op.1 = op.2
レジスタ転送 ST op.2 = op.1
レジスタ転送 MOV op.2 = op.1

レジスタ交換 XCH op.1とop.2の値を交換

M[sp] = op.1. sp = –
レジスタ待避 PUSH
sp 1
sp = sp + 1, op.1 =
レジスタ復帰 PULL
M[sp]
M[sp] = PC, sp = sp +
呼び出し JSR
2
sp = sp + 2, PC =
サブルーチン復帰 RET
M[sp]

RETI 全レジスタ復帰後、サブルーチ
割込復帰 ン復帰

割込待ち WAIT 全レジスタ退避後、割込待ち

何もしない NOP
分岐 BRA 無条件分岐
分岐しない BRN 何もしない
等しければ分岐 BEQ Z = 1なら分岐

異なれば分岐 BNE Z = 0なら分岐

キャリー分岐 BCS C = 1なら分岐

キャリー分岐 BCC C = 0なら分岐

正かゼロなら分岐 BPZ N = 0なら分岐

負なら分岐 BMI N = 1なら分岐

オーバーフロー分岐 BVS V = 1なら分岐

オーバーフロー分岐 BVC V = 0なら分岐

BGTA Z + ( N∀V ) = 0 なら分

算術分岐
岐
算術分岐 BGEA N∀V = 0なら分岐

算術分岐 BLTA N∀V = 1なら分岐

BLEA Z + ( N∀V ) = 1 なら分

算術分岐
岐
大きければ分岐 BGT C + Z = 0なら分岐

少なければ分岐 BLE C + Z = 1なら分岐

無条件分岐 JMP 分岐