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.c BU1924 / BU1924F / BU1924FS

Audio ICs
t 4U
e
RDS h/ eRBDS decoder
a S
at / BU1924F / BU1924FS
BU1924
.D
w
w The BU1924, BU1924F and BU1924FS are RDS / RBDS decoders that employ a digital PLL and have a built-in

w anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power
consumption.

zApplications

o m
.c
RDS / RBDS compatible FM receivers for American and European markets, car stereos, high-fidelity stereo systems and
components, and FM pagers.

zFeatures

4 U
t
1) Low current.
2) Two-stage anti-aliasing filter (LPF).
3) 57kHz band-pass filter.
4) DSB demodulation (digital PLL).
5) Quality indication output for demodulated data.

e e
zAbsolute maximum ratings (Ta = 25°C)

S h
a
Parameter Symbol Limits Unit Conditions

t
Power supply voltage VDD −0.3~+7.0 V VDD1 VDD2
Maximum input voltage VMax. −0.3~VDD+0.3 V All input pins
Maximum output voltage

a
IMax. ±4.0
1000∗1(BU1924)
mA All output pins

.D
Power dissipation Pd 300∗2(BU1924F) mW −
500∗3(BU1924FS)
Operating temperature
Storage temperature
w Topr
Tstg
−40~+85
−55~+125
°C
°C
−
−

w
∗1 Reduced by 10.0mW for each increase in Ta of 1°C over 25°C.(BU1924)
∗2 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.(BU1924F)
∗3 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.(BU1924FS)

w
zRecommended operating conditions (Ta = 25°C)
m
Parameter Symbol Min. Typ. Max. Unit
o
Power supply voltage
VDD1 2.7 − 5.5 V
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VDD2 2.7 − 5.5 V

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et
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 BU1924 / BU1924F / BU1924FS
Audio ICs

zBlock diagram

560p

VSS3 CMP

MUX 100kΩ (7) (8)

(4)

270p
120kΩ 100kΩ
8th Switched
capacitor filter

comparator
anti-aliasing
Vref (3) filter

(16) RCLK
2.2µF

VDD1 (5)

∗1 Analog
Power supply QUAL
(1)

VSS1 (6)

PLL RDATA
PLL Bi-phase (2)
57kHZ Differential
∗1 VDD2 (12) RDS 1187.5Hz decoder decoder

∗2 Digital
Power supply
(11)
VSS2

Reference Measurement
clock circuit

(13) (14) (10) (9)

XI XO
T1 T2
4.332MHZ

∗1 : VDD1 and VDD2 are separated within the IC.

∗2 : Have VDD2 (digital power supply) of a sufficiently low impedance.
33pF 33pF
∗3 : Match the capacitor constants with the crystal manufacturer.
∗3 ∗3
(N.C.)
RCLK

VDD2

VSS2
XO

T1

T2
XI

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8
VDD1

VSS1

VSS3
RDATA

Vref

MUX
QUAL

CMP

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 BU1924 / BU1924F / BU1924FS
Audio ICs

zPin descriptions
Pin No. Symbol Pin name Functions Input/Output type
1 QUAL Demodulator quality Good data : High, bad data : Low Type C
2 RDATA Demodulator data Refer to output data timing Type C
3 Vref Reference voltage 1/2 VDD1 (refer to input/output circuits) Type E
4 MUX Input Composite signal input (refer to input/output circuits) Type F
5 VDD1
6 VSS1 Analog power supply 2.7V to 5.5V −
7 VSS3
8 CMP Comparator input C-junction (refer to input/output circuits ) Type D
9 T2
Test input Open or connected to ground Type B
10 T1
11 VSS2
Digital power supply 2.7V to 5.5V −
12 VDD2
13 XI Connects to 4.332MHz oscillator
Crystal oscillator Type A
14 XO (refer to input/output circuits)

15 (N.C.) − − −
16 RCLK Demodulator clock 1187.5Hz clock (refer to the timing diagram) Type C

zInput / Output circuits

Type A Type B Type C

10MΩ

Type D Type E Type F

VREF

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 BU1924 / BU1924F / BU1924FS
Audio ICs

zElectrical characteristics (unless otherwise noted, Ta = 25°C, VDD1 = VDD2 = 5.0V, VSS1 =VSS2 = VSS3 = 0.0V)
Parameter Symbol Min. Typ. Max. Unit Conditions
Operating current IDD − 6.5 10.0 mA IDD1+IDD2
Reference voltage Vref − 1/2VDD1 − V Pin 3
Input current 1 IIN1 − − 1.0 µA MUX VIN=VDD1
Output current 1 IOUT1 − − 1.0 µA MUX VIN=VSS1
Input current 2 IIN2 − 0.5 − µA XI XI=VDD2
Output current 2 IOUT2 − 0.5 − µA XI XI=VSS2
VDD2 VDD2
Output high level voltage 1 VOH1
−1.0 − V RCLK RDATA QUAL IO=−1.0mA
−0.3
Output low level voltage 1 VOL1 − 0.2 1.0 V RCLK RDATA QUAL IO=1.0mA
〈Filter block〉
Center frequency FC 56.5 57.0 57.5 kHz
Gain GA 20 23 26 dB F=57.0kHz
Attenuation 1 ATT1 18 22 − dB 57kHz±4kHz
Attenuation 2 ATT2 65 80 − dB 38kHz
Attenuation 3 ATT3 35 50 − dB 67kHz
S / N ratio SN − 35 − dB 57kHz VIN=3.0mVrms
〈Demodulator〉
RDS detector sensitivity SRDS − 0.5 1.0 mVrms
RDS input level VRDS 1.0 − 300 mVrms
Data rate DRATE − 1187.5 − Hz
Clock transient vs. data CT − 4.3 − µs
Not designed for radiation resistance.

zOutput data timing

RCLK

RDATA

T1 T5 T1 T3 T4 T2 T6 T2
T1=T2=4.3µS T3=T4=421µS T5=T6=416.7µS

The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced
in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the
rising or falling edge of the clock as the reference. The data is valid for 416.7µs. after the reference clock edge.

QUAL pin operation : Indicates the quality of the demodulated data.

(1) Good data : HI
(2) Poor data : LO

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 BU1924 / BU1924F / BU1924FS
Audio ICs

zElectrical characteristic curves

30

20

10
FILTER GAIN : G (dB)

−10

−20

−30

−40

−50

−60
−70
10 20 30 40 50 60 70 80 90 100

FREQUENCY : f (kHz)

Fig.1 Band-pass filter characteristics

zExternal dimensions (Units : mm)

BU1924 BU1924F

19.4±0.3 10.0±0.2
16 9
16 9
6.5±0.3

4.4±0.2
6.2±0.3

1 8
0.51Min.

7.62

0.15±0.1
3.2±0.2 4.25±0.3

1 8
1.5±0.1

0.3±0.1

2.54 0.5±0.1 0 ∼15

0.11

1.27 0.4±0.1 0.3Min.

0.15

DIP16 SOP16

BU1924FS

6.6±0.2

16 9
4.4±0.2
6.2±0.3

0.3Min.

1 8
0.15±0.1
1.5±0.1

0.11

0.1
0.8
0.36±0.1

SSOP-A16

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