Chapter II

Solving Digital Circuit Layout Problem based on

Graph Partitioning Technique

2.1 Introduction
The circuit partitioning problem consists of finding a decomposition of the target circuit
into non overlapping sub circuits with at least one logical gate in each sub circuit. The
partitioning Problem is NP-complete problem; this means it is unlikely that a polynomial
time algorithm exists for solving the problem (Garey et.al., 1976). Therefore, one must
use heuristic techniques for generating approximate solutions. Due to the changing
requirements there is a need to devise new algorithmic solutions to effectively solve
newly emerging complex design problems. This section categorizes and elucidates the
work done so far in the field of Digital Circuit layout in context with graph partitioning.
The literature survey has been organized into three parts. Initially the basic inspiration
summarizes the techniques of implementing partitioning driven min cut algorithms for
the global placement of standard cells in Digital circuit layout. Secondly the literature
concerned with preliminary work of graph partitioning has been reviewed. Subsequent
literature review gives an insight of various evolutionary approaches for solving graph
partitioning problem for Digital Circuit layout.

2.2 The Basic Inspiration

The success of min cut techniques in fixed-die placement is based on the speed and
strength of multi level hypergraph partitioners, the convenient top down framework that
efficiently captures available on chip resources. Algorithms based on balanced min cut
partitioning have been known at least as early as in the 1970s and reached the state of the
art again in the late 1990s after successful implementations of multi-level min cut
partitioners were reported at DAC ’97 (Alpert & Kahng, 1997).

Placement by recursive partitioning is one of the oldest approaches to a fundamental

problem in computer aided design. Partitioning based approaches determine cell locations

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by recursively dividing an initial area (region) with successive bisections or quad
sections. This approach has become more attractive recently; advances in partitioning
research have provided a number of fast algorithms which produce extremely good
results. The list of authors worked on min cut placement are Breuer (1977), Dunlop and
B. W. Kernighan, (1985), Huang and Kahng (1997), Hill et al. (1988), Caldwell et al. d.
(2000), Yildiz and Maddena (2001), Alpert et al. (2003), Kahng and Reda (2004),
Khatkhate, et al. (2004), Jiang et al. (2006), Roy et al. (2006), Changdao et al. (2011) etc.

Breuer (1977) identified the repeated graph bisections to obtain a circuit placement. In
this methodology, the placement region is represented by a series of placement bins
which represent a placement region with allowed module locations, a collection of circuit
modules to be placed in this region, all signal nets incident to the modules in the region,
and fixed cells and pins outside the region that are adjacent to modules in the region.
Breuer studied two types of cut line direction selection techniques and found that
alternating cut-line directions from layer to layer produced better half perimeter wire
length than using only horizontal cuts. The author utilized extension of Kernighan and
Lin (Kernighan & Lin, 1970) for repeated graph bisections to obtain a circuit placement

Dunlop and B. W. Kernighan, (1985) further extended top-down partitioning-based

placement through the use of terminal propagation. They extended formulation of
"partitioning with fixed terminals", where the terminals are considered to be fixed in
("propagated to") one or more partitions, and assigned zero areas. Terminal propagation
provides a simple method to insert fixed “dummy” vertices, so that the partitioning
considers these external connections. The approach was proven to be popular and
competitive.

Huang and Kahng (1997) showed that net weighting and quadric section can be used to
minimize a wide range of objectives such as minimal spanning tree cost. They
incorporated two techniques cycling and overlapping. Cycling technique improves the
results by partitioning every placement bin multiple times for each layer until there is no
further improvement of a cost function. In cycling technique the pieces of neighbouring
bins can be coalesced into a new bin and split to improve solution quality. The method
consists of computing vectors of weights for each net and using these weights in quadric
sections. This work required the discrimination of pin locations into the centres of bins
and calculation of sixteen weights per net for partitioning.

Hill et al. (1988) proposed a new two-step approach based on min cut techniques
combined with a placement evaluation function. The first step is optional. In the first
step if higher level hierarchy information is available, it can be used to group cells
into clusters which form the basis for a two dimensional min-cut placement. The next
step does not depend on higher level information. The clusters are dissolved and the cells
internal to them placed using a stochastic two dimensional min cut placement technique
that attempts to minimize a cost function. The cells are then bound to physical rows, and
a simulated annealing touch up is applied. Finally, the logic cells are dissolved into their
constituent transistors and the design proceeds to detailed placement and routing.

Caldwell et al. (2000) introduces that Min cut placement is highly scalable due in large
part to algorithmic advances in min cut partitioning and typically produces routable
placements. State of the art placers generally use a wide range of hypergraph partitioning
techniques to best fit partitioning problem size optimal, and large-scale. Partitioning
driven placement algorithms based on balanced min-cut partitioning have been known at
least as early as in the 1970s.

Yildiz and Maddena (2001) presented a dynamic programming technique to choose

optimal cut sequences for partitioning based placement and found that nearly optimal cut
sequences could be determined from the aspect ratio of the bin to be split. The authors
implemented a second partitioning based tool, Feng Shui which has comparable
performance to Capo on the majority of MCNC benchmark circuits. Feng Shui
incorporates hMetis partitioner by bisecting all regions at the same time based on
partitioning by iterative deletion. In this placement tool the cut line direction is
determined by an aspect ratio AR which is defined by the ratio of the height of a region
by its width .If AR exceeds a user specified value, the region is bisected horizontally. If it
falls below the specified value, the region is bisected vertically.

Yildiz and Maddenb (2001) focused on aspects of the placement problem which cannot
be captured with bisection, dealing with them through a new approach derived from
recent work on k-way partitioning. They used large values of k, and objective functions
which are more complex than the traditional min-cut. The placement tool, integrates this
new k-way partitioning method into a traditional recursive bisection framework.
Experimental results showed the effect of the approach; there is reduced variation in
solution quality, in 8 of 11 benchmarks best case wire length is improved, and average
wire length is improved for 9 of 11 benchmarks,.

Alpert et al. (2003) suggested integration of analytical techniques and min cut
techniques. The results suggested that analytical constraint generation (ACG) is effective
at improving the performance of min cut placement on designs with large amounts of
whitespace while retaining the good performance and routability of min cut placers on
constrained designs.

Caldwell et al. (2003) introduced a scheme for managing whitespace in top down
placement, uniform whitespace allocation of standard cell row based ASIC designs. With
a straightforward practical adjustment, partitioning tolerance slowly increases as the
placer descends to lower levels. The authors limited relative whitespace in all blocks
from below, and this constraint prevents overcapacity blocks in the assumption that all
partitioning solutions are legal. Experiments on industrial testcases with up to 114K cells
showed that the technique practically achieves cell overlaps in hundredths of a percent of
the total areas and is superior to a commonly used straightforward technique since it
achieves better wirelength in the assumption of comparable cell overlaps.

Kahng and Reda (2004) presented a similar type of technique for min cut bisection
called placement feedback. The placement feedback technique serves to reduce the
number of ambiguously propagated terminals, by repeatedly partitioning each layer n
times. Each successive round of partitioning uses the resulting locations from the
previous partitioning for terminal propagation. Empirical results show that placement
feedback is effective in reducing HPWL, routed wirelength and via count.

Khatkhate, et al. (2004) proposed a two stage approach to mixed size placement. The
authors extended the traditional recursive bisection standard cell placement tool FengShui
to directly consider mixed block designs. First, the min cut placer FengShui generates an
initial placement for the mixed-size netlist without trying to prevent overlaps between
modules. The second stage consists of removing overlaps by a fast legalize designed to
handle large modules along with standard cells. On a set of current benchmarks, the new
version obtains placements with wire lengths substantially lower than other current tools.
In Comparison to FengShui 2.4, the placements using a Capo-based approach have 29%
higher wire lengths, while the placements of mPG are 26% higher. The tool has lower run
times, and the general approach is scalable.

Taghavi et al. (2005) introduced a mixed size placer, Dragon 2005 which combines min
cut bisection with simulated annealing for placement. The placer utilizes recursive
bisection with the hMETIS partitioner with a feedback mechanism followed by simulated
annealing to improve HPWL. The process is repeated and the partitioning phase
terminates when each bin contains only a few cells. Then bins are aligned to row and cell-
based simulated annealing is performed followed by removing cell overlaps and local
detail placement improvements.

Jiang et al. (2006) proposed a hybrid placer called that uses both min cut partitioning and
analytical techniques for standard cell and mixed size designs. Initially the placement is
done by analytical technique followed by hMETIS partitioner for partitioning net cut.
The placer firstly places the objects in a placement bin by an analytical technique
followed by partitioning with hMETIS partitioner. Along with cutline shifting and
weighted net cut technique, NTUPlace2 has resulted in very good solution quality.
Roy et al. (2006) proposed to integrate min cut placement with fixed-outline
floorplanning to solve the more general placement problem, which includes cell
floorplanning, placement, mixed-size placement, and achieving routability. At each step
of min-cut placement, either wirelength-driven fixed-outline floorplanning or partitioning
is invoked. If the latter fails, the authors undo an earlier partitioning decision, merge
adjacent placement regions, and floorplanning the larger region to find a legal placement
for the macros. Empirically, this framework improved the scalability and quality of
results for traditional wirelength driven floorplanning. Additionally, the authors proposed
that free-shape rectilinear floorplanning can be used with rough module-area estimates
before logic synthesis.

Changdao et al. (2011) presented a multilevel hypergraph partitioning method that

balances constraints on not only the cell area but also the wire weight with a partition-
based global placement algorithm that maximizes the wire density uniformity to control
chemical-mechanical polishing (CMP) variations. In this method, the multilevel
partitioning alternately uses two FM variants in the refinement stage to give a more
uniform wire distribution. A top down recursive bisection framework acts as the basis of
global placement. The partitioning algorithm is used in the bisection to impact the wire
density uniformity. Tests show that, with a 10% constraint, the partitioning produces
solutions with more balanced edge weights that are 837% better than from hMetis,
1039.1% better than MLPart, and 762.9% better than FM in terms of imbalance
proportion and that this global placement algorithm improves ROOSTER with a more
uniform wire distribution by 3.1% on average with an increased wire length of only
3.0%.

2.3 Graph Partitioning related preliminary Work

The application of these partitioning algorithms depends on several factors. An important
factor is the trade off between computation time and solution quality. Some algorithms
executes fast but deliver solutions of medium quality while others require significantly
longer time but produce excellent quality partitions and even other that can be tuned
between both extremes. This preference of time vs. quality is problem dependent. In the
context of VLSI design, even a slight improvement of partition quality can be of
significant importance. For these applications, it is worthwhile to employ a partition
algorithm able to obtain excellent quality solutions even if the algorithm is
computationally intensive. Another factor that has to be considered when designing an
appropriate partitioning algorithm is the partition balance. While some applications
require partitions of perfect balance, others tolerate imbalance up to a certain degree in
order to achieve a partition of better cut-size. All of these imply that there is no single
best algorithm for all the cases.

Schweikert and Kernighan (1972) extended KL to hypergraphs and proposed a new

hypergraph model for circuit partitioning problem. This model was computationally
straightforward and was easily adapted to the typical heuristic solution strategies. The
authors pointed out the major flaw of the clique graph model. After bipartitioning,
vertices connecting large nets tend to end up in the same block, whereas vertices
connected to two point nets end up in different blocks. They combined their hypergraph
model in Kernighan Lin partitioning heuristic and obtained much better results on circuit
partitioning problems.

Fiduccia and Mattheyses (1982) presented an iterative improvement algorithm that

modified the Kernighan and Lin heuristic to speed up the search. They introduced a new
data structures called a bucket list to achieve the linear run time per pass. The proposed
local search heuristic determined which vertex to move based on its gain instead of
exchanging pairs of vertices as in KL. The authors also introduced the concept of
preserving balance in the size of blocks Like KL, the FM algorithm performed passes
wherein each module was moved exactly once, returning the best solution observed
during a pass, and terminating when a pass fails to improve the cost function.
However, FM permitted a much faster O (|P|) per pass implementation on hypergraphs,
with P being number of pins in the netlist.

Sechen and Chen (1988) introduced another modification of the original KL and FM
descriptions. They observed that the Min-Cut Bisection objective was not ideal when
the partitioning solution was to be used as the basis of hierarchical placement. If a
net e was having more than one pin in both C1 and C2, then e might cross the cut more
than once after routing. For each net e, the authors considered every possible
assignment of modules in e to rows 1, 2, ..., |e|, computed the number of times e
would cross the cut when routing each configuration, then averaged the results to
derive an expected cutsize for e. This expected cutsize was used to compute module
gains.

Johnson et al. (1989) conducted an extensive empirical study of simulated annealing

versus iterative improvement approaches. The authors used various random graphs as a
test bed for the Min-Cut Bisection problem. They stated that any partition of vertices into
two sets is a valid solution, even if the sub partitions are not of the same size. The
algorithm attempted to even out partition sizes by moving the vertex that resulted in the
least increase in cutsize from the larger set to the smaller set using the cost function. The
authors concluded that simulated annealing produced smaller netcuts than iterative
methods, albeit with much greater runtimes .The approach, outperformed KL for uniform
and geometric random graphs. The authors suggested that multiple runs of KL with
random starting solutions may be preferable to simulated annealing for sparse graphs that
have local structure.

Kring and Newton (1991) extended FM to include module replication moves for
reducing net cut. The methodology defined the gain for replicating a module as the
change in cutsize. The authors observed that once a module is replicated, that
module tended to remain replicated, retaining the modules in their clusters. They
restricted the number of replications by keeping three separate bucket structures
for normal, replicating and unreflecting moves. Separate structures permitted the
unreplication of a module if its unreplication gain is higher than a prescribed threshold.
They also prescribed a minimum replication gain threshold below which a module
replication is prohibited, even if it is the best move available.
Wei and Cheng (1991) presented a two-way partitioning algorithm that significantly
improved on the highly unstable results typically obtained from the traditional
Kernighan-Lin-based algorithms. The authors applied a hierarchical version of Wei s
(Wei et al., 1989) algorithm to obtain clustering’s for use within two-phase FM. The
algorithm grouped highly connected components into clusters and rearranged the clusters
into two final subsets with specified sizes. To prevent degeneration, a ratio cut approach
was used to do the grouping. By a set of experiments based on the trade off between CPU
time and cut weight, the value which controls the resultant number of groups was
determined. Good experimental results were observed for cut weight and CPU time.

Hagen et al. (1992) concentrated on the problem of partitioning of circuit netlists in

VLSI design. Using the well known Fiedler vector, they presented a good approximation
of the optimal ratio cut partition cost. Using Lenclos method for the sparse Eigen value
problem was found to be a robust basis for computing heuristic ratio cuts based on the
Fiedler vector. They also considered the intersection graph representation of the circuit
netlist as a basis for partitioning, and proposed a heuristic based on spectral ratio cut
partitioning of the netlist intersection graph which was tested on industry benchmark
suites and the results compared favourably with those of Wei and Cheng (1991) in terms
of both solution quality and runtime.

Cong and Smith (1993) presented a bottom up clustering algorithm based on recursive
collapsing of small cliques in a graph which lead to a natural parallel implementation in
which multiple processors are used to identify clusters simultaneously. This algorithm
was used as a pre-processing step to both bisection algorithm by Fiduccia and Mattheyses
and a ratio cut algorithm by Wei and Cheng. The algorithm obtained 49.6% smaller cut
size than bisection algorithm and 66.8 % smaller ratio cut sizes than ratio cut algorithm
and produced much stable results than direct partitioning.

Alpert and Kahng (1994) used a space filling curve traversal of the space spanned by a
small set of eigenvectors to determine where to split the ordering induced by the set of
eigenvectors. The authors discussed clustering methods that form blocks by splitting a
linear ordering of vertices using dynamic programming. The technique embedded a linear
ordering obtained from multiple eigenvectors in multidimensional space and used a
travelling salesman problem (TSP) heuristic to traverse the points. The authors pointed
that the points that are close together in the embedding are in proximity to one another in
the linear ordering. A space filling curve was then used as a good TSP heuristic because
it traverses the points that are near to each other before wandering off to explore other
parts of the space.

Yeh et al. (1994) gave an extension of Sanchis multi-way partitioning algorithm (Sanchi,
1989) that alternated "primal" passes of module moves with “dual” passes of net moves.
A dual pass allowed more than one module to be moved simultaneously, thereby
expanding the neighborhood structure. For each net e, the authors defined the critical set
with respect to Ci .A move in a dual pass consisted of either moving the critical set out of
Ci or moving the complementary critical set into Ci. The gain was the decrease in cost of
the partitioning solution resulting from the move. Due to the complexity of the gain
computation, a dual pass typically required around 9-10 times the CPU of a primal
pass.

Bultan and Aykanat (1995) formulated a mean field annealing (MFA) algorithm for the
circuit partitioning problem using the net-cut model. The authors also developed an
efficient implementation scheme, which reduced the complexity of the proposed
algorithm by asymptotical factors. Comparative performance analysis of the proposed
algorithm with two well known heuristics, simulated annealing and Kernighan-Lin
indicated MFA as a successful alternative heuristic for the circuit partitioning problem.
The authors also observed that, with the increase in the number of partitions, the solution
quality and the speed advantage of the proposed MFA heuristic increased in comparison
with those of the KL heuristic.

Dutt and Deng (1996) pointed out that the FM based iterative improvement algorithms
could only remove small clusters from the cutset while it likely locks bigger clusters in
the cutset. The authors proposed a technique CLIP (Cluster-oriented Iterative-
improvement Partitioned which divided the cell gain into initial gain calculated before a
cell movement and the update gain was generated from the cell movement afterwards. In
this method the decision regarding which subsequent vertices to move was based on the
updated gain component exclusively paying more attention to the neighbours of moved
cells and encouraging the successive moves of closely connected cells The technique
implicitly promoted the move of an entire densely connected group (a cluster) into one
subset of the partition .By focusing on the update gain when choosing cells to move, they
reported very successful results for bipartitioning experiments reducing both the
minimum and average cutsize of multiple runs.

Hauck and Borriello (1997) examined many of the existing techniques for logic
bipartitioning and presented a methodology for determining the best mix of approaches.
The authors demonstrated that technology mapping before partitioning was a poor choice,
significantly impacting mapping quality. They found that Connectivity clustering
performed well, while dual passes were not worthwhile, and greatly increased run times.
They suggested that bucket insertion and removal ordering also did not seem to
significantly impact the quality of an optimized KLFM algorithm. By appropriately
applying the techniques discussed they proposed a novel bipartitioning algorithm that
included both new and pre existing techniques. The algorithm produced results that were
at least 16% better than the state-of-the-art while also being efficient in run-time.

Xu et al. (1998) presented a fast implementation of the recursive spectral bisection

method for k-way partitioning since recursive bisections for k-way partitioning using
optimal strategies at each step may not lead to a good overall solution. The relaxed
implementation accelerated the partitioning process by relaxing the accuracy requirement
of spectral bisection method. Since the quality of the solution of a spectral bisection of a
graph primarily highly depends on the accuracy of its Fiedler vector, they proposed a
tight iteration number bound and a loose residual tolerance for Lanczos algorithms to find
the Fiedler vector.
Battiti and Bertossi (1999) applied Tabu search to the graph partitioning problem. And
proposed a new MIN-MAX-GREEDY algorithm based on a tie-breaking rule and an
effective randomized and reactive Tabu Search scheme The MIN-MAX-GREEDY
algorithm was very fast, and roughly comparable in speed with a trivial random
initialization, and it reached results that are significantly better than previous greedy
approaches, without requiring detailed problem-specific knowledge beyond the
connectivity structure of the graph. The relationship between prohibition-based
diversification (Tabu Search) and the variable-depth Kernighan Lin algorithm was
discussed. On the first series of graphs a better performance for equivalent or smaller
computing times was obtained, while on the large “real-world” instances significantly
better results than those of multi level algorithms were obtained but for a much larger
computational effort.

Mak and Wong (2000) presented a fast non-flow-based algorithm for computing a
minimum cut in a hypergraph directly. The approach avoided the transformation of the
hypergraph into a larger flow network and then applying a flow based algorithm on the
network to find a minimum cut in a hypergraph. Unlike the most minimum cut
algorithms which relied on flow computations in a network, the proposed algorithm was a
non-flow-based algorithm. The authors concluded that as the netlist of a circuit could be
modelled naturally as a hypergraph, this opened the opportunity for finding very high
quality solutions for the circuit partitioning problem.

Cherng et al. (1999) presented a two level bipartition algorithm named Two Level
Partitioned (TLP) algorithm combining a hybrid clustering technique with an iterative
partitioning process for VLSI circuits. The hybrid clustering algorithm consisted of a
local bottom-up clustering technique to merge modules and a global top down ratio cut
technique for decomposition. To generate a partitioning solution, the authors also
proposed module migration based partitioning algorithm MMP as the base partitioned for
the TLP algorithm. The MMP algorithm implicitly promoted the move of clusters during
the module migration processes. Experimental results obtained indicated that the TLP
partitioned generated promising results in either the minimal net cut or the average net
cut. On the other hand, the TLP partitioned also improved the unstable property of
module migration based partitioned such as FM and STABLE in terms of the average net
cut value

Dutt and Deng (2002) proposed new IIP methods CLIP and CDIP that selected cells to
move with a view to moving clusters that straddle the two subparts of a partition, into one
of the subparts The new algorithms significantly improved partition quality while
preserving the advantage of time efficiency. The proposed new algorithms generated
much better mincut results than classic IIP techniques such as lookahead (LA) gain
calculation method and Fidducia Mattheyses(FM), and state of the art non IIP methods
such as Paraboli and MELO. They also obtained comparable mincuts but at much higher
speeds than state of the art multilevel IIP algorithms such as hMetis.

Ouyang et al. (2002) introduced a cooperative multilevel hypergraph partitioning

algorithm. The authors looked at the standard multilevel paradigm as a variant of k-
exchange, a technique used to define the move sizes of move-based heuristics. The
vertices of coarsened hypergraphs were used as a mechanism to select the move sizes and
configuring of the local search heuristics that partition the netlist. They introduced a
cooperation protocol that specified how those heuristics shared states at run time. The
runtimes of the current CoMHP algorithm did not compare well with a partitioning
method like hMETIS. The experimental results on ISPD98 benchmark suite showed that
their algorithm outperformed hMETIS.

Cherng and Chen (2003) presented a multi level bipartitioning algorithm(MLP) by

integrating a clustering technique and an iterative improvement based partitioning
process for VLSI circuit design in order to minimize the number of interconnects
between the subsets of the circuit in order to reduce interconnect delays in deep
submicron technology. The proposed clustering algorithm was used to reduce the
partitioning complexity and improved the performance of partitioning. To obtain a high-
quality partitioning solution, a new algorithm named module migration based partitioning
algorithm MMP was also proposed as the based partitioner for the MLP algorithm. The
MMP algorithm implicitly promoted the move of clusters during the module migration
processes by paying more attention to the neighbours of moved modules, controlling the
module migration direction and relaxing the size constraints temporarily during the
migration process. Experimental results obtained showed that the MLP algorithm
generated high-quality partitioning results than MELO and CDIP.

Banos et al. (2004) presented a new parallel multilevel hybrid metaheuristic algorithm
for static graph partitioning by mixing different heuristics, such Tabu Search, Simulated
Annealing, and some selection mechanisms. The parallel algorithm simultaneously
optimised several solutions. Each solution evolved independently applying the multilevel
paradigm with different annealing parameters. Eventually, during the refinement phase,
an elitist selection mechanism was used in order to best utilise the computational
resources in the search for the best solutions. The authors concluded that the diversity of
the initial partitions was essential in the search process They also analysed the
consequences of modifying the number of solutions and the number of iterations in the
refinement phase of the multilevel algorithm .The elitist selections strategies allowed the
computational resources to be concentrated in the exploration of the best solutions. The
efficiency of the new algorithm was compared with other previously proposed algorithms
with promising results.

Choe, T. Y. and Park C. (2004) stated that recursive spectral bisection for the k-way
graph partition was underestimated because it tried to balance the bipartition strictly.
However, the spectral bisection could identify clusters efficiently by loosening the
balancing constraint. The authors proposed a k-way graph partitioning algorithm based on
clustering using recursive spectral bisection. After partitioning the graph, the partition
was adjusted in order to meet the balancing constraint. Experimental results showed that
the clustering based k-way partitioning generated partitions with 83.8-108.4% cut sets
compared to the strict recursive spectral bisections or multi-level partitions.

Trifunovi and Knottenbelt (2004) presented a coarse-grained parallel multilevel

algorithm for parallel multilevel k-way partitioning that significantly improved on the
work in terms of run time and scalability behaviour by improving processor utilisation
and reducing communication and synchronisation overheads. . The algorithm featured
novel schemes for resolving conflicts that arose during the parallel coarsening process
and for reducing vertex thrashing during parallel refinement. The algorithm consistently
outperformed the approximate partitions produced by a state of the art parallel graph
partitioning tool, by up to 27% in terms of partition quality.

Felner A. (2005) first showed how to format graph partitioning problem as a search
problem .The authors introduced a sequence of admissible heuristic functions estimating
the size of the optimal partition by looking into different interactions between vertices of
the graph and then optimally solved GPP with these heuristics. The authors stated that
introducing new domain independent search algorithms by suggesting new methods for
expanding nodes did not lead to a large reduction in the search effort. More accurate
heuristic functions might be the method of choice for significantly reducing the search
effort. Experimental results showed that the advanced heuristics achieved a speedup of up
to a number of orders of magnitude. The experimental comparison of the approach to
other states of the art graph partitioning optimal solvers on a number of classes of graphs
showed that the algorithm outperformed them in many cases.

Andreev and Racke (2006) considered the problem of partitioning a graph into k
components of roughly equal size while minimizing the capacity of the edges between
different components of the cut. The authors presented a polynomial time approximation
algorithm for the (k, ν)-balanced partitioning problem that achieved an O (log1.5 n) -
approximation ratio with respect to the capacity of edges between different partitions
using the spreading metrics technique. The algorithm extended in a straightforward
manner to the case where the nodes of the graphs were weighted and the goal was to
balance the weight among the partitions. For value of ν as 1 and k greater than or equal
to 3 it was shown that no polynomial time approximation algorithm can guarantee a
finite approximation ratio unless P = NP.
Devine et al. (2006) presented a parallel software package for hypergraph partitioning
developed at Sandia National Labs which was a variation on multilevel partitioning and
used a two-dimensional data distribution among processors. The authors showed that the
partition quality was similar to that of serial hypergraph partitioners (PaToH), and in
most cases it was much faster than the recent similar code Parkway. The results showed
that the parallel implementation achieved good parallel speedup on several large
problems up to 33 million non zeros with up to 64 processors on a Linux cluster. The 2D
data distribution gave better performance than the standard 1D layout.

Jianhua Li (2006) indicated that circuit partitioning is a fundamental problem in very

large-scale integration (VLSI) physical design automation. The author presented a new
connectivity-based clustering algorithm for VLSI circuit partitioning. The new proposed
clustering method focuses on capturing natural clusters in a circuit, which are the groups
of cells that are highly interconnected in a circuit. Thus, the proposed clustering method
can reduce the size of large-scale partitioning problems without
losing partitioning solution qualities. Using ISPD98 benchmark suite, the performance of
the proposed clustering algorithm is evaluated .The experimental results show that the
previously reported best partitioning solutions from state-of-the-art practitioners are
further improved by applying the proposed clustering algorithm.

Chardaire et al. (2007) proposed a new heuristic algorithm, PROBE_BA, which was
based on the recently introduced metaheuristic paradigm population reinforced
optimization-based exploration (PROBE), for solving the Graph Partitioning Problem.
PROBE BA used standard graph partitioning methods to explore search spaces and
perform local optimization, the Differential-Greedy algorithm of Battiti & Bertossi and a
modification of KL due to Bui and Moon. Experiments were used to investigate
properties of PROBE and results were comparable with other solution methods based on
randomized reactive tabu search, genetic algorithms, or more specialized multilevel
partitioning techniques. In addition, PROBE_BA found new best cut values for 10 of the
34 instances in Walshaw's graph partitioning archive.
Sun and Leng (2007) presented an effective multi-level algorithm based on simulated
annealing for bisecting graph. The success of the algorithm relied on exploiting both the
simulated annealing procedure and the concept of the graph core. In the multilevel
algorithm the multi-level simulated annealing refinement (MLSAR) algorithm was
adopted during the refinement phase and effective matching-based coarsening scheme
during the coarsening phase that used the core-sorted heavy-edge matching (CSHEM)
algorithm on the original graph and the sorted heavy-edge matching (SHEM) algorithm
on the coarser graphs. The experimental evaluations on 18 different graphs showed that
the algorithm produced encouraging solutions compared with those produced by MeTiS
that was a state-of-the-art partitioner in the literature.

Aykanat et al. (2008) claimed that hypergraph partitioning with multiple constraints and
fixed vertices should be implemented using direct K-way refinement, instead recursive
bisection paradigm and described an implementation of a multi-level direct K-way
hypergraph partitioning algorithm, which performs better than a recursive-bisection-
based partitioning algorithm in hypergraph partitioning with multiple constraints and
fixed vertices. The authors proposed specialized coarsening and initial partitioning with a
novel formulation that uses bipartite graph matching. The experiments conducted on
benchmark datasets indicated that the proposed algorithm is quite fast and effective in
minimizing the cutsize compared to PaToH, the state-of-the-art hypergraph partitioning
tool.

Bichot (2008) presented an application of the Fusion-Fission method to the multi-way

graph partitioning problem. The Fusion-Fission method was first designed to solve the
normalized cut partitioning problem. The adaptation of Fusion-Fission to the multi-way
graph partitioning problem used the pMETIS multilevel algorithm and its Kernighan-Lin
refinement algorithm. The Fusion-Fission algorithm was slower than the state-of-the-art
graph partitioning packages. The Fusion-Fission algorithm was compared with state-of-
the-art graph partitioning packages JOSTLE, METIS, CHACO and PARTY .The
partitions searched were of cardinal numbers 2, 4, 8 and 16, with a balance of 1.00, 1.01
and 1.03. Results showed that up to two thirds of time were the partitions returned by
Fusion-Fission of greater quality than those returned by state-of-the-art graph partitioning
packages.

Benlic and Hao (2010) presented a multilevel algorithm approach for balanced graph k-
partitioning, called, a multi level iterated tabu search (MITS) which integrated a powerful
refinement procedure based on tabu search with periodic perturbations. The dedicated
tabu search algorithm included features like the joint use of two neighbourhoods, guided
selection strategies for vertex migration based on long term memory and a dynamic tabu
tenure technique. The tabu search algorithm was combined with a perturbation
mechanism to escape from deep local optima Experimental evaluations on a wide
collection of benchmark graphs showed that the proposed approach not only competed
very favourably with the two well-known partitioning packages METIS and CHACO, but
also improved more than two thirds of the best balanced partitions ever reported in the
literature.

Holtgrewe et al. (2010) demonstrated that high quality graph partitioning can be
obtained in parallel in a scalable way. They described an approach to parallel graph
partitioning that scales to hundreds of processors and produces a high solution quality.
All components were implemented by scalable parallel algorithms. The quality
improvements compared to previous systems were due to better prioritization of edges to
be contracted, better local search heuristics, better approximation algorithms for
identifying matching’s and perhaps, a parallelization of the FM local search algorithm
that worked more locally than previous approaches. Moreover, their parallelization
approach even seemed to ameliorate partition quality, and in some cases improved the
best known partitions reported in the literature.

Yoon et al. (2011) analyzed two essential problems arising from edge-based graph
partitioning and showed one of them being an NP-hard problem but the other is in P.
They presented a novel methodology that linked linear algebra theory to the graph
problems as a part of proving the facts. The authors examined the computability of the
two problems, Check Partition and Closest Partition. They showed that Check Partition
could be easily computed and also proposed a linear-time algorithm as a part of proving
the fact. They also proved that Closest Partition being an NP-complete problem.

Batra and Malik (2012) say that electronic design automation is concerned with the
design and production of VLSI systems. The next vital step in creating a VLSI circuit is
Physical Design. Physical design problems are combinatorial in nature and of large
problem sizes. Due to its high complexity, the physical design is normally divided into
various sub-steps. The circuit has to be partitioned to get some (up to 50) macro cells
which have to be placed on the chip (floor-planning). In the routing phase pins on the
walls of these modules have to be connected. The last step in the physical design is the
compaction of the layout, where chip is compressed in all dimensions so that the total
area is reduced. This survey work aims at a study on Efficient Algorithms for Partitioning
in VLSI design and observes the common traits of the superior contributions.

Safro et al. (2012) focused on the coarsening phase, responsible for creating structurally
similar to the original but smaller graphs. They introduced a new coarsening scheme for
multilevel graph partitioning based on the AMG coarsening and emphasized the success
of the proposed AMG coarsening and the algebraic distance connectivity measure
between nodes demonstrated on highly irregular instances They compared different
matching and AMG-based coarsening schemes, experimented with the algebraic distance
between nodes, and demonstrated computational results on several classes of graphs that
emphasized the running time and quality advantages of different coarsening. They
observed a number of examples for which the unbalanced coarsening produces noticeably
better results.

Chen and Zhu (2013) proposed a discrete dynamic convex method for the circuit
partitioning problem. The authors formulated the problem as an equivalent constrained
integer programming problem by constructing an auxiliary function. A global search
method, entitled the dynamic convex method, was developed for the integer
programming problem. The Fiduccia– Mattheyses (FM) algorithm was modified for the
circuit partitioning problem, to minimize the auxiliary function. They showed both
computationally and theoretically that the method could escape successfully from
previous discrete local minimisers by taking increasing values of a parameter.
Experimental results on ACM/SIGDA and ISPD98 benchmarks showed up to 58%
improvements over the well known FM algorithm in terms of the best cutsize. The
algorithm was integrated with the state-of-the-art practical multilevel partitioner MLPart.
Experiments results on the same set of benchmarks showed that the solutions obtained in
this way had 3–7% improvements over that of the MLPart.

Manikandan et al. (2013) focused on that Partitioning is a significant area of VLSI

Design and has been an energetic area of research. VLSI circuit partitioning is an
imperative part of physical design stage. The authors compared the performance of K-
way partitioning and Markov Clustering Algorithm. The comparative study provided a
clarification to approach problems in circuit partitioning pertaining to VLSI Design.
Using Simple Full Adder Circuit, the performance of both approaches is compared. From
this analysis it is proved that the Markov Clustering Algorithm achieves greater
performance compared to K-way partitioning

Jone and Papachristou (2013) the author presents a circuit partitioning and test pattern
generation technique for pseudo-exhaustive built in self testing of VLSI circuits.
The process of circuit partitioning divides a given circuit into a set of subcircuits which
can be exhaustively tested. The test pattern generation process generates reduced
exhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR).
These two problems are considered separately in conventional approaches. However, in
this work, both problems are considered and solved in the same phase. The authors
proposed a graph theoretic model of VLSI circuits. Based on this model,
a circuit partitioning algorithm using the concept of minimum vertex cut is devised
to partition the circuit into a set of exhaustively testable subcircuits with restricted
hardware overhead. Each time a subcircuits is generated by the partitioning algorithm
considering the test pattern generation problem. Experiments using ISCAS
benchmark circuit simulation have been conducted. The results of the experiments
demonstrated that the proposed method is very good
Yoon and Kim (2013) proposed a new tie breaking strategy in an iterative improvement
algorithm for graph partitioning. The authors improved the traditional champion, namely
the LIFO strategy, by considering the types of gain updates. The algorithm considered
three types of gain updates in the KL algorithm: gain increases (type A), no change (type
B), and gain decreases (type C). The new LIFO strategy selects the vertices is the same as
in LIFO but differs in the vertex insertion. Each vertex of type A is inserted at the head of
the bucket. Each vertex of type C is inserted at the tail of the bucket. There is no change
for the vertices of type B. The authors suggested that it might be advantageous to move
vertices having a close relationship with recently moved vertices. The proposed method
is simple but nevertheless performed better than other traditional techniques.

2.4 Various evolutionary approaches for graph partitioning

In recent years, metaheuristics are used for combinatorial optimization in which an
optimal solution is sought over a discrete search space. A metaheuristic is
a procedure designed to find a good solution to a difficult optimization problem (Blum
and Roli, 2003). Metaheuristics make few assumptions about the optimization problem
being solved, and so they are usable for a variety of problems. Some metaheuristics have
already been used to partition graphs, like genetic algorithms (Bessiere and Talbi, 1991;
Greene, 2001) or ant like agents (Kuntz et al., 1997, Langham and Grant, 1999).
Therefore, for all of these tools, there is a need to find a near optimal partition in
reasonable time. Because minimum cut algorithms were well studied (Kernighan and Lin,
1970; Fiduccia and Mattheyses, 1982, Ercal et al., 1990), most partitioning methods use
recursive bisections. But these methods often provide a partition which is far from
optimal (Simon and Teng, 1997), regarding the minimization of the sum of the weight of
edge cuts. Conversely, spectral graph partitioning methods (Pothen, 1990; Hagen and
Kahng, 1992) and multilevel partitioning algorithms (Hendrickson and Leland, 1995)
produce good partitions. The most widely used heuristic like Kernighan Lin algorithm
(Kernighan and Lin, 1970) and Fiduccia-Mattheyses algorithm (Fiduccia and Mattheyses,
1982) are not very suitable for solving real VLSI partitioning problems their performance
is strongly dependent on the starting point and they are unable to handle any additional
constraints in an efficient way. In such a case evolutionary algorithms (EAs) seem to be a
promising alternative as they have already turned out to be powerful tools for solving
hard combinatorial problems (Garey et al., 1976). A few EA based approaches to VLSI
circuit partitioning have been described in the literature (Raman and Patnaik, 1996;
Vermuri, 1994).

Ackley (1987) proposed a single operator by combining crossover and mutation of

genetic algorithm for min cut bisection problem where every gene value in the child
offspring was decided based on the probability p. The selection scheme is purely
random and the replacement scheme eliminates a random solution in the current
population which has below average quality. This GA may create unbalanced solutions
that are not legal bisections, and therefore the technique incorporated penalty term in cost
function to avoid unbalanced solutions.

Chatterjee and Hartley (1990) presented an SA-based heuristic which performed

partitioning and placement simultaneously. Their cost function was the sum of five
components: conflict and capacity costs which combined to measure the feasibility of
mapping a cluster onto the chip, a wasted space cost that penalized unused resources on
the chip, a half perimeter net cost, and a pin cost. These works illustrated the ease with
which SA could address relatively arbitrary objective functions

Saab and Rao (1990) proposed a simulated evolution bisection heuristic which has no
crossover operator, but rather a more complex mutation operator. The adaptive algorithm
iteratively improves upon a given initial bisection of a graph. The authors presented a
sufficient condition for optimality of a given bisection which led to an algorithm that
always finds an optimal bisection for a certain class of graphs. A greedy approach was
used to develop a more powerful heuristic. The performance of the algorithm was
compared with Kernighan-Lin method on many random graphs with large numbers of
vertices. The results indicated that the new adaptive heuristic produces bisections with
costs within 2% of those produced by the Kernighan-Lin method with a three times faster
computation speed in most cases
Chandrasekharam et al (1993) employed a stochastic search by a genetic algorithm
(GA) to find a near optimal solution for the node partitioning problem. An elegant data
structure was used for solution representation together with genetic operations and
selection policies. The proposed GA does not require the number of disjunct node sets to
be given a priori. The authors solved three application problems in VLSI design as
instances of NP. The experimental results presented in each case of these application
problems bring out the efficacy of genetic algorithms.

Areibi and Vannelli (1994) described the application of a combined Tabu Search and
Genetic Algorithm heuristic to guide an efficient interchange algorithm to explore and
exploit the solution space of a hypergraph partitioning problem. Good initial partitions
obtained by the Genetic Algorithm method allows the iterative improvement method
under the guidance of Tabu Search to enhance the quality of solutions in a reasonable
amount of time by exploring and exploiting the solution space of a hypergraph
partitioning problem. The hybrid approach applied tabu search to every member of
population. Results obtained indicate, that the generated solutions and running time of
this hybrid are superior to results obtained from a combined eigenvector and node
interchange method.

Majhi et al. (1995) solved the problem of partitioning for Multichip Modules using the
GA approach. The performance of GAs was compared with that of Simulated Annealing
(SA), by implementing the algorithms on three benchmark circuits. Encouraging results
were observed as GAS outperformed SA in the solution obtained for the same
computation time in both the algorithms. The effect of varying the parameters of
the algorithm on the performance of GAs was studied. As the probability of mutation was
increased from 0.001 to 0.005, the GA was observed to climb faster. But further increase
of the mutation decelerates the rate of fitness function increased objective interconnect
cost, constraints. The authors further concluded that increasing the population size to a
very high value was not advisable because, in that case for every building block
processed, the number of non-building blocks processed was enormously high.
Alpert et al. (1996) integrated the Metis multilevel partitioning algorithm into a genetic
algorithm and proposed a hybrid approach that uses graph partitioner Metis as a solution
generator. The generated solutions are then combined within a genetic algorithm
framework. .This approach involves a hypergraph to graph transformation. The technique
produced better results than simple metis package by firstly applying metis to partition
the netlists of circuit and then using genetic algorithm to further construct new solutions
from previous metis solutions. The results produced using this approach on the
ACM/SIGDA (MCNC) benchmark suite is comparable with that of FM algorithm.

Langham and Grant (1999) used an Ant Foraging Strategy (AFS) employing self
organizing properties of ant colonies to tackle the classical combinatorial optimization
problem of graph partitioning. The graph was mapped onto an artificial environment in a
manner that preserves the structural information. Ants from a number of colonies
compete for resources which led to a restructuring of the global environment
corresponding to a good partition. On the example graphs the Ant Foraging Strategy
(AFS) outperformed the Recursive Spectral Bisection, Recursive Spectral Bisection plus
Kernighan Lin and also Multilevel Kernighan Lin algorithms.

Merz and Freisleben (2000) proposed a memetic algorithm for graph bipartitioning
problem, which is based on the observations made from an exhaustive landscape analysis
on a set of local optima sampled with the KL and greedy heuristics respectively. The
authors observed that different graphs have different problem spaces. They designed
experiments with two local heuristics. Using greedy crossover operation which repairs
unbalanced partitioning, the experimental results showed that the problem space became
smoother as the average degree increased.

Kim and Moon (2001) proposed a hybrid genetic algorithm for multiway graph
partitioning including an efficient local optimization heuristic. The algorithm utilized
cyclic movements of vertices. By attempting direct k-way partitioning and allowing more
freedom to vertex movements, it improved the solution quality. Hybrid GAs with local
optimization algorithms specialized for multi-way partitioning showed good results .The
comparison between multi-start CP and GCMA showed the superiority of the proposed
genetic algorithm.

Cincotti et al. (2002) used order-based encoding where, a chromosome is represented by

a permutation of |V |integers with each integer representing the vertices of graph. To
reconstruct or evaluate a partitioning of vertices represented by this encoding, a decoding
process is required. The process assigned each vertex to the partition that maximized the
sum of the edge weights between the vertices in the same partition; the resulting
partitioning becomes the phenotype of the chromosome. This type of encoding does not
require normalization but it cannot represent all feasible solutions and its decoding
process takes a long time.

Muhlenbein and Mahnig (2002) presented a theory of population based optimization

methods using approximations of search distributions and proved convergence of the
search distribution to the global optima for the Factorize Distribution Algorithm (FDA) if
the search distribution is a Boltzmann distribution and the size of the population is large
enough. In the work an upper bound on the hyper parameter was derived and relation of
the FDA approach to methods used in statistical physics was discussed. The algorithm
applied bipartitioning of graphs gave good empirical results than existing methods

Kohmoto et al. (2003) investigated the performance of the genetic algorithm (GA) for
the graph partitioning problem by comparing it with standard heuristics on well-known
benchmark graphs. The authors incorporated a simple local search algorithm into the GA.
The search ability of the GA was compared with standard heuristics such as multistart
local search and simulated annealing, which used the same neighborhood structure of the
simple local search, for solving the GPP. The multistart local search (MSLS) attempted
multiple runs of the local search starting from randomly generated solutions. The process
was repeated until a. given computation time and the best solution among obtained
solutions was output as a result. Experimental results showed that the GA performed
better than its competitors.
Kim et al. (2004) propose a combination of a genetic algorithm with an FM-based
heuristic for hypergraph bipartitioning. The algorithm is experimentally compared to a
simple FM implementation and the hMeTiS multilevel tool on the (older) ACM/SIGDA
benchmark circuits. The authors observe that their FM-based heuristic without the genetic
algorithm is an improvement over the simple FM algorithm. In combination with the
genetic algorithm, the resulting partitioning algorithm computes partitions that are
competitive with those produced by hMeTiS. The reported runtimes are also very
competitive with hMeTiS. The authors note, however, that the test hypergraphs used are
considerably smaller than those in the ISPD98 circuit benchmark.

Kucukpetek et al. (2005) presented a genetic algorithm for the coarsening phase of a
multilevel scheme for graph partitioning. A number of researchers investigated multilevel
schemes, that coarsen the graph by collapsing vertices and edges, partition the smaller
graph, and then uncase it to construct a partitioning of the original graph. The proposed
approach demonstrated to improve the solution quality at the expense of running time.

Ganesh et al. (2006) applied a swarm intelligence based approach to the circuit-
partitioning problem for pseudo exhaustive testing which ensured a reduction in the
number of test vectors required to detect faults in VLSI circuits. The proposed algorithm
is based on the circuit’s maximum primary input cone size (N) and minimum fanout (F)
values to decide the location and number of partitions where Particle swarm optimization
(PSO) is used to determine the optimal values of N and F to minimize the number of
partitions, the number of test vectors, and the increase in critical path delay due to the
added partitions. The algorithm has been applied to the ISCAS’85 benchmark circuits
and the results are compared to other partitioning approaches. The results showed that the
PSO partitioning algorithm produces similar results, about one-order of magnitude faster.

Martin (2006) proposed that GAs can be enhanced by obtain relationships between
genes. The technique was called the singular value decomposition (SVD), in which the
initial population was created using eigenvectors of the incidence matrix of a graph. Then
in each generation, it applies a process named genetic engineering, which constructs a
graph using the gene relationships that are found by rank-2 SVD on several promising
solutions. This spectral technique has high running time and is suitable where the fitness
function is expensive to compute.

Leng et al. (2008) proposed an effective multi-level algorithm for bisecting graph based
on ant colony optimization (ACO) which exploited both the ACO method and the
concept of graph core. During its coarsening phase, an improved matching approach
based on the global information of the graph core was developed with its guidance
function. The vertex gain was exploited as ant’s heuristic information and a positive
feedback method based on pheromone trails was used to find the global approximate
bipartitioning during the refinement phase. The experimental evaluation showed that it
performed well and produced encouraging solutions on 18 different graphs benchmarks
compared with those produced by state of the art partitioner, Metis.

Sun and Leng (2007) presented an effective multi-level algorithm based on simulated
annealing for bisecting graph. The success of the algorithm relied on exploiting both the
simulated annealing procedure and the concept of the graph core. In the multilevel
algorithm the multi-level simulated annealing refinement (MLSAR) algorithm was
adopted during the refinement phase and effective matching-based coarsening scheme
during the coarsening phase that used the core-sorted heavy-edge matching (CSHEM)
algorithm on the original graph and the sorted heavy-edge matching (SHEM) algorithm
on the coarser graphs. The experimental evaluations on 18 different graphs showed that
the algorithm produced encouraging solutions compared with those produced by MeTiS
that was a state-of-the-art partitioner in the literature.

Moraglio et al. (2007) proposed a new geometric crossover for graph partitioning based
on a labelling independent distance that filters out the redundancy of the encoding. They
proposed the method to find the optimal numbering using the Hungarian method a
correlation analysis of the fitness landscape based on this distance showed that it is well
suited to graph partitioning. A new geometric crossover for permutations with repetitions
was designed that naturally suits partition problems and tested it on the graph partitioning
problem. It was then combined with the labelling-independent crossover to obtain a much
superior geometric crossover inheriting both advantages. In extensive experimentation it
was demonstrated that this crossover outperformed previously known methods by either
providing new lower bounds or equalling known best lower bounds in a variety of graph
partitioning benchmark problems.

Coe et al. (2007) investigated the implementation of a Memetic algorithm for VLSI
circuit partitioning on reconfigurable hardware to present a new implementation of a
Memetic algorithm on FPGAs. The implementation of algorithm incorporated a novel
local search methodology for circuit partitioning by exploiting parallelism and pipelining.
The authors found achieved on average 88% of the solution quality and concluded that
the hardware implementation produced significant performance improvements over the
software program. The hardware based local search implementation executed nearly 2.5
times faster than the software producing the same results

Datta et al. (2008) developed a modified form of NSGA-II, a multi-objective

evolutionary algorithm (MOEA) for solving the graph partitioning problem which is
applied to four randomly generated graphs for partitioning them by optimizing three
common objectives under five general constraints. The applications show that the
MOEA is successful, in most of the cases, in achieving the expected results by
partitioning a graph into a variable number of zones

Farshbaf and Derakhshi (2009) firstly modelled the graph partitioning problem, as a
multi-objective optimization problem with constraints. Then a multi-objective GA
method with some modifications to NSGA-II algorithm was proposed to optimize the
graph partitioning. The authors used the Pareto front method to find the suitable curve of
non-dominated solutions, composed of a high number of solutions a simulation research
is carried out to investigate the effectiveness of the proposed algorithm .Finally a
simulation research for the graph partitioning problem on a real distribution system was
conducted. The simulation results confirmed the effectiveness of the proposed multi-
objective GA method.

Armstrong et al. (2010) investigated six different parallel Memetic Algorithms for
solving the circuit-partitioning problem. In each parallel implementation a global shared-
memory to exchange information is used which seeks to reduce runtime by exploiting the
multiple cores available in today's commodity hardware. The empirical results showed
that near-linear speedups for all six MAs can be achieved, at the same time still
producing high-quality solutions, when tested with the widely used ACM/SIGDA
benchmark suite.

Subbaraj et al. (2010), proposed algorithm an efficient hybrid Genetic Algorithm (GA)
incorporating the Taguchi method as a local search mechanism to solve both
bipartitioning and recursive partitioning problems in VLSI design process. The
incorporation of systematic reasoning ability of the Taguchi method after the crossover
operation of GA improved the searching ability of GA. The results of proposed Hybrid
Taguchi Genetic Algorithm (HTGA) tested with fifteen popular bench mark circuits of
ISCAS 89 (International Symposium on Circuit and Systems-89) proved that HTGA is
able to converge faster in reaching the nearer-to-optimal solutions. The result of the
proposed HTGA is compared with that of the standard GA and Tabu Search method and
it was concluded that the proposed HTGA is superior and consistent both in terms of
number of iterations required reaching nearer-to-optimal solution and also the solution
quality.

Peng et al. (2010) proposed a multi-objective discrete PSO (DPSO) algorithm for the
problem of VLSI partitioning. In iterative process of DPSO, two heuristic local search
strategies were incorporated to accelerate the convergence. The main aim of this multi-
objective problem was optimizing the minimum cut and timing performance (delay)
while area balance was taken as a constraint. The fitness function of phenotype sharing
was used to evaluate solution by both pareto dominance and neighborhood density. The
experimental results on ISCAS89 benchmarks were performed for verifying the
feasibility and efficiency of the proposed algorithm. Compared with genetic algorithm
(GA) and Tabu Search (TS) the proposed algorithm obtained more markedly better
solutions for bipartition problem.

Soliman et al. (2010) used a new Similarity carrying Ant Model (SCAM) in the ant-
based clustering algorithm to solve graph partitioning problem. In the proposed model,
the ant was able to collect similar items while it moved around. The flexible template
mechanism was used integrated with the proposed model to obtain the partitioning
constraints which used minimal information about the involved clusters to construct the
full template. Random graph was used to compare the new model with the original ant
model and the model with short-term memory. The result of the experiments proved the
impact of the SCAM compared with other models. The model was capable of achieving
excellent results in acceptable computing time. The F-measure and ARI metrics
demonstrated the performance enhancement that the new model was able to get compared
with original model and its memory feature modification. The integration of new model
and template allowed the proposed algorithm to realize separated and balanced portions
for the graph in practical computation time.

Chen and Wang (2011), proposed an efficient genetic algorithm to solve m-way graph
partitioning problem. The proposed method searches a large solution space and finds the
best possible solution by adjusting the intensification and diversification automatically
during the optimization process. The method is tested on a large number of instances and
compared with some existing algorithms. The results showed that the proposed algorithm
is superior to its competitors in terms of computation time and solution quality

Galinier et al. (2011) presented a new memetic algorithm named MAGP (Memetic
Algorithm for Graph Partitioning) for the solution of the graph partitioning problem
which used both a tabu operator and a specialized crossover operator. The algorithm used
a very simple population management technique, a tabu search operator and a specially
designed crossover operator to deal with partitions and no mutation operator. The
crossover operator was based on the optimal matching between two partitions. The
algorithm was tested by using the benchmarks of the graph partitioning archive. The
experiments showed obtained remarkable results on the tested instances and the
algorithm outperformed state of the art algorithms proposed.

Kim et al.(2011) discussed a number of problem specific issues in applying genetic

algorithms to the graph partitioning problem These issues included the main topics of
GAs such as representation, crossover, normalization, constraint handling, local
optimization, and hybridization. The authors concluded that as the requirement for
algorithms that manage huge graphs is increasing, traditional GAs cannot manage it
effectively. There is a need to design novel genetic operators tailored for huge graphs.

Kurejchik and Kazharov (2012) presented that the block diagram of swarm intelligence
can be described as a graph or hypergraph, generally consisting of a set of agents
interacting locally with the environment. The agents themselves are usually quite simple,
but they all together, interact locally, creating so called "swarming intelligence." The
authors analyzed and studied algorithms for swarm intelligence to solve the problem
layout blocks EVA planning of VLSI. Experimental studies showed the effectiveness of
the swarms of algorithms for solving optimization problems compared to standard,
heuristic, iterative and genetic algorithms.

Lee et al. (2012) proposed a new circuit bipartitioning algorithm based on a novel
Memetic Quantum-Inspired Evolutionary Algorithm (MQEA) framework. The key idea
is to perform global search with QEA and local search with the FM algorithm to improve
its local tuning capability. The authors used the Fiduccia- Mattheyses (FM) algorithm for
the local optimization, and modified the operator of QEA called Q-gate to apply this to
QEA. Experimental results show that the proposed MQEA algorithm achieves significant
improvement of quality over the conventional FM algorithm or QEA. To alleviate the
slowdown caused by executing local search algorithm and QEA together, the memetic
QEA was parallelized. With 8 threads in parallel, the speed of the algorithm was
improved on average by 2.5 times and up to 3.35 times.
Shanavas & Gnanamurthy (2012) proposed a memetic algorithm which hybrids two
algorithms like Genetic Algorithm and Simulated Annealing to solve the graph
partitioning and floorplanning problem. It addresses the problem of VLSI netlist
partitioning with the objective of reducing delay and then floorplanning with the
objective of reducing area to minimize the wirelength. The algorithm incorporates several
genetic algorithm characteristics, namely, selecting a population and crossover of the
selected chromosomes to get better stable solutions. The algorithm begins by
incorporating the circuit as un weighted connected graph and thereafter applying the
Genetic algorithm metaphor to generate a partition that is highly interconnected within
but disconnected from other sub partitions while trying to minimize the number of cuts
and time consumed. After a predetermined number of iteration by Genetic algorithm,
local search is applied to few random individual to get the optimal solution by Simulated
Annealing. The results showed the advantage of memetic algorithm which is 45% faster
than the simple genetic algorithm by reducing the delay and area in partitioning and
floorplanning respectively.

2.5 Gaps in Literature Survey

Graph layout problems are a particular class of combinatorial optimization problems
whose goal is to find a linear layout of an input graph in such way that a certain objective
function is optimized. A linear layout is a classification of the vertices of a graph with
distinct integers. A large amount of relevant problems indecent domains can be
formulated as graph layout problems. These include optimization of networks for parallel
computer architectures, numerical analysis, VLSI circuit design, information retrieval,
graph theory, computational biology, scheduling and archaeology. Moreover, the minimal
values of some layout costs are also related to interesting graph theoretic invariants of
graphs. Most interesting graph layout problems are NP-hard and their decisional versions
NP-complete, but for the majority of their applications, the feasible solutions with an
almost optimal cost are sufficient. As a consequence, approximation algorithms and
effective heuristics are preferred in practice.
The complexity and size of digital circuits have grown exponentially. Now a today's
circuits can contain millions of logic elements. Evolutionary algorithms have become
popular due to their ability to reduce circuit sizes. The method of clustering enables
circuit layout design problems, such as circuit partitioning and placement to be performed
faster and with higher quality. Current conventional algorithms and the effect of these
algorithms on industry test benchmarks are studied during literature survey. It is revealed
that the evolutionary algorithms are the most successful clustering techniques for circuit
layout design and deserve more future research investigations.

There is a tremendous interest in the development of the theory and applications

of evolutionary computing techniques both in industry and universities. These algorithms
are used successfully in many applications requiring the optimization of a certain
multidimensional function. The population of possible solutions evolves from one
generation to the next, eventually arriving at a satisfactory solution to the problem. The
difference in these algorithms is in the way a new population is generated from the
present one and in the way the members are represented within the algorithm.

Since the general graph partitioning problem is NP-complete, approximate methods

constitute a natural and useful approach to address this problem. In the past several
decades, this problem inspired a great number of methods and heuristics such as greedy
algorithms, spectral methods, multilevel approaches, as well as algorithms based on well-
known metaheuristics like tabu search, ant colony, simulated annealing, genetic and
memetic algorithms. Iterative improvement methods produce high quality partitions, but
excessive computation time is required to do so. On the other hand, constructive methods
yield not as high quality partitions as iterative improvement methods, yet good, in a much
shorter time. Ideally, both quality and computational efficiency of the solution are crucial
for a practical partition method. Quality of solution is important for performance of the
circuit and computational efficiency is essential for curtailing the design procedure,
especially for large circuits where weeks, months or even years may be required to
realize these circuits. Another factor that has to be considered when designing an
appropriate partitioning algorithm is the partition balance. While some applications
require partitions of perfect balance, others tolerate imbalance up to a certain degree in
order to achieve a partition of better cut size. The fact that future partition and routing
tasks will be much more complicated due to the increasing size of the circuits and the
growing design objectives implies that faster partition and routing tools should be
developed to handle such immense complexity.

Table 2.1: Summary of Literature on Role of Major contributors in Digital circuit

layout problem based on graph partitioning technique and their Analysis
References Topics covered Comments/Analysis
B. W. Kernighan KL heuristic for graph Complexity of the algorithm too high even for moderate
and S. Lin,(1970) bipartitioning size problems
D. G. Schweikert Hypergraph model in The performance of the Kernighan–Lin algorithm
and B. W. the Kernighan–Lin largely depends on the quality of the bisection that it
Kernighan,(1972) partitioning heuristic starts with.
Produce poor partitions for larger hypergraphs
L.Hagen,D. FM algorithm -vertices FM algorithm was able to provide satisfactory solutions
J.H.Huang, and A. removed and inserted only for smaller to medium size problems
B.Kahng,(1997)
from the bucket list F-M produce poor partitions for larger hypergraphs
using a last-in-first-out depends on the quality of the initial partitions that it
(LIFO) scheme starts with
B. Krishnamurty, Extended FM algorithm
(1984) -Krishnamurthy’s look-
ahead scheme for
circuit bipartitioning
L. A. Sanchis,(1989) Sanchis extends the FM Better quality than KL, FM but at the expense of
concept to deal with increased runtime
multiway partitioning.
Johnson et al. Simulated annealing for Smaller netcuts than iterative methods, albeit with much
(1989) graph partitioning greater runtimes
S.W. Hadley et al. Generate initial The approach requires transformation of every multi-
(1992) partitions is based on terminal net into two terminal nets which could result in
eigen vector a loss of information needed for a performance based
decomposition partitioning
 Bultan and Meanfield annealing for Greater runtimes
Aykanat (1995) multi way partitioning
algorithm
Cong.J, W.labio k-way net based multi Produce better quality solutions than the FM algorithm
and N.Sivakumar, way partitioning but only for smaller size problems.
(1994) algorithm
Yang and Maximum flow problem There is no constraint on the sizes of the resulting
Wong,(1996) subsets.
G. Karypis Multilevel Clustering Poor flexibility, objective functions for clustering are
et.al.(1999) approach-hMetis difficult to formulate, the approach is less efficient with
larger size integrated circuits.
Cherng and Based on the Multilevel
Chen,(2003) flat partitioning
Drechsler et al. Recursive partitioning Increasing recursion depth more run time is invested.
(2003)
Mardhana et.al. Results depend on moves generated by a neural network.
(2003).

Physical design problems are generally combinatorial in nature and have very large
problem sizes, thus necessitating the use of heuristics such as evolutionary algorithms.
The Table 2.1 and 2.2 summarizes various approaches for Digital circuit layout problem
based on graph partitioning technique and various evolutionary approaches for graph
partitioning technique along with their analysis.

Table 2.2 : Summary of Literature on Evolutionary approaches for graph

partitioning technique and their Analysis
References Sub topics covered References Sub topics covered
Ackley (1987) GA for min cut bisection Sait. Et.al (2006) Metaheuristic algorithms
problem based on Genetic Algorithm
(GA) and Tabu search (TS)
Chatterjee and An SA-based heuristic which Sun and Leng An effective multi-level
Hartley (1990) performed partitioning and (2007) algorithm based on simulated
placement simultaneously. annealing for bisecting graph.
Saab and Rao A simulated evolution Moraglio et al. A new geometric crossover for
(1990) bisection heuristic which has (2007) graph partitioning based on a
no crossover operator labelling-independent distance
that filters out the redundancy
of the encoding.
Chandrasekharam A stochastic search by a Coe et al. (2007) Investigated the
et. al. (1993) genetic algorithm (GA). implementation of a Memetic
algorithm for VLSI circuit
partitioning by exploiting
parallelism and pipelining
Areibi and A combined Tabu Search and Datta et al. A multi-objective evolutionary
Vannelli (1994) Genetic Algorithm for (2008) algorithm (MOEA) for solving
hypergraph partitioning the graph partitioning problem
problem.
Majhi et al. (1995) The GA approach. Leng et al. Proposed an effective multi-
(2008) level algorithm for bisecting
graph based on ant colony
Alpert et al. (1996) Integrated the Metis into a Farshbaf and A multi-objective GA method
genetic algorithm for graph Derakhshi to optimize the graph
partitioning (2009) partitioning.
Langham and Ant Foraging Strategy (AFS) Armstrong et al. Six different parallel Memetic
Grant (1999) for graph partitioning. (2010) Algorithms for solving the
circuit partitioning problem.
Merz and A memetic algorithm for graph Subbaraj et al. Efficient hybrid Genetic
Freisleben (2000) bipartitioning problem (2010) Algorithm (GA) incorporating
the Taguchi method as a local
search mechanism to solve
both bipartitioning and
recursive partitioning.
Kim and Moon A hybrid genetic algorithm for Peng et al. A multi-objective discrete
(2001) multiway graph partitioning (2010) PSO (DPSO) algorithm for
VLSI partitioning
Cincotti et al. An order-based encoding to Soliman et al. Ant Model (SCAM) to solve
(2002) evaluate a partitioning of (2010) graph partitioning problem.
vertices represented by this
encoding, a decoding process
is required. Its decoding
process takes a long time.
 Muhlenbein and presented a theory of Chen and Wang An efficient genetic algorithm
Mahnig (2002) population based optimization (2011) to solve m-way graph
methods using approximations partitioning problem.
Kohmoto et al. incorporated a simple local Galinier et al. Memetic algorithm, used both
(2003) search algorithm into the GA. (2011) a tabu operator and a
specialized crossover operator
Kim et al. (2004) a combination of a genetic Kim et al.(2011) Discussed a number of
algorithm with an FM-based problem-specific issues in
heuristic for hypergraph applying genetic algorithms to
bipartitioning. the graph partitioning problem
Kucukpetek et A genetic algorithm for the Kurejchik and The block diagram of swarm
al. (2005) coarsening phase of a Kazharov (2012) intelligence described as a
multilevel scheme for graph graph or hypergraph
partitioning. It improves the
solution quality at the expense
of running time.
Ganesh et al. A swarm intelligence based Lee et al. (2012) A novel Memetic Quantum-
(2006) approach to the circuit- Inspired Evolutionary
partitioning problem Algorithm (MQEA)
framework.
Martin (2006) Proposed GAs technique as the Shanavas & A memetic algorithm which
singular value decomposition Gnanamurthy hybrids Genetic Algorithm
(2012)
(SVD), This spectral technique and Simulated Annealing to
has high running time and is solve the graph partitioning
suitable where the fitness
function is expensive to
compute.

Several formulations of the partitioning problem are known to be NP-complete (Perl and
Snir, 1983). As a result, a variety of heuristic algorithms for partitioning have been
proposed in literature, which aim at finding near optimal solutions in a reasonable
computation time. After the thorough analysis of the related literature, the following gaps
are identified.

 It is found that the traditional heuristic methods for solving circuit partitioning problem
either consume vast amount of computation time or provide inferior quality of
solutions due to local convergence of solutions.
 The literature survey reveals that many of the existing evolutionary approaches for
solving circuit partitioning problem are compared with state of the art algorithms in
terms of solution quality only. However in the area of VLSI design, the running time is
also an important factor to be considered. Therefore the proposed approach should be
compared with the state of the art algorithms both in terms of solution quality and
runtime.

 During the comparative analysis of the algorithmic approaches, the constraints on the
algorithms have not been taken into account. For example in the routing problem, the
evolutionary algorithm which is expressed only in terms of number of vias is compared
with the other approaches that minimize the net length concurrently (Geraci et al.,
1991).

 There are a large number of CAD tools in VLSI design; benchmarks data are available
for all major design steps, eg. [EDA Benchmarks (1997)]. The literature survey
revealed that the most of evolutionary approaches developed for VLSI design are not
tested with the appropriate benchmarks which reflect large, real world VLSI design
problems.

 Major work in literature has been focused on using genetic algorithm for circuit
partitioning. Less attention has been paid on rest of evolutionary approaches.

 Many of the existing approaches don’t incorporate statistical analyses (e.g., significance
tests) of the results which are necessary to evaluate the significance of solution quality
variation in diverse circumstances (Brglez, 1998).

2.6 Objectives of Study

The literature survey reveals that the evolutionary techniques can be applied in the
current work for developing the Graph Partitioning algorithm. Partitioning efficiency can
be enhanced within three broad parameters.
a) The system must be decomposed carefully so that the original functionality of the
system remains intact.

b) An interface specification is generated during the decomposition, which is further

used to connect all the subsystems. The system decomposition should guarantee
minimization of the interface interconnection between any two subsystems.

c) Finally, the decomposition process should be simple and efficient so that the time
required for the decomposition is a small fraction of the total design time.

Keeping in view the advantages of evolutionary approaches for the solving complex
combinatorial optimization problems, a research study with the title “DEVELOPMENT
OF AN ALGORITHM USING EVOLUTIONARY APPROACH FOR DIGITAL
CIRCUIT LAYOUT BASED ON GRAPH PARTITIONING TECHINQUE” was
envisaged with the following objectives.

 Transformation of graph partitions into problem domain.

 Development of an algorithm using evolutionary approach.

 Evaluation of developed algorithm by taking number of iterations, memory

requirements and minimum cuts during computation.

 To verify the algorithm by comparing with existing approaches.

2.7 Scope of Study

Following are the Scope of study related to research problem under investigation.

 The sample of problem under consideration will be taken only using VLSI
Benchmark Circuits, not other digital circuits.
  The work will be carried out on Chip Level Partitioning.

 Simulation will be done on bi-partitioning of digital circuits which doesn’t

include the use of multiple partitions

 The developed algorithm will be applied on partition of combinational circuits.

Due to circuit feedback and memory requirements, it is not possible to use the
thesis work on sequential circuits.

 Due to the inclusion of evolutionary computation, the search process will be

based on probabilistic rules, following a certain stochastic law, leading to the
optimal solution in the sense of probability.

2.8 Summary of Chapter

The chapter presents a detailed review of literature related to the techniques and tools
used to predict the graph partitioning and evolutionary algorithms. It outlines the basic
inspiration for choosing the topic, graph partitioning related preliminary work and use of
evolutionary approaches for digital circuit layouts. Various existing gaps in literature
regarding the digital circuit layouts and significance of evolutionary approaches are
identified so that they can be used in VLSI and FPGA circuit partitions. The objectives
based on the research gaps are envisaged and scope of the study is defined.

Paper Published
Maninder Kaur, Kawaljeet Singh, Solving Digital Circuit Layout Problem based on
Graph Partitioning Technique: A Glance. IRACST – Engineering Science and
Technology: An International Journal (ESTIJ), ISSN: 2250-3498, Vol.2, No. 6, June
2013, pp 2200-2204.