IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO.

3, MARCH 2010 153

A Brief Introduction to Time-to-Digital and

Digital-to-Time Converters
Gordon W. Roberts, Fellow, IEEE, and Mohammad Ali-Bakhshian

Abstract—This paper presents a short review of time-to-digital

and digital-to-time converters (TDCs and DTCs, respectively)
adopting a time-mode signal-processing perspective. The primary
definitions, operating principles, and basic building blocks are
presented. The discussion applies to most, if not all, DTCs and
TDCs. A series of voltage-controlled delay units are used as the
primary building block of these converter circuits. When con-
figured in a servo-loop manner, a very short time resolution is
achievable with excellent manufacturing robustness. Such designs
can be synthesized in field-programmable gate arrays (FPGAs) Fig. 1. Adopting TMSP for analog and digital processing.
or constructed in custom silicon. TDCs and DTCs are not new,
as they have extensively been used for making very accurate and
repeatable time measurements in both the physics-related and the design gap between analog and digital design, which is a
semiconductor industry. Today, TDCs and DTCs are finding new very important issue facing the analog design community.
applications in phase-locked loops and frequency synthesizers. Since most analog information begins in the form of a
Index Terms—Data converters, digital, digital-to-time convert- voltage, a voltage-to-time converter (VTC) is employed to
ers (DTCs), reconfigurable circuits, time-mode signal processing convert the input signal into a time-difference variable. The
(TMSP), time-to-digital converters (TDCs). time signal is then processed by various circuits resulting in
a time-difference output. The time-mode signal can then be
I. I NTRODUCTION converted back to a voltage signal using a time-to-voltage
URING the past decades, CMOS process has become converter (TVC). Conversely, we can also envision information
D dominant due to its level of integration, ease of design,
and low cost of fabrication. As emerging CMOS technologies
beginning in the form of a digital signal, whereby a digital-
to-time converter (DTC) is employed to convert a digital sig-
are typically optimized for the needs of digital circuitry, the fea- nal into a time-difference variable and after some time-mode
ture size dimensions are being reduced to increase the packing processing converted back into digital form using a time-to-
density and to reach higher levels of integration; however, the digital converter (TDC). We illustrate these two situations with
reduction in transistor gate-oxide thickness forces the system the block diagrams shown in Fig. 1.
voltage to decrease, making analog design difficult to do. This is TMSP is used for a wide range of applications in differ-
largely a result of poor bias point operation, large gate leakage, ent domains, such as nuclear science for Positron Emission
reduced input voltage swings, and linearity problems. Topography (PTE) imaging [2], instrumentation for digital stor-
In order to offset some of the design challenges imposed age oscilloscopes, and radio-frequency transmitters for digital
by digitally driven deep-submicrometer CMOS processes, we phase-locked loops (PLLs) [3]. In this paper, the basic concepts
are seeing the development of time-based or time-mode signal and the most popular topologies of TDCs and DTCs will be
processing (TMSP) [1]. TMSP is a novel approach to ma- reviewed.
nipulate and process analog sample information using digital This paper is organized as follows. In Section II, TMSP is
blocks. Adopting this methodology, where conventional volt- briefly described, and basic building blocks are reviewed. The
age and current variables are replaced by corresponding time most frequently implemented topologies for data conversion
differences between two rising edges as the time variables, logic from digital-to-time and time-to-digital domains are listed in
circuits can substitute for the large-sized and power-hungry Sections III and IV summarizes this paper.
analog blocks. Moreover, adopting digital elements as the basis
of the analog circuit enables digital synthesis and test methods II. TMSP
to be used. This fact is an important step forward in bridging
TMSP can be defined as detection, storage, and manipulation
of sampled analog information using time-difference variables.
Manuscript received December 17, 2009. Current version published It provides a means to implement analog signal-processing
March 17, 2010. This work was supported in part by the Canadian Micro-
electronics Corporation. This paper was recommended by Associate Editor functions in any technology using the most basic element avail-
T. C. Carusone and U.-K. Moon. able, i.e., propagation delay. A time-difference variable ∆T
The authors are with the Department of Electrical and Computer Engineer- is defined as the quantity of time between an event occurring
ing, McGill University, Montreal, QC H3A 2A7, Canada (e-mails: gordon.
roberts@mcgill.ca; mohammad.alibakhshian@mcgill.ca). with respect to a reference time or event. The delay may be
Digital Object Identifier 10.1109/TCSII.2010.2043382 produced by either an arbitrary series of delay blocks, such
1549-7747/$26.00 © 2010 IEEE

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154 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 3, MARCH 2010

Fig. 5. (a) Voltage-to-time integrator. (b) Timing diagram for the integrator.
Fig. 2. (a) Reconfigurable arbitrary set of delay elements to implement a
desired delay. (b) VCDU CMOS schematic.
Defining the output of the differential VTC as ∆TO , i.e.,
the time difference measured with respect to the reference time
tREF , we subtract (4) from (3) and write

∆TO = tO − tREF = Gφ (νIN − VREF ). (5)

For a voltage-to-time adder configuration, the input to one of

the VCDUs is an input clock, and the other is a reference signal.
Equations (3) and (4) can then be written as

Fig. 3. (a) Symbolic input/output signals of a VCDU. (b) Symbolic input-to-

tO = tIN + Gφ νIN + bφ (6)
output delay time in terms of the input voltage.
tREF = tClk + Gφ VREF + bφ . (7)

The time difference between the two output signals will be

related to the time difference between the input signals as

∆TO = tIN −tClk + Gφ (νIN −VREF ) = ∆TIN + Gφ ∆VIN . (8)

By connecting the output of an adder to its input through

an inverter, the voltage-to-time integration can be implemented
by configuring two ring oscillators, as shown in Fig. 5(a).
The frequency difference between the signal oscillator (top) and
Fig. 4. (a) VTC. (b) Voltage-to-time adder block diagrams.
the reference one (bottom), due to VIN (n), is integrated into the
as those shown in Fig. 2(a), or a voltage-controlled delay unit phase difference between the two outputs of the oscillators, as
(VCDU) [1], as shown in Fig. 2(b). Upon arrival of any falling shown in Fig. 5(b).
edge at ΦIN , the inherent capacitor is charged to VDD; during A comparison of two time-mode variables can easily be
high signal at ΦIN , the VIN controls the discharge current of performed by a D-type edge-triggered flip-flop. If the edge
the embedded capacitor and, therefore, the time for the output of ΦIN , which is connected to the D-input, is leading ΦREF
rising edge in Fig. 3(a) to occur as follows: connected to the clock input, then the output Q is a logic 1, and
if the edge of ΦIN is lagging ΦREF , then the output is a logic 0.
tO = tI + Gφ νIN + bφ (1) By rearranging the aforementioned basic building blocks,
different analog applications can be developed. A system based
where Gφ and bφ are the slope and the y-intercept of a line on the error-feedback structure for a ∆Σ modulator might
drawn through the linear region of the VCDU transfer charac- be designed by adopting TMSP. The complete system of the
teristic shown in Fig. 3(b). Rearranging (1), we can express the TM∆Σ modulator is presented in Fig. 6, and it consists of
VCDU input–output delay behavior or time difference as two dual-input integrators, some inverters, and a D-type edge-
triggered flip-flop. The reference oscillator, i.e., the bottom
∆TO,I = tO − tI = Gφ νIN + bφ . (2) dual-input integrator, provides the clock reference φREF [n]
generating the analog time reference with the secondary func-
As shown in Fig. 4(a) and (b), the combination of two tion of clocking the data out of the D-type flip-flop. The signal
VCDUs might be used as a VTC or a voltage-to-time adder, oscillator, i.e., the top integrator, sums the input voltage with
respectively. Mathematically, for a VTC configuration, we can the inverse of the digital output voltage, and the output flip-flop
write the output equations as determines the polarity of the phase output of the integrator to
provide the proper feedback to the oscillators. The promising
tO = tClk + Gφ νIN + bφ (3)
performance of this modulator and its superior advantage re-
tREF = tClk + Gφ VREF + bφ . (4) garding the area and power is reported in [1].

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ROBERTS AND ALI-BAKHSHIAN: BRIEF INTRODUCTION TO TIME-TO-DIGITAL AND DIGITAL-TO-TIME CONVERTERS 155

Fig. 6. First-order single-bit Σ∆ time-mode delta-sigma modulator.

Fig. 8. (a) Block diagram for a DTC adopting a DLL. (b) Signal waveform of
the internal nodes of a DLL.

of delays, each node presents the input clock delayed by a

determined portion of the clock period, as shown in Fig. 8(b).
DLLs have widely been used as clock de-skewing circuits
Fig. 7. DTC symbol and the signal waveforms for both pulse-based and edge-
based outputs due to the prespecified digital inputs. in high-speed serial transceivers, interchip communication in-
terfaces, and clock distribution networks to improve overall
III. DATA C ONVERSION system timing. Although these functions can also be performed
with PLLs, DLLs are often preferred due to their ease of
Data conversion is simply the process of moving between design, better immunity to on-chip noise, and stability. A DLL
different number domains, typically involving integers and real incorporated with a digital multiplexer, such as that shown in
numbers. The following will describe several time-mode data Fig. 8(b), results in a simple but effective DTC. Here, a 3-bit
conversion techniques. digital input selects one out of the eight delayed versions of the
input clock. Since the delay is controlled through a feedback
loop locked to clock reference with a precise period, subclock
A. DTC timing resolution is achieved.
A DTC takes a digital input and converts it to the form of 2) Band-Limiting DTC Output: The digital input informa-
a time instant, i.e., a pulse in a specific time slot. It might tion fed to the DTC will be embedded into the phase of the
be considered equivalent to a phase-modulated (PM) signal, as output PM signal. To smooth the discrete output and limit the
shown in Fig. 7. The phase difference between the output pulse phase spectrum to exclude the unwanted frequencies created by
and the clock signal will be the analog equivalent of the input the reconstruction process, inherent in any data conversion, the
digital code. (For example, the digital representation for the output of the DTC needs to be band limited. One method that
integer value of 4 would correspond to the fifth out of the eight is often used is through the application of a PLL, as shown in
possible time slots, as shown in Fig. 7.) As sequential logic is Fig. 9(a).
edge based, we can replace the pulse with an edge placement as By adopting PLLs as band-limiting blocks in TMSP, the
shown in the same figure. concept of sigma-delta modulation has been extended to a TDC
1) DLL: A delay-locked loop (DLL) is a servomechanism with a PLL [6], as shown in Fig. 9(b).
in which a path of VCDUs is adjusted in order to produce
a desired phase relationship between two signals [4], [5]. As
B. TDC
shown in Fig. 8(a), a chain of delays is used to delay the input
clock signal. The delayed signal is compared with itself, and A TDC is responsible for converting a time interval between
the phase difference is extracted. The phase detector output is two clock edges into a digital number. As with all sampling
used to control the input voltage of the VCDUs in the delay processes, the continuous time signal must be band limited to
chain through a negative feedback loop. Regarding the number prevent aliasing effects. To band limit the PM input signal, one

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156 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 3, MARCH 2010

Fig. 9. (a) Band-limiting DTC output. (b) Extending the Σ∆ concept to DTC.

Fig. 12. Block diagram for a flash TDC.

Fig. 10. Process of time-to-digital conversion including anti-aliasing filtering.

Fig. 11. Single-counter TDC.

method is through the application of a PLL (see Fig. 10), as

explained in the previous section.
A TDC can be realized with time comparators (D flip-
flops) and other digital blocks, as described in the succeeding
sections.
1) Single Counter: The simplest of the TDC architectures is
that shown in Fig. 11. In this converter, the input time interval
∆T between the rising edges of a start and a stop pulse is Fig. 13. (a) Fine-resolution flash TDC adopting DLL. (b) Refining the time
measured by a counter running on a high-frequency reference resolution by adopting Vernier delay line.
clock. The AND gate ensures that the counter is enabled only
when Start and Stop are logically different. The resolution ∆T , assuming that the flip-flops are given sufficient time to
of this device is constrained by the speed of the reference settle. The drawback to this implementation is that the temporal
clock and can be no higher than a single clock period. The resolution can be no higher than the delay through a single
constraints on the frequency and stability of on-chip clocks gate in the semiconductor technology used. To achieve subgate
limit the application of this architecture. temporal resolution, the flash converter can be constructed
2) Flash TDC: Flash TDCs are analogous to flash ADCs with a Vernier delay line [8], as shown in Fig. 13(b). This
for voltage amplitude encoding and operate by comparing a architecture achieves a resolution of τ1 − τ2 , where τ1 > τ2 .
signal edge with respect to various reference edges all displaced Again, two individual DLLs should be implemented for each
in time. The elements that compare the input signal to the delay chain to make them reasonably accurate.
reference are usually D-type flip-flops. In the single VCDU Flash TDCs are well suited for use in on-chip timing mea-
chain flash TDC shown in Fig. 12, each buffer produces a delay surement systems, because they are capable of performing a
equal to τ . To ensure that τ is known reasonably accurately, the measurement on every clock cycle and can be operated at rela-
delay chain is often implemented and stabilized by a DLL [7] tively high speeds. In addition, they can easily be constructed in
[as shown in Fig. 13(a)]. any standard CMOS process, because they are composed solely
To determine the time difference ∆T between the rising of digital components.
edges of pulses Input and Ref Clock by the eight-level delay 3) Vernier Oscillator: A component-invariant Vernier oscil-
chain converter in Fig. 12, each flip-flop compares the displace- lator TDC with phase detector shown in Fig. 14 is composed
ment in time of the delayed Ref Clock to that of the Input of two ring oscillators producing plesichronous square waves
signal. The thermometer-encoded output indicates the value of to quantize a time interval based on a very small frequency

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ROBERTS AND ALI-BAKHSHIAN: BRIEF INTRODUCTION TO TIME-TO-DIGITAL AND DIGITAL-TO-TIME CONVERTERS 157

Mathematically, we can write a difference equation of system

behavior as

WOUT [n] = α × WOUT [n − 1] (9)

where WOUT [0] = WIN . The general solution can then be

found as follows:

WOUT [n] = αn × WIN . (10)

The output counter counts until the final pulsewidth violates

Fig. 14. Block diagram for a Vernier oscillator TDC.
the hold time of the counter; thus, the number counted by the
counter will be a representative of the input pulsewidth. Similar
to the Vernier oscillator, there is a long conversion time required
for the cyclic pulse-shrinking TDC.

IV. S UMMARY
This paper has briefly summarized some of the developments
Fig. 15. Block diagram for a cyclic pulse-shrinking TDC.
happening in the field of time-based or time-mode data con-
version. The field has slowly been developing for more than
difference between the two oscillators; this difference is due to
30 years now but has found renewed interest as IC designers
the different delays introduced by the VCDU in each oscillator
looking for new ways to construct analog circuits in fine-line
[9]. The Start and Stop pulses enable the oscillators. The phase
CMOS processes.
detector and counter measure the time difference between these
two signals by detecting the instant one edge catches up with
the other. Due to its small size and relatively high temporal R EFERENCES
resolution, the Vernier oscillator is amenable for use in on-chip [1] C. S. Taillefer and G. W. Roberts, “Delta–Sigma A/D conversion via
time-mode signal processing,” IEEE Trans. Circuits Syst. I, Reg. Papers,
test systems. Phase locking the delay elements using a DLL vol. 56, no. 9, pp. 1908–1920, Sep. 2009.
can correct for any process variations and temperature effects [2] B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle,
in the delay of VCDUS and VCDUF . In addition, the use of E. Breeding, and K. M. Baldwin, “100-ps time-resolution CMOS time-to-
digital converter for positron emission tomography imaging applications,”
the oscillators reduces the matching requirements on the delay IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1839–1852, Nov. 2004.
buffers used to quantize a time interval. This feature is used [3] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A wide power supply
to overcome the temporal uncertainties caused by component range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,”
IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42–51, Jan. 2008.
variation in the delay lines of Vernier delay flash TDCs. [4] M.-J. E. Lee, W. J. Dally, T. Greer, R. Farjad-Rad, J. Poulton, and
One negative aspect of this architecture, however, is that it R. Senthinathan, “Jitter transfer characteristics of delay-locked loops—
takes many cycles to complete a single measurement (i.e., has a Theories and design techniques,” IEEE J. Solid-State Circuits, vol. 38,
no. 4, pp. 614–621, Apr. 2003.
long dead time). Compared to flash converters that can make a [5] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on
measurement every cycle, the Vernier oscillator requires a long self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11,
conversion time. pp. 1723–1732, Nov. 1996.
[6] B. R. Veillette and G. W. Roberts, “High frequency sinusoidal genera-
4) Cyclic Pulse-Shrinking TDC: Through the application of tion using delta-sigma modulation techniques,” in Proc. IEEE Int. Symp.
a time attenuator or pulse-shrinking circuit in a feedback loop, Circuits Syst., May 1995, vol. 1, pp. 637–640.
a TDC can be created [10] (Fig. 15). An input pulse of width [7] D. M. Santos, S. F. Dow, and M. E. Levi, “A CMOS delay locked loop
and sub-nanosecond time-to-digital converter chip,” in Proc. IEEE Nucl.
WIN is reduced as it propagates around the feedback loop by Sci. Symp., Med. Imaging Conf. Rec., Oct. 1995, vol. 1, pp. 289–291.
some scale factor α; eventually, the pulsewidth disappears. As [8] P. Dudek, S. Szczepanski, and J. V. Hatfield, “A high-resolution CMOS
the rising edge of the pulse reaches a counter, a count is made time-to-digital converter utilizing a Vernier delay line,” IEEE J. Solid-
State Circuits, vol. 35, no. 2, pp. 240–247, Feb. 2000.
until the pulse disappears, i.e., undetectable. The inverter chain [9] A. H. Chan and G. W. Roberts, “A jitter characterization system using a
is used to set the feedback delay to be longer than the pulse component-invariant Vernier delay line,” IEEE Trans. Very Large Scale
duration, so that the pulse-shrinking element operates on only Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004.
[10] P. Chen, S. I. Liu, and J. Wu, “A CMOS pulse-shrinking delay element for
one signal at a time (i.e., the input on the first cycle and the time interval measurement,” IEEE Trans. Circuits Syst. II, Analog Digit.
feedback signal on all other cycles). Signal Process., vol. 47, no. 9, pp. 954–958, Sep. 2000.

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