7/1/2019 Creating Power-Switch Arrays and Rings

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Performing Power Planning > Power Switch Overview

Creating Power-Switch Arrays and Rings

As process technology continues to scale to smaller and smaller geometries, the leakage current of CMOS devices
increases exponentially. An effective method of controlling leakage power is to use multithreshold-CMOS
technology with shutdown transistors. The following sections illustrate the use of multithreshold-CMOS and power
gating to reduce leakage power in CMOS designs. The following sections describe the implementation of a
power-switch network in a multivoltage design.

Power Switch Overview

Selecting the Proper Power-Switch Strategy

Creating a Power-Switch Array

Creating a Power-Switch Ring

Exploring Different Switch Configurations

Optimizing Power Switches

Connecting Power Switches

Power Switch Overview

You can implement power switching in your design during floorplanning to reduce static leakage power to idle
circuit blocks. Power switching is a technique that reduces leakage power by cutting the flow of current between
VDD and VSS while the circuit block is idle. There are two types of power switches: header switches and footer
switches. Header switches with PMOS transistors are placed between VDD and the block power supply pins;
footer switches with NMOS transistors are placed between VSS and the block ground pins. In many designs, only
one type of switch is used. Switch cells are encapsulated within standard cells.

Figure 32 Power-Switching Network Transistors

The switching strategy shown in Figure 32 is a coarse-grain strategy; this strategy applies power switching to
the entire block through a single control. Multiple transistors in parallel drive a common supply net for the block.
In a fine-grain strategy, each library cell has its own power switch, allowing fine-grain control over which cells are
powered down. The fine-grain approach has better potential for power savings, but requires more area.

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Figure 33 shows the layout view of the power-switch array used to shut down power to a circuit block. The
power-switch network controls the current flow from the permanent power network to the virtual power network.
Permanent power is a constant supply that originates from the top-level circuit pads and virtual power is switched
by the power switch.

Figure 33 Power Switch and Power Rails

Selecting the Proper Power-Switch Strategy

Although power gating uses relatively large power-switch cells, the actual current available to the switched power
network might be less than that available on the permanent power supply rails. The current reduction depends on
the dynamic power requirements of the shutdown block, the size of the voltage area, and the number of
power-switch cells. The physical placement of the power-switch cells is critical to achieve an acceptable IR
distribution within the shutdown block.

Two primary placement styles are used when placing power-switch cells: array-style placement and ring-style
placement. In the array-style approach, cells are placed in a uniform grid within the voltage area. Array-style
placement provides high drive current and minimizes resistance, which in turn affects IR drop. The benefits of an
array-style placement include

Greater control over IR drop distribution

Better optimization that allows for fewer gating cells than the ring-style method

The shortcomings of the array-style approach include

Less available cell placement area

More difficult or impossible implementation with hard macros, as the existing placement must be modified
to accommodate power gates inside the voltage area

Potentially more congestion or increase in area

Potentially greater power grid complexity

In a ring-style approach, the tool places power-switch cells in a ring that surrounds the shutdown voltage area.
The benefits of a ring-style placement include:

Easier power grid creation for the block

Easier application to designs that contain hard macros, without the need for modification inside the block.
No extra cells or routing is required, with the exception of support for retention, isolation, level shifting, and
always-on logic.

Easier connection of power and daisy chains by using abutment

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A major limitation of the ring-style approach is that the IR drop impact might be unacceptable toward the center
of the voltage area as the distance increases from the power-switch cells. The severity of the IR drop depends on
the voltage area size, shape, and internal dynamic power requirements of the block. For some designs, it might
be impossible to implement a ring-style approach without violating IR drop and inrush current requirements.

Defining a Power Switch Placement Strategy

You can use the set_power_switch_place_pattern_strategy command to define a power switch placement pattern for the
create_power_switch_array command.

set_power_switch_place_pattern_strategy
[-direction horizontal | vertical]
[-connect_mode HFN | DAISY]
[-driver driver_switch_cell]
[-pattern pattern_name]
[-flip]
[-connect_power_switch]

Use this command to specify the pattern direction, daisy-chain or high-fanout net connection mode, the driver
switch cell name, whether the pattern is flipped during placement and whether the power switch cells are
connected during placement. Specify a name for the pattern with the -pattern pattern_name option and use the same
pattern name when you specify the create_power_switch_array -place_pattern command.

Creating a Power-Switch Array

You can use the create_power_switch_array command to add power switches in a uniform grid array inside the voltage
area. After inserting the power switches, the command legalizes the power switches and locks their position by
setting the is_fixed attribute on each power switch. The create_power_switch_array command syntax is as follows:

create_power_switch_array
-x_increment dx
-y_increment dy
[-lib_cell lib_cell_or_power_switch
[-individual_mode normal | staggered]]
[-voltage_area voltage_area]
[-bounding_box { {llx lly} {urx ury} }]
[-relative_to_voltage_area]
[-offset_to_voltage_area offset_spec]
[-design hierarchy_name]
[-start_row index]
[-start_column index]
[-orientation {N | W | S | E | FN | FE | FS | FW}]
[-respect avoid_object_types]
[-place_pattern place_pattern_name]
[-prefix prefix_name]

The following example creates a power-switch array by using the create_power_switch_array command. The command
instantiates the POWERSWITCH1 cell in a staggered pattern within the V_DOMAIN1 voltage area with a spacing
between cells of 120 microns in the y-direction and 120 microns in the x-direction. The command attaches the
V_DOMAIN1_ prefix to each inserted power-switch cell.

icc_shell> create_power_switch_array -lib_cell POWERSWITCH1 \

-voltage_area V_DOMAIN1 -y_increment 120 -x_increment 120 \
-prefix V_DOMAIN1_ -individual_mode staggered

Creating a Power-Switch Ring

The create_power_switch_ring command creates a full or partial ring of switch cells around the voltage areas or macro
cells in your design. You can use command options to control the cell density of the switch cell ring, the type of
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filler cells that are inserted between the power-switch cells, the startpoint, the orientation, and other settings.
The command places only the power-switch cells; it does not connect the power, ground, and control pins. The
command does not honor blockages or existing cells, but a warning message is issued if the inserted cells create
conflicts. The create_power_switch_ring command syntax is as follows:

create_power_switch_ring
-switch_lib_cell lib_cell_or_power_switch
[-vertical_switch_lib_cell lib_cell_or_power_switch
[-filler_lib_cell collection_of_filler_lib_cell_names]
[-vertical_filler_lib_cell collection_of_filler_lib_cell_names]
[-outer_corner_lib_cell outer_corner_lib_cell_name]
[-inner_corner_lib_cell inner_corner_lib_cell_name]
[-area_object voltage_area_or_macro
| -polygon {list_of_points}]
[-design hierarchy_name]
[-prefix string]
[-switch_orientation N | W | S | E | FN | FE | FS | FW]
[-outer_corner_orientation N | W | S | E | FN | FE | FS | FW]
[-inner_corner_orientation N | W | S | E | FN | FE | FS | FW]
[-density switch_density | -switch_number number_of_switches]
[-offset offset_values]
[-start_point {point}]
[-end_point {point}]
[-check_overlap]
[-same_orientation]
[-respect avoid_object_types]
[-x_increment dx]
[-y_increment dy]
[-place_pattern pattern_syntax]
[-continue_pattern]

You can create a power-switch ring with each power-switch cell in the same orientation by specifying the
-same_orientation option. Use the -x_increment and -y_increment options to control the spacing of the power switches in
the ring. If the power-switch cell is a standard cell, the command automatically snaps the cell to the nearest site
row and ignores the -switch_orientation option.

The following example creates a power-switch ring around the DOMAIN1 power domain. The command uses the
SWITCH_HEADER power-switch cell and creates a ring pattern using the FILLER and HEADER library cells. Figure
34 shows the ring created by using the command in the example.

icc_shell> create_power_switch_ring -area_object DOMAIN1 \

-switch_lib_cell SWITCH_HEADER \
-place_pattern { { FILLER HEADER FILLER } * }

Figure 34 Power-Switch Ring

When you specify more than one power-switch cell by using the map_power_switch command, you can reference a
particular cell by using the switch_name:lib_cell_name syntax with the -switch_lib_cell option to the
create_power_switch_ring command. The following example maps two power-switch cells to the SW switch name and
places the cell_2 cell in the power-switch ring.

icc_shell> map_power_switch SW –domain VA –lib_cells {cell_1 cell_2}

icc_shell> create_power_switch_ring -area_object INST \
-switch_lib_cell SW:cell_2

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You can specify unique power switch cells for placement on the vertical edges of the power domain by using the
-vertical_switch_lib_cell and -vertical_filler_lib_cell options of the create_power_switch_ring command. Use the
-inner_corner_lib_cell and -outer_corner_lib_cell options to specify the inner and outer corner cells. For example, the
following command places the sw_h power switch cell and filler_h filler cell on the horizontal edges of the power
domain, and places the sw_v power switch cell and filler_v filler cell on the vertical edges. You can specify
multiple filler cells in decreasing priority within the braces ({}); the highest priority filler cell that fits the space is
inserted into the power switch ring.

icc_shell> create_power_switch_ring -switch_lib_cell sw_h \

-vertical_switch_lib_cell sw_v -filler_lib_cell {filler_h} \
-vertical_filler_lib_cell {filler_v} \
-outer_corner_lib_cell corner_outer \
-inner_corner_lib_cell corner_inner \
-area_object PD1 \
-switch_number 77

You can specify a UPF strategy name together with the -switch_lib_cell and -vertical_switch_lib_cell options. The
following example uses the map_power_switch command to create a mapping between the PD1 power domain and the
sw_h and sw_v power switch cells.

icc_shell> map_power_switch -domain PD1 -lib_cells {sw_h sw_v} PSW

icc_shell> create_power_switch_ring -switch_lib_cell PSW:sw_h \
-vertical_switch_lib_cell PSW:sw_v \
-filler_lib_cell {filler_h} \
-vertical_filler_lib_cell {filler_v} \
-outer_corner_lib_cell corner_outer \
-inner_corner_lib_cell corner_inner \
-area_object PD1
-switch_number 77

You can create the same power switch ring by using the following alternative syntax as shown in the following
example:

icc_shell> map_power_switch –domain PD1 –lib_cells {sw_h} PSW1

icc_shell> map_power_switch –domain PD1 –lib_cells {sw_v} PSW2
icc_shell> create_power_switch_ring -switch_lib_cell PSW1 \
-vertical_switch_lib_cell PSW2 \
-filler_lib_cell {filler_h} \
-vertical_filler_lib_cell {filler_v} \
-outer_corner_lib_cell corner_outer \
-inner_corner_lib_cell corner_inner \
-area_object PD1
-switch_number 77

Exploring Different Switch Configurations

There are many possible configurations you can select when creating a power-switch array network; the challenge
is to determine the optimal configuration. You can use the explore_power_switch command to estimate the IR drop of
various power-switch array configurations. The explore_power_switch command invokes both power network
synthesis and power network analysis and requires power network synthesis constraints set by using the
set_fp_rail_constraints command.

To perform power-switch exploration, provide the power-switch library cells for insertion, the switch array x- and
y-pitches, and the permanent and virtual supply names. The explore_power_switch command automatically loops
through the configurations you provide and performs the following steps:

Inserts header or footer arrays based on your specification

Legalizes placement after power-switch insertion

Logically connects permanent and virtual PG nets to power switches

Performs multivoltage power network synthesis and creates a virtual power and ground grid for all voltage
areas
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Connects power switches automatically to the global supply

Preroutes standard cells if the -create_virtual_rails option is not specified

Performs power network analysis on the current configuration by using the analyze_fp_rail –nets {vdd+vdd_local}
command

The explore_power_switch command creates a report containing a sorted list of maximum IR drop values for all
configurations. Based on the results of the command, you can select the appropriate power-switch configuration
to achieve the required IR drop for your design.

The following command performs power-switch cell exploration on the current design. The command explores the
IR drop in the VA1 voltage area by instantiating the FOOTER8, FOOTER16, and FOOTER32 power-switch cells
using the x-spacing values of 25, 50, and 100 microns. The VIRTUAL_VSS virtual ground net and VSS real ground
net are used in the analysis. See the man page for a complete list of command options.

icc_shell> explore_power_switch \
-lib_cells {"FOOTER8" "FOOTER16" "FOOTER32"} \
-x_increment {25 50 100} -voltage_area VA1 \
-virtual_pg_net VIRTUAL_VSS -real_pg_net VSS

Optimizing Power Switches

After you insert power switches into a design, you can optimize the power switches by using the
optimize_power_switch command. The command sizes the power-switch cells to attempt to reduce the IR drop to the
target level set by using the set_mtcmos_pna_strategy command. The following example uses the optimize_power_switch
command to optimize the power-switch network to achieve a target IR drop of 120 mV.

icc_shell> set_mtcmos_pna_strategy -target_voltage_drop 120

icc_shell> optimize_power_switch -virtual_pg_net VIRTUAL_VDD \
-real_pg_net VDD

Connecting Power Switches

The control pins of the cells within the power-switch cell network must be connected to a master sleep control
signal. There are three connection styles: high fanout, daisy chain, and fishbone. The high-fanout connection
style uses a single net and buffers to simultaneously power up the switch-cell network. The daisy-chain
connection style enables the switch cells in a sequential fashion and results in a lower inrush current. The
fishbone configuration connects power switches along the primary direction, either vertical or horizontal, then
creates additional routes to connect the remaining switches in the orthogonal direction. Figure 35 shows a
schematic view of these three connection schemes.

Figure 35 Daisy-Chain and High-Fanout Connection Styles

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To connect the sleep control pins on the power-switch cells in daisy-chain mode, use the connect_power_switch -mode
daisy command. In the following example, the connect_power_switch command connects the sleep control pins by
using a daisy chain.

icc_shell> connect_power_switch -source SLEEP -port_name sleep_port \

-mode daisy -direction horizontal -verbose -voltage_area { VA1 VA2 }

To control how the tool creates connections to power switch cells during fishbone mode routing, use the
mv_mtcmos_detour_obstruction application variable. Set this variable to true to avoid creating route connections in the
orthogonal direction over hard macros and create trunk lines in the primary direction on either side of the hard
macro. This reduces the routing over the hard macro and creates better quality of results.

© 2019 Synopsys, Inc. All rights reserved.

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