The document describes the design of a clamping circuit. It discusses:
1) Clamping the positive peak of an input signal (like a sinusoid) to zero level using a diode and capacitor.
2) Adding a resistor R in parallel with the diode to reduce the time constant, allowing the signal to be re-clamped to zero in a few cycles when the input abruptly falls.
3) Choosing R to be significantly smaller than the diode's reverse resistance Rr but larger than its forward resistance Rf, to both discharge the capacitor quickly and replenish its charge.
The document describes the design of a clamping circuit. It discusses:
1) Clamping the positive peak of an input signal (like a sinusoid) to zero level using a diode and capacitor.
2) Adding a resistor R in parallel with the diode to reduce the time constant, allowing the signal to be re-clamped to zero in a few cycles when the input abruptly falls.
3) Choosing R to be significantly smaller than the diode's reverse resistance Rr but larger than its forward resistance Rf, to both discharge the capacitor quickly and replenish its charge.
The document describes the design of a clamping circuit. It discusses:
1) Clamping the positive peak of an input signal (like a sinusoid) to zero level using a diode and capacitor.
2) Adding a resistor R in parallel with the diode to reduce the time constant, allowing the signal to be re-clamped to zero in a few cycles when the input abruptly falls.
3) Choosing R to be significantly smaller than the diode's reverse resistance Rr but larger than its forward resistance Rf, to both discharge the capacitor quickly and replenish its charge.
Design a clamping circuit to clamp the positive peak of an input signal
(say, a sinusoidal signal) to zero level as shown in fig. below:
When the diode is OFF, ideally its reverse resistance is either
infinity or, in practice, very large (of the order of tens of mega ohms). Design of Clamping Circuit
If the input abruptly falls in amplitude, as
shown in Fig., the time constant associated with the discharge of C(= RrC) is large. Then the positive peak of the signal in the output may not be clamped to zero, even after many cycles, in the absence of R. In numerous applications, the requirement is that the signal should once again be clamped to zero level in at least a few cycles. Hence, R is shunted across the diode D to reduce the time constant. On this account, R is so chosen that it is significantly smaller than Rr. Hence,
where a is a large number.
Design of Clamping Circuit
During the period the diode is OFF, some
charge is lost by the condenser C. This lost charge is replenished when the diode is ON; during this period the resistance offered by the diode is Rf , which is very small (of the order of few tens of ohms). To ensure that the charge is acquired by the capacitor in a relatively small amount of time, R should be significantly larger than Rf . Hence
R=aRf Design of Clamping Circuit Clamping Circuit Theorem
This theorem enables us to calculate the voltage level to which the
output is clamped by considering the areas above and below the
reference level, when the values of Rf and R are known.
The clamping circuit theorem states that under steady-state conditions,
for any input waveform, the ratio of the area under the output voltage
curve in the forward direction to that in the reverse direction is equal to
the ratio Rf /R.
Clamping Circuit Theorem
To prove the clamping circuit theorem, consider a typical steady-state
output for the clamping circuit, represented below: