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Ex-2 1 0 1 1 0 1 0 12
27 + 0 + 25 + 24 + 0 + 22 + 0 + 20 = 18110
= 23 + 0 + 21 + 0. + 0 + 2-2 + 2-3
= (10.375)10
DECIMAL-TO-BINARY CONVERSION
4510 = 32 + 8 + 4 + 1 = 25 + 0 + 23 + 22 + 0 + 20
=1 0 1 1 0 12
7610 = 64 + 8 + 4 = 26 + 0 + 0 + 23 + 22 + 0 + 0
= 1 0 0 1 1 0 02
DECIMAL-TO-BINARY
CONVERSION
Flowchart for repeated-
division method of decimal-to-
binary conversion of integers.
Same process can be used to
convert a decimal integer to any
other number system.
Convert 3710 to binary
Thus,
3710 = 1001012
Ex1.1 Mano: Convert decimal 41 to binary
Decimal-to-Hex Conversion
Decimal-to-binary conversion: repeated division by 2
Decimal-to-hex conversion: repeated division by 16
Ex 2-3 (a) (Tocci): Convert 42310 to hex
Ex 2-3 (b) (Tocci): Convert 21410 to hex
9F216 = 9 F 2
=1 0 0 1 1 1 1 1 0 0 1 0
= 1001111100102
3 0 6 . D
Binary-to-Hex Conversion:
Conversion from Binary to hex is just the reverse of
the process above.
1 1 1 0 1 0 0 1 1 02 = 0 0 1 1 1 0 1 0 0 1 1 0 = 3A616
3 A 6
2 C 6 B F 2
Counting in Hexadecimal
Counting in hex, each digit position is incremented by
1from 0 to F.
37810 = 17A16
Hex value is converted easily to binary 000101111010.
37810 is expressed as a 16-bit number by adding four
leading 0s: 37810 = 0000 0001 0111 10102
Summary of Conversions
From binary [or hex] to decimal, use the method of
taking the weighted sum of each digit position.
8 7 4 (decimal)
Solution:
Locate each character (including the space) in Table
and record its ASCII code
0 is added to the leftmost bit of each ASCII code
because codes must be stored as bytes (eight bits).
REVIEW QUESTIONS
Truth Table
2-line-to-4-line Decoder
with NAND Gates
74HC138 is
high-speed
CMOS
version of
this decoder
Indicate the states of the 74ALS138 outputs for each
of the following sets of inputs
(a) E3 = E′2 = 1, E′1 = 0, A2 = A1 = 1, A0 = 0
(b) E3 = 1, E′2 = E′1 = 0, A2 = 0, A1 = A0 = 1
Logic Symbol
of 74ALS138
Decoder
Fig shows how four 74ALS138s & an INVERTER can be arranged to function as a 1-
of-32 decoder. Decoders are labeled Z1 to Z4 for easy reference, and eight outputs from
each one are combined into 32 outputs. Z1’s outputs are O′0 to O′7; Z2’s outputs O′0 to
O′7 are renamed O′8 to O′15 respectively; Z3’s outputs are renamed O′16 to O′23 ; and
Z4’s are renamed O′24 to O′31 . A five-bit input code A4A3A2A1A0 will activate only one
of these 32 outputs for each of the 32 possible input codes.
(a) Which o/p will be activated for
A4A3A2A1A0 = 01 101
(b) What range of input codes will activate Z4 chip?
Logic diagram of
BCD-to-Decimal
Decoder
74LS42
74HC42
7442
BCD-to-decimal decoder
Logic symbol;
BCD-to-Decimal Decoder/Driver
TTL 7445 is a BCD-to-decimal decoder/driver. The
7445’s outputs can sink up to 80 mA in the LOW state,
and they can be pulled up to 30 V in the HIGH state.
This makes them suitable for directly driving loads
such as indicator LEDs or lamps, relays, or dc motors.
Decoder Applications; Memory Systems etc.
Most decoders accept an input code and produce a
HIGH (or a LOW) at one and only one output line. In
other words, we can say that a decoder identifies,
recognizes, or detects a particular code. The opposite
of this decoding process is called encoding and is
performed by a logic circuit called an encoder An
encoder has a number of input lines, only one of which
is activated at a given time, and produces an N-bit
output code, depending on which input is activated.
Figure is the general diagram for an encoder with M
inputs and N outputs. Here, the inputs are active-
HIGH, which means that they are normally LOW
Encoder
An encoder is a digital circuit that performs inverse
opn of a decoder. An encoder has 2n (or fewer) input
lines and n output lines. The o/p lines, generate binary
code corresponding to the input value. An 8-line-3-line
Encoder can be implemented with OR gates whose
i/ps are determined directly from truth table. O/p z is
equal to 1 when the input octal digit is 1, 3, 5, or 7.
O/p y is 1 for octal digits 2, 3, 6, or 7, & O/p x is 1 for
digits 4, 5, 6, or 7.
These conditions are expressed by Boolean O/p fns:
z = D1 + D3 + D5 + D7 This Encoder is
y = D2 + D3 + D6 + D7 implemented with
x = D4 + D5 + D6 + D7 three (4-I/p) OR gates
Logic ckt of 8-line-3-line
encoder. For proper opn,
only 1 input should be
active at a time.
These conditions are expressed by Boolean O/p fns:
O0 = A′1 + A′3 + A′5 + A′7 This Encoder is
O1 = A′2 + A′3 + A′6 + A′7 implemented with
O2 = A′4 + A′5 + A′6 + A′7 three (4-I/p) OR gates
74147 decimal-to-BCD priority encoder
O0 = A′1 + A′3 + A′5 + A′7 + A′9
O1 = A′2 + A′3 + A′6 + A′7 Boolean function & Truth
Table of decimal-to-BCD
O2 = A′4 + A′5 + A′6 + A′7
priority encoder 74147
O3 = A′8 + A′9
Decimal-to-BCD
Switch Encoder
A priority encoder is an encoder circuit that includes
the priority function. The operation of the priority
encoder is such that if two or more inputs are equal to
1 at the same time, the input having the highest
priority will take precedence. The truth table of a four-
input priority encoder is given in Table 4.8 . In
addition to the two outputs x and y , the circuit has a
third output designated by V ; this is a valid bit
indicator that is set to 1 when one or more I/ps = 1
Priority Encoder
x = D 2 + D3
y = D3 + D1 D′2
V = D 0 + D 1 + D2 + D3
MULTIPLEXERS (DATA SELECTORS)
A digital multiplexer or data selector is a logic circuit
that accepts several digital data inputs and selects one
of them at any given time to pass on to the output. The
routing of the desired data input to the output is
controlled by SELECT inputs (often referred to as
ADDRESS inputs)
MULTIPLEXERS (DATA SELECTORS)
Two-input
multiplexer
4-input Mux
8-I/p Mux
Two 74HC151s
combined to form
a 16-input Mux
Quad 2-Input MUX(74ALS157/HC157)
Logic diagram
74ALS157 MUX
Truth table
Logic symbol
Two-to-one-line
multiplexer
(a) Logic diagram
(b) Block diagram
Four-to-one-line
multiplexer