QUIZ 4 – MOCK TEST 2

Q1) F(A,B,C,D) = B’D’ + AD’+B’C

i. Build the truth table for F output.

ii. Design the logic circuit for function F using 3:8 Decoder as shown in Figure Q1 (a)
iii. You are only provided with a few IC 74153 (Dual 4:1 Multiplexer) and its function table as
shown in the Figure Q1(b-c), perform output F using this Multiplexer.

(a)

Input
Data Inputs Enable Output
Selectors
SB SA nC0 nC1 nC2 nC3 nG nY
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H
H: HIGH Level L : LOW Level X : Don’t Care
(b) (c)
Figure Q1

Q2) Using only half adders as shown in Figure Q2 and build the circuit to calculate addition of 3-bit
binary numbers A (A2A1A0) and B (B2B1B0) that yield C3S2S1S0

Figure Q2
QUIZ 4 – MOCK TEST 2

Q3) A D flip flop is connected as shown in Figure Q3(a), complete the function table (Table Q3) and
the timing diagram (Figure Q3(b)).

Figure Q3(a)

Table Q3

CLK PRE’ CLR’ A B Qnext FF State

↓ 0 1 X X 1 SET
↓ 1 0 X X 0 RESET
0,1 1 1 X X Q NC
↑ 0 1
↑ 1 0
↑ 1 1
↑ 1 1
↑ 1 1
↑ 1 1
1: HIGH State 0: LOW State NC: No Change

Figure Q3 (b)
QUIZ 4 – MOCK TEST 2

Q1) F(A,B,C,D) = Σm(2,3,8,10,11,14)+ Σd(0,12)

i. Build the truth table for F output.

ii. Design the logic circuit for function F using 3:8 Decoder as shown in Figure Q1 (a)
iii. You are only provided with a few IC 74153 (Dual 4:1 Multiplexer) and its function table as
shown in the Figure Q1(b-c), perform output F using this Multiplexer.

(a)

Input
Data Inputs Enable Output
Selectors
SB SA nC0 nC1 nC2 nC3 nG nY
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H
H: HIGH Level L : LOW Level X : Don’t Care
(b) (c)
Figure Q1

Q2) Using only half adders as shown in Figure Q2 and build the circuit to calculate addition of 3-bit
binary numbers A (A2A1A0) and B (B2B1B0) that yield C3S2S1S0

Figure Q2
QUIZ 4 – MOCK TEST 2

Q3) A D flip flop is connected as shown in Figure Q3(a), complete the function table (Table Q3) and
the timing diagram (Figure Q3(b)).

Figure Q3(a)

Table Q3

CLK PRE’ CLR’ A B Qnext FF State

↓ 0 1 X X 1 SET
↓ 1 0 X X 0 RESET
0,1 1 1 X X Q NC
↑ 0 1
↑ 1 0
↑ 1 1
↑ 1 1
↑ 1 1
↑ 1 1
1: HIGH State 0: LOW State NC: No Change

Figure Q3 (b)
QUIZ 4 – MOCK TEST 2

Q1) F(A,B,C,D) = (A+B’)(B’+D’)(C+D’)

i. Build the truth table for F output.

ii. Design the logic circuit for function F using 3:8 Decoder as shown in Figure Q1 (a)
iii. You are only provided with a few IC 74153 (Dual 4:1 Multiplexer) and its function table as
shown in the Figure Q1(b-c), perform output F using this Multiplexer.

(a)

Input
Data Inputs Enable Output
Selectors
SB SA nC0 nC1 nC2 nC3 nG nY
X X X X X X H L
L L L X X X L L
L L H X X X L H
L H X L X X L L
L H X H X X L H
H L X X L X L L
H L X X H X L H
H H X X X L L L
H H X X X H L H
H: HIGH Level L : LOW Level X : Don’t Care
(b) (c)
Figure Q1

Q2) Using only half adders as shown in Figure Q2 and build the circuit to calculate addition of 3-bit
binary numbers A (A2A1A0) and B (B2B1B0) that yield C3S2S1S0

Figure Q2
QUIZ 4 – MOCK TEST 2

Q3) A D flip flop is connected as shown in Figure Q3(a), complete the function table (Table Q3) and
the timing diagram (Figure Q3(b)).

Figure Q3(a)

Table Q3

CLK PRE’ CLR’ A B Qnext FF State

↓ 0 1 X X 1 SET
↓ 1 0 X X 0 RESET
0,1 1 1 X X Q NC
↑ 0 1
↑ 1 0
↑ 1 1
↑ 1 1
↑ 1 1
↑ 1 1
1: HIGH State 0: LOW State NC: No Change

Figure Q3 (b)
QUIZ 4 – MOCK TEST 2

ANSWER

Q1

i. Build the truth table for F output.

ii. Design the logic circuit for function F using 3:8 Decoder as shown in Figure Q1 (a)
iii. You are only provided with a few IC 74153 (Dual 4:1 Multiplexer) and its function table as
shown in the Figure Q1(b-c), perform output F using this Multiplexer.

F(A,B,C,D) = (A+B’)(B’+D’)(C+D’) F(A,B,C,D) = B’D’ + AD’+B’C F(A,B,C,D) =

Σm(2,3,8,10,11,14)+
Σd(0,12)

A B C D F A B C D F
0 0 0 0 1 0 0 0 0 X
0 0 0 1 0 0 0 0 1 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 1 0
0 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0
1 0 0 0 1 1 0 0 0 1
1 0 0 1 0 1 0 0 1 0
1 0 1 0 1 1 0 1 0 1
1 0 1 1 1 1 0 1 1 1
1 1 0 0 1 1 1 0 0 X
1 1 0 1 0 1 1 0 1 0
1 1 1 0 1 1 1 1 0 1
1 1 1 1 0 1 1 1 1 0
QUIZ 4 – MOCK TEST 2
QUIZ 4 – MOCK TEST 2

Q2)

A2 A1 A0
+ B2 B1 B0
---------------
C3 S2 S1 S0
---------------

Using only Half Adder

Q3)
CLK PRE’ CLR’ A B Qnext FF State
↓ 0 1 X X 1 SET
↓ 1 0 X X 0 RESET
0,1 1 1 X X Q NC
↑ 0 1 X X 1 SET
↑ 1 0 X X 0 RESET
↑ 1 1 0 0 Q NC
↑ 1 1 0 1 1 SET
↑ 1 1 1 0 0 RESET
↑ 1 1 1 1 Q’ TOGGLE
1: HIGH State 0: LOW State NC: No Change
QUIZ 4 – MOCK TEST 2