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ECE617 Junior Laboratory Exercise Three - 2008

Design of Digital CMOS Logic Circuits

1. Introduction

CMOS technology is widely used to implement digital circuits because of its low
power requirements, small feature size (high transistor density), ease of manufacture,
available design tools, scalable parameters, and mature fabrication processes. CMOS
technology is used in the implementation of discrete logic gates (40XX, 74CXX,
74ACLXX, 74HCLXX, etc. series), programmable logic devices, field programmable
gate arrays, microprocessors/microcontrollers, custom VLSI logic, etc.
Because CMOS is such an important technology, one should understand how
circuits are implemented at the transistor level. Understanding the logic at the
transistor level allows one to relate transistor properties to circuit parameters.
Important circuit parameters include I/O voltage switching levels, I/O current
requirements, I/O delays and rise/fall times, and power requirements.
In this laboratory exercise the student will construct a number of CMOS logic
circuits using the CD4007 dual complementary pair CMOS array. The CD4007 is an
array of three PMOS and three NMOS transistors. I/O parameters will be measured
using the available laboratory equipment.

2. Purpose

ƒ To investigate the properties of PMOS and NMOS transistors used in switching

ƒ To configure and investigate the properties of a CMOS transmission gate.
ƒ To understand how basic CMOS logic gates are constructed.
ƒ To measure the I/O parameters of a basic CMOS logic circuit.

3. References Sedra and Smith Textbook (fifth edition), Sections 10.1 and 10.2
Sedra and Smith Textbook (fifth edition), Sections 10.3 and 10.5

4. Prelab

For the pre-lab you are to design two CMOS circuits. In the laboratory we will
use the CD4007 CMOS transistor array to construct these circuits. However,
Multisim does not have the model of the CD4007 device in its library. Instead use
the four (4) terminal enhancement mode PMOS and NMOS transistors (MOS_4TEP
and MOS_4TEN) to simulate your circuit design. Notice that you can change the
length and width parameters of these MOS transistors, thus changing the gain
constant that relates Vds and Vgs to Ids. You may want to change these parameters to
see what effect they have on circuit performance. Recall that increasing the width
increases the gain constant and decreasing the length also increases the gain constant.
Because the MOS_4TEP and MOS_4TEN transistors are not exact models of the
transistors in the CD4007 array, the simulations in Multisim will only confirm the
functionality of the circuits you designed and not the actual circuit delays.
Referring to section 13.3 in the referenced textbook, design a CMOS logic gate to
implement the logic function assigned in section 7 of this handout. Be prepared to
implement this circuit using the CD4007 CMOS transistor array. Annotate your logic
diagram with package pin numbers. Use the Multisim schematic capture tool and the
four terminal NMOS and PMOS enhancement mode FET components. Simulate
your circuit to confirm its functionality.
Referring to section 13.5 in the referenced textbook, design a CMOS transmission
gate (see Figure 2) with an input/output connections (Va) and (Vb), and a control
signal (CTL) to turn the transmission gate on and off. The transmission gate can be
used to implement digital logic functions or used as an analog switch. In this exercise
we will use the transmission gate as an analog switch. Use the MultiSim schematic
capture tool and the four terminal NMOS and PMOS enhancement mode FET
components. Simulate your circuit to confirm its functionality. Use a properly biased
sine wave source as the input to the transmission gate. Annotate your logic diagram
with package pin numbers.
5. CMOS Inverter
pin 14

pin 13

pin 6 Vout
V5 pin 8

pin 7

Figure 1a

pin 14 Q6

0m 2e-005m

pin 13
50kHz pin 6
pin 8

0m 2e-005m
pin 7

Figure 1b

Title: l4_f1_inv

Figure 1a and 1b

Designed by: Frank Hludik Document N: 1.0 Revision: 1.0

Checked by: Date: 9/24/2008 Size: Custom

Approved by: Sheet 1 of 1
5.1. Referring to Figure 1, construct a CMOS inverter using the CD4007 transistor
array. Use the PMOS transistor connected to pin 14 and the NMOS transistor
connected to pin 7. Recall that the pin 14 also connects all PMOS substrates to
VDD (the most positive voltage) and pin 7 connects all the NMOS substrates to
VSS (the lowest voltage in the circuit, usually ground).

5.2. Using an adjustable DC power supply (V2 in Figure 1a) and a DMM, measure
and record the input switching levels Vih and ViL (when output changes by .05 v).
Measure and record the output voltage levels Voh and VoL (when input is 0 v or 5
5.3. Using a function generator as shown in Figure 1b (pulse output – 0 to 5 volts at
50 KHz) and an oscilloscope measure and record the propagation delay times
(tphL and tpLh) and the rise and fall times (transition times – ttLh and tthL). Perform
these measurements for a Vcc setting of 5 volts and capacitive loads of 0 pF, 100
pF, and 400 pF. Use a BNC cable instead of the scope probe and observe the
difference in delay measurements. Why is there a difference in values when
using the BNC cable?

6. CMOS Transmission Gate

6.1. Construct the CMOS transmission gates as shown in Figure 2. Use a DC power
supply voltage of 10 v.

6.2. Connect a function generator (sine wave at 10 KHz, properly DC biased) to the
input of the transmission gate. Measure and record the input and output
waveforms of the transmission gate with the transmission gate turned on and
turned off. Use the control signal to turn the transmission gate on and off.
Explain how the circuit works. What is the maximum output voltage?
6.3. Connect an ohmmeter between Va and Vb and measure the Roff and Ron
resistances of the transmission gate.

7. Assigned CMOS Logic Function

7.1. Construct the assigned CMOS logic function using the CD4007 transistor array.
Have the design checked by a laboratory instructor.

Assigned Logic Function: _______________________

8. Laboratory Report

8.1. Cover page with name, date, title, and abstract.

8.2. Table of recorded values for section 5.
8.3. Discuss the significance of the I/O voltages measured in section 5, i.e., why are
input voltage switching levels different from the output voltage levels?
8.4. Discuss how the capacitive loads affect the delays measured in section 5.
8.5. Discuss the results obtained from section 6 and 7.
8.6. Include logic diagrams and simulations for sections 6 and 7.