INDEX

 ABSTRACT ... 3

 LIST OF COMPONENTS …4

 LIST OF FIGURES …5

 LIST OF TABLES …6

 LIST OF ACRONYMS …7

CHAPTER 1: OVERVIEW OF REAL TIME PERSONAL ASSISTANT

1.1 INTRODUCTION TO REAL TIME PERSONAL ASSISTANT … 8

1.2 BLOCK DIAGRAM … 10

1.3 DESCRIPTION OF BLOCK DIAGRAM … 11

1.4 PROJECT OVERVIEW … 12

CHAPTER 2: HARDWARE DESCRIPTION … 14

2.1 AT89C51 MASTER MICROCONTROLLER … 14

2.3 DS1307-REAL TIME CLOCK … 25

1
CHAPTER 3: PROTOCOLS

… 34

3.1 INTER IC (I2C) PROTOCOL … 34

CHAPTER 4: FLOWCHARTS AND ALGORITHMS … 43

4.1 INTERFACING OF DS1307 (REAL TIME CLOCK) … 43

4.3 INTERFACING OF LIQUID CRYSTAL DISPLAY UNIT … 47

CHAPTER 5: PROGRAMMING … 51

5.1 INTRODUCTION TO KEIL MICROVISION … 51

5.2 SOURCE CODE … 54

CHAPTER 6: CONCLUSIONS … 70

6.1 ADVANTAGES … 70

6.2 LIMITATIONS … 70

6.3 RESULTS … 71

2
  APPENDIX

 REFERENCES

ABSTRACT

The aim of the project is to design programmable real time personal assistant
system to sense and control various appliances in a home. Using the real time clock we
will set the time for each appliance with the key pad. The LCD will display the times for
each appliance. When ever the time comes, the 8051 microcontroller is activated which
gives the signal to the corresponding appliance through output relays. In this project we
are controlling one device from controller.

LIST OF COMPONENTS:

COMPONENT QUANTITY

IC1 AT89C51 1

IC3 DS1307 1

IC4 74LS30 1

IC5 74LS04 1

IC6 MAX232 1

TRANSISTOR BC 547 2

CRYSTAL 11.0592 MHz 1

CRYSTAL 32.768 MHz 1

PUSH BUTTONS 4

3
 6V RELAY 2

D-Type 9 PIN FEMALE 1

CONNECTOR

BRIDGE RECTIFIER 1

7805 VOLTAGE
REGULATOR 1

230 / 18V CENTER TAP 1

TRANSFORMER

LED’S 2

LCD DISPLAY UNIT 1

RESISTORS

CAPCITORS
LIST OF FIGURES:
Fig 1: Block diagram of temperature monitoring system. … 10

Fig 2: Pin diagram of AT89C51 microcontroller. … 18

Fig 3: Functional block diagram of AT89C51. … 19

Fig 4: Pin diagram of DS1621. … 20

Fig 5: Functional block diagram of DS1621. … 24

Fig 6: Pin diagram of DS1307. … 26

Fig 7: Functional block diagram of DS1307. … 29

Fig 8: Pin diagram of MAX232 … 30

Fig 9: 9 Pin connector on a DTE device (PC connection) … 32

Fig 10: Schematic representation … 33

4
 Fig 11: Timing diagram for valid data on I2C bus. … 35
Fig 12: Start and Stop conditions on I2C bus. … 36

Fig 13: Acknowledgement condition on I2C bus. … 38

Fig 14: Connection of devices to I2C bus. … 40

Fig 15: Example of data transfer using RS-232. … 42

Fig 16: Flowchart for interfacing DS1307. … 44

Fig 17: Flowchart for interfacing DS1621. … 46

Fig 18: Flowchart for working of LCD unit. … 48

Fig 19: Flowchart for serial transfer of data. … 50
Fig 20: Snapshot of RIDE interface. … 52

Fig 21: Snapshot of main program and compilation windows … 53

Fig 22: Example of LCD display in CLOCK MODE. … 71

Fig 23: Example of LCD display in TEMPERATURE MODE. … 71

Fig 24: Example of LCD display in PC MODE. … 72

Fig 25: Display of time and temperature in PC MODE. … 73

Fig 26: Flowchart for selection of mode of operation. … 74
LIST OF TABLES

TABLE 1: Characteristics of types of temperature sensors …9

TABLE 2: Pins and signals of a D-type 9 pin connector … 32

5
LIST OF ACRONYMS

1. I2C Inter-IC.
2. RTD Resistance Temperature Detector.

6
 3. ADC Analog to Digital Converter.
4. LCD Liquid Crystal Display.
5. IC Integrated Circuit.
6. SDA Serial Data Access.
7. SCL Serial Clock Line.
8. ROM Read Only Memory.
9. EPROM Erasable and Programmable Read Only Memory.
10. RTC Real Time Clock.
11. SRAM Static Random Access Memory.
12. I/O Input/ Output.
13. ALE Address Latch Enable.
14. PROG Program pulse input.
15. PSEN Program Store ENable.
16. DIP Dual Inline Package.
17. MSB Most Significant Byte.
18. LSB Least Significant Byte.
19. BCD Binary Coded Decimal.
20. DTMF Dual-Tone Multi Frequency.
21. EEPROM Electrically Erasable Programmable Read Only Memory.
22. CMOS Complementary Metal Oxide Semiconductor
23. NMOS N-channel MOSfet.
24. ASCII American Standard Code for Information Interchange.
25. TCON Timer CONtrol.
26. TMOD Timer MODe.
27. SCON Serial CONtrol.
28. IE Interrupt Enable.
29. SBUF Serial BUFfer.

CHAPTER 1: OVERVIEW OF TEMPERATURE MONITORING

SYSTEM

7
1.1 INTRODUCTION TO TEMPERATURE MONITORING

Using the real time clock we will set the time for each appliance with the key pad.
The LCD will display the times for each appliance. When ever the time comes, the 8051
microcontroller is activated which gives the signal to the corresponding appliance
through output relays. In this project we are controlling one device from controller.

1.2 BLOCK DIAGRAM

8
 Fig 1: Block diagram home automation system

1.3 DESCRIPTION OF BLOCK DIAGRAM

Using the real time clock we will set the time for each appliance with the key pad.
The LCD will display the times for each appliance. When ever the time comes, the 8051
microcontroller is activated which gives the signal to the corresponding appliance
through output relays. In this project we are controlling one device from controller.

1.4 PROJECT OVERVIEW

The aim of the project is to design programmable home automation system to
sense and control various appliances in a home. Using the real time clock we will set the
time for each appliance with the key pad. The LCD will display the times for each
appliance. When ever the time comes, the 8051 microcontroller is activated which gives
the signal to the corresponding appliance through output relays. In this project we are
controlling one device from controller.

9
CHAPTER 2: HARDWARE DESCRIPTION

2.1 AT89C51 MASTER MICROCONTROLLER

Microcontrollers, as the name suggests, are small controllers. They are

like single chip computers that are often embedded into other systems to function as
processing/controlling unit. A microcontroller is an integrated chip that is often part of an
embedded system. The microcontroller includes a CPU, RAM, ROM, I/O ports, and
timers like a standard computer, but because they are designed to execute only a single
specific task to control a single system, they are much smaller and simplified so that they
can include all the functions required on a single chip. Because of this inherent simplicity
of design and operation microcontrollers find application in a variety of fields.

The AT89C51 is a low-power, high-performance CMOS 8-bit

microcomputer with 8K bytes of Flash programmable and erasable read only memory
(PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory
technology and is compatible with the industry-standard 80C51 and 80C52 instruction set
and pinout. The on-chip Flash allows the program memory to be reprogrammed in-a-
system or by a conventional nonvolatile memory programmer. By combining a versatile
8bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful
microcomputer which provides a highly-flexible and cost-effective solution to many
embedded control applications. The AT89C51 provides the following standard features:
256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, six-vector two-level
interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89C51 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue

10
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next hardware reset.

PIN DESCRIPTION

VCC
Supply voltage.

GND
Ground.

Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 can also be configured to be the multiplexed low order
address/data bus during accesses to external program and data memory. In this mode, P0
has internal pull-ups. Port 0 also receives the code bytes during Flash programming and
outputs the code bytes during program verification. External pull-ups are required during
program verification.

Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in
the following table. Port 1 also receives the low-order address bytes during flash
programming and verification.

Port 2

11
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port
2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In
this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents
of the P2 Special Function Register. Port 2 also receives the high-order address bits and
some control signals during Flash programming and verification.

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also
serves the functions of various special features of the AT89C51 Port 3 also receives some
control signals for Flash programming and verification.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.

ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external data memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit
set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

12
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.

PSEN
Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.

EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming when 12-volt
programming is selected.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2
Output from the inverting oscillator amplifier.

AT89C51 has 3 timers, a UART and a baud rate generator. It has six external
inputs. Apart from above mentioned functions pins of ports 1, 2 and 3 have other special
functions. Apart from its normal mode of operation 89C52 can also operate in idle mode
and power down modes of operation.

13
Pin diagram

Fig 2: Pin diagram of AT89C51 Microcontroller

14
15
Fig 3: Functional block diagram of AT89C51

16
2.3 DS1307 REAL TIME CLOCK

IC clocks are semiconductor integrated circuits (ICs) designed to generate

time. IC clocks are important components in virtually all electronic components,
maintaining synchronization and timing control in telecommunications applications,
consumer electronics, wireless handhelds, and global positioning systems. IC clocks are
silicon based timing devices that accurately align a reference clock signal with a clock
distribution signal. Quartz crystal-based oscillators are also used as timing devices in
electronics equipment. Both are used in conjunction in many applications.

Description
The DS1307 is a low-power clock/calendar with 56 bytes of battery-
backed SRAM. The clock/calendar provides seconds, minutes, hours, day, date, month,
and year information. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections for leap year. The clock operates
in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307 operates as
a slave device on the I2C bus. Access is obtained by implementing a START condition
and providing a device identification code followed by a register address. Subsequent
registers can be accessed sequentially until a STOP condition is executed. When VCC
falls below 1.25 x VBAT, the device terminates an access in progress and resets the
device address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from an out-of tolerance system. When
VCC falls below VBAT, the device switches into a low-current battery-backup mode.
Upon power-up, the device switches from battery to VCC when VCC is greater than
VBAT +0.2V and recognizes inputs when VCC is greater than 1.25 x VBAT.

17
 Fig 6: Pin diagram of DS1307 Real time clock

Pin description:
X1, X2 – Crystal connections
Vbat – Battery Backup
GND – Ground
Vcc – Power Supply
SQW/OUT – Square wave output
SCL- Serial clock Line
SDA – Serial data Line

The DS1307 uses an external 32.768 kHz crystal. The oscillator circuit
does not require any external resistors or capacitors to operate. If using a crystal with the
specified characteristics, the startup time is usually less than one second. The accuracy of
the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the
crystal was trimmed. Additional error will be added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into the oscillator circuit may result in
the clock running fast. The time and calendar information is obtained by reading the
appropriate register bytes. The time and calendar are set or initialized by writing the
appropriate register bytes.

The contents of the time and calendar registers are in the BCD format. The
day-of-week register increments at midnight. Values that correspond to the day of week
are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday,

18
and so on.) Illogical time and date entries result in undefined operation. When reading or
writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user
buffers are synchronized to the internal registers on any I2C START. The time
information is read from these secondary registers while the clock continues to run. This
eliminates the need to re-read the registers in case the internal registers update during a
read. The divider chain is reset whenever the seconds register written. Write transfers
occur on the I2C acknowledge from the DS1307. Once the divider chain is reset, to avoid
rollover issues, the remaining time and date registers must be written within one second.

Data Transfer
The DS1307 supports the I2C protocol. A device that sends data onto the
bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled by the master are
referred to as slaves. The bus must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates the START and STOP
conditions. The DS1307 operates as a slave on the I2C bus.

The DS1307 may operate in the following two modes:

1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA
and SCL. After each byte is received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end of a serial transfer. Hardware
performs address recognition after reception of the slave address and direction bit. The
slave address byte is the first byte received after the master generates the START
condition. The slave address byte contains the 7-bit DS1307 address, which is 1101000,
followed by the direction bit (R/W), which for a write is 0. After receiving and decoding
the slave address byte, the DS1307 outputs an acknowledge on SDA. After the DS1307
acknowledges the slave address + write bit, the master transmits a word address to the

19
DS1307. This sets the register pointer on the DS1307, with the DS1307 acknowledging
the transfer. The master can then transmit zero or more bytes of data with the DS1307
acknowledging each byte received. The register pointer automatically increments after
each data byte are written. The master will generate a STOP condition to terminate the
data write.

2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in
the slave receiver mode. However, in this mode, the direction bit will indicate that the
transfer direction is reversed. The DS1307 transmits serial data on SDA while the serial
clock is input on SCL. START and STOP conditions are recognized as the beginning and
end of a serial transfer. The slave address byte is the first byte received after the START
condition is generated by the master. The slave address byte contains the 7-bit DS1307
address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read.
After receiving and decoding the slave address the DS1307 outputs an acknowledge on
SDA. The DS1307 then begins to transmit data starting with the register address pointed
to by the register pointer. If the register pointer is not written to before the initiation of a
read mode the first address that is read is the last one stored in the register pointer. The
register pointer automatically increments after each byte are read. The DS1307 must
receive a Not Acknowledge to end a read.

FEATURES
DS1307 has a pin SQW/OUT that can be used to generate square
waves of frequency up to oscillator frequency. It has an automatic power fail detect and
switch circuitry that switches to battery backup in case of a power failure. In battery
backup mode it consumes less than 500nA with oscillator running. It has a 56-byte
battery backed non-volatile(NV) for data storage. It has leap year compensation. It is an
I2C protocol compatible device.

20
Fig 7: Functional block diagram of Real time clock DS1307

21
CHAPTER 3: PROTOCOLS

3.1 INTER-IC (I2C) BUS

In consumer electronics, telecommunications and industrial electronics,
there are often many similarities between seemingly unrelated designs. For example,
nearly every system includes:
 Some intelligent control, usually a single-chip microcontroller.
 General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or
data converters.
 Application-oriented circuits such as digital tuning and signal processing circuits
for radio and video systems, or DTMF generators for telephones with tone
dialing.

To exploit these similarities to the benefit of both systems designers and

equipment manufacturers, as well as to maximize hardware efficiency and circuit
simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC
control. This bus is called the Inter IC or I2C-bus. At present, Philips’ IC range includes
more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in
all three of the previously mentioned categories. All I2C-bus compatible devices
incorporate an on-chip interface which allows them to communicate directly with each
other via the I2C-bus. This design concept solves the many interfacing problems
encountered when designing digital control circuits.

Definition of I2C-bus terminology

Transmitter: The device which sends data to the bus.
Receiver: The device which receives data from the bus
Master: The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave: The device addressed by a master.

22
Multi-master: More than one master can attempt to control the bus at the same time
without corrupting the message
Arbitration: Procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the winning message is not corrupted.
Synchronization: Procedure to synchronize the clock signals of two or more devices

GENERAL CHARACTERISTICS
Both SDA and SCL are bi-directional lines, connected to a positive supply
voltage via a current-source or pull-up resistor. When the bus is free, both lines are
HIGH. The output stages of devices connected to the bus must have an open-drain or
open-collector to perform the wired-AND function. The number of interfaces connected
to the bus is solely dependent on the bus capacitance limit of 400 pF.

BIT TRANSFER
Due to the variety of different technology devices (CMOS, NMOS,
bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and
‘1’ (HIGH) are not fixed and depend on the associated level of Vdd. One clock pulse is
generated for each data bit transferred.

Data validity
The data on the SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only change when the clock signal on
the SCL line is LOW.

Fig 11: Timing diagram for valid data on I2C bus

23
START and STOP conditions
Within the procedure of the I2C-bus, unique situations arise which are
defined as START(S) and STOP (P) conditions. A HIGH to LOW transition on the SDA
line while SCL is HIGH is one such unique case. This situation indicates a START
condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition. START and STOP conditions are always generated by the master. The
bus is considered to be busy after the START condition. The bus is considered to be free
again a certain time after the STOP condition. The bus stays busy if a repeated START
(Sr) is generated instead of a STOP condition. In this respect, the START (S) and
repeated START (Sr) conditions are functionally identical. Detection of START and
STOP conditions by devices connected to the bus is easy if they incorporate the necessary
interfacing hardware. However, microcontrollers with no such interface have to sample
the SDA line at least twice per clock period to sense the transition.

Fig 12: Start and Stop conditions on I2C bus

TRANSFERRING DATA
Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes
that can be transmitted per transfer is unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave
can’t receive or transmit another complete byte of data until it has performed some other
function, for example servicing an internal interrupt, it can hold the clock line SCL LOW

24
force the master into a wait state. Data transfer then continues when the slave is ready for
another byte of data and releases clock line SCL. In some cases, it’s permitted to use a
different format from the I2C-bus format (for CBUS compatible devices for example). A
message which starts with such an address can be terminated by generation of a STOP
condition, even during the transmission of a byte. In this case, no acknowledge is
generated.

Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related
clock pulse is generated by the master. The transmitter releases the SDA line (HIGH)
during the acknowledge clock pulse. The receiver must pull down the SDA line during
the acknowledge clock pulse so that it remains stable LOW during the HIGH period of
this clock pulse. Set-up and hold times must also be taken into account. Usually, a
receiver which has been addressed is obliged to generate an acknowledge after each byte
has been received, except when the message starts with a CBUS address. When a slave
doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit
because it’s performing some real-time function), the data line must be left HIGH by the
slave. The master can then generate either a STOP condition to abort the transfer, or a
repeated START condition to start a new transfer.
If a slave-receiver does acknowledge the slave address but, some time
later in the transfer cannot receive any more data bytes, the master must again abort the
transfer. This is indicated by the slave generating the not-acknowledge on the first byte to
follow. The slave leaves the data line HIGH and the master generates a STOP or a
repeated START condition. If a master-receiver is involved in a transfer, it must signal
the end of data to the slave- transmitter by not generating an acknowledge on the last byte
that was clocked out of the slave. The slave-transmitter must release the data line to allow
the master to generate a STOP or repeated
START condition.

25
 Fig 13: Acknowledge condition on I2C bus

ARBITRATION AND CLOCK GENERATION

Synchronization
All masters generate their own clock on the SCL line to transfer messages
on the I2C-bus. Data is only valid during the HIGH period of the clock. A defined clock
is therefore needed for the bit-by-bit arbitration procedure to take place. Clock
synchronization is performed using the wired-AND connection of I2C interfaces to the
SCL line. This means that a HIGH to LOW transition on the SCL line will cause the
devices concerned to start counting off their LOW period and, once a device clock has
gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached.
However, the LOW to HIGH transition of this clock may not change the state of the SCL
line if another clock is still within its LOW period. The SCL line will therefore be held
LOW by the device with the longest LOW period. Devices with shorter LOW periods
enter a HIGH wait-state during this time.
When all devices concerned have counted off their LOW period, the clock
line will be released and go HIGH. There will then be no difference between the device
clocks and the state of the SCL line, and all the devices will start counting their HIGH
periods. The first device to complete its HIGH period will again pull the SCL line LOW.
In this way, a synchronized SCL clock is generated with its LOW period determined by
the device with the longest clock LOW period, and its HIGH period determined by the
one with the shortest clock HIGH period.

26
Arbitration
A master may start a transfer only if the bus is free. Two or more masters
may generate a START condition within the minimum hold time of the START condition
which results in a defined START condition to the bus. Arbitration takes place on the
SDA line, while the SCL line is at the HIGH level, in such a way that the master which
transmits a HIGH level, while another master is transmitting a LOW level will switch off
its DATA output stage because the level on the bus doesn’t correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits. If
the masters are each trying to address the same device, arbitration continues with
comparison of the data bits if they are master-transmitter or acknowledge-bits if they are
master-receiver. Because address and data information on the I2C-bus is determined by
the winning master, no information is lost during the arbitration process. A master that
loses the arbitration can generate clock pulses until the end of the byte in which it loses
the arbitration. As an Hs-mode master has a unique 8-bit master code, it will always
finish the arbitration during the first byte. If a master also incorporates a slave function
and it loses arbitration during the addressing stage, it’s possible that the winning master is
trying to address it. The losing master must therefore switch over immediately to its slave
mode.

To meet the demands for higher speeds, as well as make available more
slave address for the growing number of new devices, the Standard-mode I2C-bus
specification was upgraded over the years and today is available with the following
extensions:
 Fast-mode, with a bit rate up to 400 kbit/s.
 High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s.
 10-bit addressing, which allows the use of up to 1024 additional slave addresses.

27
 Fig 14: Connection of devices to I2C bus

I2C-bus compatible ICs allow a system design to rapidly progress directly

from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto
the I2C-bus without any additional external interfacing, they allow a prototype system to
be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

28
CHAPTER 4: FLOWCHARTS AND ALGORITHMS

4.1 FLOWCHART AND ALGORITHM FOR DS1307

Algorithm:
1. Initialize micro controller.
2. Make SCL and SDA lines high i.e. SCL=1, SDA=1.(initialization of I2C bus).
3. Make SCL and SDA lines low i.e. SCL=0, SDA=0. (Micro-controller holds I2C
bus for sending data).
4. Start bit is issued by the Micro-controller to slave i.e. SDA=1 indicating start of
data transfer. (Immediately SDA becomes low i.e. SDA=0).
5. Micro-controller puts the 8-bit id of device DS1307 on the I2C bus.
6. Micro-controller receives an acknowledgement from DS1307.
7. Master starts data transfer through SDA.
8. DS1307 sends an acknowledgement to the master indicating completion of
transfer.
9. Master sends a stop bit to the slave device i.e. SDA=1.
10. Master accesses or updates registers of DS1307.
11. Registers present in DS1307 are accessed by the master through I2C bus by
sending the locations of the registers.
12. Data received from REAL TIME CLOCK by master is displayed on LCD.

29
Fig 16: Flowchart to interface DS1307

30
4.3 FLOWCHART AND ALGORITHM FOR LCD UNIT

Algorithm:
1. Initialize micro controller.
2. Set EN=1 and RS=0 for command data.
3. Master sends 0x38 to initialize it in 8-bit mode, 5x7 character font, 16x2 display.
4. Master sends 0x0E to place cursor.
5. Master sends 0x06 to right shift cursor automatically.
6. Master sends 0x01 to clear LCD screen.
7. Set EN=1 and RS=1 for displaying data.
8. Master sends data through 8-bit data line connected to LCD.

31
Fig 18: Flowchart for working of LCD unit

32
CHAPTER 5: PROGRAMMING

5.1 INTRODUCTION TO RIDE

RIDE is a 32-bit Windows Integrated Development Environment (IDE),

which contains a set of development tools for 8051 and XA microcontroller applications.
This development environment includes color-coded syntax highlighting editor, a project
manager, on-line help, and provides all the facilities needed to call the different
RAISONANCE development tools. RIDE contains everything needed to write, edit,
compile, link and debug your microcontroller application, depending on the tool chain
used:
• Editor.

33
• Translation tools: Macro-Assemblers, C Compilers.
• Utility tools: Linker, Library Manager...
• Real Time Kernel.
• Debug tools: Simulator and/or Emulator.

RIDE requires the following minimum configuration:

• A Pentium processor (or better) running a 32-bit Microsoft operating system :
Operating System
Microsoft Windows 98, 2000, XP or NT
Memory Required
32 megabyte (MB) of RAM
• A hard-disk drive with 70 megabytes of free space. The actual space required depends
on the options you select. Additional space is needed for the source-code files and the
executable files created from them.

RIDE provides an integrated project manager, which includes a syntax-

highlighting text editor to manage, edit, and print source files. Most of the editor’s
procedures like file and text handling, and moving around in a file, are similar to other
Windows-based text editors.

34
Fig 20 : Snapshot of RIDE interface.

35
Fig 21 : Snapshot of main program and compilation message windows.

5.2 SOURCE CODE

36
;*****I2C IMPLEMENTATION***********
SCK BIT p3.0
SDA BIT P3.1

;****LCD INTERFACE**************
RS BIT P3.7 ;REGISTER SELECT
RW BIT P3.6 ;READ/WRITE
EN BIT P3.5 ;LCD ENABLE
WRITE_RTC EQU 0D0H
READ_RTC EQU 0D1H
FLAGS DATA 20H
LASTREAD BIT FLAGS.0
_12_24 BIT FLAGS.1
PM_AM BIT FLAGS.2
OSC BIT FLAGS.3
ACK BIT FLAGS.5
BUS_FAULT BIT FLAGS.6
_2W_BUSY BIT FLAGS.7
BITCOUNT DATA 21H
BYTECOUNT DATA 22H
BYTE DATA 23H

org 00
AJMP START

37
 org 30H

START:
MOV SP,#70H ; Position stack above buffer.

;******EXTERNAL INTERRUPTS FOR NEW REMINDER AND

VIEWING REMINDER

; MOV IE,#85H ;INT0->NEW REMINDER; INT1->VIEW

REMINDER

LCALL LCD_INIT

SETB SDA ; ENSURE SDA HIGH

LCALL SCL_HIGH ; ENSURE SCL HIGH
CLR ACK ; CLEAR STATUS FLAGS
CLR BUS_FAULT
CLR _2W_BUSY
SETB P3.2
;CLR P3.3
;clr p3.0
;clr p3.1
setb p0.7
MAIN_PROG:

LCALL READ_CLOCK

38
 LCALL DELAY
LCALL DELAY
LCALL DELAY
LCALL MATCH
LCALL MATCH1
JB P3.2,MAIN_PROG
MOV A,#01H
ACALL COMMAND
MOV DPTR, #TEXT0 ; PUT MAIN MENU ON SCREEN
LCALL WRITE_TEXT

LCALL SCANKEY

CJNE A,#'A',NOTA ; CALL SET CLOCK FUNCTION

LCALL SET_TIME
SJMP MAIN_PROG ; RETURN TO MAIN MENU

NOTA: CJNE A,#'B',NOTB

SJMP MAIN_PROG

NOTB: CJNE A,#'C',NOTC ; CALL READ CLOCK

FUNCTION
LCALL REMINDER_1
LCALL MATCH
SJMP MAIN_PROG ; RETURN TO MAIN MENU
NOTC: CJNE A,#'D',NOTD

39
 LCALL VIEW_REMINDER1
ACALL DELAY
ACALL DELAY
SJMP MAIN_PROG ; RETURN TO MAIN MENU
NOTD: CJNE A,#'E',NOTE
LCALL REMINDER_2
LCALL MATCH1
SJMP MAIN_PROG ; RETURN TO MAIN MENU
NOTE: CJNE A,#'F',NOTF
LCALL VIEW_REMINDER2
ACALL DELAY
ACALL DELAY
SJMP MAIN_PROG ; RETURN TO MAIN MENU
NOTF:
SJMP MAIN_PROG ; RETURN TO MAIN MENU

SCL_HIGH:
SETB SCK ; SET SCL HIGH
JNB SCK,$ ; LOOP UNTIL STRONG 1 ON SCL
RET

SET_TIME:
MOV A,#01H
ACALL COMMAND
MOV R1,#2EH ; SET R1 TO SCRATCHPAD
MEMORY FOR DATE/TIME

40
 MOV DPTR, #YEAR ; GET THE DATE/TIME
INFORMATION FROM THE
LCALL WRITE_TEXT ; USER. WRITE THE
DATE/TIME TO SCRATCHPAD
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA ; MEMORY
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #MONTH
LCALL WRITE_TEXT
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #DAY
LCALL WRITE_TEXT
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA

41
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #DAYW
LCALL WRITE_TEXT
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #HOUR
LCALL WRITE_TEXT
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #MINUTE
LCALL WRITE_TEXT

42
 MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA
MOV @R1,A
DEC R1
ACALL DELAY
MOV A,#01H
ACALL COMMAND
MOV DPTR, #SECOND
LCALL WRITE_TEXT
MOV A,#0C0H
ACALL COMMAND
LCALL READ_KEYBDATA
MOV @R1,A

MOV R1,#28H ; POINT TO BEGINNING OF CLOCK DATA

IN SCRATCHPAD MEMORY
LCALL I2C_START ; START CONDITION

MOV A,#WRITE_RTC ; DS1307 WRITE COMMAND

LCALL I2C_WRITE

MOV A,#00H ; SET DATA POINTER TO REGISTER 00H

ON
LCALL I2C_WRITE ; THE DS1307
SEND_LOOP:

43
 MOV A,@R1 ; MOVE THE FIRST BYTE OF DATA TO
ACC
LCALL I2C_WRITE
INC R1
CJNE R1,#2FH,SEND_LOOP ; LOOP UNTIL CLOCK DATA
SENT TO DS1307
LCALL I2C_STOP ; STOP CONDITION
RET

READ_CLOCK:

MOV R1,#28H ; START OF CLOCK REG IN

SCRATCHPAD
MOV BYTECOUNT,#00H ; COUNTER UP TO 8 BYTES
FOR CLOCK
CLR LASTREAD ; FLAG TO CHECK FOR LAST
READ
LCALL I2C_START ; SEND START CONDITION
MOV A,#WRITE_RTC ; SET POINTER TO REG 00H ON
DS1307
LCALL I2C_WRITE
MOV A,#00H
LCALL I2C_WRITE
LCALL I2C_STOP ; SEND STOP CONDITION

44
 LCALL I2C_START ; SEND START CONDITION
MOV A,#READ_RTC ; SEND READ COMMAND TO DS1307
LCALL I2C_WRITE
READ_LOOP:
MOV A,BYTECOUNT ; CHECK TO SEE OF DOING
LAST READ
CJNE A,#07H,NOT_LAST
SETB LASTREAD ; SET LASTREAD FLAG
NOT_LAST:
LCALL I2C_READ ; READ A BYTE OF DATA
MOV @R1,A ; MOVE DATA IN SCRATCHPAD
MEMORY
MOV A,BYTECOUNT
CJNE A,#00H,NOT_FIRST
CLR OSC ; CLR OSC FLAG
MOV A,@R1 ; MOVE SECONDS REG INTO ACC
JNB ACC.7,NO_OSC ; JUMP IF BIT 7 OF IS A 0
SETB OSC ; SET OSC FLAG, BIT 7 IS A 1
CLR ACC.7 ; CLEAR BIT 7 FOR DISPLAY
MOV @R1,A ; PURPOSES
NO_OSC:
NOT_FIRST:
INC R1 ; INC COUNTERS
INC BYTECOUNT
MOV A,BYTECOUNT
CJNE A,#08H,READ_LOOP ; LOOP FOR ENTIRE CLOCK
REGISTERS

45
 LCALL I2C_STOP ; SEND STOP CONDITION
LCALL DISP_CLOCK ; DISPLAY DATE/TIME FROM
SCRATCHPAD
RET

DISP_CLOCK:
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT1 ; DATE:
LCALL WRITE_TEXT
MOV R1,#2CH ; DAY
MOV A,@R1
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
MOV R1,#2DH ; MONTH
MOV A,@R1
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
MOV R1,#2EH ; YEAR
MOV A,@R1
LCALL WRITE_BCD
MOV A,#0C0H
LCALL COMMAND
MOV DPTR,#TEXT2 ; TIME:
LCALL WRITE_TEXT

46
 MOV R1,#2AH ; HOURS
MOV A,@R1
LCALL WRITE_BCD
MOV A,#':' ; COLON
LCALL DISPLAY
MOV R1,#29H ; MINUTES
MOV A,@R1
LCALL WRITE_BCD
MOV A,#':' ; COLON
LCALL DISPLAY
MOV R1,#28H ; SECONDS
MOV A,@R1
LCALL WRITE_BCD
RET

REMINDER_1:
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT3 ; REMINDER1:
LCALL WRITE_TEXT
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT1 ; DATE:
LCALL WRITE_TEXT
ACALL READ_KEYBDATA ;MONTH
MOV 40H,A
MOV A,#'/'

47
 LCALL DISPLAY
ACALL READ_KEYBDATA ;DAY
MOV 41H,A
MOV A,#'/'
LCALL DISPLAY
ACALL READ_KEYBDATA ;YEAR
MOV 42H,A
MOV A,#0C0H
LCALL COMMAND
MOV DPTR,#TEXT2 ; TIME:
LCALL WRITE_TEXT
ACALL READ_KEYBDATA
MOV 43H,A ; HOURS
MOV A,#':' ; COLON
LCALL DISPLAY
ACALL READ_KEYBDATA ;MINUTES
MOV 44H,A
MOV A,#':' ; COLON
LCALL DISPLAY
ACALL READ_KEYBDATA ;SECONDS
MOV 45H,A
RET

MATCH:
PUSH ACC
MOV A,45H
CJNE A,28H,N_MATCH

48
 MOV A,44H
CJNE A,29H,N_MATCH
MOV A,43H
CJNE A,2AH,N_MATCH
MOV A,42H
CJNE A,2EH,N_MATCH
MOV A,41H
CJNE A,2DH,N_MATCH
MOV A,40H
CJNE A,2CH,N_MATCH
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT4 ; ALARM
;setb p3.0
; clr p0.7
setb P1.0
setb P1.1
acall delay
;clr p3.2
;setb p3.3
; setb p0.7
LCALL WRITE_TEXT
N_MATCH:POP ACC
RET

VIEW_REMINDER1:
MOV A,#01H

49
ACALL COMMAND
PUSH ACC
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT1 ; DATE:
LCALL WRITE_TEXT
; DAY
MOV A,40H
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
; MONTH
MOV A,41H
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
; YEAR
MOV A,42H
LCALL WRITE_BCD
MOV A,#0C0H
LCALL COMMAND
MOV DPTR,#TEXT2 ; TIME:
LCALL WRITE_TEXT
; HOURS
MOV A,43H
LCALL WRITE_BCD
MOV A,#':' ; COLON

50
 LCALL DISPLAY
; MINUTES
MOV A,44H
LCALL WRITE_BCD
MOV A,#':' ; COLON
LCALL DISPLAY
; SECONDS
MOV A,45H
LCALL WRITE_BCD
POP ACC
RET

REMINDER_2:
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT5 ; REMINDER2:
LCALL WRITE_TEXT
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT1 ; DATE:
LCALL WRITE_TEXT
ACALL READ_KEYBDATA ;MONTH
MOV 50H,A
MOV A,#'/'
LCALL DISPLAY
ACALL READ_KEYBDATA ;DAY
MOV 51H,A

51
 MOV A,#'/'
LCALL DISPLAY
ACALL READ_KEYBDATA ;YEAR
MOV 52H,A
MOV A,#0C0H
LCALL COMMAND
MOV DPTR,#TEXT2 ; TIME:
LCALL WRITE_TEXT
ACALL READ_KEYBDATA
MOV 53H,A ; HOURS
MOV A,#':' ; COLON
LCALL DISPLAY
ACALL READ_KEYBDATA ;MINUTES
MOV 54H,A
MOV A,#':' ; COLON
LCALL DISPLAY
ACALL READ_KEYBDATA ;SECONDS
MOV 55H,A
RET

MATCH1:
PUSH ACC
MOV A,55H
CJNE A,28H,N_MATCH1
MOV A,54H
CJNE A,29H,N_MATCH1
MOV A,53H

52
 CJNE A,2AH,N_MATCH1
MOV A,52H
CJNE A,2EH,N_MATCH1
MOV A,51H
CJNE A,2DH,N_MATCH1
MOV A,50H
CJNE A,2CH,N_MATCH1
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT8 ; ALARM
;setb p3.3
;clr p3.0
;clr p3.2
; clr p0.7
clr P1.0
clr P1.1
acall delay

; setb p0.7
LCALL WRITE_TEXT
N_MATCH1:POP ACC
RET

VIEW_REMINDER2:
MOV A,#01H
ACALL COMMAND
PUSH ACC

53
MOV A,#01H
ACALL COMMAND
MOV DPTR,#TEXT1 ; DATE:
LCALL WRITE_TEXT
; DAY
MOV A,50H
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
; MONTH
MOV A,51H
LCALL WRITE_BCD
MOV A,#'/'
LCALL DISPLAY
; YEAR
MOV A,52H
LCALL WRITE_BCD
MOV A,#0C0H
LCALL COMMAND
MOV DPTR,#TEXT2 ; TIME:
LCALL WRITE_TEXT
; HOURS
MOV A,53H
LCALL WRITE_BCD
MOV A,#':' ; COLON
LCALL DISPLAY
; MINUTES

54
 MOV A,54H
LCALL WRITE_BCD
MOV A,#':' ; COLON
LCALL DISPLAY
; SECONDS
MOV A,55H
LCALL WRITE_BCD
POP ACC
RET

WRITE_BCD:
MOV R5,A
ANL A,#0F0H
RR A
RR A
RR A
RR A
MOV R4,#30H
ORL A,R4
ACALL DISPLAY
MOV A,R5
ANL A,#0FH
MOV R7,#30H
ORL A,R7
ACALL DISPLAY
RET

55
I2C_START:
SETB _2W_BUSY ; INDICATE THAT 2WIRE OPERATION IN
PROGRESS
CLR ACK ; CLEAR STATUS FLAGS
CLR BUS_FAULT
JNB SCK,FAULT ; CHECK FOR BUS CLEAR
JNB SDA,FAULT ; BEGIN START CONDITION
SETB SDA ;
LCALL SCL_HIGH ; SDA
CLR SDA
LCALL DELAY ; SCL ^START CONDITION
CLR SCK
RET
FAULT:
SETB BUS_FAULT ; SET FAULT STATUS
RET

I2C_STOP:
CLR SDA ; SDA
LCALL SCL_HIGH ;
SETB SDA ; SCL ^STOP CONDITION
CLR _2W_BUSY
RET

I2C_READ:

56
 MOV BITCOUNT,#008H ; SET COUNTER FOR 8 BITS OF
DATA
MOV A,#00H
SETB SDA ; SET SDA HIGH TO ENSURE LINE FREE
READ_BITS:
LCALL SCL_HIGH ; TRANSITION SCL LOW-TO-HIGH
MOV C,SDA ; MOVE DATA BIT INTO CARRY BIT \
RLC A ; ROTATE CARRY BIT INTO ACC.0
CLR SCK ; TRANSITION SCL HIGH-TO-LOW
DJNZ BITCOUNT,READ_BITS ; LOOP FOR 8 BITS
JB LASTREAD,ACKN ; CHECK TO SEE IF THIS IS THE
LAST READ
CLR SDA ; IF NOT LAST READ SEND ACKNOWLEDGE
BIT
ACKN:
LCALL SCL_HIGH ; PULSE SCL TO TRANSIMIT
ACKNOWLEDGE
CLR SCK ; OR NOT ACKNOWLEDGE BIT
RET

I2C_WRITE:
MOV BITCOUNT,#08H ; SET COUNTER FOR 8 BITS
SB_LOOP:
JNB ACC.7,NOTONE ; CHECK TO SEE IF BIT 7 OF ACC IS A
1
SETB SDA ; SET SDA HIGH (1)

57
 JMP ONE
NOTONE:
CLR SDA ; CLR SDA LOW (0)
ONE:
LCALL SCL_HIGH ; TRANSITION SCL LOW-TO-HIGH
RL A ; ROTATE ACC LEFT ONE BIT
CLR SCK ; TRANSITION SCL HIGH-TO-LOW
DJNZ BITCOUNT,SB_LOOP ; LOOP FOR 8 BITS
SETB SDA ; SET SDA HIGH TO LOOK FOR
ACKNOWLEDGE PULSE
LCALL SCL_HIGH ; TRASITION SCL LOW-TO-HIGH
CLR ACK ; CLEAR ACKNOWLEDGE FLAG
JNB SDA,SB_EX ; CHECK FOR ACK OR NOT ACK
SETB ACK ; SET ACKNOWLEDGE FLAG FOR NOT ACK
SB_EX:
LCALL DELAY ; DELAY FOR AN OPERATION
CLR SCK ; TRANSITION SCL HIGH-TO-LOW
LCALL DELAY ; DELAY FOR AN OPERATION
RET

READ_KEYBDATA:
MOV R4,#0 ; CLEAR R0
LCALL SCANKEY ; READ BYTE FROM KEYBOARD
ANL A,#0FH ; ENSURE BITS 4-7 ARE CLEARED
SWAP A
MOV R4,A
LCALL SCANKEY

58
 ANL A,#0FH
ORL A,R4 ; INSERT BITS 0-3 OF R0 INTO ACC
RET

SCANKEY:
MOV P2,#0F0H
MOV A,P2
ANL A,#0F0H
CJNE A,#0F0H,SCANKEY
TP1:ACALL DEBOUNCE
MOV A,P2
ANL A,#0F0H
CJNE A,#0F0H,TP2
SJMP TP1
TP2:ACALL DEBOUNCE
MOV A,P2
ANL A,#0F0H
CJNE A,#0F0H,NXT
SJMP TP2
NXT:CLR P2.0
SETB P2.1
SETB P2.2
SETB P2.3
MOV A,P2
ANL A,#0F0H
CJNE A,#0E0H,NXT1
MOV A,#'0'

59
 ACALL DISPLAY
LJMP TP
NXT1:CJNE A,#0D0H,NXT2
MOV A,#'1'
ACALL DISPLAY
LJMP TP
NXT2:CJNE A,#0B0H,NXT3
MOV A,#'2'
ACALL DISPLAY
LJMP TP
NXT3:CJNE A,#70H,LOP
MOV A,#'3'
ACALL DISPLAY
LJMP TP

LOP:SETB P2.0
CLR P2.1
SETB P2.2
SETB P2.3
MOV A,P2
ANL A,#0F0H
CJNE A,#0E0H,LOP1
MOV A,#'4'
ACALL DISPLAY
LJMP TP
LOP1:CJNE A,#0D0H,LOP2
MOV A,#'5'

60
 ACALL DISPLAY
LJMP TP
LOP2:CJNE A,#0B0H,LOP3
MOV A,#'6'
ACALL DISPLAY
LJMP TP
LOP3:CJNE A,#70H,TYP
MOV A,#'7'
ACALL DISPLAY
LJMP TP

TYP:SETB P2.0
SETB P2.1
CLR P2.2
SETB P2.3
MOV A,P2
ANL A,#0F0H
CJNE A,#0E0H,TYP1
MOV A,#'8'
ACALL DISPLAY
LJMP TP
TYP1:CJNE A,#0D0H,TYP2
MOV A,#'9'
ACALL DISPLAY
LJMP TP
TYP2:CJNE A,#0B0H,TYP3
MOV A,#'A'

61
 ACALL DISPLAY
LJMP TP
TYP3:CJNE A,#70H,LOOP
MOV A,#'B'
ACALL DISPLAY
LJMP TP

LOOP:SETB P2.0
SETB P2.1
SETB P2.2
CLR P2.3
MOV A,P2
ANL A,#0F0H
CJNE A,#0E0H,LOOP1
MOV A,#'C'
ACALL DISPLAY
LJMP TP
LOOP1:CJNE A,#0D0H,LOOP2
MOV A,#'D'
ACALL DISPLAY
LJMP TP
LOOP2:CJNE A,#0B0H,LOOP3
MOV A,#'E'
ACALL DISPLAY
LJMP TP
LOOP3:CJNE A,#70H,TP
MOV A,#'F'

62
 ACALL DISPLAY
TP:RET

WRITE_TEXT:
PUSH ACC ; SAVE ACC BYTE ON STACK
WT1:
CLR A ; CLEAR ACC
MOVC A,@A+DPTR ; MOVE FIRST BYTE OF STRING
; TO ACC
INC DPTR ; INC DATA POINTER
CJNE A,#0,WT2 ; CHECK FOR STRING
; TERMINATOR - 0
POP ACC ; RESTORE ACC
RET ; RETURN WHEN STRING IS SENT
WT2:
LCALL DISPLAY ; SEND BYTE OF STRING OVER SERIAL
PORT
SJMP WT1

LCD_INIT:
MOV A,#01H
ACALL COMMAND
MOV A,#38H
ACALL COMMAND
MOV A,#0eH
ACALL COMMAND

63
 MOV A,#06H
ACALL COMMAND
MOV A,#80H
ACALL COMMAND
RET

COMMAND:
MOV P0,A
CLR RS
CLR RW
SETB EN
CLR EN
ACALL DELAY
RET

DISPLAY:
MOV P0,A
SETB RS
CLR RW
SETB EN
CLR EN
ACALL DELAY
RET
DELAY:
MOV R6,#020H
EXT1:MOV R7,#0FFH
EXT:DJNZ R7,EXT

64
 DJNZ R6,EXT1
RET

I2C_DELAY:
MOV R6,#0FFH
EXT5:MOV R7,#0FFH
EXT4:DJNZ R7,EXT4
DJNZ R6,EXT5
RET

DEBOUNCE:
MOV R6,#0DBH
EXT3:MOV R7,#0E5H
EXT2:DJNZ R7,EXT2
DJNZ R6,EXT3
RET

YEAR:
DB 'YEAR (0 - 99) : ',0
MONTH:
DB 'MONTH (1 - 12) : ',0
DAY:
DB 'DAY OF MONTH : ',0
DAYW:
DB 'DAY OF WEEK : ',0
HOUR:

65
DB 'HOUR (0 - 23) : ',0
MINUTE:
DB 'MINUTE (0 - 59) : ',0
SECOND:
DB 'SECOND (0 - 59) : ',0
TRIER:
DB 'PRESS ANY KEY TO SET THIS TIME ',0
TEXT0:
DB ' EVENT SCHEDULER '
;DB 'PLEASE CHOOSE AN OPTION TO CONTINUE '
;DB '------------------------------------ '
DB 'A. SET TIME(MANUAL)'
DB 'B. REPEATED TASK'
DB 'C. SET REMINDER_1'
DB 'D. VIEW REMINDER_1'
DB 'E. SET REMINDER_2'
DB 'F. VIEW REMINDER_2'
TEXT1:
DB 'DATE: ',0
TEXT2:
DB 'TIME: ',0
TEXT3:
DB 'REMINDER1',0
TEXT4:
DB '****EVENT1***',0
TEXT5:
DB 'REMINDER2',0

66
TEXT6:
DB 'REPEATED TASK',0
TEXT7:
DB 'SECONDS',0
TEXT8:
DB '****EVENT2****',0

END
CHAPTER 6: CONCLUSIONS

6.1 ADVANTAGES

1. Size and simplicity of the design.

2. Since semiconductor ICs are used the circuit has a wide voltage range and
temperature range.
3. Since ICs are used to measure temperature and time the accuracy of the circuit is
greatly increased.
4. Pertaining to its design the circuit has tolerance towards mechanical shocks and
vibrations.
5. The power consumption of the circuit is of the order of milli watts and hence can
be operated on battery pack if required.
6. Owing to the use of I2C protocol to interface ICs to micro-controller, it is very
easy to modify or extend the design.

6.2 LIMITATIONS

1. The heat dissipated from the circuit is relatively more compared to circuits
containing passive devices.

67
 2. Since the semiconductors ICs are sensitive to temperature this places limitations
on the operating temperature range of the whole circuit.

6.3 RESULTS

The circuit has been designed to be operated in three modes. They are:
Mode 1 - CLOCK MODE: Circuit acts as a real time clock and displays time, day and
date. .

1 1 : 3 0 : 0 0 M O N
2 6 / 0 3 / 2 0 0 6

Fig 22: Example of LCD Display in clock mode

68