Signed number, twos complement-Arithmetic

operations
Booth Multiplier
Division-
 Basic division algorithm
Digit Recurrence Algorithm
Restoring Division
Non-Restoring Division
SRT Division (Sweeney, Robertson, and Tocher)
Multiplicative Algorithm
Approximation Algorithms
CORDIC Algorithm
Continued Product Algorithm
Useful site
http://www.ecs.umass.edu/ece/koren/arith/simulator
Definition and notations
 Restoring division
Put x in register A, d in register B, 0 in register P, and perform n divide
steps (n is the quotient word length)

Each step consists of

(i) Shift the register pair (P,A) one bit left
(ii) Subtract the contents of B from P, put the result back in P
(iii) If the result is -ve, set the low-order bit of A to 0 otherwise to 1
(iv) If the result is -ve, restore the old value of P by adding the
contents of B back in P
Restoring division (contd..)
Initially0 0 0
0 0 1 0 0 0
0 0 0
1 1
Shift 0 0 0
0 1 0 0 0
Subtract 1 1 1
0 1 First cycle
Set q0 1 1 1
1 0
Restore 1 1
10 0 0 0 0 1 0 0 0 0
Shift 0 0 0 1 0 0 0 0
11 1000
11 Subtract 1 1 1 0 1
Set q0 1 1 1 1 1 Second cycle
10
Restore 1 1
0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Third cycle

Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1
Fourth cycle
Restore 1 1
0 0 0 1 0 0 0 1 0

Remainder Quotient

7
 Restoring division

-3 -3
Non Restoring division
Non-restoring division (contd..)
Initially0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0 First cycle
Subtract 1 1 1 0 1
Set q0 1 1 1 1 0 0 0 0 0

Shift 1 1 1 0 0 0 0 0
Add 0 0 0 1 1 Second cycle
10 Set q0 1 1 1 1 1 0 0 0 0
11 1000
11 Shift 1 1 1 1 0 0 0 0
10 Add 0 0 0 1 1 Third cycle
Set q0 0 0 0 0 1 0 0 0 1

Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourth cycle
Set q0 1 1 1 1 1 0 0 1 0

Quotient
1 1 1 1 1
Add 0 0 0 1 1 Restore
0 0 0 1 0 remainder

Remainder
10
 Non Restoring division

-3

-3-
 Basic Architecture
Control unit and Processor
datapath Control unit Datapath

Note similarity to ALU

Controller Control
single-purpose /Status
processor
Registers
Key differences
Datapath is general
PC IR
store the algorithm
the algorithm is
I/O
Memory
memory
 Datapath Operations
Load
Read memory location Processor
into register Control unit Datapath

ALU
Controller Control +1
ALU operation /Status

Input certain registers Registers

through ALU, store
back in register
10 11
PC IR
Store
Write register to
I/O
memory location ...
Memory
10
11
...
 Control Unit
Control unit: configures the datapath
operations Processor
Sequence of desired operations Control unit Datapath

ALU
Controller Control
Instruction cycle broken into /Status
several sub-operations, each one
clock cycle, e.g.: Registers
Fetch: Get next instruction into IR
Decode: Determine what the
instruction means
Fetch operands: Move data from PC IR R0 R1
memory to datapath register
Execute: Move data through the
ALU I/O
Store results: Write data from 100 load R0, M[500] Memory
...
register to memory 500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 compute
jump/branch
targets

memory register alu

file

+4
addr
PC control din dout
memory
extend
new
forward
pc detect
unit
hazard
Instruction Instruction Write-
Fetch Decode Execute Memory Back
IF/ID ID/EX EX/MEM MEM/WB
 C int x = 10;
compiler x = 2 * x + 15;
r0 = 0
MIPS
addi r5, r0, 10 r5 = r0 + 10
assembly muli r5, r5, 2 r5 = r5<<1 #r5 = r5 * 2
assembler addi r5, r5, 15 r5 = r15 + 15
op = addi r0 r5 10
machine 00100000000001010000000000001010
code 00000000000001010010100001000000
00100000101001010000000000001111
op = addi r5 r5 15
CPU
op = r-type r5 r5 shamt=1 func=sll
Circuits

Gates

Transistors
16
Silicon
 C int x = 10;
compiler x = 2 * x + 15;
High Level
MIPS Languages
addi r5, r0, 10
assembly muli r5, r5, 2
assembler addi r5, r5, 15

machine 00100000000001010000000000001010
code 00000000000001010010100001000000
00100000101001010000000000001111
CPU Instruction Set
Architecture (ISA)
Circuits

Gates

Transistors
17
Silicon
 Machine Instruction
Characteristics
The operation of the processor is determined by the
instructions it executes, referred to as machine instructions or
computer instructions

The collection of different instructions that the processor can

execute is referred to as the instruction set

Each instruction must contain the information required by the

processor for execution
Elements of a Machine Instruction
Operation code Source operand
(opcode) reference
Specifies the operation The operation may
to be performed. The involve one or more
operation is specified by source operands, that
a binary code, known as is, operands that are
the operation code, or
opcode inputs for the
operation

Result operand Next instruction

reference reference
The operation may This tells the processor
produce a result where to fetch the next
instruction after the
execution of this
instruction is complete
 Instruction Representation

Within the computer each instruction is represented by a

sequence of bits
The instruction is divided into fields, corresponding to the
constituent elements of the instruction

4 bits 6 bits 6 bits

Opcode Operand Reference Operand Reference

16 bits

Figure 10.2 A Simple Instruction Format

Figure 12.2 A Simple Instruction Format

Instruction Representation
Opcodes are represented by abbreviations
called mnemonics
Examples include:
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory

Operands are also represented symbolically

Each symbolic opcode has a fixed binary representation

The programmer specifies the location of each symbolic
operand
 Instruction Representation
In machine code each instruction has a unique
bit pattern
For human consumption (well, programmers
anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD
Operands can also be represented in this way
ADD A,B
ADD R,Y
 Source and result operands can be in
one of four areas:
1) Main or virtual memory
As with next instruction references,
the main or virtual memory address
must be supplied
2) I/O device
The instruction must specify the I/O
module and device for the operation.
If memory-mapped I/O is used, this
is just another main or virtual
memory address
3) Processor register
A processor contains one or more
registers that may be referenced
by machine instructions.
If more than one register exists
each register is assigned a unique
name or number and the
instruction must contain the
number of the desired register
4) Immediate
The value of the operand is
contained in a field in the
instruction being executed
Types of Operands
 Numbers
All machine languages include numeric data types
Numbers stored in a computer are limited:
Limit to the magnitude of numbers representable on a machine
In the case of floating-point numbers, a limit to their precision

Three types of numerical data are common in computers:

Binary integer or binary fixed point
Binary floating point
Decimal

Packed decimal
Each decimal digit is represented by a 4-bit code with two digits stored per byte
To form numbers 4-bit codes are strung together, usually in multiples of 8 bits
 Characters
A common form of data is text or character strings
Textual data in character form cannot be easily stored or transmitted by
data processing and communications systems because they are designed
for binary data
Most commonly used character code is the International Reference
Alphabet (IRA)
Referred to in the United States as the American Standard Code for
Information Interchange (ASCII)

Another code used to encode characters is the Extended Binary Coded

Decimal Interchange Code (EBCDIC)
EBCDIC is used on IBM mainframes
 Logical Data
An n-bit unit consisting of n 1-bit items of data, each item having the
value 0 or 1
Two advantages to bit-oriented view:
Memory can be used most efficiently for storing an array of Boolean or
binary data items in which each item can take on only the values 1
(true) and 0 (false)
To manipulate the bits of a data item
o If floating-point operations are implemented in software, we need
to be able to shift significant bits in some operations
o To convert from IRA to packed decimal, we need to extract the
rightmost 4 bits of each byte
Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand

Data
address operation address address
Operation
calculation decoding calculation calculation

Return for string

Instruction complete, or vector data
fetch next instruction

Figure 12.1 Instruction Cycle State Diagram

 Terminology
Instruction address calculation (iac)
Determine the address of the next instruction
to be executed.
Instruction fetch (if)
Read instruction from its memory location into the
processor
Instruction operation decoding (iod)
Analyze instruction to determine type of
operation to be performed and operand(s) to
be used.
 Terminology
Operand address calculation (oac)
If the operation involves reference to an operand in
memory or available via I/O, then determine the
address of the operand.
Operand fetch (of)
Fetch the operand from memory or read it in
from I/O.
Data operation (do)
Perform the operation indicated in the instruction.
Operand store (os)
Write the result into memory or out to I/O.
 Control Unit Sub-Operations
Fetch Processor
Control unit Datapath
Get next ALU
instruction into IR Controller Control
/Status
PC: program
Registers
counter, always
points to next
instruction PC 100 IR
load R0, M[500]
R0 R1

IR: holds the

I/O
fetched instruction 100 load R0, M[500] Memory
...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Control Unit Sub-Operations
Decode Processor
Control unit Datapath
Determine what ALU

the instruction Controller Control

/Status

means Registers

PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Control Unit Sub-Operations
Fetch operands Processor
Control unit Datapath
Move data from ALU

memory to Controller Control

/Status

datapath register Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Control Unit Sub-Operations
Execute Processor
Control unit Datapath
Move data ALU

through the ALU Controller Control

/Status

This particular Registers

instruction does
nothing during PC 100 IR R0
10
R1
load R0, M[500]
this sub-
operation I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Control Unit Sub-Operations
Store results Processor
Control unit Datapath
Write data from ALU

register to Controller Control

/Status

memory Registers

This particular
instruction does PC 100 IR R0
10
R1
load R0, M[500]
nothing during
this sub- I/O
...
operation 100 load R0, M[500]
101 inc R1, R0
Memory
500 10
501
102 store M[501], R1 ...
 Instruction Cycles
PC=100 Processor

Fetch Decode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control
/Status

Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Instruction Cycles
PC=100 Processor

Fetch Decode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control +1
/Status

PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 101 IR R0 R1
inc R1, R0

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0 501
102 store M[501], R1 ...
 Instruction Cycles
PC=100 Processor

Fetch Decode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control
/Status

PC=101
Registers
Fetch Decode Fetch Exec. Store
ops results
clk
10 11
PC 102 IR R0 R1
store M[501], R1
PC=102
Fetch Decode Fetch Exec. Store I/O
ops results ...
100 load R0, M[500] Memory
clk 500 10
101 inc R1, R0 501 11
102 store M[501], R1 ...
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