Design of Hybrid Encoded Booth Multiplier with
Reduced Switching Activity Technique and Low
Power 0.13µm Adder for DSP Block in Wireless
Sensor Node
S.Saravanan Department of
ECE, K.S.R.College of
Technology Tiruchengode-
637215, India.
saravanan.nivi@gmail.com
Abstract-This paper explores the design approach of a
low power Hybrid Encoded Booth Multiplier (HEBM) with
Reduced Switching Activity Technique (RSAT) and low
power 0.13µm adder for DSP functions that encounter a
wide diversity of operating scenarios in battery powered low
power wireless sensor network system. This RSAT approach has
been applied on the hybrid encoder of the multiplier to
reduce the power consumption. The hybrid encoder in the
low power multiplier uses both the Booth and proposed
technique. If the number of 1’s less than or equal to three the
proposed encoding technique used otherwise go for Booth
technique. The proposed adder cell used in the multiplier
block consumes less power than the other previous adder
techniques. The switching activity of the proposed multiplier has
been reduced by 86% and 46% compared with conventional
and Booth multiplier respectively. It is observed from the
device level simulation using TANNER 12.6 EDA that the
power consumption of the proposed multiplier has been
reduced by 87% and 26% compared with conventional
and Booth multiplier.
Keywords-low power, Hybrid Encoded Booth Multiplier,
RSAT, wireless sensor node.
I. INTRODUCTION
Wireless sensor networks are composed of a set of
autonomous microsystems scattered in a specific
environment. Each node monitors physical quantities of its
close environment and the measured data are stored and then
sent through the self organized network to a base
station. Main applications of these sensor networks are
monitoring of environmental physical quantities such as
temperature, humidity or vibrations in different places such
as buildings, industries or automotive environments. Low
power and low energy VLSI circuits have become an
important issue in today's consumer electronics.
The number of embedded devices that must run
with battery power or parasitic power are increased. The
traditional approaches for designing these systems vary
according to the need of low power design. Improving the
performance and reduce the power consumption of the
circuit designs are having the challenges in low power
VLSI Design. The energy
978-1-4244-5137-1/10/$26.00 ©2010 IEEE
M.Madheswaran
Department of ECE
Muthayammal Engineering College
Rasipuram-647408, India
madheswaran.dr@gmail.com
efficient Digital Signal Processing (DSP) modules are
becoming necessary in wireless sensor networks, in which
tens to thousands of battery operated micro sensor nodes are
deployed remotely and used to relay sensing data to the end
user [1-4]. The DSP functions mostly make use of the
Multiply and Accumulate (MAC) operation in which the
multiplication function is the most power consuming task. It is
essential to implement the power-efficient multipliers for low
power DSP modules. The development of multiplier with
short critical path and low power consumption has become the
important area of investigation. The inclusion of multiplying
capabilities to processor architecture can provide increase in
performance for low power wireless multimedia and DSP
applications. These DSP applications may be Fourier
Transform (FFT), Discrete Cosine Transform (DCT),
quantization, or neural networks. It is well known that the
clamp down approach of dynamic power which is the
major part of total power dissipation may provide
significant reduction in power consumption. This can be
achieved by minimizing the transition capacitance.
The reduction of dynamic power consumption by
minimizing the switched capacitance has been reported by
many researchers [5-11]. Choi et al [5] proposed Partially
Guarded Computation (PGC) which divides the arithmetic
units such as adders and multipliers into two parts, and freeze
the unused part to minimize the power consumption. The
reported results show that the PGC can reduce power
consumption by 10% to 44% in an array multiplier with
30% to 36% area overhead in speech related applications.
A 32-bit 2’s complement adder equipping a Dynamic-
Range Determination (DRD) unit and a sign-extension unit
was reported by Chen et al [6]. This design tends to
reduce the power dissipation of conventional adders for
multimedia applications. Chen et al [7] presented a
multiplier using the DRD unit to select the input operand
with a smaller effective dynamic range to yield the Booth
codes and it saves 30% power dissipation than
conventional ones. Benini et al [8] reported that, the
technique for glitching power minimization by replacing
some existing gates with functionally equivalent one. This
saves 6.3% of total power dissipation since it operates in
the layout level environment which is tightly restricted. The
double-switch circuit-block switch scheme
ICWCSC 2010X
capable of reducing power dissipation during down time by
shortening the settling time after reactivation was proposed
by Henzler [9]. Huang et [10] also presented the
arithmetic details about the signal gating schemes and
illustrates 10% to
45% power reduction for adders. The combination of the
signal flow optimization (SFO), left-to-right leapfrog (LRLF)
structure, and upper/lower split structure was incorporated
in the design to optimize the array multipliers by Huang [11]
and it is reported that the new approach can save about
20% power dissipation. Wen et al [12] reported that the
turning off some columns in the multiplier array
whenever their outputs are known can save 10% power
consumption for random inputs. K.H.Chen [13] reported that
the spurious power suppression technique has been applied
on both compression tree and modified Booth encoder to
enlarge the
power reduction. Full adder is the core element of complex
arithmetic units like addition, multiplication, division,
exponentiation and MAC units reported by U.Ko [14] and
P.J.Song [15]. Several varieties of static CMOS logic styles
have been used to implement low-power one bit adder cells. Figure 1. The micro sensor network consists of hundreds to thousands of
In general, they can be broadly divided into two major nodes and individual node consists of an array of sensors, A/D
conversion, DSP and radio transceiver.
categories: the complementary CMOS and the pass-
transistor logic circuits.
In practice, however the actual inputs to the multiplier are
The complementary CMOS full adder is based on the typically less such as 8 bit. Calculating an 8-bit multiplication
regular CMOS structure with pMOS pull-up and nMOS pull- on a 64-bit multiplier can lead to serious energy inefficiencies
down transistors was reported by A. Shams [16]. The due to unnecessary digital switching on the high bits. The
complementary pass transistor logic full adder with swing input bit size variation of the multiplication is a source of
restoration structure uses 32 transistors was reported by A. P. operational diversity and large monolithic
Chandrakasan [17]. The basic difference between the multiplier circuits are insufficiently power
pass- transistor logic and the complementary CMOS logic aware. An architectural solution to high input bit width
styles is that the source side of the pass logic transistor diversity is the incorporation of additional smaller multipliers
network is connected to some input signals instead of the of varying sizes, as shown in Fig 2.
power lines. The advantage is that one pass-transistor network
is sufficient to implement the logic function, which results in
smaller number of transistors and smaller input load. A
Transmission Function full Adder (TFA) based on the
transmission function theory was presented by N. Zhuang
[18]. N.Weste [19] presented a Transmission Gate Adder
(TGA) using CMOS transmission gates circuit is a special
kind of pass-transistor logic circuit. Chang et al [20] proposed
a hybrid style full adder circuit in which the sum and carry
generation circuits are designed using hybrid logic styles.
In order to improve the performance of the multiplier in this
paper, low power multiplier architecture with reduced
switching activity technique has been introduced. This
multiplier can be used in the DSP blocks of the wireless
sensor nodes.

II. WIRELESS SENSOR NETWORK

In a Wireless Sensor Network (WSN) the node consists

of four major components: sensing, data processing,
communicating and power supply as shown in Fig. 1. A
node’s digital signal processing circuits are typically used for
digital signal processing of collected data and implementation
of the protocol stack. Today CMOS circuits become complete
digital systems through the combination of functional units,
like adders, multipliers and memory cells. These are
the fundamental building blocks of DSP and microcontrollers
Figure 2. The ensemble of different size multipliers
for protocol stacks. Multiplier circuits are typically designed
for a fixed maximum operand size, such as 64 bit.
 The ensemble routes each pair of incoming operands to
the smallest multiplier that can compare the result to
take advantage of the lower energy consumption of the
smaller circuit. Incoming multiplications are routed to the
smallest multiplier that can compute the result, reducing the
energy overhead of unused bits. An ensemble of point
systems, each of which is energy efficient for a small range of
inputs, takes the place of a single system whose energy
consumption does not scale as gracefully with input. The
power consumption has been reduced further by using the
proposed low power multiplier and low power adder. This
proposed multiplier uses hybrid encoding technique and
reduced switching activity technique.
III. HYBRID ENCODED BOOTH MULTIPLIER
The proposed hybrid encoded low power
multiplier basic block diagram has been shown in Figure 3.
It consists of three major working units as hybrid encoder,
multiplier and controller. Consider a 16 bit encoding if the
number of 1’s in the multiplier less than or equal to three,
consider the entire 16 bit other wise go for 8 bit encoding.
Now the 16 bit is separated in to two 8 bit and again check for
three
1’s. If the condition is satisfied control goes to the proposed
technique other wise control goes to modified Booth encoding.
In the Partial Product (PP) compression the row bypassing has
been used when the entire row of the PP is zero. This is done
by freeze the adder at that time of the above scene occurs and
it will avoid the unwanted switching activity and save power.
In the adder unit a column bypassing provision is available to
avoid the unwanted addition operation where ever it’s
possible. The detection logic circuit used to detect the effective
data range. When a portion of data does not affect the
final
computing results, the data controlling circuit latch this portion
to avoid useless data transitions. A glue circuit has been used
to control the carry and sign extension unit which will manage
the sign.

ENCODING MULTIPLICATION CONTROLING

Multiplie Multiplicand Multiplicand Multiplier

r

PP Generator
Proposed Detection Logic
Recode Encoder
Selector PP Compression

Booth Encoder
Asserting Circuit
Row
Bypassing

Glue Circuit
Final Adder with
Column Bypassing
Sign Extension

Register

Category
Number of
1's in the multiplier PRODUCT
Position of the 1
Figure 3. Block diagram of proposed hybrid encoded low power multiplier
Operation
 1
1st bit
Add 0 to Multiplicand (M)
B
Here a new hybrid encoding
1 scheme has been proposed IV. LOW POWER ADDER CIRCUIT DESIGN
as shown in the following Table I. According to the number
ith bit The proposed full adder cell is shown in Figure 5
of one’s and the position of 1 presented in the multiplier, the
operation
Shift M left by i-1 and can
add be
0 defined. which consists of both sum and carry circuit. The sum and
carry circuit are designed according to the following
C equations.
TABLE I. HYBRID ENCODING SCHEME Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8.
2
1st and ith C = AB + BC + CA (1)
bit
S = A′B′C + A′BC ′ + AB′C ′ + (2)
Shift M left by i-1 and add M ABC
D

2
th
i and
i+jth bit
Shift M left by j , add M and shift the result left by i-1

h st th
=1 , j
and kth bit

hift M by k-j , add M and shift the result left by j-i, add M and shift the result left by i-1

For example according to category A, number of 1’s in
the multiplier has been one and 3 its position is first bit, the
result has been arrived by add zero to the multiplicand (M). If
the number of 1’s has been more than three then the
, j and multiplier split in to two and the same above process is
h th
Figure 5. The proposed full adder cell
Here a pull down nMOS transistor is connected near the
carry output which has been used to give the undistorted carry
output. In the above proposed adder four inverters are used ,

continued. The constant value 34 is now multiplied with the

kth bit the sum and carry circuits are joined together. Here the
neighbouring value 85 as shown in Figure 4. For this 0.13µm TSMC technology files were used for simulation.
multiplication it needs The output wave form of the full adder with pull down
hift M by k-j8 , add
partial products
M and shift thefor conventional
result multiplication
left by j-i, add andresult
M and shift the 4 left
transistor
by i is shown in Fig 6.
partial products for Booth recoding but only one partial
product is
enough for our proposed hybrid encoding method. Moreover
in our proposed technique no need for 2’s complement
process and virtual 0 which is to be placed as a first bit of
Booth recoding. By this the number of switching activity has
been reduced to12.5% and 25% compared with conventional
and Booth encoding respectively.
0 1 0 1 0 1 0 1 Multiplicand (85)

X 0 0 1 0 0 0 1 0 0 Multiplier (34)

+1 -2 +1 -2 Booth recoding (4PP)

Group 4 Proposed recoding (1PP)

1 0 1 1 0 1 0 0 1 0 1 0 Result (2890)
Figure 6. Output wave form of the full adder

Figure 4. Hybrid encoded multiplication

 V. RESULTS AND DISCUSSIONS Booth multiplier which needs 4PP and proposed multiplier
The various adder circuits like C-CMOS, CPL, TFA, which needs 1PP. The switching activity of the proposed
TGA, hybrid and proposed adders are simulated using the multiplier has been reduced by 86% and 46% compared with
TSPICE TANNER 12.6 EDA tool. The operating frequency is conventional and Booth multiplier respectively. The power
set at 100 consumption of the proposed multiplier has been reduced
MHz. The power and delay of above mentioned adders with by
supply voltage ranges from 0.8 V to 2.4 V are shown in the 87% and 26% compared with conventional and Booth
Table II for comparison. The excessive power dissipation and multiplier.
long delay are attributed to the threshold voltage drop
problem and the poor driving capability of some internal VI. CONCLUSON
nodes at input combinations that create non full-swing In this paper the design approach of a low power Hybrid
transitions. TFA and TGA have lesser transistor count but due Encoded Booth Multiplier (HEBM) with Reduced Switching
to the lack of drivability, additional buffers are required at Activity Technique (RSAT) and low power 0.13µm adder has
each output, been presented. This RSAT approach has been applied on the
which increase their short-circuit power as well as switching hybrid encoder of the multiplier to reduce the power
power. Hybrid is slightly faster than C-CMOS and as a result, consumption. The hybrid encoder in the low power multiplier
it exhibits smaller power-delay-product than C-CMOS except uses both the Booth and proposed technique. By this proposed
at very low voltage of 0.8 V. Despite being the fastest technique the number of partial products reduced. The
circuit, CPL consumes higher power than hybrid and C- proposed adder cell used in the multiplier block consumes less
CMOS because of its dual-rail structure and the substantial power than the other previous adder techniques. It is observed
number of internal nodes. It is shown that the proposed adder from the device level simulation using TANNER 12.6 EDA
cell consumes less power than the other adder cells in all the switching activity of the proposed multiplier has been
operating voltage ranges. reduced by 86% and 46% compared with conventional and
Booth multiplier respectively. The power consumption
TABLE II. POWER AND DELAY ANALYSIS OF DIFFERENT of the proposed multiplier has been reduced by 87% and 26%
ADDERS compared with conventional and Booth multiplier. This low
Vdd in volts power multiplier can be used in DSP functions that encounter
Adder type
0.8 1.2 1.6 2.0 2.4
a wide diversity of operating scenarios in battery powered low
power wireless sensor network system.
Power in µw
C-CMOS [16] 0.84 2.12 4.91 8.77 15.9 REFERENCES
CPL [17] 1.03 2.64 5.64 11.2 17.7
TFA [18] 1.50 3.60 6.25 10.6 17.6 [1] A. Wang and A.Chandrakasan, “Energy efficient DSPs for
wireless networks,” IEEE Signal Processing magazine vol. 19, no 4,
TGA [19] 1.49 3.30 6.12 10.0 16.5 pp.68-78, July 2002.
Hybrid [20] 0.92 2.35 4.75 8.71 15.9 [2] M. Bhardwaj, R.Min and P.Chandrasekaran, “Quantifying and
Proposed 0.39 1.33 1.83 3.90 4.36 enhancing power awareness of VLSI systems,” IEEE Transaction
on Very Large Scale Integration (VLSI) System, vol. 9, no.6,
Delay in ns pp.757-772, Dec. 2002.
C-CMOS [16] 1.42 0.53 0.33 0.27 0.24 [3] R.Min, M.Bhardwaj, S.H.Cho, N.Ickes, E.Shih, A.Wang and
CPL [17] 0.91 0.32 0.19 0.18 0.17 A.Chandrakasaran, “Energy-centric enabling technologies for
wireless sensor networks,” proceedings of IEE Wireless
TFA [18] 1.53 0.51 0.32 0.27 0.25 Communications, vol.9, no 4, pp.28- 39, Aug.2002.
TGA [19] 1.42 0.49 0.32 0.27 0.25 [4] A. Wang and A.P.Chandrakasan, “Energy- aware architectures for a
real-valued FFT implementation,”Proceedings of International
Hybrid [20] 1.40 0.48 0.32 0.26 0.23
Symposium on Low Power Electronics and Design, pp.360-365,
Proposed 2.16 1.06 0.56 0.27 0.26 August.
2003.
TABLE III. POWER AND DELAY ANALYSIS OF DIFFERENT [5] J. Choi, J. Jeon, and K. Choi, “Power minimization of functional units
MULTIPLIERS by partially guarded computation,” in Proceedings of
IEEE International Symposium on Low Power Electron. Devices, pp.
Multiplier Vdd in volts 131–136,
Parameter
type 0.8 1.2 1.6 2.0 2.4 2000.
Conventional Power (mw) 0.03 0.12 0.25 0.53 0.66 [6] O. Chen, R. Sheen, and S. Wang, “A low power adder operating
multiplier
Delay (ns) 11.2 4.17 2.77 2.29 1.93 on effective dynamic data ranges,” IEEE Transaction on Very Large
Scale Integration (VLSI) System, vol. 10, no.4, pp.435–453, Aug. 2002.
Booth Power (mw) 0.01 0.05 0.11 0.26 0.28 [7] O. Chen, S. Wang, and Y. W. Wu, “Minimization of
multiplier switching activities of partial products for designing low-power
Delay (ns) 4.80 1.79 1.19 0.98 0.83
multipliers,” IEEE Transaction on Very Large Scale Integration
Proposed Power (mw) 0.01 0.02 0.04 0.08 0.09 (VLSI) System, vol. 11, no.3, pp. 418–433, Jun. 2003.
multiplier [8] L. Benini, G. D. Micheli, A. Macii, E. Macii, M. Poncino, and
Delay (ns) 1.60 0.59 0.39 0.33 0.28 R. Scarsi, “Glitching power minimization by selective gate
freezing,” IEEE Transaction on Very Large Scale Integration (VLSI)
System, vol. 8, no. 3, pp. 287–297, June 2000.
Table III shows the power consumption comparison of [9] S. Henzler, G. Georgakos, J. Berthold, and D.Schmitt-Landsiedel,
conventional multiplier which needs 8 partial products “Fast power-efficient circuit-block switch off scheme,” Electronics
(PP), Letter. vol. 40, no. 2, pp. 103–104, Jan. 2004.
[10] Z.Huang and M.D.Ercegovac, “On signal-gating schemes for low [15] P.J.Song and G.De Micheli, “Circuit and architecture trade-offs for
power adders,” Proceeding of 35th Asilomar Conference on Signal, high- speed multiplication,” IEEE Journal on Solid-State
Systems & Computer.pp.867-871, 2001. Circuits, Vol.26,no.9, pp.1184-1198, Sep.1991
[11] Z. Huang and M. D. Ercegovac, “High performance low power left- [16] A. Shams, T. Darwish and M. Bayoumi, “Performance analysis of low
to- right array multiplier design,” IEEE Transaction on Computer., power 1-bit CMOS full adder cells,” IEEE Transaction on Very
vol. Large Scale Integrartion (VLSI) System, vol. 10, no. 1, pp. 20–29, Feb.
54, no. 3, pp. 272-283, March 2005. 2002.
[12] M. C. Wen, S. J. Wang and Y. N. Lin. “Low-power parallel [17] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS
multiplier with column by passing,” Electronic Letter vol. 41, no. 12, Design. Norwell, MA: Kluwer, 1995.
pp. 581–583, May 2005. [18] N. Zhuang and H. Hu, “A new design of the CMOS full adder,” IEEE
[13] K.H.Chen and Y.S.Chu, “A low power multiplier with spurious power Journal on Solid-State Circuits, vol. 27, no. 5, pp. 840–844, May 1992
suppression technique,” IEEE Transaction on.Very Large [19] N.Weste and K. Eshraghian, Principles of CMOS VLSI Design, A
Scale Integration (VLSI) System.vol. 15, no.7, pp. 846–850, July 2007. System.Perspective. Reading, MA: Addison-Wesley, 1993.
[14] U.Ko, P.Balsara and W.Lee, “Low-power design techniques for [20] Chang.C.H, Gu.J, Zhang.M, “A review of 0.18-µm full adder
high- performance CMOS adders,” IEEE Transaction on Very performances for tree structured arithmetic circuits,” IEEE
Large Scale Integration (VLSI) System. volume.3, no.2, pp.327-333, Transaction on Very Large Scale Integration (VLSI) System vol. 13,
June 1995. no.6, pp. 686–
695, 2005.