34 Atmel Atmega32a PDF

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W O A W
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W W. .COM This documentation WW containsY .CO code
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W . 00
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Y
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W .100 general O M purpose
W O registers. Within a single
Y.C
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WW .100registers Y.C W
or.Tbetween WW and.1an
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W O WW 00logical, Y.C and.Tbit-functions. W 00Y
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WW .10into 0Y.C three main
M .T Wcategories W – arithmetic,
. 1 M
W WSome implementations
W .1 O M .of the
W architecture O W O W .C
WW .1and .C also provide a powerful
W WW .multiplier Y.C supporting W both signed/unsigned W .100
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W
WW .100Y.C M.TW
O
W O W O
6.3
W
WW .100Y.C M.TW
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W O W .COresult.T WW executed
W CO
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WW The.1Status 0 0Y.CRegister . T Wcontains information WW about 1 0 0 Ythe
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WWconditional . 1 0 0 M .T WNote thatW the Status
W . 1 0 Register O M .
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WW specified 00inYthe Instruction WW This . 1 0Yin
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W
WW .100Y.C M.TW
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W .C O is not automatically W W.1 Y.entering CO
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W WW 0 Y.C
O
W
WTheW Status Register
0 Y .T W W stored when
0 0 .an
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.1 0 M.T
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W
WW .100Y.C M.TW
fromOan interrupt. This mustW
W
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00Y
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.TW WW .100Y.C M.T
. 1 M
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
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C W . C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Register OM .1 M
6.3.1 SREG – AVR W
W Status
Y .C W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
.TW W Bit .100 M7 .
T 6 W 4 .1
00 3 M.2T
O M W O 5 W
W S 00YV. C O 1 0
Y .C W W W 0 Y .C I .TWT H W N.TW Z C SREG

00 .T .10 M R/W .1 OM
W.1 Y.COM W W Y. C O W W
00Y
.C
.TW 0
WWInitial Value
Read/Write R/W R/W R/W R/W R/W R/W R/W
00 .T . 100 0 M.
TW W
0 W.1 0 O M
W . 1 O M W O 0 0
W .C 0 0
Y .C W W W 0 Y .C T W W 0 0 Y .T W
.100 M.T W .10 M.
OInterrupt W.1 Y.COM W
WW 00Y.CO .TW • Bit
W W 7 – I: Global
0 Y
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W
WW .100Y.C M.TW WW enable.1control
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W O
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WW .CO .TW
WW .100Y.C M.TW WW is cleared,
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W O W .1 O M W W .C O
WW .100Y.C M.TW
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WW .100Y.C M.TW the application WW with 0 0 Y.CSEI and.TCLI
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W .C O W W.1 Y.COM W W W
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W W W 0
W
W .100
Y
O M.T
W
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W W.1 Y.COM W
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WW .100Y. W
M.T The Bit CopyW
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WW .100Y. M
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W
WW .100Y.C M.TW
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W 00Y
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. 1 M
W W .C O • Bit 5 – H: Half W
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W Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W Carry Flag
.10 0 .1 M
W.1 Y.COMThe W W C OMcarry in some arithmetic WWoperations. .COHalf Carry
W W 00 .T
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M .T W W .10 0 Y
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for detailed information.
WW .100Y.C M.TW W . 1 00Y M .TW W O
W O
W
WW .100Y.C • M
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W O C
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WW .100Y.C M.TW
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WW .100Y•.CBit 3M–.T
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W W The
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W W WW 0Flag 0 Y .CVOsupports .T W two’s complement
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W 00 .T 1 . 1 M
W.1 “Instruction
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W W • Bit .C2O – N: Negative W Flag WWW Y .CO .TW W WW 00Y.CO .TW
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M .T W W . 1 00 Y
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WW .100Y.C M.TW
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WWSet Description”
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W
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W
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W O WW .100Y .C
WW .100Y.C M.TW WW .100Y.C M.TW M.TW
W O W O
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W W
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Y
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WW .100Y.C M.TW
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W W .C O
W 00 Y .T W .1
W W 0 0 .T W
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WW .100Y .C W
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6.4 General Purpose W Y .C W W WW 00Y.CO .TW
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W W W 0 0 Y .T W W 1 0 0 .T
O M.T W
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M.T
W .100 OM
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W.1 Y.COM W W .C O W W Y .C W
00 .T WW• One.18-bit 00YoutputM .TW and oneW8-bit result
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W W
.1 00 Y
M .T W W
W . 0
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W .1 0
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WW .100Y.C M.TW
W O Figure 6-2 shows structure of the 32 general purpose working
WW Registers O
W .C O W W Y .CO General W W 0 Y.C W
W W
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M .T W Figure W 6-2.
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O M .T Purpose Working
W .1 0
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W O WW Addr. Y. C
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WW .100Y.C M.TW
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WW .100Y.C M.TW R0 WW $00.100Y.C M.TW
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WW .100Y.C M.TW Registers W . 100Y M
W
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WW .100Y.C M.TW W O
W W Y .C O
W W WW 00Y.COR26 .TW $1AWW 0 0 Y.CLow Byte .TW
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W W.1 Y.COM W WW 00Y.CR27 W
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WW .100Y.C M.TW WW .100YR31 M .TW $1F W Z-register .100High Byte OM.T
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W W WW on00the Y .CRegister .T
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imple-
W . O W C O
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WW Y.C W Y. .TW
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WW .100Y.C M.TW WW .100Y.C M.TW WW .1in00the file.
M.T
W
W O W C O
W
WW .100Y.C M.TW
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W O W O
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WW .100Y.C M.TW
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W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
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W W .100 M.T
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WW .100Y.C M.TW 8155B–AVR–07/09
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WW .100Y.C
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W O M.T ATmega32A
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W W WW 00Y.CO .TW
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W W.1 Y.COM W WW 00Y.CO .TW
6.4.1 TWThe X-register, Y-register and Z-register W
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W .100 OM
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W 0 0 Y to their general.TW purpose usage. These regis-
1 00 M .T . 1 0 16-bit address M . pointers for indirect W . 1addressing O M
. ters are
WW 00Y.CO .TW Y.C of the Data Space. The three indirect
W
0 Y .CO .TW W address registers X, Y, and Z are WW as described
defined .1 0 0 in M.T 6-3.
Figure
W
. 1 0 M W . 1 O M W C O
. 1 M O
W6-3. The X-, Y-, and Z-registers W W .C O
WW 00Y.CO .TW Figure
WW .100Y.C M.TW W . 1 00Y M .TW
W. 1 OM W O W W .C O
WW .100Y.C M.TW WW .100Y.C 15 M.TW XH W .1 00Y M.T XL
W 0
O W O W .C O
W
WW .100Y.CR27 ($1B) WW .10R26
X - register 7 0 7 0
WW .100Y.C M.TW M .TW 0Y($1A) M .TW
W O W O
W
WW .100Y.C M.TW
O
W O
W O
WW .100Y
W .CO .TW WW .100Y.C M TW
WW .100Y.C M.TW 15
M YH
W O YL. 0
W C O Y - register W
W 7 Y.C
O W Y .C W
W . W W W 0 7
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W
W .100
Y
O M.T
W
W .100R29 ($1D)OM.T W W
R28 ($1C) .C OM
C W .C Y .TW
WW .100Y. M .TW W . 1 00Y M .TW W
W . 100 O M
W O
WW .15
W .CO .ZH WW .100Y.C ZL M.TW
WW .100Y.C M.TW 1 00Y M TW
W O0 0
W C O W W .C O 0 W Y .C W
WW .100Y. W Z - register
W 7
0Y W W 7
00 .T
W O M.T W .10($1F)
R31 O M.T R30 ($1E)
W W.1 Y.COM W
W .C
WW .100Y.C M.TInWthe differentWaddressing .
Y
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W
0
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W O M W O
W
WW .100Y.C M.TW
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6.5 W W Pointer
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W 00 Y W .1
W.1 Y.COThe M.TStack is mainly used .1
WWfor storing .CO
M
temporary data, for storing WWlocal00variables .CO and
M
for storing
W W 00 W
.Taddresses after interruptsW 1 0 Y
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Y
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M .TW
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M . O calls. Note that W the as
W O WW memory .Clocations. W Y.C W to the
WW .100Y.Cgrowing .T W
from higher W
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M .T WThe Stack W
Pointer 1
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points
W W .C OM
top of the W Stack. The Stack WW Pointer0Y .CO to the
points W data SRAM W WWarea00where
Stack Y .COthe Subroutine
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W Y
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. 1 M O
W A Stack PUSH command will decrease W O
WW .100Y.C M.TW
W O the Stack Pointer.
WWany 0subroutine O calls are
W W The
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W W Wmust W be Y
0 .CO by.Tthe
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W 0 Y.C .TW
W . 1 00executed M .T interrupts are enabled.
or . 1 0Initial Stack M Pointer value equals W .
the1 last addressO M of the
W O W O
.Cbe set to W Y.C see Figure
WW .10internal 0Y.C SRAM .T W and the W
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WPointer 0 0
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point above W
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.1 0 0
SRAM, M .TW
. 1 M W O
W OM 18. W O
WW .100Y.C M.TW
WW .17-2 00Y
.Cpage
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M W O W O
WW .See
W
0 Y .CO 6-1 for
Table
. T WStack Pointer W details. 00Y.C
W .T W WW .100Y.C M.TW
0
W 1 Y.COM W .1 M WW 00Y.CO .TW
W W WW 00Y.CO .TW W
W
W .100
Table 6-1.
O M.T
Stack Pointer instructions
W .1
.C OM W W.1 Y.COM W
Y. C W W
WW Instruction .100
W
M.T pointer
Stack WDescription
W .100
Y
O M.T
W
W .100 OM
.T
W .C O W Y. C W Y .C W
WW PUSH 1 00Y Decremented M .TW by 1 W Data is pushed
. 100 onto the M .TW
stack W
W .100 O M.T
W . O W .C O W Y . C W
WWCALL.100Y.C M.TW WW address
Return
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onto the stack withW a subroutine
. 100call or OM.T
W O W
WW
ICALLW
RCALL.100Y
O
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by 2 interrupt
W W .C OM
WPOP .100 Incremented Y .T by 1 Data is popped W .1 M
W .C OM W W.1from the Y .C OM
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W WW 00Y.CO .T
W Y W W 00 .T W
WRET
W .100Incremented O M.Tby 2 Return address is
W .1popped
. C
fromM
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.C W W
Y W .100
RETI subroutine or return from interrupt
WW .100Y M .TW W . 100 M .T W
W O
WW 00Y.CO .TW W 00Y
.C .TW WW
TheW AVR Stack . 1 Pointer isMimplemented asW two 8-bit . 1registers in Mthe I/O space. The number of
bits actually W Wused isYimplementation
.C O
W dependent. W WNote W
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the data .T
space W in some implementa-
W 0 0 .T .1 0 M
W W.1 Y.COM W WW 00Y.CO
W 00 .T W
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 11
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 of theO
Wtions C
M architecture is so W
AVR smallW.1that only .CSPLOMis needed. In this case, the SPH Register
W W Y .
00 be present.
will.1not M .T W W . 1 0 0 Y
M .TW
W O W O
OM W Pointer O W O
0 Y.C
6.5.1
.T
SPH and SPLW
W W
– Stack
0 0 Y.C High.Tand W Low Register WW .100Y.C M.TW
0 . 1 M
W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
W
0 0
W.1 Y.COM W
.T Bit W.1
.C O15M 14 13
W W12.1 Y.11 CO
M 10
W
9 8
W W 0 Y T W W 0 0 .T
W .100 O M.T W .10 SP15
O M. SP14 SP13
W W.1 Y
SP12 SP11
.C OM SP2 SP10 SP9 SP8 SPH
W Y.C W WW .100Y .CSP7

TW
SP6 SP5 W SP4
00 SP3
.T W SP1 SP0 SPL
1 00 .T M . W . 1 O M
W. OM W .CO R/W
7 6 5
W 4 3
Y.C R/W.TW R/W
2 1 0
WW .100Y.C M.TW WW .100YR/W .TW R/W W R/W W.100R/W
W O
Read/Write
W C O M W .C OM R/W
WW . Y W
WW .100Y.C M.TW 00Y0 W W .1000 M.T 0
R/W R/W R/W R/W R/W R/W R/W R/W
W O Initial Value W.1 O M0.T 0 0

W W .C O 0 0
W Y . C W W W 0 Y .C .T W W 0 0 Y 0 .TW0
W
W .100 O M.T W .10 0
.C O M0 0 0
W W.1 Y.COM W
0 0
W
WW .100Y.C M.TW W .100
Y
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W W
W .100 OM
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W
6.6 O
Instruction Execution W
Timing C O W . C W
WW .100Y.C M.TW WW .100Y. M .TW W Y
.100 for instruction M.T execution. The AVR
This section W
describes the Ogeneral access timing W
concepts C O
W O
WW .100Y.C M.TW CPU is driven WW by the 0Y.CclockMclk
0CPU W
.TCPU WW .100Y. M .TWclock source for the
W . 1 O , directly generated W from the selected
O
W O
WW .100Y.C M.TWchip. No internal WW clock 0Y.C isM
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W W .C O
W WW Y
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Y W 0 M. T
.100 .10 W.1 Y.COM W
W Figure 6-4 shows the parallel fetches and instruction executions enabled by the Har-
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WW .100Y.C M.TW TW File concept.
the fast-access
W . 00Y
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W
This is the basic.T
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W
WW .100Y.C Mfunctions .TW WW and.1functions 00Y
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W
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W
WW .100Y.C M.TW
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WW O
W .C O Figure 6-4. The Parallel WW Instruction Y.CO Fetches W and Instruction W Executions
0 Y.C W
W W
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W . 10 0
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0
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W O WW .100Y. C
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W O WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW Wclk . 1 M
W W .C O
W WCPUW Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T Instruction FetchW.10 W 0 .1 M
W.1 Y.COM 1stW W .C OM WW 00Y.CO .TW
W W 0 Y .T W W
W
W .100 O M.T
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WW .100Y. 2nd W
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MInstruction
W
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W 00
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2nd Execute W . C O W
WW .100Y.C 3rd TW
.Instruction WW .100Y
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W O M W O W W .C O
WW .100Y.C 3rd Instruction
.TW Execute WW .100Y.C M.TW W .100
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W
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W
WW .100Y.C M.TW
O
W O W O
W
WW Figure 0 Y.C
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W O
W
WWtion .register. .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y
W W 1
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W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
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W
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W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
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0 Y.C W
W .1 0
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WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
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.10 6-5.OMSingle Cycle ALU Operation .1 M
W WFigure Y .C W W WW 00Y.CO .TW
W 00 .T W.T1 1 MT2
W.1 Y.COM W
T3 T4
W W W 0 Y .CO .TW
W W .100 .T 0
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.C W W
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M.T clkCPU
W .100 OM
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W.1 Y.COM W W C O
0Y. Execution
W W Y .C W
00 .T WW .10Total M .TW Time
W .100 M.T
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W .CO .TW WW .100Y.C M.TW WW .100Y .TW
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W Operands O Fetch W O M
W W. 1
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W WALU W Operation Y .COExecute W W WW 00Y.CO .TW
Y W 0 .T
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W
W W
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W .100 WriteOBack
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M.T
W
W .100 O M.T
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W O W C O
W
WW 6.7.100YReset .CO .TW WW .100Y.C M.TW WW .100Y. M .TW
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W O WW 00Y.CO .TW WW These .C
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theW . 1 O M
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WW
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Y Depending TW
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bits BLB02 or BLB12
W C O W W. . C OM W W Y CO “Memory
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W . are
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security. See
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the .T Program-
W . 1 00Y M
W
W . 100 O M .T W C O M
W O WW .100Y .
WW .100Y.C M.TW
ming” on page 266 for details. W
WW .100Y.C M.TW W O M.T
W O The lowest addresses W
W in the .C
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Ydefined as.TtheW Reset and
WW .100Y.C M .TW Vectors.WThe complete . 1 00Y list ofM .TW is shownW W .100 on page O M
W W Y .C O Interrupt
W W WW 00Y.CO .TW vectors in
W
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W 0 0 Y.C 45.
.T
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W
W 00 M.T
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W W.1 Y.COpriority level. RESET WWthe highest
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W 00 .T W W .1 0 0 M .T . 1 0 M
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WW .100Y.Cbit inMthe .TW W . 1 00YRegister M TW Refer W
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W W .C O General
W
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W Y .CO W
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W WW 00Y.C
“Interrupts” 45
.T
for more
W
W Y
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W . 1 O M W C O W .C O
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W . 1 00YProgramming” M .TW on page W W .100 O M .T W .10 O M.
W O 252.
WW .100Y .C
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W When Oan interrupt occurs, theWGlobal .C Enable WI-bit is cleared WWand .all Y.C
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WW There .1 0 0 Yare basically
M .T Wtwo types of Winterrupts.
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W .1 O M.T
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WW tor.1in0order 0Y.C to execute .TW the interrupt W handling . 1 00Y M .T hardware clears .100 M
W W .C O M W W routine,
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corresponding
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0 0 Y bit is .TW
W . 1 0 0 M .T . 1 0 M W . 1 O M
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W W bit 0is0Y
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W
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W
WW .100Y.C M.TW
global interrupt enable O bit is set, and will then
WW be .executed 0 0 Y.C by order .T W of priority. WW
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W typeY.of C O W 1 as the
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00
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W Y .C W W 0 Y W W
W is enabled,
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W.1 Y.COM W
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W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
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C W .C
WW .100Y. M.T
W W .100
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W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 the AVR OMexits from an interrupt, .1 M to the main program and execute one
W WWhen Y .C W W WWit will0always 0 Y .COreturn .TW
W more
. 100instruction M .T any pending interrupt
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W
W
WW Note.1that 0Ythe .CO .TW WW .100Y.C M.TW
.T 0 M
Status Register is not automatically stored when entering an interrupt routine, nor
.C OM
W
W
Wrestored Y .COreturning W W WW 00Y.CO .TW
00 Y .T W .10 0when
M. T from an interrupt routine.
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W.1 Y.COM W W C O W W .C OM
WW Y. .TW Y W
. 1 00 M .T When .using
W 100 the CLI O M instruction W interrupts,
to disable
W .100 theOinterrupts M.T will be immediately disabled.
W .CO .TW Winterrupt .Cbe executed W Y .C TW
1 00Y M
WNo . 1 00Y will
M .TW after theWCLI instruction, W . 100 even O M
if.it occurs simultaneously with the
. W O .C be used
WW 00Y.CO .TW CLIW instruction.
W EEPROM 10 0Y.C
The following example shows
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can
M .TW
to avoid interrupts during the
W. 1 OM timed W . writeO M
sequence. W O
Assembly W Code Example O W O
W
WW .100Y.C M.TW
O
; store SREG value W O
WW 00Y.CO .TW
in r16, SREG
W .C O W W 0 Y.C W
W W
.1 00 Y
M .TW W cli
W
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O M during timed W
0
.1 sequence O M.T
W O .C start WW .100Y. C
WW .100Y.C M.TW WW
sbi EECR, EEMWE
1 00Y ; M .TWEEPROM write M .TW
. W O
W O
WW .EEWE
W .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW 00Y
sbi EECR,
1 M
W O Wr16 ;O restore SREG value W W .CO .TW
WW .100Y.C M.TW
out SREG, (I-bit)
WW .100Y.C M.TW W . 1 00Y M
W W .C O C Code Example W W Y .C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
W .100 O M.T char cSREG; W .C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W cSREG W = SREG;
Y
100store OSREG
./* M.T value */
W 00
W.1 Y.COM W
.T
W O W .C W
WW .100Y.C M.TW /* disable WW interrupts . 100
Y during
M .TW timed sequence W */.100 M.T
O W O W .C O
W
WW .100Y.C M.TW_CLI(); W
W Y.C .TW WW .100Y M.T
W
W . 100 O M W O
W O
WW .100Y.C M.TW
W Y.C .TW
WW .100Y.C M.TWEECR |= (1<<EEWE);
EECR |= (1<<EEMWE); /* start EEPROM writeW */
W .100 O M
W O W
WW/* restore .CO .TW WW 0Y.C M.TW
WW .100Y.C M.TSREG W = cSREG; . 1 00Y SREGMvalue (I-bit) */ W.10 O
W O
W
WW .100Y.C M.TW
O
WW following O
W When using the SEI instruction
O WW 0to .CO interrupts,
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be exe-
WW .100Y.Ccuted .T W
before any W
pending . 1
interrupts, 0 Y
as shownM .T W
in this example.
W
W .1 0 0
O M
W OM WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.CAssembly .T W
Code Example W.
W 1 M
W OM W .CO .TW WW 00Y.CO .TW
WW .100Y.C sei T W
M. ; set global interrupt
W .1 0 0 Y W
W.1 Y.COM W
W C O W W enable
.C OM W
WW .100Y. sleep; W Y W W 00 .T
W O M.T enter sleep, W
W waiting
W .100 for interrupt O M.T W W.1 Y.COM W
.C
WW .100Y.C; note: M .TW will enterWsleep before
.
Y
100 any M .TW
pending W
W .100 O M.T
W O W O W .C
WW .100Y.C M.TW
; interrupt(s)
WW .100Y.C M.TW W .100
Y
M.T
W
W O W C O
W C CodeOExample
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y. M .TW
W O W O
W Y.C
_SEI();
WW .100_SLEEP();
O /* set global interrupt
.T W WW .100enable Y.C */.TW WW .100Y.C M.TW
M /* enter sleep,Wwaiting W M
forOinterrupt */ W O
W
WW .10/* .CO .TW
0Ynote: W before 0 0 Y.C .T W WW .100Y.C M.TW
will enter sleep
W. 1 any OM
pending interrupt(s) */W O
W OM WW .100Y.C M.TW
6.7.1 W TimeY.CO
Interrupt Response
W W WW 00Y.CO .TW W WW 00Y.CO .TW
W 1
W
TheW .100 execution
interrupt
.T
OM response for allWthe W.1enabled .C OM interrupts is four clock
AVR W W.cycles Ymini-
M
.CO .TW
W .C Y W W 0
Wmum. After Y
.100four clock .TW the program
Mcycles
W vector 00
W.1 address OforMthe.T actual interrupt handling 0
W.1 routine C OM
W .C O W Y .C W W
W onto the 0 Y. W
is W
W executed.
. 1
Y
00During this.T
M
fourW clock cycle Wperiod,.1the
W
00Program
O M .T
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W .10Stack. O M.T
TheW W O
Y.C a .jump WW routine, .C .TWtakes three
W cycles. Y.C
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W . 100 If OM.T
WW 00instruction, O
WW .100Y.C
an interrupt W occurs during
O execution of a multi-cycle this instruction is completed
WWthe interrupt 0 Y.Cis served. .T W Woccurs Y.C .T W
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when the MCU M is in sleep mode, the interrupt
W W .C OM
W W W Y .C O
W W WW to the
execution response Y time is increased by four W clock cycles.
10 0 This increase.T comes in addition
W 100 the selected
W.from
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start-up W time . C Y . .TW
W .1 00Y M .TW W
W . 100 O M
W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y.CO .TW W
0
WA.1return OMan interrupt handling .1 M clock cycles. During these four clock
W Y .Cfrom
W W WW routine takes
0 Y .COfour.T W
W . 1 00 the Program
cycles, M .T Counter (two bytes) . 0
1is poppedOback M from the Stack, the Stack Pointer is
W .C O W W Y .C W
W Y W W 0 T
M .TW W incremented
W . 100 by two,
O M .Tand the I-bit in SREG W .is10set. OM.
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
0
W. 1
.C OM
Y W .1
M
W .1 O M W.1 Y.COM W W W.1 Y.COM W
.C W W 00 .T
WW .100Y M.T
W W .100 M.T W.1 Y.COM W
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
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WW .100Y.C M.TW
O
W O W O
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WW .100Y.C M.TW
O
W O W O
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WW .100Y.C M.TW
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W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
W O W . C O W
W W .100 M.T
W O W O W W .CO
Y
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W
W O W C O
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WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
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W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
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W .100 OM
.T
W W.1 Y.COM W
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WW .100Y. M.T
W W .100
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W 00
W.1 Y.COM W
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W O W . C O W
W O W O W W .C O
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W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
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W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
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WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
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O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
7.OMAVR .TW Memories W
W .100 O M.T
W
W .100 O M.T
WW .100Y. C
00Y
. 1 M W O W O
W
0 .CO Overview
1 0 .CO .TWThe AVR architecture has two
W. .C OM
W WW
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section0describes Wdifferent W WW in the
memories 0 0 YATmega32A.
Y W .T
.100 M.T W .10 spaces, OM the Data MemoryWand W.1the Program M
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WW 00Y.CO .TW main
W W memory
1 0 Y .C
0features an .T W W . 1 0 Y
0 storage. M .T W space. In addition, the
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W data O All three memory spaces are linear
W Y .C W andW W W
regular. 0 Y .CO .TW W W 0 0 Y.C .T W
W 00 .T 0
W.1 Y.COM W .1 M
W W.1 Y.COM W W W WW 00Y.CO .TW
W 100 In-System M.T
W 00 .T W.1 Y.COM W
W .7.2
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W W.1 Flash .C OMProgram Memory
W W
WW .100Y M .TW The
W
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Y
100contains O M .T bytes On-chip
32K
W
W
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W O W .C W Y .C TWFlash is organized as
WW .100Y.C M.TW program W storage. 0 0 Y all AVR
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W .C O W W.1 Y.COM W WW 0 .CO is divided
Yspace W into two sections,
W W 0 Y .T W 16K x 16.
W For software0 0 security, .Tthe Flash W
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W
WW .100Y.C M.TW
O Boot Program
WW .100Y.C M.TW
section and Application Program section. WW .100Y. M .TW
W O W O
an.Cendurance
W
W write/erase O
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WW .100Y.C M.TWProgram Counter WW .has
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W O WW Y. section .and Y.C memory locations. The
TW protection are
WW .100Y.C M.TW operation ofW Boot Program . 1 0 0 M T WassociatedWBoot Lock .1 0 0bits for M .
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W O WW .CO Support W
WW .100YSelf-Programming” .CO .TW
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W O W O W . C
WW .100Y.C Mming
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WWor Parallell Y.Con page 266 contains
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W . 100 Programming O M
W
WW .100Y.C M
O
.TW tables can WW .100Y.C M.TW WW .100Y.C M.TW
WW address O
W W Y .C O Constant
W W WW 00Y.CO .TW
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W 00 .T Program MemoryW
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M .1 M
W W.1 Y.COM W W Y .CO .TW W WW 00Y.CO .TW
W 00 W 0 0 in.1“Instruction
W.1 Y.CO M.T diagrams for instruction
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W W.1 fetch .C OM
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W Y.
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W W 12. Y W W 0 0 .T
W
W .100
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O M
W
W .100 OM
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W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W .100
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W W and Y .C O – EEPROM Address
W WW Y .CO .TW W WW 00Y.CO .TW
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W 00 .T W.1 4 Y.CO3M W2
W WBit.1 Y.COM 7 W 6 5W 1 0
.T W W . 1 0 0 M .T W . 1 00 M .T
.C OM
W WW Y .CO R/W .TW R/W
MSB
W WW 00Y.CO .TW LSB EEDR
00 Y .T W 10
Read/Write 0 R/W .1
R/W R/W M R/W R/W R/W
W.1 Y.COM W W W.Value .C O0M WW 0 00Y.C0O .T0W
0 .T W Initial
0 0 Y .T W 0 0
W .1 M
0 0
1 0 . 1 M W O
W. OM W .CO .TW WW .100Y.C M.TW
0 0 Y.C .TW W• W Bits 7:0
1 0 0
– YEEDR7.0: EEPROM Data
.1 M W. OM WW Register O
WW 00Y.CO .TW WWthe EEPROM
For 0 0 Y.C write .operation, T W theW EEDR
. 1 00Y.Ccontains M .TW the data to be written to the
. 1 M W . 1 O M W C O
W O EEPROM W in the Y.C address given by the WW .100Y
EEAR Register. . For the EEPROM
.TW read operation, the
WW .100Y.C M.TW W
EEDR contains . 1 0 0 the data M . T W
W at the address O M
W O read out from the EEPROM given by EEAR.
W
WW .100Y.C M.TW
O
W W7.6.3 Y.CO EECR – W EEPROM Control WWRegister Y .CO .TW W WW 00Y.CO .TW
W 00 .T W 0 0 .1 M
W.1 Y.COM W W W.1 Y.COM W WW 3 00Y.C2O .T1W
W W 0 W
W .100 .10– M.T – .1
Bit 7 6 5 4 0
W O M.T W C O W W .C OM EEWE
WW .100Y.C M.TW Read/Write WW .R100Y. R M.TW
– –
W EERIE
. 1 00YR/W MR/W
EEMWE
.TW R/W EERE EECR
R R R/WW O
W O WW 0 00Y.C0O .T0W WW0 .100Y0 .C MX.TW 0
WW .100Y.C M.TW Initial ValueW . 1 M 0
W O
WW .100Y.C M.TW• Bits 7:4W .1 M
W W .C O
W
– Res:W
W
Reserved
Y
Bits
.CO .TW W WW 00Y.CO .TW
W 00 Y .T These bits are reservedW 0
0bits in the ATmega32A and will always .1 read as zero. M
W W 00 .T W .1
W
W .100 O M.T• Bit 3 – EERIE:W EEPROMW.1 Ready .C OM Interrupt Enable WW Y .C OM
W
.C Y W W 00
WW .100Y M .TW EERIE W
Writing to one W . 100 the O
enables M
EEPROM .T Ready Interrupt W if.1the I bit in O M.T is set. Writing
SREG
W O
WW the 0Y.C The WWinterrupt Y.C W
WW .100Y.C M .TW to zero disables
EERIE . 1 0interrupt. M
W
.TEEPROM Ready
W .100generates O M .Tconstant
a inter-
W C O W W .C O W Y .C W
WW .100Y . rupt when
W EEWE is cleared. Y W W 0 0 .T
W O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. • M Bit.T2W – EEMWE:W EEPROM.1Master 00Y Write M.T Enable
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.CTheMEEMWE .TW bit determines WW whether Y. TW to one W 0Y
.10EEPROM Mto.Tbe written.
W . 100 setting O M .EEWE causes the
W C O
W O EEMWE is set, setting W EEWE C fourTW
Y.within Wwrite data Y.to the EEPROM .TW at
WW .100Y.C
When
M .TW address IfWEEMWE . 100zero, M . clock cyclesW will
W .100 O M
the selected
WW 00Y.C is O
setting EEWE will have no effect. Y.C
When EEMWE W has
W
WW .100Ybeen .CO written T W
. to one by software, W .T W W W
1 0 0
. clock cycles. .T
M See the
1
W.hardware clears
M the bit to zero after four
W W .C OM of the EEWE bit W
W Y .COwrite.T W W WW 00Y.CO .TW
W 00 Y
description .T W for an EEPROM
0 0 procedure. .1 M
W W
W
W .10•0 Bit 1O– M .T EEPROMWWriteWEnable
EEWE: .100 OM
.T
W W.1 Y.COM W
.C W Y .C W WEEPROM. 00
WW .1The 00YEEPROM W
M.TWrite Enable Signal
W
W .100 is the
EEWE
O
.T strobe to the
write
M W.1 When M.T
Oaddress
W O C W .C
WW .and 0 0Y .C are correctly
data
.TW set up,Wthe EEWE
W
1 00bit
.
Y must be.Twritten
M
W to oneW to write the
.
Y
100value O .TW
into the
M
1 M . W
WEEPROM. .COThe EEMWE bit must be WW written toY.one CObefore a logical one isW
TW shouldWbe followed
written to0Y .C oth-
EEWE, W
WW erwise .1 0 0 Yno EEPROM M .T W
write takes
Wplace.
WThe. 1 0 0following
O M .
procedure W .1 0 when writing
O M.T
W .CO (the.T .C WW .100Y. C
WW the.1EEPROM 00Y W of stepsW
order
W
3 and 4 is 1 00Yessential):
not M .TW M .TW
M W . O W O
W
WW 1. .1Wait .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Yuntil EEWE becomes zero.
W W Wait Y .C OM
W WW zero. Y .CO .TW W WW 00Y.CO .TW
2. until SPMEN in SPMCR W
becomes 0
W .100 O M.T 10
W.(optional). OM W W.1 Y.COM W
3.WWrite new .C W .C W
W W
.1 00Y
EEPROM
M .TW
address to WEEAR
W . 100
Y
O M .T W
W .100 O M.T
4. W O
Write new EEPROM data to EEDR W .C WW .100Y .C W
WW .100Y.C M.TW W (optional). . 00Y
1writing M .TW M.T
W O W O
WW .100Y.C M.T
5. Write a logical one to the EEMWE bit while a zero to EEWE in EECR.
W WW 00Y.CO .TW W
WEEMWE, 1 0Y.C M.TW
0write
6. Within . 1 four clock M
cycles after setting . a logical one to EEWE.
WW 00Y.CO
W W Y .C O
W W WW 00Y.CO .TW W
The WEEPROM 00can not be T
.programmed during a CPU
W.1 write to the
OM Flash memory. The .1
software
W W.1that the Y .C OM programming is completed
W W 0 Y . C W W WW write.
must W check
00 Flash W .10
before
M.T
initiating a new EEPROM
Step 2 is W.1relevant
only M.T
ifOthe software containsW aW Boot Loader .C OallowingW
W W 0 0 Y .C
.T W W .1 0 0 Y
M .T the CPU to program the
Flash. If the W .1 is never
Flash OM being updated by the CPU, W step 2 can O be omitted. See “Boot Loader
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 M .1 M
W WSupport Y .C–ORead-While-Write
W W WW 00Y.CO on
Self-Programming”
.TW
page 252 for details about boot
W .1 0 0
programming. M .T . 1 M
W .1 step 6 O
O M.T W W .1
Caution:
.C OM
An interrupt between step 5W
W
and
Y
M
.C will make W
the write cycle fail, since the
Y .C W W 0 Y T W W 0 0 .T
00
W.1 Y.COM W
.T EEPROM
W .10 Master
O M.
Write Enable will time-out.
W W .1 If an interrupt
. C OM
routine accessing the EEPROM is
WW interrupting .C
Yanother EEPROM Y EEDR reGister W will be modified, causing the
1 00 M .T . 100 EEPROM M .TW Access, W the EEAR
W .100
or
O M.T the Global Interrupt Flag cleared
. W
interrupted O Access to fail. It is recommended .C to have
W .CO .TW W .C
00Ysteps toMavoid .TWthese problems. WW .100Y .TW
. 1 00Y M
Wduring
W all
. 1the
O W O M
WW 00Y.CO .TW WW the.1write 0
C
0Y.access .TWhas elapsed, WW .100Y.C M.TW
W. 1 OM When W O M time the W EEWE bit C is Ocleared by hardware. The user soft-
.C W Y .C W W W 0 Y. next byte. W
W W
.1 00 Y
M .T W W
ware can
W
poll
. 10 0
this bit and
O M .T
wait for a zero before writing
W .1 0 the
O M.T When EEWE has been set,
W O W is halted .C two cycles W Y.Cis executed. .TW
WW .100Y.C M.TW
theW CPU for
. 1 00Y M .TWbefore theWnext instruction W . 100 O M
W O WW 00Y.CO .TW W 00Y
.C W
WW .100Y.C M.TW • BitW 0 – EERE: . 1 EEPROMMRead Enable W W . 1 O M.T
W O C
W O
WW .100Y.C M.TW The EEPROM WW Read .C
00YEnableM .TW– EERE –W
Signal
W
is the read . 0Y. to M
10strobe the.T W
EEPROM. When the cor-
W . 1 O W C O
W O C W . .TW
WW .100Y.C M.TW trigger the
rect
WW .100Y.
address is set up in the
M
EEAR
.TW Register, W the EERE
. 1
bit
00Y must be
M
written to a logic one to
EEPROM read. The EEPROM read access Wtakes one O
instruction,
W O W
WW immediately. Y.C
O
WWis read, Y.C W and the requested
WW .100Y.C M.TW data is available 1 0 0 .
WhenT W the EEPROM . 1 00the CPU Mis.Thalted for four cycles
W C O W W. . C OM W W Y .CO .TW
W . W before the next instruction Y is executed. W W 0 0
W
W .100
Y
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W startingW
WW .100Y. W
The user should
M.T progress, it is neither
W poll .the Y
100EEWEObit M.T
before the read.1 00
operation.
WchangeYthe
IfM
OEEAR
T operation is in
a .write
W O W possible .C to read the EEPROM, nor W to .C W
WW .100Y.C M.TW WW .100Y M .TW W . 100 M .TRegister.
W O W O
W O The calibrated Oscillator
WW .100Y.C Mgramming .TW WW .1is00used Y.C to time.Tthe W EEPROMWaccesses. W
. 1 0Y.C 7-1M
0Table .TW
lists the typical pro-
W O M W O
WW .100Y.C M.TW
W O time for EEPROM access
.C from the CPU.
WW .100Y.C M .TW7-1. WW Programming . 1 00Y M .TW
W W .C O Table
W
EEPROM
WW 00Y.CO .TW
Time
W WW 00Y.CO .TW
W 00 Y .T W .1
W.1 Y.COM W Symbol WW. 0Number
1 Mof Calibrated RC Oscillator
WW 00Typ OM
W W Y .CO .TCycles W (1) W Y.CProgramming.TW Time
W . 1 00 M .T .1 0 M W . 1 O M
W O WW 00Y.CO .T8448 WW .100Y.C 8.5Mms.TW
WW .100Y.C EEPROM . T W write (fromWCPU) . 1 M
W
W W .C OM
W W W Y . CO W W WW 00Y.CO .TW
Y W 0 T
. Fuse setting.
W 00 Note: M.1. T Uses 1 MHz clock, independent 0 W.1 Y.COM W
of CKSEL
W.1 YThe .C Ofollowing code examples W W.1showY.one C OM
W W
W W
. 1 00 EEPROM. M .TW W
W .100 O
assembly
M .T and one W C
W .100 for writing
function
O M.T to the
W O The examples assume
W that Y.C
interrupts are controlled
WW .100Y
(for example by.Cdisabling
Tinter-
W
WW .100rupts Y.C globally) .T W W . 1 0 0 M .T W M .
M so that no interrupts will occur Oduring execution of these Wfunctions. TheO examples
W O WW 00Y .C WIfWsuch.1code .C
00Yis present, .TW
WW .10also 0Y.Cassume M .T W no FlashW
that Boot Loader . 1 is present M .TinW the software.
W O M the
W C O W Wwait forYany .C Oongoing SPM command W Y .C W
WW .100Y EEPROM . write
.TW
function must also W W to
.100
finish.
M.T
M
W
W . 100 O M .T W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
OM.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100
WAssembly OM Example
.T
W W.1 Y.COM W
W .C Code W
M .TW W
W . 00 Y
1EEPROM_write:O M .T W
W .100 O M.T
00Y WW .10;0Y M .T W M .TW
. 1 M W Wait O for completion of W
previous write O
W
0 Y.C
O
.T W WW .1sbic 0 0Y.C .TW WW .100Y.C M.TW
0 EECR,EEWE M
W. 1
.C OM
W WW rjmp Y .CO .TW W WW 00Y.CO .TW
Y W 0 EEPROM_write
.100 M.T 0
W;.1Set Yup.CO M W.1 Yregister M
.CO .TW
WW 00Y.CO .TW W W 0 addressW (r18:r17)W inWaddress 0 0
W .1 O M W .10EEARH, Or18M.T W W.1 Y.COM W
.C W out .C W 00
WW .100Y M.T
W W out.1EEARL, 00Y r17 M.T
W
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW WW; Write Y
.100 data O
W
M.T to data register
(r16) W .100 M.T
W O W W W .C O
WW .100Y.C M.TW WW Y.C .TW W .100
Y
M.T
W
100
out EEDR,r16
W . O M W C O
W
WW .100Y.C M.TW
O
W;W Write logical
0 0Y.C one to EEMWE
.TW WW .100Y. M .TW
. 1 M W O
W O WW 00Y.CO .TW
sbi EECR,EEMWE
WW .100Y.C M.TW
WW .100Y.C M.TW WStart
; . 1
eeprom write M by setting EEWE W O
W W Y .C O
W W W W
0 Y .CO .TW WW .100Y.C M.TW
W 00 .T sbi EECR,EEWE 1 0
W.1 OM W. OM W O
WW .100Y.C M.TW retWW
0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y .C O
WC Code Example W WW 00Y.CO .TW W
W 00 .T
W.1 Y.COM W void EEPROM_write(unsigned W.1 Y.COM int W.1 Y.COM W
Wunsigned
W W
W W .100 M.T
uiAddress, char ucData)
W . 1 00 M .T W
W . 100 O M .T W C O
W O { W Y.C WW .100Y . W
WW .100Y.C M.TW /* WaitWfor completion . 100 M TW
.previous W O M.T
W O of write */
W O
WW .100Y.C M.TW while(EECR WW& (1<<EEWE)) 00Y
. 1 M
W W . CO
Y ; W
W 00
W.1 Y.COM W
.T .1 M
.CO registers W.1 Y.COM W
WW and W */ WW
W Y .100 .T
/* Set up address data
W .10 0 M. T
W
W .100 O M.T EEAR = uiAddress; W C O W W .C OM
W
WW .100Y.C M.TEEDR W = ucData; WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M/*
O
.TW Write logical WW one.1to .C
00YEEMWE M */.TW WW .100Y. M .TW
W O W O
W
WW .100Y.C M
O EECR |= (1<<EEMWE);
.TW WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O /* Start eeprom write
W WW by00setting Y .CO EEWE W */ W WW 00Y.CO .TW
Y W .T
W 00
W.1 Y.COEECR M.T |= (1<<EEWE);WW.1 .C OM W W.1 Y.COM W
W Y W W .100 M.T
W . 1 00 } M.TW W
W . 100 O M .T W .C O
W O W
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 next code OMexamples show assembly .1 OM for reading the EEPROM. The exam-
W WThe Y .C W W WW and 0 0 YC.Cfunctions
.TW will occur during execution of
W ples
. 1 0
0assume that
M .Tinterrupts are controlled . 1 so that O noMinterrupts
W O W
.T W WW these 0 0Y.C M.TW
functions. WW .100Y.C M.TW
. 1 W O
OM W CO
Y.Code WW .100Y.C M.TW
0 0 Y.C .T W WW Assembly . 10 0 .T
Example
M
W
W.1 Y.COM W WW EEPROM_read: Y .CO .TW W WW 00Y.CO .TW
W 0
0 0
W.1 Y.COM W
.T
W.1; Wait
0
.C O M W W.1 Y.COM W
W Y for completion W of W previous 0 0
write .T
W .100 O M.T
W
W .100 EECR,EEWE O M.T W W.1 Y.COM W
.C WW .100Y
sbic .C
W
1 00Y M .TW M .TW W
W .100 O M.T
. O W rjmp EEPROM_readO .C
W
WW .100Y.C M.TW WW ; Set Y.C W WW .100register Y
M.T
W
W . 100up address O M .T(r18:r17) in addressW O
W
WW .100Y.C M.TW
O
WWout .EEARH, .C
00Y r18M.TW WW .100Y.C M.TW
1
W W . C O
W Wout W EEARL, Y .Cr17
O
W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W.1 Y.COM W ;W W.1 eeprom
Start
Y .C OreadM by writing EERE
W WW 00Y.CO .TW
W Wsbi EECR,EERE 0 0 .T W .1
W
W .100 O M.T
WRead data
;
W .100 from Odata M.Tregister W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W inW r16,EEDR
.100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW
ret
WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
WW .100Y.C M.TW
C Code Example
WW .100Y.C M.TW WW .100Y M .TW
W O W O
W O unsigned W .C W Y.C .TW
WW .100Y.C M.TW { W char EEPROM_read(unsigned uiAddress)
.TW
int W
. 1 00Y M W . 100 O M
WW .100Y.C M.TW /* WaitWfor completion . 1 M
of previous write */ W O
W O
W W W
0 Y .C O
.T W while(EECR W W & 0 0
(1<<EEWE)) Y .C
.T W W W
.1 0 0Y.C M.TW
0
W.1 Y.COM W ; .1 M WW 00Y.CO .TW
W W WW 00Y.CO .TW W
W 00 .T .1 M .1 M
W W.1 Y.COM W /* Set up address WW register Y .CO */ .TW W WW 00Y.CO .TW
W 0
W 00
W.1 Y.COM EEAR
.T = uiAddress;
0
W
W W
. 1 00 M .T/*WStart eeprom W read
W . 10by0 writing
O M .TEERE */ W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C MEECR .TW |= (1<<EERE); WW .100Y.C M.TW M .TW
W O W O
W
WW .100Y.C M.TW
O /* Return data from
WW data 00Y
.C
register
.T*/W WW .100Y.C M.TW
.1 M
W W . C O return EEDR;
W 00 Y .T W .1 M
W.1 Y.C}OM W W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
.TW
8.OMSystem W and
Clock W .100Clock O M .T
Options
W
W .100 O M.T
WW .100Y. C
00Y
. 1 M W O W O
W
0 .CO Clock
Y8.1 .T W Systems WWand.1their 0 0Y.C Distribution . TW WW .100Y.C M.TW
1 0 M CO and Ttheir
W. .C OM
W WW 8-10presents
Figure Y .CO the.T W
principal clockW WW in0the
systems 0 Y.AVR . W distribution. All of the clocks
00 Y .T W . 1 0 M . 1 M
. 1 M W O W O
.C consumption,
WW 00Y.CO .TW need
WW
not be active
1 0 0Ycan .C at a given .
time. In orderW
TW by using W
to reduce Y
. 1
power
00 modes,Mas W
.Tdescribed
the clocks to modules
W. 1 OM not being . used be M halted different W sleep O in “Power Manage-
W Y .C W mentW WandW
Sleep 0 Y .CO on.Tpage
Modes” W 33. The W W
clock systems 0 0 C
Y.are detailed . T WFigure 8-1.
W 00 .T 0
W.1 Y.COM W .1 M
W .100 M.T
W 00 Distribution .T W.1 Y.COM W
W .C O Figure 8-1.
W W.1 Clock .C OM
W W
WW .100Y M .TW W
W .
Y
100 General O M .T W
W .100 ORAMM.T
W O Asynchronous
W .C I/O
W Y . C TW EEPROM
Flash and
WW .100Y.C M.TW Y Modules .TW ADC CPU Core
W Timer/Counter
0 0 W . 1 0 0 M .
.1 M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W
W .10 0
O M.T W .1
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W . C W
WW .100Y.
clk
Y
WW .100Y.C M.TW .TW W .100 M.T
ADC
O W O M W .C O
W
WW .100Y.C M.TW WW .100Y.clk C I/O W Clock
.TControl
AVR WclkW .100Y
CPU
M .TW
W O M W O
Y.C
Unit
W O .C W .TW
WW .100Y.C M.TW WW .100Y clk
M .TW W clk . 100 M
W ASY
O FLASH
W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW WWLogic .100Watchdog Y.C Timer .TW
WW .100Y.C M.TW
Reset
W O W C O W W . C OM
.C W Y. W W 0 Y W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O WWWatchdog Y. C
WW .100Y.C M.TW WW .100Y.C M.TW .TW
Source Clock Clock
W . 100 O M
O W OClock .C
W
WW .100Y.C M.TW WW .100Y.CMultiplexer .TW WW .1Watchdog 00Y M.T
W
W O M W Oscillator
C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W RC .1External 00 Clock M.T Crystal W
Low-frequency .1
W
W .100 O M.T
Timer/Counter
Oscillator
External
Oscillator W
W . C O Oscillator W W
Crystal Oscillator
Y
OM
Calibrated RC
.C
Oscillator W
.C W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O WW .100Y. C
WW – clk 0 0 Y.C .T W WW .100Y.C M.TW M .TW
8.1.1 CPU Clock . 1
W CPU Y.CO M W O W .C O
WW The 0
CPU clock .T
is Wrouted to WWof the.10system
parts 0Y.C concerned .TW with operation WW of.1the 00YAVR core. M.T
W
.1 0 M W O M W CO
W O
WW 0Y.C Register
W Register Y. .TW
WW Examples . 1 0 0Y.Cof such M .Tmodules
W are the General0Purpose
. 1 M .TW File, the W Status
W .100 andOthe M
Oholding the Stack Pointer. WHalting the CPU O clock inhibits the core .C
W memory
data
WWgeneral 0 Y.C .T Wcalculations. WW .100Y.C M.TW WW from . 1
performing
00Y M.T
W
.1 0 operations M and W O W .C O
W O WW .100Y
W O W O
8.1.2 I/O Clock – clkI/OWW
W 0 Y.C
O
1 0 O
The I/O W. clockYis.Cused OMby the majority of the WW I/O modules,
Y .COlike Timer/Counters,
W WW
SPI,
W
and USART.
0 Y.C W
W W
The I/O clock .1 00 is also M W W
.T by the External Interrupt
used W . 0
10 module, O M .T
but note that some external W .1 inter- OM.T
0
W .CO .TW WW .C
WWare detected
rupts 00Y by asynchronous logic,WW allowing10such
. 0Y.Cinterrupts M .TW to be detected even if.1the00YI/O M.T
W . 1 O M W O W W .C O
clockW is halted. Also
Y.C note that Waddress recognitionWW .1in00the Y.CTWI module .TW
is carriedWout asynchro-
.100
Y
W
nously when .1 00I/O
clk is M
halted, .Tenabling TWI address W reception Oin Mall sleep modes. W
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
.1FLASH OM .1 M
8.1.3 Flash Clock –W
W clk
W 0 clockMcontrols
.10Flash .T 1 interface. M
WThe
.C O operation of the
W W.Flash Y .CO The W
Flash clock is usually active simul-
W W W taneously 0 0 Y with the . T
CPU W clock. W 1 0 0 .T
.T .1 M . M
.C OM
Y W
00
W.1 Y8.1.4
.T
OM AsynchronousW TimerW.1 Clock .C–O clk MASY W W.1 Y.COM W
.C W
. 1 00 M .TW W . 100
WThe Asynchronous Y
O M .T clock allows the W
Timer
W .100
Asynchronous O M .T
Timer/Counter to be clocked directly
W .C O W an external Y .C 32 .kHz W W W The 0dedicated0 Y . C T W domain allows using this
Y W W from 0 T clock crystal. .
clock
.100 M.T W.1 Yas
0 M
aOreal-time W.1 the device M
.CO is in.Tsleep
WW 00Y.CO .TW Timer/Counter
W W
1 0 0 .C
.T W counter even W Wwhen
. 1 0 0 Y
M
W mode.
W. 1 M W . O M W O
WW .18.1.5 .CO ADC W WW .100Y.C M.TW WW .100Y.C M.TW
00Y .T Clock – clkADC
CO halting
W OM WWis provided O
Y.C with a.T WW This 0Y.allows .TW the CPU and I/O clocks
WW .100Y.C M.TW TheW ADC
. 1 0 0 M
W
dedicated clock Wdomain.
W . 1 0
O M
W O in orderW toW reduce noise .COgenerated WW .1This
by digital circuitry.
00Y
.C more
gives
.TW
accurate ADC conversion
WW .100Y.C M.TW results.
W . 1 00Y M .TW W O M
W O
W
WW .100Y.C M.TW
O
W W
8.2 .C
Clock O Sources
W 0 Y W .1
W .10 O M.T W .1
C OMclock source options, W W OM
.Cby
W W 00 Y .C W The deviceW
.T below. The clockWfrom
W has the 0 .
following
Y
10 the selected M .T W W selectable
. 0 0 Y
1 clock O
Flash
M .TW Fuse bits as shown
. 1 M . O W
WW .100Y.C M.TW
W O source is input to the AVR generator, and routed to the
WW .100Y.C M.TWappropriateWmodules.
W 0 0 Y.C .T W
.1 M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00
W.1 Y.COM Table
.T 8-1. Device W.1Clocking .C OM Select(1)
Options W W.1 Y.COM W
W W
W W
. 1 00 M .TW Device Clocking
W
OptionW . 100
Y
O M .T W
W .100 O M.TCKSEL3:0
W O WW .100Y .C
WW .100Y.C M.TExternal W WW .100Y.C M.TW .TW
M1111
Crystal/Ceramic W Resonator O W O - 1010
W
WW .100Y.C MExternal
O
.TW Low-frequency WW Crystal 0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO 1001
W .C O WW 00Y.CO .TW W W
W W
. 1 00 Y
M
W
.T RC Oscillator W.1
External
W
O M W .1 O1000M.T- 0101
W O .C WW .100Y. C W
WW .100Y.C Calibrated .TW Internal RC WW .
Oscillator1 00Y M .TW 0100 M -
.T
0001
M W O W O
W
WW .100Y.C External
O
.T W Clock WW .100Y.C M.TW WW .100Y.C 0000 M.T
W
M W O W C O
W O W .C W Y. .TW
WW .100Y.C Note: M.1. TWFor all fusesW “1” means . 1 00Y
unprogrammed M TW “0” meansW
.while W
programmed. .100 O M
WW 00Y.C O .C
W
WW .100YThe .COvarious .T Wchoices forW each clocking option is .TW in the following
given WW sections. . 1 00Y When TWCPU
M.the
M W .1 O M W C O
W O .C WW is .used Y . W
WW .100wakes Y.C up from .TWPower-down WW or Power-save,
. 1 00Y theMselected .TW clock source 100 to time .Tstart-
the
M
W O M W O W
W When O
C CPU starts
.the
0Y.C allowing
up, .ensuring stable Oscillator W operation before instruction execution Wstarts.
WW .10from 0Y CReset, .T W Wadditional 1 0 M .TW .1 00Y levelMbefore .TW
M there is as an W . delay O the power to reach W a stable O
W .CO .normal WWThe Watchdog 0Y.C Oscillator TW is used forWtiming this
W Y.C part
00real-time W
WW .1commencing
00Y M T W operation.
W . 1 0
O M . W .1 O M.T of
W O .C W C
0Y. in Table
WW .the 0 Y.C time.
0start-up .TW The numberW ofW WDT Oscillator
1 00Y cycles M
W for eachWtime-out
.Tused . 1is0shown M .TW
1
W8-2. The O M W . O W O
.C Sum-
WW mary” 0 Y .Cfrequency .T W
of the Watchdog Oscillator is voltage
WW .100Y.C M.TW
dependent as shown
WW in.1“Register 00Y M.T
W
.1 0 on page M 334. W O W C O
W
WW .100Y.C M.TW
O
W O
Table
W 8-2.Y.CONumberWof Watchdog W W
Oscillator .CO .TW
Cycles
WW .100Y.C M.TW
WW .Typ 00Time-outM . T W . 1 00Y M
W W 1
. C O (VCC = 5.0V) TypW
W Time-out .(V
Y CCC O = 3.0V)
W
Number
W WWof Cycles 0 Y .CO .TW
Y W W 0
0 ms M. T 0
W 00
W.1 Y.4.1 Oms M.T W.1 4.3 Y . C O 4K W W.1 Y.COM W
(4,096)
C W W
W W
.1 00 65 msM.TW W
W . 00ms
169 O M .T W
64K W .100
(65,536) O M.T
W O WW .100Y .C
W
W O W O
8.3 Default Clock Source
W
WW .100Y.C M.TW
O
The W W is shipped
device .C O with CKSEL = “0001”W and
WSUT =Y“10”. .COThe.default W clock W WWsetting
source 0 Y
is.CO
Y W W 0 0 T .1 0
W
thereforeW the .1100MHz Internal .T
OM RC Oscillator withWlongest W.1 startup .C
M This default setting
Otime. WW ensures
W Y .C W W source 0 Y W W
thatW all users.1can
W
00 make M .T
O their desired clock W
0
W.1 setting O M.T an In-System or Parallel
using
C .C
W
Programmer. W
1 00Y
.
M .TW W .100
Y
M .TW
W . O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
8.4 Crystal Oscillator
W W WW 00Y.CO .TW
W .100 and XTAL2
XTAL1
W
.T
OM are input and output, W
.1
Wrespectively, M
.CO of an.Tinverting amplifier which can be con-
W W W 0 Y .C T W W 0 0 Y W
M.T figured
.1 0 for use as
M .an On-chip Oscillator,
W. 1
as shown OM
in Figure 8-2. Either a quartz crystal or a
C O W W .C O W Y .C W
. .TW W ceramic Y
resonator may Wbe used. W The CKOPT
.100Fuse selects .T between two different Oscillator
00Y
W.1 Y.COM W W
amplifier.100modes.OWhen M.T CKOPT is programmed, W W the .C OM output will oscillate will a full rail-
Oscillator
WW Y. C Y W
1 00 M .T to-rail . 100 on the
swing M .TW This mode
output.
W
is suitable
W .100when operatingO M.T in a very noisy environment or
. W O .C
W .CO .TW W the 0output 0Y.C from .TW drives W
W 00Y buffer. .TWmode has a wide frequency
. 1 00Y M
Wwhen
W . 1 O M XTAL2 a second.1clock
W O M This
.C smaller
WW 00Y.CO .TW WW When
range.
1 0 Y.C is unprogrammed,
0CKOPT .TW Wthe W Oscillator
. 1 00Yhas a M .TW output swing. This reduces
W. 1 OM W . M
Oconsiderably. This mode W O
WW .100Y.C M.TW
power consumption has a limited frequency range and it can not be
WW .100Y.C M.TW WW
used to drive . 1 0Y.CclockMbuffers.
0other .TW W O
WW .100Y.C M.TW W
W .C O For resonators,
W W.1 theYmaximum .CC1 OM frequency is 8 MHz
W WW with CKOPT
0 .COunprogrammed
Yfor
and 16 MHz with
W and resonators. The
W Y W CKOPT W programmed. 0 and .T C2 should W
always be 0
equal both .T
crystals
W 00 .T
W.1 Y.COM W optimal value W.of10
.C OM depends on theW W.1 Y.COM W
W W W the
0 0 Y capacitors
.T W W crystal or resonator in.Tuse, the amount of stray
100
W .1 00 M .T capacitance, . 1
Wand theYelectromagneticO M noise of W W .
the environment.
M
.CO Some initial guidelines for
W W .C O W .C W W 0 Y TW
.ceramic
W 0 0 Y .T W choosing Wcapacitors . 1 0 0for use M with.Tcrystals are given in .Table 1 0 8-3. For M resonators, the
W W.1 Y.COM W capacitor values WWgiven Y
O
.Cthe W W W W
0 Y .CO .TW
W 00 .T W 0 0 by .T
manufacturer should be used..1 0 M
W W 0 .T W
W
W .100 O M.T Figure 8-2. W Crystal
W .10Oscillator
.C OM Connections W W.1 Y.COM W
WW .100Y. C W Y W W 00 .T
W O M.T
W
W .100 O M.T C2 W W.1 Y.COM W
WW .100Y . C
WW .100Y.C M.TW M .TW WXTAL2.100
W O M.T
O W O .C
W
WW .100Y.C M.TW WW .100Y.C M.C1 TW WW .100Y M.T
W
W O W O
WW .100Y.C M.TW
W O XTAL1
W W .C O
W 00 Y .T W .1 M GND .1 M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C TW each optimized
WW .100Y. The Oscillator M.T
W can operate W in three Y
.100 different M.modes,
W
W
00a specific
.1for .T
OM frequency
W O W C O W .C
Y 8-3. .TW
WW .100Yrange. .C The .TW WWis selected Y. .TWCKSEL3:1W 00Table
operating mode
.100 by the Mfuses as shown.1in M
W W .C O M W W Y .C O
W W W W
0 Y .CO .TW
W Y W
00Table 8-3. .T Crystal OscillatorW W .10
Operating 0 Modes .T .1 0 M
W.1 Y.COM W W .C OM WW 00Y.CO .TW
W W Frequency Y
00 RangeM.T Recommended RangeW W
W
W .100 O M.T W.1(MHz)Y C O W W.1for Capacitors
.C OM C1
.C W . W Y (pF) .TW
WW .100Y W .100
CKOPT CKSEL3:1 and C2 for Use with Crystals
.TW W . 1 00 M .T M
W W 1 .C O M 101 (1)
W W 0.4 - 0.9 Y .C O
W W W– W
0 Y . O .TW
C
00Y W W 00 .T 0
W
W.1 1Y.COM 110
.T W.-13.0 Y.COM W W W.1 Y.COM W
W 0.9 12 - 22
W W
.1 00 M .TW W
W . 100 O M .T W
W .100 O M.T
W 1 O 111 3.0 - 8.0 Y.C W-W Y. C
WW .100Y.C M.TW WW 1 00 M .TW
12 22
.100 M .TW
W 0 O 110, 111 W≤ . O W W .C O
WW .100Y.C M.TW 00Y W
101, 1.0 12W - 22
WW .100Y.C M.TW W . 1 O M.T
W 1. ThisOoption should not be usedWwith crystals, W O .C
WW .100Y.C M.TW
Note: W .C
00Y only with W resonators.
ceramic
.T WW .100Y M.TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 CKSEL0
WThe .C OM Fuse together with the W.1 fuses
WSUT1:0 Y
M
.COselect.Tthe Wstart-up times as shown in Table 8-
W Y W W 0 0
W 4. .100 M .T . 1 M
W
O M.T Table
W .1 8-4. O
C
M
Start-up Times for the Crystal W W.1 Oscillator .COClock
M Selection
00 Y .C
.T W W W
1 0 0 Y .
M .T W W . 0 0 Y
1 Additional M .TW
. 1 M W . O Start-up Time fromW O Delay
W Y.C
O
WW .100Y.C M.TWPower-down WW and .100 from Reset
Y.C W
. 1 0 0 M .T W
W O W O M.T
W .CO .TW .C WW .100(VYCC = 5.0V) .C
00Y WW CKSEL0 YSUT1:0
100 M .TW
Power-save
M .TW Recommended Usage
. 1 M W . O W .C O
WW 00Y.CO .TW WW0 .100Y.00 C
.TW 258 CK(1) W
W
. 1 00Y 4.1 ms M.TW
Ceramic resonator, fast rising
W. 1 OM M W O power
W Y .C W W WW 00Y.CO .TW W W 0 0 Y.C . T W
W 00 .T 0 W.
1 01 OM .1 M Ceramic resonator, slowly
W W.1 Y.COM W W Y .C W258 CK(1)
W WW 0650Y ms.CO .Trising W power
W .1 00 M .T W . 1 00 M .T W . 1 O M
WW 010 O
W
WW .100Y.C M.TW
O
W 0 0Y.C M.T1K WCK(2) WW .10–0Y.C M.Ceramic TW resonator, BOD
W . 1 O W C O enabled
W
WW .100Y.C M.TW
O
W O Ceramic resonator, fast rising
W W Y .C O
W 0
W WW 11 00Y.CO 1K .T
CK
W
(2)
W W 4.1 ms
1 0 0 Y.C power .T W
W 0 0 .T .1 M . M
W W.1 Y.COM W WW 00Y.CO .TW W WW 00Y.COCeramic .TWresonator, slowly
W 00 .T 1 W 00.1 M
1K CK (2)
65 .
ms 1 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C rising M
power
.TW
O W O W .C O
Crystal Oscillator, BOD
W
WW .100Y.C M.TW 1 WW01 .100Y.C 16KMCK .TW WW– .100Y enabled M .TW
W O W O W
WW .100Y.Crystal CO
WW .100Y.C M.TW 1 WW .100Y.C M.TW M .TW fast rising
Oscillator,
O 10 W 16KO CK 4.1 ms W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y power
M.T
W
W O W O
W O 11 W .C W Y.C Oscillator,
Crystal
.TWslowly
WW .100Y.C M.TW1 W . 100Y16K CKM.TW 65W ms
W .100rising power O M
W O
W
WW .100Y.C Notes:
O
W OM 1. These options W should only beO used when not operating close
Y.C stability.TatWstart-up is not WWto the 0Y .CO frequency
maximum
TWThese
of the
WW .100Y.C M.TW device, and WW 0 0
only if frequency Wimportant . 1 0
for the .
application.
M
W.1 for crystals. OM W O
W O
WW .100Y.C M.T2.W These options
options are not
WW .100Y.C M.TW
suitable WW .100Y.C M.TW
W O areW intended forC O with ceramic resonatorsWand
use Wwill ensure O
.Cfrequency stability
W W 0 Y.C
.T W W W
at start-up. They can also 0 0 Y . T W
be used with .crystals when not operating W .1 0 0 Y
close to the M .TW fre-
maximum
0 1
W. if frequency OMstability at start-up is W O application.
W.1 OM quency of the device, Y.C
W .Cthe
Yfor W
WW .100Y.C M.TW WW and .1 0 0 M .T W W not important . 1 0 0 M.T
O W O W . C O
8.5
W
WW .100YCrystal
Low-frequency .C W
.TOscillator WW .100Y.C M.TW WW .100Y M .TW
M O W O
W .COa 32.768 WW as 0the .C source
0Yclock TWfor the device, WWthe Low-frequency 00Y
.C .TW
WW .10To 0Yuse .T WkHz watchWcrystal
M be selected byW . 1 M . W .1 O M Crystal
W Oscillator .CO must W
W setting.10the .CO fuses
0YCKSEL TW to “1001”.WThe crystal
W Y.C be .con-
00should W
WW .1nected00Y as shown M .T W
W O M . W .1 O MT
W .CO on XTAL1
in Figure 8-2. By programming
Y.C
the CKOPT Fuse, the user can
WW .100Y. The M
enableC internal
WW .capacitors
00Y .TW and XTAL2, WWthereby 1 00removing M .TW
the need for external capacitors. .TW
inter-
1 M W . O W O
W capacitors
WW nal 0 Y.C
O have a nominal value
.T W WW of 36 pF.
0 0Y.C M.TW WW .100Y.C M.TW
0 . 1
W.1 Y.COM W WW times Y.are COdetermined W by theW WW 00Y.CO .TW
WW When . 1 0 0this Oscillator
M . T is selected,W start-up
. 1 0 0 M .T SUT fuses
W .1 as shown OM
in
W O W C O W . C W
WW .100Y.C M.TW
Table 8-5. WW .100Y. M .TW W .100
Y
M.T
W O W .C O
WW
W .CO .TW W .C
00Y Crystal W W
WSelection 100
Y .TW
Table 8-5.
. 1 00Y Start-up M
Times for the WLow-frequency . 1 O M .T
Oscillator Clock
W . O M
W O WW 0Delay 0Y.C M.TW WW .100Y.C M.TW
WW .100Y.C Start-up.T W from WAdditional
Time
. 1
W W .C OM
Power-down
W
and WfromW Reset Y.CO W W WW 00Y.CO .TW
W SUT1:0.100 Y .T W 0 0 .T .1 M
W . C
Power-save
OM (1) W W.1 Y.CORecommended
(VCC = 5.0V) M
W
Usage
WW 00Y.CO .T
W
W 00 .100Y 1K M W W 4.1 ms.100 .T W
W O
CK.T
W . C
Fast
OMrising power or BOD enabled W W.1 Y.COM
.C W W
W01 W
. 1 00Y 1K CK M
(1) W
.T W 65 ms .100 Slowly
W
Y
O M T power W
.rising W .100
10W
W .CO .TW W65Wms .100Y.C .TW at start-up WW
W . 1 00Y 32K CK M
StableM frequency
W O
WWReserved
W .CO .TW
WW .100Y.C M.TW
11
. 1 00Y M
W W Y .C O
W W WW 00Y.CO
W 00 .T W.1
W W.1 Y.COM W W
28 ATmega32A W W.100 OM.T W
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
. T W WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 1. O M options should onlyW .1 M
W WNote: Y .C These
W W
beWused if frequency
0 Y .CO stability .TW
at start-up is not important for the
W .1 0 0 .
application.
M T . 1 0 M
W
8.6
O M.TExternal RC Oscillator W .1
.C OM W W.1 Y.COM W
.C W W
00Y .TW W Y
.100 insensitive M.T applications, theWexternal
W .100 RC configuration
OM
.T
W.1 Y.COM W ForWtiming
W 0 Y .C O
W W
W
0 0 Y .C
.T W shown in Figure 8-3 can be
0 T W 0 .T 1
0
W.1 Y.COM W
. used.
W
The
.1 frequency
C OM
is roughly estimated
W W.
by the equation
.C OM f = 1/(3RC). C should be at least 22
W
WpF. By programming Y . the CKOPTW Fuse, Wthe user.1can Y
00 enable M an.T W
internal 36 pF capacitor between
W .100 O M.T W .100GND, thereby O M.T removing the need W Wfor an external .C O capacitor. For more information on
W Y.C W
XTAL1 and
WW .1operation 0Y .C TW on howWto choose 0R0Yand C, M .TW
1 0 0 .T Oscillator 0 andM .details W . 1 O refer to the External RC Oscillator
W W. .C OM WW note. Y .CO .TW W W 0 Y.C .T W
W 00 Y .TW W
application . 10 0 M .1 0 M
.1 M W O W O
W
WW .100Y.C M.TW
O
W W .C O
W
Figure 8-3.
WW External Y .CORC Configuration W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W.1 Y.COM W W W.1 Y.COM WV CC
WW 00Y.CO .TW
W W 0 0 .T W .1
W
W .100 O M.T
W
W .100 OM R
.T NC
W
1
W.XTAL2 .CO .TW
M
W Y. C W W W 0 Y . C T W W 0 0 Y
W 00 .T 0 . .1 M
W.1 Y.COM W W W.1 Y.COM W WWXTAL1 0 Y .CO .TW
W W 0
W
W .100 O M.T
W
W .100 OMC
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
GND
00
W.1 Y.COM W
.T
W O W . C O W
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y M.T
W
W O W O
W O
WW .C WWoptimized Y.C .TW frequency
WW .100Y.C M .TW
The Oscillator can operate . 1 00inYfour different M .TWmodes, each W .100 for aOspecific M
O W O .C
W
WW .100Y.C range. .T WThe operating WW mode is0selected 0Y.C by TWfuses CKSEL3:0
the
. WW as .shown 1 00Y in Table M.T8-6.
W
M W . 1 O M W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.CTable
O 8-6.
.T W External WW RC Oscillator 0 0Y.COperating .TW Modes WW .100Y.C M.TW
. 1 M O
W W .C OM
W CKSEL3:0 WW 00Y.CO .TW Frequency W WW Range 0 0 Y.C
(MHz) .TW
W 00 Y .T W . 1 M .1 M
. 1 M O W O
W O WW 00Y.C 0.1W 00Y
.C W
WW .100Y.C M.TW 0101 W .1 M .TW W - 0.9
W . 1 O M.T
O W O .C
W
WW .100Y.C M.TW 0110 W
W 00Y
.C .TW W-W
0.9 3.0
. 100
Y
M .TW
W . 1 O M W O
W O
WW .100Y.C M.TW
W Y.C .TW
WW .100Y.C M.TW
0111 3.0W - 8.0
W .100 O M
W O W O W .C
WW .100Y.C M.TW
1000
WW .100Y.C M.TW 8.0 - W 12.0
.1 00Y M.T
W
W O W C O
W CO Oscillator WWstart-up Y.C are determined .TW WW Y. .TinW
WW .When 1 0 0Y.this M .TW is selected, .1 00times M
by the SUT fuses
W . 100 as shown O M
W O
WTable 8-7.O
W O W O
W
WW Table 0 Y.C
O
. T W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 8-7. OStart-up M Times for the External W RC Oscillator O Clock SelectionWW
Y.C
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00 M.T
W
O W
Additional Delay O W .C O
W
WW .100Y.C Power-down
Start-up Time
.TW and W from
from W 00Y
Reset
M W . 1 O M W O
W
WWSUT1:0 0
O
Y.C Power-save .T W WW(VCC =.15.0V) 0 0Y.C M TW
Recommended
. WW .100Y.C M.TW
Usage
0
W W00
.1
.C OM18 CK
W WW– 00Y.CO BOD.Tenabled W W WW 00Y.CO .TW
Y W .1
W
01W
.100 O18 M.CK T
W Wms .1
.C
M
OFast WW 00Y.CO .T
M
W .C W 4.1 Y rising
W power W
W
W .100
Y
O MCK .T W
W .100 .T
OM rising power W W.1 Y.COM
10 .C 18 W
65 ms .C Slowly W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100
6O (1)
11 W
WW1. This 0Y.Cshould
CK
TWbe used when
.not
4.1Wms 00Y.Fast
Woperating C risingTpower
. W frequency WW
or BOD enabled
Note: . 1 0option M . 1 close to the Mmaximum of the device.
W W Y . C O
W W WW 00Y.CO .TW
W 0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 29
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
W.1 RC
0
OM .1 M
8.7 Calibrated W Internal Y .C Oscillator W W WW 00Y.CO .TW
W 0
.10Calibrated .T .1
WThe
C OMInternal RC Oscillator W W
provides OM 1.0, 2.0, 4.0, or 8.0 MHz clock. All fre-
a.Cfixed
.TW
W
W quencies Y .
100 are nominal M
W
.T values at 5V and 25°C. W 0 Y
.10This clock Mmay .TW be selected as the system clock by
OM W . O W W .C O
C W .C Y .TW it will operate with no external
1 00Y
.
M .TW W programming. 1 00Y the M CKSEL.TW fuses as shown W
W . 100 8-8. O
in Table If selected,
M
W . O W
components. TheO CKOPT Fuse shouldW .C
0 Y.C .T W WW 0 0Y.Chardware . TW W always.10be0Yunprogrammed M
when using this clock option.
.TWinto the OSCCAL Register and
1 0 During . 1
Reset, M loads the calibration byte for theO 1MHz
W. OM WW automatically Y.C
O WW 00Y.C .TWand 1.0 MHz Oscillator fre-
0 0 Y.C .T W Wthereby . 1 0 0 M .T W
calibrates the WRC Oscillator.
. 1 At 5V,M25°C
. 1 M W O W O
WW 00Y.CO .TW WW selected,
quency
0 0Y.Cthis calibration .TW gives aWfrequency
W
. 1 0Y.C ± 3%
0within M TW
.of the nominal frequency. Using
. 1 M calibration W . 1methods Oas M described in application W notes C
available O at www.atmel.com/avr it is possi-
W O .C WW 0Y . .TW
WW .100Y.C M.TW WtoWachieve
ble . 1 00±Y1% accuracy M .TWat any given V and.1 0Temperature. M When this Oscillator is used
W W .C O W W Y .C O
W W WCCW
0 Y .CO .TW
Y W as W
the Chip
.100
Clock, the
M.T
Watchdog Oscillator will still .10
be used for the Watchdog Timer and for the
W
W .100 O M.T W O
.C information W W .C O M
Y calibration W value, see the section
WW .100Y.C M.TW WW .1For
reset time-out.
00onYmore
M .TW
on theW pre-programmed
.100 M.T
“Calibration W Byte” page O 268. W C O
W
WW .100Y.C M.TW
O
W O
W O
WW Internal
WW .100Y.C M.TW Table 8-8. . 1 00YCalibrated M RC Oscillator Operating
WW 00Y.CO .TW
Modes
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T W.1CKSEL3:0 OM .1 Nominal Frequency M
W.1 Y.COM W WW 00Y.CO .TW
(MHz)
W W W 0 Y .C T W W
W 0 0 .T 0
.10001 (1)
M . . 1 M
1.0
W 00 .T W 1 .1 2.0M
W.1 Y.COM W W W.0010 Y .C OM
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T W.1 Y.COM W
0011
W W.1 Y.C4.0OM W
.C W W 00 .T
WW .100Y M.T
W W 0100 .100 M.T W.1 Y8.0 OM
W O W C O W .C
WW .100Y.C M .TW 1. The device
Note: WW is shipped 1
.
00Ywith thisMoption .TWselected. W W.100 M .TW
. O
W O
WW
W CO
0Y.start-up WW by.10the .C fuses
0YSUT W
WW .100Y.C When M .T W this Oscillator is selected,
. 10 M TW are determined
times
. W O M.T
as shown in
W O C
W
WW .100Y.C M.TW
O Table 8-9. XTAL1 and XTAL2
WW .100Y.C M.TW
should be left unconnected
WW .100Y.
(NC).
M .TW
W O 8-9. W for the O W W .C O
WW .100Y.CTable .T W Start-up WW Times
. 1 0 0Y.C M .TW
Internal Calibrated RCW Oscillator
.1 00Y Selection
Clock
M.T
W
M W O W C O
W
WW .100Y.C M.TW
O Start-up WWTime .from 00Y
.C W Delay WW .100Y.
Additional
.Tfrom M .TW
Power-down W 1
and O M Reset W O
W O W .C
WW .100Y.C SUT1:0 .T W WW .100Y.C M(V.TCCW= 5.0V) W Recommended
Power-save . 1 00Y Usage M.T
W
O M W O W .C O
W
WW .100Y.C 00 M.TW 6W CK W 00Y
.C .TW – WW BOD enabled
. 100
Y
M .TW
W . 1 O M W O
W O
WW .100Y.C M4.1
W rising power Y.C .TW
WW .100Y.C01 M.TW 6 CK .Tms W WFast
W .100 O M
W O
W
WW .100Y10 .C(1)O .TW 6 CK WW .100Y.C M 65.ms TW WW rising
Slowly
.1 0Y.C M.TW
0power
M W O W O
W
WW .100Y11 .CO .TW WW .100Y.C Reserved .T W WW .100Y.C M.TW
M M WW 00Y.CO .TW
W WNote: Y.1. C OThe deviceW is shipped W Wthis
with
W
option 0 Y .CO .TW
selected. W
W
W .100 O M.T W .1 0
.C OM W W.1 Y.COM W
C W W
8.8
WW
External ClockW.10
0Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
O W C O W .C W
WWTo drive .C W WW .source, Y. W W Y
.100 in Figure M.T
.1 00Y the device M .Tfrom an external clock W 100 XTAL1 O M .Tshould be driven as W shown C O
W COdeviceTW Y.C fuses WW .10to0Y . W
WW 8-4. To 0run 0Y.the . on an external WW clock, .the 1 00CKSEL M .TWmust be programmed “0000”. M.T
. 1 M W can enable O W O
By W programmingOthe CKOPT Fuse, W
WW .100Y.C M.TW
theW user
00Y
.C an .internal TW 36 pFW
W
capacitor
. 0Y.C M.TW
10between
. 1 M W O
XTAL1 W and GND. .C O WW 00Y.CO .TW W W 0 Y.C W
W W
. 1 00 Y
M .T W W
W .1 O M W .1 0
O M.T
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 8-4.OMExternal Clock DriveWConfiguration
WFigure .C W.1 Y.COM W
W W
W
W .100
Y
O M.T
W
W .100 OM
.T
C W .C W
.TW WW .100Y. M .TW W .100
Y
M.T
M W O W C O
.CO .TW WW .100Y.C M.TW WW .100Y. .TW
. 1 00Y M W O W O M
W
0 Y.C
O
0
W. 1
.C OM
W WW 00Y.CO .TW EXTERNALW WW 00Y.CO .TW
Y W .1
.100 M.T W.1 Y.COM W CLOCK
WW 00Y.CO .TW
M
WW 00Y.CO .TW W W 00 .T SIGNAL W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O
W O
WW
W source .CO .TWstart-up times WW .C the.TSUT
00Y byM W fuses as shown in
WW .100Y.C M.TW
When this clock
. 1 00Y is selected, M
are determined
W . 1 O
Table 8-10. W O C
W
WW .100Y.C M.TW
O
W O
W O Table 8-10.WWStart-up W .COfor the WW Selection00Y.C W
WW .100Y.C M.TW
Times
. 1 00Y M .TExternal
W Clock
W .1 O M.T
O W O .C
W
WW .100Y.C M.TW WW Start-up .C from
Time
00Y andM.TW
Additional WWDelay.100Y M .TW
. 1
Power-down O from Reset W O
W O WWPower-save .C W Y.C .TW Usage
WW .100Y.C M.TWSUT1:0 W . 1 00Y M .TW (VCC = W5.0V)
W . 100 Recommended O M
W O W O W Y.Cenabled.TW
WW .100Y.C M.TW00 WW .610CK 0Y.C M.TW –W
. 1 00BOD M
W O W 6 CK Y.CO WW 0Fast CO power
.rising
W W 00Y
.C
.T W 01 W W
1 00 M .T W 4.1 ms W .1 0 Y
M .TW
. 1 M . W O
W O
WW 6 CK
W .CO .TW 65 ms WW .C power
00Y rising M .TW
WW .100Y.C M.T10 W . 100Y M W . Slowly
1 O
W O W O W Y. C
WW .100Y.C M.T 11W WW .100Y.C M.TW ReservedW . 100 M .TW
O W O W .C O
W
WW .100Y.CWhen .T W
applying WW clock,
an external 0 0itYis.Crequired .TtoWavoid sudden WW changes .1 00inYthe applied W
M.T clock fre-
M W . 1 O M W C O
W O
quency to ensure stable W C MCU.TAWvariation inWfrequency
of .the W .
ofYmore W from
WW .100Y.C .TW W operation . 1 00Yto unpredictable
M . .100 to ensure
than.T2%
M
one M
clock cycle to the next can lead O behavior. It is Wrequired O that the
W .CO is kept WW 00Y.C W W W 0 Y.C T W
WW .100YMCU M .T W in reset duringW such .changes
1 in the
M .Tclock frequency. W . 1 0
O M .
O W O .C
W
W O W O
8.9 Timer/CounterW O
Oscillator
O WWTOSC2), Ocrystal is
W W ForYAVR .C Omicrocontrollers with Timer/Counter
W W WW 00Y.COscillator .T W pins (TOSC1 and
W 0 0 Y.C the
.TW
W .1 00
connected M .T between the pins.
directly W . 1 external
No O Mcapacitors are needed. W The.1 Oscillator O M
is opti-
W .CO with .C W Y. C
WW .mized 00Y for use .TWa 32.768 kHz WWwatch.1crystal. 00Y Applying M .TWan externalWclock W 100 to TOSC1
source
. M .TisW
1 M W O O
Wnot recommended.
WW .100Y.C M.TW
O
W .CO WWthe same COof crystal
Y.type Woscillator asW WW 00YOscillator .CO .TW
WW Note: 0 0 YThe Timer/Counter
.T W Oscillator Wuses 1 0 0
. nominal .T
M of 36 pF.
Low-Frequency
.1 M
W W.1 and .C OM
the internal capacitors have the
W Wsame Y .C Ovalue
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
W .100 O M.T W .C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W . C O W
O W O W .C O
W
W
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M
W
8.10 .TRegister W
Description
W . 100 O M .T W
W .100 O M.T
.CO WW .100Y. C
00Y 8.10.1M.TW WW .100Y.C M.TW M .TW
. 1 OSCCAL – W
Oscillator Calibration O Register W O
W
0 Y.C
O
0
W. 1
.C OM
W WW 00Y.CO
Bit 7
W 6 5
W WW4 00Y.3CO .2TW 1 0
00 Y .T W . 1 M T
. CAL6 . 1 CAL3 OMCAL2
. 1 M CAL7 O CAL5 W
CAL4 CAL1 CAL0 OSCCAL
WW 00Y.CO .TW W WW
Read/Write 00Y R/W
.C .T W W
R/W W R/W .100R/W
Y.C R/W.TW R/W
W.1 Y.COM W
R/W
O M R/W
W.1 Y.COM W InitialW Value WW Calibration
Device Specific
W 0 Y.C Value W
W W
.1 00 M .T W
W . 10 0
O M . T
W .1 0
O M.T
W
WW .100Y.C M.TW
O
• BitsWW7:0 –.1CAL7:0: .C
00Y Oscillator .TW Calibration WWValue.100Y.C M.TW
Wcalibration O M WWthe Internal O
W .C O W Y .Cbyte W W 0 Y.C Oscillator W
W W
.1 00 Y
M .TW Writing W the
W . 1 0 0
O M
to .Tthis address will trim
W .1 0
O M.T to remove process vari-
W O ations from W the Oscillator .C frequency. W During Reset, WW the.110MHz C
0Y. calibration
WW .100Y.C M.TW in the W 1 00YHigh Byte M .T M .TWvalue which is located
signature . row (address 0x00) is W
automatically O
loaded into the OSCCAL Regis-
W .C O W W Y CO
.is W W W 0 Y.C W
W W
.1 00 Y
M .T W ter. If W
the internal
W . 1 0 0
RC used
O M .T
at other frequencies,
W the
. 1 0 calibration
O MT . values must be loaded
W O .C by first W .C
WW .100Y.C M.TW manually.WThis can.1be
W 00Y done
M .TW reading the W signature
. 00Yby a programmer,
1row M .TW and then store
W O
W O the calibration W
Wvalues in the .CO Flash or EEPROM. Then
WW .100Y.C M.TW
the value can be read by software and
WW .100Y.C M.TWloaded intoWthe OSCCAL . 1 00Y Register. M
W
.TWhen OSCCAL is zero, the lowest
W W .C O W
Wnon-zero Y .CO to this W W WW the 0 Y .CO available.T W
frequency is
Y W
chosen. WritingW .10 0 values
M. T register will increase .1 0 frequency of the Internal Oscil-
W
W .100 O M.T lator. Writing $FFWtoWthe . C O W Wfrequency. Y.C OTheM
W
WW .100Y.C M.TisW
register gives the highest available calibrated Oscillator
W .
Y
100and Flash M .TW W
W .100 is written, O M.T
O used to time EEPROM W O access. If EEPROM or Flash .C do Wnot calibrate to
W
WW .100Y.C Mmore .TW than 10%WaboveWthe
W 0Y.C frequency. .TW Otherwise, WWthe EEPROM 1 00Y or M .T write may fail.
. 10nominal M . Flash
W O Note that the Oscillator .CO .TW WW
W
0Y8.0.CO TW to other
WW .100Y.C M .TW WW is.1intended 00Y forMcalibration to 1.0, 2.0, 4.0,.1 0or MHz.M .Tuning
W as indicated O in Table 8-11. W O
W
WW .100Y.C M.TW
O values is not guaranteed,
W O W O
W
WW .100Y.C Table
O
.T 8-11.
W Internal WW RC Oscillator 0 0 Y.CFrequency .T WRange. WW .100Y.C M.TW
OM .1 M WW O
W WW .CinOPercentage Y.Cin Percentage W of
WW .100Y.C OSCCAL M .T W W Min Frequency
. 0 0 Y
1 Frequency M .T W of WMax Frequency
W .1 0 0
O M.T
Value W
Nominal O (%) Nominal C
Frequency (%)
W
WW .100Y.C M.$00
O
TW WW .100Y.C M.TW WW .100Y. M .TW
W O W O
WW .100Y.C M.TW
W O 50 100
WW .100Y.C M$7F .TW WW .100Y.C M.TW
WW 150 O
WW 00Y.CO .TW
75
W W Y .C O
W W W 0 0 Y.C .TW
W . 1 00 M
$FF .T . 1 100 M W . 1200 O M
W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
. C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
.TW
9.OMPower W
Management W .100 andOM Sleep.T Modes
W
W .100 O M.T
WW .100Y. C
00Y
. 1 M W O W O
W
0 .CO Sleep
Y9.1 .T W ModesWW .100Y.C M.TW WW .100Y.C M.TW
1 0 .CO modules
W. .C OM
W WWmodes
Sleep Y .CO the
enable W
application toW WWdown00unused
shut Y .TW in the MCU, thereby saving
00 Y .T W . 1 0 0 M .T . 1 M
. 1 M WThe AVR O W O
.C the user
WW 00Y.CO .TW power.
WWto the.1application’s
0
provides various sleep modes
0Y.C Mrequirements. .TW WW .allowing 1 00Y M .TW
to tailor the power consump-
1 tion W O
W. OM WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W
Figure 8-1 . 1 M W systems O
W O Won page Y.C
25Opresents the differentW clock
0Y.Csleep
in the ATmega32A, and their distri-
WW .100Y.C M.TW WWThe .figure
bution. 0 0 is helpful .T Win selecting Wan appropriate . 1 0 M TW Table 9-1 shows the
.mode.
1 M W O
W O W
WWclock.1options .CO their WW .100Y.C M.TW
WW .100Y.C M.TW different
00Y andM .TW wake-up sources.
W O
W O
W
WW .100Y.C M.TW
O
W W .C O
W WWActive Y .CO .TW W WW 00Y.CO .TW
Y W 0
W
W .100
O M.T Table 9-1.
W .1 0 Clock
. C OM
Domains and Wake Up
W W.1 inYthe
Sources
.C O M
Different
W
Sleep Modes
C W W
WW .100Y. M.T
W W Active Y
.100 ClockOdomains M.T
W
Oscillators
W .100 .T
OM Sources
Wake-up
W O W C W .C W
WW .100Y.C M.TW WW .100Y. .TW W .100
Y
M.T
Timer Oscillator
Source Enabled
SPM / EEPROM
O W O M W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y .TW
TWI Address
M
Main Clock
W O W O
W
WW .100Y.C M.TW
O
Enabled
clkFLASH
Ready
clkADC
Match
clkCPU
clkASY
Timer
WW 00Y.CO .TW
Other
WW 00Y.CO .TW
ADC
INT2
INT1
INT0
clkIO
W W .C O W
I/O
Y W W
W 00 .TSleep Mode
W.1 Y.COM W W.1 Y.COM W
2
W.1 Y.COM IdleW W (2) WW
W W
.100 M.T
W
W .1X00 X OXM.T X X X
W .10X0 X M.TX
O
X X
W .C O W Y .C W W W 0 Y .C T W
WW .100Y M
ADC .TW Noise W .100 X XOM.TX X(2) X(3) W.1X
0 X OM X
. X
W .C O Reduction W W Y .C W W 0 Y .C W
W Y W W 0 0 .T W .1 0 .T
W 00 M.T W.1 Y.COM W M
.CO .TW
W W.1 Y.COPower-down W W X(3) WWX
W 0 Y
W .100 M.T
W
W .100 X(2) OM.T X(2) X(3) WW
.10 X(2) OM
0Y.C M.TW
W Power-save
O .C X
C W W
WW .100Y. Standby .T W W . 1 0 0 Y
M .T W .1 0
M WXW 00Y.CO .TW
(1) (3)
W CO WW 00Y.CO X .TW X
WW .100Y.Extended M. T W W .1 (2) OM (2)
W
W.1X(2) Y.COM W
W .C O W W X .C X X W X (3) W X
WW .100YStandby (1) W W .100
Y
M.T
W 00 .T
W O M.T W .C O W W.1 Y.COM W
W
WW .10Notes: 0Y.C 1.MExternal .TW Crystal or Wresonator . 0Y asM
10selected .TW
clock source.
W
W .100 O M.T
W O W O W . C
WW .100Y.C 2. M .T2Wbit in ASSRW
W Y.C .TW W .100
Y
M.T
W
If AS is set.
W . 100 O M W C O
W
WW .100Y.C M.TW
3.O Only INT2 or level interrupt
WW INT1 00Y
C
and .INT0.
.TW WW .100Y. M .TW
.1 M W O
WTo enter CanyO of the six sleep modes,
Y.instruction WW The
Wthe SEYbit .CO in MCUCR must be written
W WW to.1logic .C and .aTW
one
00Y Register
WW SLEEP 0 0 .T Wmust be executed. . 1 0 0SM2, SM1,M .Tand SM0 bits in the MCUCR M
W W.1 Y.COM W WNoiseW Y .CO Power-down, W W WW 00Y.CO .TW
select which sleep mode (Idle, W
ADC
.10 0
Reduction,
M. T Power-save, .1 Standby, or
W
W . 100 O M .T W C O W W .C OM
W the SLEEP Y. instruction. Y W
WW .100Y.C M.TW
Extended Standby) will be activated Wby . 100 M .TWSee TableW 9-2 for a summary.
W .100 O M.T
If W O W
WMCU is00inYa.Csleep mode, O W up. 0The .C
WW an enabled
0 0Y.Cinterrupt .Toccurs
W whileW the
1 M .TW the MCUW wakes
. 1 0 MCU
Y
M.TW
. 1 M to W . O W C O
is then
WW halted
Wresumes 0
forOfour cycles in addition W
Y.C from .T W W following
the start-up
0 Y.Ctime, it .executes
0SLEEP. W
Tcontents
the interrupt
WW routine, . 1 0Y.and
0File M.TW
1 0execution the instruction . 1 M
The of the Register
W and O
.
WW are0unaltered OM WW up00from O
Y.C sleep..TIfW WW during Y.C W
SRAM
W 0 Y.C when
.T Wthe device Wwakes .1 M a Reset occurs . 1 00sleep M.T
. 1 M W O W O
W
WW .100Y.C M.TW
mode, the MCU wakes O up and executes from
WW the.1Reset 00Y
.CVector. TW
. WW .100Y.C M.T
M WW 00Y.CO
W W Y .C O
W W WW 00Y.CO .TW W
9.2 Idle Mode W 00 .T W.1 Y.COM W .1
W W.1 Y.COM W W 0 W WW
W 0 .T the MCU enter Idle mode,
When W the SM2:0 100bits areOwritten
W.CPU M.T to 000, the SLEEP instruction
W.1 Y.COM W
makes
stopping W the but. Callowing SPI, USART, W
Analog Comparator, ADC,
.T Two-wire Serial Inter-
W .1 00Y M .TW W
W .100 O M
W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Timer/Counters, W.the1 M
Wface, C OM Watchdog,W and .CO system
interrupt to continue operating. This sleep
W W 0 0 Y . .T W W . 1 0 0 Y
M .TW
W W.1 Y.COM WCPU
mode basically halts clk and clkFLASH
W W , while
0
allowing
Y .CO .TW
the other clocks to run.
W W Idle.1mode 00 enables .T W .10 external
O M.T W W .C OM the MCU to wakeWupWfrom Y
M
.CO triggered W
interrupts as well as internal
Y .C W W 0 Y T W W 0 0 .T
00
W.1 Y.COM W
.T ones
W
like
.10 the Timer
O M. Overflow and USART
W W
Transmit
.1
.C
Complete
OM
interrupts. If wake-up from the
WW Analog Comparator .C interrupt Y TW
1 00 M .T . 00Y
1the M .TW is not required, W
W
the0Analog
.10Control O
Comparator
M.Status
can be powered down by
. O setting W ACD Obit in the Analog Comparator .C and Register – ACSR. This will
W
0 Y.C .T W W
Wreduce 0 0 C
Y.consumption .T W in Idle mode. WWIf the.1ADC 0 0Y is enabled, M .TWa conversion starts automati-
.1 0 M W. 1
power M W O
WW 00Y.CO .TW WWwhen.1this
cally 0Ymode.CO is entered. .T W WW .100Y.C M.TW
0 M
W 00 .T W .1 .1 M
W.19.3 Y.CADC OM Noise Reduction W WMode .C OM WW 00Y.CO .TW
W W Y W W
W
W .100 O M.T
W
When theW .100 bits O
SM2:0 are
.T
Mwritten to 001, the SLEEP
W W.1 instruction . C OM makes the MCU enter ADC
.C W Y . C W 0 Y TWExternal Interrupts, the
WW .100Y M .TW Noise WReduction . 100mode,Ostopping M .T the CPUW but allowing
W .10 the ADC, O M.the
O W C
Y. the Watchdog
W
WW .100Y.C M.TW Two-wire WW .C
00Y address
Serial Interface .TWwatch, Timer/Counter2 WW .100and M .TW to continue operat-
. 1 M W O
W O ing (if enabled).
WWto run.
W This Y .CO mode
sleep basically halts W
W clkI/O, .clk 0Y.,Cand clk TW , while allowing the
WW .100Y.C M.TW other clocks . 1 00 M .TW W 1 0CPU
O M .FLASH
W O W
WW the .noise .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW This improves 1 00Yenvironment
O WW OM for the ADC, enabling W higher .CO resolution measurements. If
W
WW .100Y.C M.TWthe ADC isW enabled,.1a0conversion 0Y.C Mstarts .TW automatically WWwhen.1this 00Ymode isMentered. .TW Apart form the
O W O W .C O
W
WW .100Y.C M.TW ADC Conversion WW Complete .C
00Y interrupt, W an External
.Tonly WWReset, .
Y
10a0 Watchdog M .T W a Brown-out
Reset,
. 1
WSerial Interface O M W O
W O Reset, a Two-wire
WW .C Address Match Interrupt,
WW .10a0Timer/Counter2 Y.C W interrupt, an
WW .100Y.C M.TSPM/EEPROM W ready . 1 00Y an M
interrupt, .TW level interrupt
External on
W INT0 or INT1,
O M .Tan
or external inter-
W W Y .C O
rupt W on INT2 can W WW up 0the
wake 0 Y .CO from
MCU .T W
ADC Noise W W
Reduction 0
mode.0 Y.C .T W
W 00 .T W.1 Y.COM W .1 M
W .100 M.T
W 00 .T W.1 Y.COM W
9.4 Power-down
W .C O Mode W W.1 Y.COM W W
WW .100Y M
When .TW the SM2:0
W
bits are W . 100 to 010,
written O M .T
the SLEEP
W
instruction W .100 the O
makes MCUM.Tenter Power-
W O WWwhile.1the .C
WW .100Y.C down .Tmode.W In thisW W
mode, the .1 0Y.C Oscillator
0External M .TW is stopped, 00Y External M .TW
interrupts, the
W O M W C O W W .C O
W .C W Y . W W 0 Y T W
W .100
Y Two-wire
Man .TW Serial Interface
W address
W .100
watch, and
.T the
OM a Brown-out Reset,
Watchdog continue
W .10 operating
O M. (if enabled).
W O
Only External Reset, a Watchdog C
Reset, W a Two-wire .C Serial
WW .100Y. address C W
.Tmatch
W
W an External 1
.
00Ylevel interrupt M .TW on INT0 or W . 00
1an
Y
M .TInterface
W
M interrupt, W . O INT1, W or External O interrupt on
W .CO can.T WWThis.1sleep 0Y.modeC W halts allW W 0 Y.C allowing T W
WW .100YINT2 W up the MCU.
wake 0 M .T
basically generated . 1 0
clocks, M . oper-
W W .
ationC OofMasynchronous modules
W WWonly.00Y.CO .TW W WW 00Y.CO .TW
Y W
W 00
W.1 Note
.T
OMif a level triggered interrupt W.1 Y.COM W W W.1 Y.COM W
.C W W 00 the changed
W W
. 1 00Y that
M .TW W
W .
is
100 used for
O M
wake-up
.T from Power-down
W .1mode, O M.T
W O W .C
0Y.C M.TW
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on pageT69W
WW .1for 00Y
.C .T W W W
. 1 0 W .1 00Y M.
details. M W O W C O
W
WW .When .CO .TW WW .100Y.C M.TW WW .100Y. .TW
1 00Y waking M up from Power-down Wmode, there Ois a delay from the wake-up W condition .C O M
occurs
W O Y.C the clock W W
WW until 0 0theY.Cwake-up.Tbecomes W WW This
effective. . 1 0 0allows M .TW to restartW and become .1 00Y stable M.T
after
.1 O M W O W . C O
W
WW having Y.C stopped. .TWThe wake-up WWperiod.1is00defined Y.C by .the TWsame CKSEL WW 00Ydefine the .TW
. 1 00been M M
fuses 1
W . that
O M
W time-outOperiod, as described inW“Clock
reset W Sources” .CO on page 26. WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M .TW
W W .C O
Y W
9.5 Power-saveW Mode .100
W OM
. C W
W
WWhen the . 1
Y
00SM2:0 bits .are
M TWwritten to 011, W the SLEEP
W . 100 instruction O M .T makes the MCU enter W
W .100Power-OM.T
saveW
WW .100Y.C M.TW
O
mode. This mode is identical to Power-down, WW .100with Y.Cone exception: .TW WW .100Y.C M.TW
M WW 00Y.CO .T
W O
WW i.e.,
W theYAS2 .CO bit in.TASSR
WW .100Y.Cis clocked
If Timer/Counter2
.T Wasynchronously,
M device can wakeW 0 0
.1 either O
W is set,W
M Overflow or Output
Timer/Counter2
W .1 OM
will run W during sleep. .C O The upW from .C Timer W W Compare Y.C
WWfrom .Timer/Counter2 W Y W 0 0
event
W 100
Y
O M.Tif the corresponding
W
W .100
Timer/Counter2 O
.T
Minterrupt enable bits are
W W.1set in
Y.C Interrupt W 0Y .C W W
TIMSK, WWand the .100
Global
M.T
WEnable bitW in SREG.1 is0set. M.T
W O W C O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WIf.1the Asynchronous.C OM Timer is NOT W W.1 asynchronously,
clocked
Y .CO .TW
M Power-down mode is recommended
W W 0 0 Y .T W W 1 0 0
W.1 Y.COM W
instead of Power-save mode because the . contents M
of the registers in the Asynchronous Timer
W W W W
0 Y .CO T W
W 0 in Power-save . mode if AS2 is 0.
W should .100 .T undefined after wake-up
be considered
.C W W
00Y .TW W This sleep Y
.100 modeObasically M.T halts all clocks
W except .100clkASYO M.T operation only of asynchronous
, allowing
W.1 Y.COM W W Y. C W W Y .C W
00 .T WW modules, including
. 100 M
Timer/Counter2
.TW ifW clocked asynchronously.
.100 M.T
. 1 O M W O W .C O
W Y.C Standby .TW Mode WW .100Y.C M.TW WW .100Y .TW
. 1 009.6 M W O W .C O M
WW 00Y.CO .TW WW the.1SM2:0
When 0 0Y.CbitsM .
areT110W and an W W
external . 1 00Y
crystal/resonator M .TW clock option is selected, the
W . 1 O M W C O W W .C O
WW .100Y .C
.TW SLEEP W
W instruction Y
100 makes
.
M
W
T MCU enterWStandby.1mode.
.the Y
00 This M mode.TWis identical to Power-down
M W . O W O
W O with the
WW
exception C the Oscillator
.that is kept W
Wrunning. From Y.CStandby.Tmode, W the device wakes up
WW .100Y.C M.TW in six clock . 100Y
cycles. M .TW W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O
WW 9.7.100YExtended Standby W Mode
W .COM When the W W.1 bitsYare
SM2:0
M
.CO111 and W an external WW 00Y.COclock.Toption
crystal/resonator W is selected, the
W W 0 Y .T W W 0 0 . T W .1 MThis mode is identical to
.1 0 M SLEEP instructionW . 1 makes O the M MCU enter Extended WStandby C
mode.O
W O
WW .100Y.C M.TW Power-save WW .C
00Ythe exception .TWthat the Oscillator WW .100Y. M .TWExtended Standby
mode.with 1 M W is kept running. O From
W O WWwakes .CinOsix clock.TWcycles. W W.100Y OM.TW
W .C
WW .100Y.C M.TWmode, the W device
. 1 00Y up
M
W O
W
WW .100Y.C M.TW
O
9.8WWMinimizing .CO Power W
Consumption WW 00Y.CO .TW W WW 00Y.CO .TW
W 0 Y T W 1 power O M
W .10 O M. There are severalW W.1 to consider
issues
.C OMwhen trying to minimize W W.the Y . C consumption
W in an AVR
W Y .C W W 0 Y
0 sleep modes .T W W 1 0 0 .T
W 00 .T
controlled system. In general,
W.1 so that OM
should be used as W.much M and the sleep
as possible,
.CO are
W W.1 Y.COMmode W should be W
selected Y . C as few as W possible of W the Wdevice’s 0 Y
functions .TW operating. All
W . 1 00 M .T W . 1 00 M .T W .10 O M
W O W O W .C
0Y.C theMlowest
functions not needed should be disabled. In particular, the following modules may need special
WW .100Y.C consideration .T W WtryingW
10 .TW possible W . 1 00Y M .TW
OM when W .
to achieve O power Wconsumption. O
W
W O W O
9.8.1 W to Digital
WW .100Y.C M.TW
Analog O Converter
W W .CIf O enabled, the ADC will be WW enabled in.C
Y
allOsleep modes. To saveW
W W
W theYADC
power,
0 .CO should .TW
be dis-
W 00 Y .T W W 1 0 0 . T .1 0 M
abled
W.1 YconversionC OM
before entering any
W W.
sleep mode.
. C OM
When the ADC is turned
W W off and on
Y .CO .TWnext
again, the
W . Wwill be an extended W 0
conversion. Y Refer W
.T to “Analog to Digital W 0 0
Converter” on page 208
W
W .100 for details O M.Ton ADC operation.WW.10 .C OM W W.1 Y.COM W
WW .100Y. C W Y W W 00 .T
W O M.T
W
.C WW .100Y . C
9.8.2 WWComparator
Analog 1 00Y M .TW M .TW W
W .100 O M.T
W . O W O W .C
WW .1When .C W mode, the W Y.C should .TWbe disabled Wif not used. Y
.100 WhenOentering M.T
W
00Y entering M .TIdle WAnalog
W .
Comparator
100 O M W C
W ADCYNoise .CO Reduction WW In theY.other sleep
WW .100Y.C M.TW
mode, the Analog Comparator should be disabled.
WW .modes, 00 the Analog .TWComparator . 100Comparator M .TW
1 M is automatically disabled. However, if the W
Analog O is
W . C O W
WReference Y .CO .TW W W 0 Y.C be dis- W
W W set
.1 00up Y to use the
M .T W
Internal W
Voltage
W . 1 0 0 as input,
O M the Analog Comparator
W .1 0
should O M.T
W allOsleep W .C WW will.1be .C
WW abled 0 0in Y.C .T
modes. Otherwise, WW .1the 00Y Internal
M .TW Reference
Voltage 00Yenabled, M .TW
. 1 M W O W on .how O
C to TW
W
independent
WWconfigure 0 .CO
Ythe
of sleep mode. Refer to
T W
“Analog
WW .100Y.C M.TW
Comparator” on page 205 for
WWdetails 1 00Y .
W .1 0 Analog
O M . Comparator. W C O W W .
.C OM
WW .100Y. C
.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
M W . O W O
9.8.3 Brown-out Detector W
WW .100Y.C M.TW
O
If theW
W
Brown-out Detector
.C O is not needed inW theWapplication, Y .COthis module W should be W
W
W off. IfYthe
turned
0 .CO .TW
W 0 Y .T W W 0
0 it will be .T 0
.1 and OM
Brown-out
Walways.10Detector
.C
is enabled by the BODEN .Fuse,
OM power. In the deeper W W1 Y . C OM enabled in all sleep
W
modes,
WW 00Yto .C
W W 00 W M.T
hence,
W . 1 00Y consume
M .T W
W
sleep
. 1 modes,
O Mthis.T will contribute significantly
W . 1
.C O
W O .C on .page W Y
the total
WW the
current consumption.
0Y.C M .TW
Refer to “Brown-out
WW .1Detection” 00Y TW 40 for details W on how .100
to
configureW .10Brown-out O Detector. W O M W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1Reference OM .1 M
9.8.4 Internal Voltage
W Y .C W W WW 00Y.CO .TW
W The 0
.10Internal M.T Reference willW
Voltage .1
beWenabled M
W W Y .C O
W W 0 Y .when
CO needed
.T
by the Brown-out Detector, the
W as described in the sections
.T W W Analog 0 0 Comparator .T or the ADC. If these 0
modules
1 areM disabled
OM W.1 theYinternal M
.CO voltage W W. Y .COand it.T Wnot be consuming power. When
Y .C W W Wabove, 0
0on again, the .T W reference W will be disabled
1 0 0 will
. 1 00 M .T . 1 M W . O M
turned user must allow
W
the
W reference
1 0 0 Y.C to start up
.T Wbefore the output is used. If the
0 0 reference .1 is kept O onMin sleep mode, the output W. can be OMimmediately. Refer to “Internal Volt-
used
W.1 Y.COM W WW
age Reference” 0 Y .Con page.T41 W for details W on Wthe 0
start-up0 C
Y.time. .TW
00 .T W . 1 0 M . 1 M
. 1 M W O W O
W W. 1 9.8.5
.C OM Watchdog
W
Timer
W W Y .CO .TW W WW 00Y.CO .TW
Y W 0
W 00
W.1 Y.COM W
.T If the Watchdog 10 TimerOis
W.Timer C
Mnot needed in the application, Win W.1 Ythis .C O M should be turned off. If the
module
W Watchdog
W W 00 Y
is. enabled, .T W
it will be enabledW all 0
sleep
10 modes, TWhence, always consume
.and
W .1 00 M .T
In W . 1 M
O modes, this will contribute W .
.C O M
W O power. W the deeper.C sleep
WW .1significantly to the
.TW
total current consump-
WW .100Y.C M.TW W . 100Y M .TW 00Y M
W W .C O
W
tion. Refer to
W W “Watchdog
Y .C OTimer” on
W
page 42 for
W WW 00Y.CO .TW the Watchdog Timer.
details on how to configure
W 00 Y .T W 0 0 .T .1 M
W.1 YPort
9.8.6 .C OM Pins W W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W .1
W
W .100 O M.T When entering W W a.1sleep mode, .C OMall port pins shouldWbeWconfigured Y
M
.COto use.Tminimum
W power. The
W W 0 Y .C T W W 0 0 Y .T W W 1 0 0
0 . most important
W.
thing1 is then OM
to ensure that no pins drive .resistive loads.M In sleep modes where
W W.1 Y.COM Wthe both the W Y .C W W W W
0 Y .CO .TW
W .100 M.T device will be W
WI/O clock 0 I/O) and
.10(clk .T ADC clock (clkADCW
the 10 stopped,
) .are Mthe input buffers of the
W O W C OM that no power W . C Othe
WW .100Y. C
.TW W disabled.
1
This
00theY . ensures
M .TW W is consumed
.
Y
100 wake-up
by
M .TW logic when not
input
M needed. In some cases,
W . O
input logic is needed for W
detecting O conditions, and it will
W O
WWRefer.1to Y.Csection.T“Digital W Y.C TWon page 54 for
WW .100Y.C M.Tthen W be enabled. 00the M
W Input
WEnable .
and1 0 0Sleep M
Modes”
O
.
W .C O details on which pins WW Y .COIf the.T W W WW and00the Y.Cinput signal W
W W
. 1 00 Y
M .T W W are
W .
enabled.
10 0
O M
input buffer is enabled
W .1 O M.T is left floating
W O or have an analog signal W will use .C
WW .100Y.C MCC
level close to V /2, the input W buffer Yexcessive power.
W
WW .100Y.C M.TW .TW W .100 O M .T
W O
W
9.8.7 WWJTAG 0Interface 0
O
Y.C and.TOn-chip W Debug WWSystem 0 0Y.C M.TW WW .100Y.C M.TW
. 1
W.1 OM W .CO by WW 0Y .CO TW down
WW .100Y.C •MIf .the TWOn-chip debug WWsystem .1 0 isYenabled
0 M .T W
the OCDEN W Fuse and 1the
. 0 chip enter .Power
M
W O or Power save sleepW W the Y
mode, main COclock Tsource W W O
.C sleep
WW .100Y.C this .T W W 0 0to .the . W remains Wenabled. .1
In these
00Y M .Tmodes,
W
M will contribute significantly
W . 1 M
total
O current consumption. WThere are O
three
C alternative
W
WW .100Y.C ways
O
.TtoWavoid this: W W.100Y OM.TW
W .C WW .100Y. M.T
W
M W O
W
WW .100Y.C• Disable
O
.T W
OCDEN Fuse. WW .100Y.C M.TW WW .100Y.C M.TW
W W .
• C OM JTAGEN Fuse. WW
Disable W Y .CO .TW W WW 00Y.CO .TW
Y W 0
W
W.1 Y
00 .T
OMone to the JTD bit inW
0
C
• .Write MCUCSR.
W W
. 1 00 M .TW W
W . 100 O M .T W
W .100 O M.T
W TheYTDO O .C W .C
WW .1not .C pin .isTleft
00 shiftingMdata. W floating when WWthe JTAG 100
Yinterface
M
is Wenabled while
.TTDO Wthe JTAG .1up 0Y controller
0TAP .TWis
Mlevel,
If the hardware W .
connected to O the pin does not W
pull the O
logic
C
W
WW .power .CO .TW will increase. WWNote .that 00Y
.C W WW in the 0Y. chainMcon-
10scan .TW
1 00Y consumption M 1 the TDI M
O pin.T for the next device W . O
W .CO that WW Writing 0Y.Cthe M TW WW register .C
00Y to oneMor .TW
WW tains .1 0 0 aYpull-up
M .T W avoids this W problem.
. 1 0 JTD . bit in the MCUCSR
W .1 O
W O C
W leaving the JTAG
WW .100Y.C M.TW
O fuse unprogrammed
WW .100Y.C M.TW
disables the JTAG interface. WW .100Y. M .TW
W O W O
9.9
W
WW .100Y.C M.TW
Register Description
O
W W .C O
Y W
9.9.1
W
MCUCR – MCU Control
00
W.1 Register OM
.C W
W
WThe MCU .1 0Y
0Control M
Register.TWcontains control W
Wbits. 00 power management.
1for O M .T W
W .100 O M.T
W O WW .100Y .C
WBitW .100Y.C7 M.TW WW 4 .100Y3.C M2.TW 1 M.T
W
W O W O
Y.C
6 5 0
W
WW .100Y.SE CO SM2 W 0Y.C ISC10 .TW ISC01 W W
100
M .TW SM1 W SM0W.10ISC11 O M ISC00
W .
MCUCR
OM.T
W O W R/WY.C R/W W Y .C
WW 0Y0.C M.0TW 0 .TW 0 W .100
Read/Write R/W R/W R/W
WR/W 1000
R/W R/W
Initial Value .10 0 W . O 0M 0 W
W O WW
W CO W O
• Bit 7 W
W – SE: Sleep 0 0 Y.Enable . T W WW .100Y.C M.TW
W.1 OM W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 SE bit must
WThe C OM be written to logic W one Wto.1makeY.the M enter the sleep mode when the SLEEP
COMCU T
W W
1
instruction
Y .
00 is executed. M
W
.T To avoid the MCU W . 0 0
1entering the M . Wmode unless it is the programmers
sleep
W . O W O
W WW purpose, 0Yit.C is recommended .TW WW
to write the Sleep Y.C (SE).Tbit
00Enable Wto one just before the execution of
M .T . 1 0 M W . 1 O M
W O C
. waking
.CO .TW WWthe SLEEP 00Y
C
.instruction .TW
and to clear W W
it immediately
100
Yafter .TW up.
. 1 00Y M . 1 M W . O M
W Y.C
O
W WW
W
0Y .CO Sleep .TW Mode Select WW Bits.12,001,Yand .C
0 M.T
W
. 1 0 0 M .T • Bits.1 0
6:4 – SM2:0: M W O
W O .C
W .CO .TW W bits0select
WThese 0Y.C between WW sleep
.TWthe six available 0Y asM
10modes .TW in Table 9-2.
shown
. 1 00Y M W . 1 O M W . O
WW 00Y.CO .TW WW 9-2..100YSleep
Table
.C
Mode .TW Select WW .100Y.C M.TW
W. 1 OM M WW 00Y.CO .TW
W Y.C W W WSM2W
0 Y .CO .TW W
W 00 .T 0
W.1 Y.COM W
SM1 SM0 .1 Mode M
Sleep
W 0 .100 .T Idle .1
W .100 M.T
0 0
W O W C OM W W .C OM
.C W Y . W W ADC Noise 0 Y W
WW .100Y M .TW W0
W . 100 0 OM.T 1
W .10 Reduction O M.T
W O .C W Y. C
WW .100Y.C M.TW W 0W
1 00Y 1 M.TW 0 WPower-down . 100 M .TW
. W O
W O 0WW
W .CO .TW 1 W 00Y
.C W
WW .100Y.C M.TW . 1 00Y1 M
W Power-save
W . 1 O M.T
W O C
W
WW .100Y.C M.TW
O 1 WW
000Y
.C .TW0 WW .100Y.
Reserved
M .TW
. 1
W 0 Y.CO M W O
W
WW .100Y.C M.TW
O 1 WW
00 .TW 1 WW .100Y.C M.TW
Reserved
. 1 M
W W .C O
W 1 WW 100Y.CO .T0W W
Standby W(1)W 00Y.CO .TW
Y W
W 00
W.1 Y.COM W 1
.T W.11 Y.COM 1 W W.1 (1) Y.COM W
WStandby
W Extended
W W
. 1 00 M .T W
W . 100 O M .T W
W .100 O M.T
W O .C W Y .C W
WW .100Y.C MNote: .TW 1. Standby WWmode.1and 00Y Extended
M .TW mode areWonly available
Standby
.100 with external
M.Tcrystals or
W O W O
WW .100Y.C M.TW
W O resonators.
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
10. M .TW
System W
Control W and
. 100 Reset O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O
W .CO Resetting
Y10.1 W the WW 00Y.CO .TW
WAVR WW .100Y.C M.TW
0 0 .T . 1 M
W. 1 OM WW Reset, COI/O Registers W
Wtheir CO and
.values,
00 Y.C
.T W WDuring
1 0 0 Y .all
M .T W are setW to
. 1 0 0
initialY
M .TWthe program starts execution
. 1 M .
W ResetY.Vector. O W O
.C Vector
WW 00Y.CO .TW from the
WW – instruction 10 0 C to M
The instruction placed
. W
Treset WW at.10the 0YReset M
must be a JMP – absolute
.TWnever enables an interrupt
W. 1 OM jump . the handling routine.
W If the program
O
W
WW the.1Interrupt .CO .TWare not used, WWand regular .C
00Y program W
WW .100Y.C M.TW source, 00Y Vectors M W .1 O M.Tcode can be placed at these
W O W O
.C the case W is in00the Y.C
WW .100Y.C M.TW WW This
locations.
1 0
is0Yalso
M .TW if the ResetW Vector
. 1
Application
M .TWsection while the Interrupt
. W O
W O Vectors are
WWin the .COsection
Boot or vice versa. The
WW 299 Y.C in Figure
circuit diagram
TW
10-1 shows the reset
WW .100Y.C M.TW logic.W “System.1and M .TW
00YReset Characteristics” on pageW . 100definesOthe M .electrical parameters of the
W C O W W . C O W Y .C W
W Y. W reset W
circuitry. 0 0 Y .T W W .1 0 0 .T
W W.1 Y.COM W The I/O ports W W WW 00Y.CO .TW
W .100 M.T
W of .the
W 100AVR are Oany
.T
Mimmediately reset to their.1initial stateM
W C O
when a reset source goes
W C O active. This W
does not require. C clock source to be W running. Y . .TW
WW .100Y. M .TW W . 1 00Y M .TW W
W . 100 O M
O W O .C
W
WW .100Y.C M.TWAfter all reset WWsources Y.C gone .inactive,
00have TW a delayWW counter0is0Y
. 1 invoked,
M.T
W
stretching the Internal
W . 1 O M W C O
W O Reset. This allows
W the power
Y.C to reach a stable level before
WW .100Y normal .
operation starts.
TW The time-out
WW .100Y.C M.TW period of theW 1 0 0 .T W M .
W C O delay W
W
.
counter is
.C OM
defined by the user through
W
the
W CKSEL
Y
Fuses.
.CO .TW The different selec-
W Y . W for the delay
tions W period Y
0 presented
0are W
.Tin “Clock Sources” W W on.1page0
0 26. M
W
W .100 O M.T W W.1 Y.COM W W Y.C
O
W
.C W 0
W W
. 1 0 0 Y
M .T W W
W . 10 0
O M .T
W .1 0
O M.T
10.2 WReset
W Sources
.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W 00Y
W W . 1
.C O M
The ATmega32A
W
has
WW 00Y.CO .TW
five sources of reset:
W WW 00Y.CO .TW
W 00 Y .T W .1
W.1 Y.COM .1 is resetOwhen M the supply voltage WW OM
W
• Power-on Reset. The
W W WW MCU
0 0 Y .C .T W W
is below Y
1 0 0 .CPower-on
the
.TW
Reset
W 0 0 .T
threshold (V ). .1 M . M
W.1 OM POT
WW .100Y.C • External M. T W Reset. W
The MCU is
.1 reset when a low level is W
present onWthe .1 RESETOpin Mfor longer
W O W C OM W .C
WW .100Y. than C the
.T Wminimum pulse W
W length. 1 00Y
.
M .TW W .100
Y
M .TW
M . O W O
W •O WWis reset 0Y.when C theTWatchdog WW .C
00Y andMthe .TW
WW .100Y.C Watchdog
Watchdog WReset. The WMCU W Timer period expires
M .T .1 0 M . W . 1 O
O is enabled. W O .C
W
WW .100Y•.CBrown-out .TW WW .100Y.C M.TW WW .100Y M .TW
M Reset. The MCU is reset when Othe supply voltage V is Wbelow the O
Brown-out
W CO threshold WW 00Y.C Detector TWis enabled.W
CCW
00Y
.C .TW
WW .100Y.Reset M .T W (VBOT) W and the Brown-out. 1 M . W .1 O M
W .COAVR.T WW
W
0Y .CO there TW Win W .C
00YRegister, TW
WW .10•0Y JTAG
M
W The MCU
Reset. is reset10
. as long as M . is a logic one the Reset
W .1 O M.one
W O C
Y. Boundary-
W
WW .100scan”
ofYthe.COscan .chains T W of the JTAG WWsystem. 00Y
.C to the.Tsection
Refer W “IEEEW1149.1 W (JTAG)
. 100 M .TW
M .1 M W O
W onO page 233 for details. WW .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW W . 100Y M W O
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 10-1. OMReset Logic .1 M
W 00 .T W.1 Y.DATA M
W.1 Y.COM W CO
BUS
W W W 0 W
M .TW W
W . 100 O M .T W .10 O M.T
.CO .TW WW .1MCU C
. and Status.TW
00Y WW .100Y.C M.TW 0Y Control
0Register (MCUCSR)M
W . 1
.CO M W W .C O
W W W Y .CO .TW
PORF
BORF
EXTRF
WDRF
Y 0
JTRF
.TW 00 W 10
00Y W
W.1 Y.COM W
.T Power-on W.
.CO .TW
M
W.1 Y.COM W W 0 W
Reset W
Circuit
0 0 Y
W 0 .T .1
M
WW 00Y.CO .TW W W 00BODEN M.T W
W .1 O M W.1 BODLEVEL .C O Brown-out
Reset Circuit W
W.1 Y.COM W
.C W Y W W 00 .T
WW .100Y M.T
W W .100 M.TResistor W.1 Y.COM W
INTERNAL RESET
W O W .C O Pull-up
W
WW .100Y.C M.TW WW .100Y SPIKE.T
M
W W .100 M.T
W O W O Reset Circuit
W W . C O
WW .100Y.C M.TW
FILTER
Y W
WW .100Y.C M.TW W
W .100 O M.T
O
COUNTER RESET
W C
W
WW .100Y.C M.TW
O
WW .100Y.C JTAG Reset .TW Watchdog WW .100Y. M .TW
RegisterM W O
W O
O WW .100Y.C M.TW
Timer
W
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW Watchdog WW .100Y.C M.TW
W O Oscillator
W O
W
WW .100Y.C M.TW
O
WW 00Y.CTIMEOUT O
WW 00Y.CO .Generator
Delay Counters
W W .C O Clock
W
CK
W .TW
W 00 Y .TW W . 1 M T .1 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C CKSEL[3:0] .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
W W Y.C O
W W WW 00Y.CO SUT[1:0] .T W W
W 00 .T W.1 Y.COM W .1 M
W Power-on
10.2.1 .100 Reset M.T
W 00 .T W.1 Y.COM W
WW .100Y .TW ResetW(POR)Wpulse
A Power-on
M . 100 is generatedO M .T by an On-chip detection W
W .100circuit. O The T
M.detection level
W C O is defined in “System and
W Reset .C
Characteristics” on page 299.W The POR Y .C
is activated W whenever
WW .100Y. V Mis W
.Tbelow W Y
.100 The POR TW
M.circuit
W .100 the Start-up .T
OM Reset, as
W O the detectionW level. C O can be usedW toW trigger .C
CC
WWin supply Y. Y W
WW .100Y.CwellM as.TtoW detect a failure . 100 voltage. M .TW W
W .100 O M.T
O W O .C
W
WW .100Y.C A Power-on .TWReset (POR) WWcircuit.1ensures 00Y that
.C TWdevice is reset
.the WWfrom.1Power-on.
00Y M .TW the
Reaching
M W O M W .C O
W
WW .100YPower-on .CO .TReset W threshold WWvoltage 0 0Y.C the
invokes . TW counter,W
delay
W 00Y how
which determines
. 1 TW the
M.long
M W .1 O M W C O
W device O .C RESET signal is activated WW again, . W
WW .100when Y.C is kept .TW
in RESET after
WWVCC .rise. 1
The
00Y level.M.TW . 100
Y
without any.Tdelay,
M
V M decreases below the detection
W O W O
W
WW .100Y.C M.TW
OCC
W W Figure .C O
10-2. MCU W Start-up, WW Tied
RESET Y .CVOCC. .TW
to W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W W
V
00 .T W .1
W 00 VCC.T
POT
W.1 Y.COM W M
W
W .100 O M.T
W
VRST WW
.100 OM
.T
W W.1 Y.COM W
C .C W
WW .100Y. RESETM.TW W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W TIME-OUTO W O W .C O
WW .100Y.C M.TW
t TOUTW
W 00Y
W . 1 O M W O
W
WW .100Y.C M.TW
O
W W .C O
W 00
INTERNAL Y .T W .1 M
W.1RESETY.COM W W W.1 Y.COM W WW 00Y.CO .T
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 10-3. OMMCU Start-up, RESET .1 OM
W WFigure Y .C W W WW Extended.C
0 0 Y Externally
.TW
W . 1 00 M .T W . 1 O M
W O
.T W WW .100Y.CVCC M.TW
VPOT
WW .100Y.C M.TW
OM W O W O
0 Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 Y.COM W WW 00RESET Y .CO .TW W WW V0RST 0 Y.C W
. 1 0 0 M .T W
W . 1 O M W .1 O M.T
W .CO .TW WW .100t Y .C
. 1 M WTIME-OUT O W O
WW .100Y.C M.TW
TOUT
WW 00Y.CO .TW WW .100Y.C M.TW
W W. 1
.C OM
W 00 Y .T W .1 M
W.1 Y.COM W W W.1
INTERNAL Y.C
OM
W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100
RESET
OM
.T
W W.1 Y.COM W
. C W . C W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 OM
.T
W O C W .C
WW 10.2.2 00Y
.CExternal .TReset
W W W
1 00Y
.
M .TW W . 100
Y
M .TW
W .1 O M .
W is generated O onW W O
C ResetTW
.pin.
WW .100Y.C M.TW
An External Reset by a low level W the RESET
WW .100Y.C M.TW minimum . 1 00Y M . pulses longer than the
O pulse Wwidth (see O“System and Reset Characteristics” W .ConO page 299) will generate a
W
WW .100Y.C M.TW reset, even WW if the clock 0 0 Yis.Cnot running. .T W Shorter pulses WW are.10not 0Yguaranteed M .TWto generate a reset.
. 1
Wsignal Y M
O the Reset Threshold W O
W W .C O When the W
applied .C
reaches W W W Voltage 0– Y .C – on.TitsWpositive edge, the
V
Y W W 00 .T 0
W .100 M.T delay counter starts W.1 has Y
RST
.1the OM the Time-out periodWtTOUT M
W W .C O W W MCU
Y .C after
W W 0 .CO .TW
expired.
Y W W 0 .T 0
W 00
W.1 Y.COM Figure
.T 0
W
W W
. 1 00 M .TW 10-4. WExternal W . 00 During
1Reset O M .T
Operation W
W .100 O M.T
W O CC W
Y.C WW .100Y .C W
WW .100Y.C M.TW W . 100 M .TW W O M.T
W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
10.2.3 Brown-out
W
WW Detection 0 Y.C
O
1 0 O
W W. ATmega32A .C OM has an On-chip Brown-out WW 0Detection Y .CO (BOD) W W WW 0the 0 YV.C TW
W .1 00 Y
M .T W W
W . 1 0
O M .T circuit for monitoring
W .1 CC
O M.dur-
level
W ing operation.CO by W for the C
. can .be
WW .100Y.C M.TW TW
comparing it to a fixed trigger level. The triggerW level YBOD
WW .selected
1 00Y by the M
W
.Tfuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), W
or . 100 (BODLEVEL
4.0V O M
W O WW O W .C
WW programmed).
0 0 Y.C The.T Wtrigger level Whas a 0
hysteresis
. 1 0Y.Cto ensure M .TWspike free W Brown-out .1 00Y
Detection. M
The .TW
.1 M W O W C O
W
WW hysteresis 0Y.Con the
O
.detection
TW levelW W be0interpreted
should 0Y.C Mas .TWVBOT+ = VBOT W+WVHYST./2 0Y. VBOT-M=.TW
10and
. 1 0 M W . 1 O W O
VWBOT - VHYST/2.
WW .100Y.C M.TW
O
The
W W BOD Y circuit
. C O can be enabled/disabled WW by00the Y
O BODEN. When theWBOD
.Cfuse W W
W is enabled
0 Y .CO .TW
W (BODEN 00 .T W W .T 0
.1Figure 10- M
W.1 programmed), .C OM and VCC decreases W Wto.1a value Y . C OM the trigger level (VW
below
W
Win
BOT-
0 Y .CO .TW
W Y .TW W activated. 00 When VM W
.Tincreases above theWtrigger .10 levelOM
W 100
W5), the .Brown-out Reset is immediately
OM the delay counterWstarts W.1 theYMCU C O CC W .C
(VW
W BOT+ .100Y in Figure .C 10-5),
.T W W .1 0 0 . after
M .T W
the Time-out W period 00Yhas M.TW
tTOUT
. 1
OM W O W O
expired. W
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.T
W for lon- O
The BOD W Wcircuit Ywill .C O
only detect a drop in VCC
W W WifWthe voltage0 Y .CO stays below
.T W the triggerW Wlevel
0 0 Y.C
gerWthan tW 0 in “System
.10given .T and Reset Characteristics” 0
W.1 Y.on M 299. .1
W
BOD
.C OM
W W C O page
W W WW
W 00 Y .T W 0 0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 10-5. OMBrown-out Reset During .1 M
W WFigure Y .C W W WWOperation 0 Y .CO .TW
W 00 .T 0
W W 0
.TW M.T BOT+
V
W 100 .T CC VBOT-.10
V
M W . O M W C O
. 1 00Y M W O RESET W O M
W
0 Y.C
O
.T W WW .100Y.C M . TW WW .100Y.C M.TW
0
W. 1
.C OM
Y W .1
.100 M.T W.1 Y.CTIME-OUT OM WW 00Y.CO tTOUT
M
WW 00Y.CO .TW W W
1 0 0 .T W W . 1 M .TW
W. 1 OM W . O M W O
W O
W O
WW .100Y
WW .100Y.C M.TW
INTERNAL
RESETM
W W .C O
Y W .1
W
W .100 OM
.T
M
W 10.2.4 Y . CWatchdog W Reset W 0 W
W 00 .T
W.1 Y.COM W When the W W.1 times
0 M.Tit will generate a short
Oout, WW reset
.1 M
.COof one
W W
Watchdog
0 Y .C T W W 0 0 pulse
Y .TW CK cycle duration. On
W 0 0 .T . 1 0 M . . 1 O M
W.1 OM the falling edge of this pulse,
WW on00page O the delay timer startsW
Y.C 42 for.T
W
counting the Time-out
0Y.C M.TW
period tTOUT. Refer to
WW .100Y.C M.TW “Watchdog WTimer” 1
W
details. W . 1 0
W. OM W O
W
WW .100Y.C M.TW
O
W W .C O Figure 10-6. W
W
W
Watchdog
Y .CODuring
Reset
WOperation
W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W.1 Y.COM W CC
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W . C O W
WW .100Y.C M.TW WW .100Y MCK.T
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
10.3 Internal WWVoltage .C
00YReference .TW WW .100Y M .TW W .100 M.T
W . 1 O M W O W W .C O
WW .1ATmega32A .C TW
.features WW bandgap
an internal Y.C .TWThis reference W is used Y
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W
00Y M W . 100 reference. O M W C O
W Detection, .COand .itTcan W be usedW asW
0 .C M.TW
an input toYthe Analog Comparator W or Wthe ADC. 0The Y. 2.56V ref- .TW
WW .erence 1 00Y to theMADC is generated from the.1 0internal bandgap reference. W . 10 O M
W O
W
WW .100Y.C M.TW
O
W O
10.3.1 Voltage Reference
WW .1Enable 0 0Y.C Signals .T Wand Start-up WTime 1 M
W voltage
The OM
.Creference has a start-up Wtime W. thatYmay .COinfluence W WW be00used.
the way it should O
Y.C The .TW
WWstart-up 0 Y T W W 0 0 .T W 1 M
0
W.1 time is given .
OM in “System and W W.1Characteristics”
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CO
M on page 299. To W. power,
Wsave .COthe
W Wreference 00 Y
is .C
not always .T Wturned on. W
The reference 10 0 Y
is
.on during
M .T W
the following Wsituations: . 1 0 0 Y
M.TW
. 1 M W . O W O
WW
W
1. When 0 Y
the.CBOD O
W
is.Tenabled WW .100the
(by programming Y.CBODEN.TFuse). W WW .100Y.C M.TW
0 M
W W .1
.C OM reference is connected
W WW to00the Y
O
.CAnalog W W WW the00Y.CO .TW
W 2. When
00 Y
the bandgap .T W .T
Comparator (by setting .1 M
W.1 bitYin.CACSR).
ACBG OM W W.1 Y.COM W WW 00Y.CO .T
W W W 00 .T W
W3. When W .10the 0 ADC isMenabled.
O
.T W.1 Y.COM W W W.1 Y.COM
. C W .Tenabling theW 0
WWwhen.1the
Thus, 00Y BOD is M not
W
.Tenabled, W
after setting . 100ACBGObit
the M or ADC, W the.10user
.CO .TW to start up W
WW allow W Y.C from.Tthe
00output WW
W Analog Comparator
must Walways . 1 00Ythe reference M
Wbefore
W .the
1 O M or
W W .C O W Y . C W
Y W W .100 .T
W
W .100 O M.T W W .C OM
WW .100Y. C W Y
W O M.T
W
W .100
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 is used. OM .1 M
W WADC Y .C To reduce power consumption
W W WW 00inY.Power-down CO Wmode, the user can avoid the three
Tbefore
W 0 0 .T . 1 M .
W W.1 Y.COM W
conditions above to ensure that the reference
W W is
0 Y
turned
.CO .TW
off entering Power-down mode.
W W 0
O M.T
W
C
. 10.4 .Watchdog TimerW .C W
00Y TW W .100
Y
M.Tis clocked from a W
W .100 OM
.T
W.1 Y.COM W The W Watchdog
0Y. C O
Timer W
separate
00Y
.C
On-chip Oscillator
.TW which runs at 1 MHz. This is
0 0 .T WW . 1 0 M .T=W5V. See characterization
W .1 M
W. 1 OM the typical value at V
WW 00Y.C data O
for typical values at other VCC levels. By
Y .C W W W W
0 Y .CO CC.TW W .T W
.100 M.T controlling 0 the Watchdog
Win.1TableY.10-1 OM
Timer prescaler, the .1 Watchdog MReset interval can be adjusted as
WW 00Y.CO .TW W
shown C on pageW 44. The W
WDR WW – Watchdog 0 Y .COReset.T–W instruction resets the Watch-
. 1 M
W
W . 00
1The O M .T W .10 O M
W O dog Timer. Watchdog
Y.C Timer is also reset
WW .100Y when it is . C
disabled and Wwhen a Chip Reset occurs.
WW .100Y.C M.TW WWdifferent . 100clock M
W
.Tperiods M .Tthe
WW 00Y.CO .TW
Eight W cycle
O can be selected to determine reset period. If the reset
W W .C O W Y .C W W
Y W W expires
period 0
0without another .T Watchdog Reset, W the.1ATmega32A
W
W .100 O M.T W.1For timing C OM W .C OMresets and executes from the
.C Reset W
Vector. Y . details W on the WatchdogW Reset, 0 Y
refer to page W
41.
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O .C WW .a10special C
0Y. turn-off
WW .100Y.C M.TW To prevent WW unintentional 1 00Y disabling M .TW of the Watchdog, M .TW sequence must be fol-
W O lowed when W
the . Watchdog O is disabled. Refer to the
W W description . C O
of the Watchdog Timer Control
W .C 00Y .TW
WW .100Y.C M.TW RegisterWfor details. . 1 00Y M .TW W
W . 1 O M
W O
W
WW .100Y.C M.TW
O
W O
W O Figure 10-7. WWatchdog W .CO .TW
YTimer WW .100Y.C M.TW
WW .100Y.C M.TW W .1 0 0 M
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 YOSCILLATOR OM
WATCHDOG
.C W WW 00Y.CO .TW
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
Y. C W Y .C W W 00 .T
10.5 Register WW Description
.100 M.T
W O W .C O W
WW – MCU .C
00YControlMand .TWStatus Register WW .100Y M .TW W .100 M.T
10.5.1 MCUCSR W . 1 O W O W W .C O
WW .1The .C
00YMCU Control .TW and Status
W
WRegister . 0Y.C information
10provides M .TW on which 00Y caused
W reset.1source M.Tan
W
M W O W C O
W
WW .MCU .CO WW .100Y.C M.TW WW .100Y. .TW
1 00YReset.M.TW W O W O M
WW Bit
W
0 Y.C
O
.T 7W 6 WW5 .1004Y.C M 3 .TW 2 W1W .1000Y.C M.TW
0 CO
W.1 Y.COM JTD W ISC2 – W JTRF .CO
Y WDRF WBORF EXTRF
W
WW PORF 0Y.MCUCSR .TW
WW Read/Write 0 0 . T WW . 1 0 0 M .T .1 0 M
. 1 M R/W R/W R
W R/W
O R/W R/W R/W W R/W
.C O
W
WW Initial.1Value .CO 0 .TW 0 W0W .100Y.C M TBitWDescription W
W 00Y M.T
W
00Y M W O
.
See
W . 1
. C O
W O WW .100Y
WW Y.C
0–0JTRF: .TW WW .100Y.C M.TW M.TW
• Bit .41 O M
JTAG Reset Flag W O W .CO
WWbit is00set
WThis Y.C .T Wbeing caused WW 0 0Y .C .T WW selected
W Reset Register . 1 00Y by M.TW
1 if a reset is by a . 1
logic one in the
M JTAG W O
W. instruction . C OMAVR_RESET. ThisW W Y .CaOPower-on W W Wwriting0a0logic Y.C W
WtheW JTAG
. 1 00 Y
M .T W W bit is
W
reset
.10 0 by
O M .T Reset, or by
W .1 O M.T
zeroWtoW the flag. .CO
.TW WW .100Y.C M.TW WW .100Y.C M.T
W 00Y
W . 1
.C O M WW 00Y.CO .TW W WW 00Y.CO
• WBitW 3 – WDRF: Y Watchdog WReset Flag W
.100 .T
OM Reset occurs. The W.is 1 OaM W W.1
This bitWisW set if a Y .C
Watchdog W W W bit reset
0 Y .Cby W
Power-on Reset, W
or by writing a
W
logic zero to W .100flag. OM.T
the W .10 O M.T
WW .100Y. C
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1Bit 2Y–.CBORF: OM Brown-out ResetWFlag W.1 Y.COM W
W W W 0
W This
W .10bit0 is set ifMa .Brown-out
O
T Reset occurs. W .10The bitCisOresetM.T by a Power-on Reset, or by writing a
.C W Y . W
.TW WW logic.1zero 00Y to the M .TW
flag. W .100 M.T
M W O W C O
. 1 00Y M • Bit
W 1 – EXTRF: O External Reset Flag W .C O M
W O Y.Cif an External WW The.10bit0Y TW
0 0 Y.C .T W WW This bit
. 1 0
is 0set M .TW Reset occurs. is reset Mby. a Power-on Reset, or by writing a
. 1 M W O W .C O
W .CO .TW W zero 0to0Y .Cflag. .TW WW .100Y .TW
. 1 00Y M
Wlogic . 1 the
O M W O M
WW 00Y.CO .TW WBit WW 00Y.C .TWReset FlagW
W
1 00Y
.C .TW
1 • 0 – . 1
PORF: M
Power-on W . O M
W. OM W .CO .TW W 0Y.Conly M TW a logic zero to the flag.
WW .100Y.C M.TW WW
This bit is set . 1 0if0Ya Power-on M Reset occurs.WThe bit is .1 0reset by.writing
W O W O
W O W Y.C W Y.C .TW
WW .100Y.C M.TW To W make use.1of00the ResetM .TWto identifyW
Flags a resetW . 100
condition, the
O M
user should read and then reset
W O W C O W .C
WW .100Y .C
.TW the MCUCSR
W W Y .
as00early as possible
1 M
W
.T in the program. W 0 Y
10 registerOisMcleared
If .the .TW before another reset
M W . O W C
W O
WW .100Y.C M.TW
occurs, the source of the reset can be found by WW examining0the Y. Reset Flags. .TW
WW .100Y.C M.TW W . 10 O M
W .CO .–TWatchdog WW Control
W
0Y .CO .TW WW .100Y.C M.TW
WW10.5.2 0 0 YWDTCR W Timer . 1 0 Register M O
W.1 OM W O W
WW .100Y.C M.TW
WW .100Y.C M.TW Bit WW 7.100Y.C6 M.T5W
.COWDP1.TWWDP0
4 3W 2 1 0
W C O W W . C O W Y
W . .TW Y W W .10 0
W . 1 00Y M
W
W
–
. 100 R OM.RT
– – WDTOE WDE
W
WDP2
C O M WDTCR
W O W .C WW .100Y . .TW 0
WW .100Y.C M.TWInitial Value W 0 .100Y0
Read/Write R R/W R/W R/W R/W R/W
M 0.
TW 0 O 0M
W O 0 W 0
W
WW .100Y.C M.TW
O
W W .C O • Bits 7:5 – Res:W
W
W
Reserved Y .CO .TW
Bits W WW 00Y.CO .TW
W 00 Y .T bits are reserved W 0
10 in the O M .1 as zero. M
W.1 Y.COMThese W W.bits Y .C ATmega32A
W
and will always WW read 0 Y .CO .TW
W W W 00 .T W 0
W
W .100 O M.T W.1 Turn-off .C OM W W.1 Y.COM W
.C W W
WW .100Y •
M
Bit
.TW 4 – WDTOE: W Watchdog
W . 100
Y
O
Enable
M .T W
W .100 O M.T
W OThis bit must be set when .Cbit is written WWOtherwise, C
0Y.the Watchdog
WW .100Y.C beMdisabled. .TW Once written WW the.1WDE 00Yhardware M TW to logic zero.
.will . 10clock M .TW will not
to one, clear this bit after Wfour O
cycles. Refer to the
W O WW 00Y.CO .TW W Y.C W
WW .100Y.Cdescription M .T W of the WDE W bit for a
. 1 Watchdog disable
M procedure. W
W .1 0 0
O M.T
W O C
W
WW .100Y.C M.TW
O
W O W O
W
WW .100YWhen
• CBit
. O 3 –.T WDE: WatchdogWEnable
W is written Wto logic.1one, 0
.C
0Ythe .TWTimer is enabled, WW .100Y.C M.TW
OM the WDE M
Watchdog
WWand 0if0the O is written
.CWDE
W W Y .C W W W W
0 Y .CO .T W W Y .TW
W . 1 00to logic zero,
M .T the Watchdog Timer . 1 0
function is disabled.
M WDE can only be
W . 1
cleared if theMWDTOE
O
W O
W
WW .10bit 0Yhas.COlogic.T level
W one. To disable WW an.1enabled 0 0Y.C Watchdog . TW Timer, theWfollowing
W
.1 0Y.C M
0procedure .TW
must be
W followed: O M W O M W W . C O
Y
M.T
W
W O W C O
W 1. In.Cthe
WW .100Yten
O same operation, writeWa logic one
.TW
C WDTOE
to
0Y.before .TW
and WDE. A logic
WW one.10must 0Y. be writ- .TW
to WDEM even thoughW it is set .1
to 0one M the disable operation starts.
W O M
W O
Y.C the .next WWwrite .CO .TW
0aYlogic WW the.1Watchdog.00Y
.C W
WW .2. 1 0 0 Within
M T Wfour clock W cycles,
W . 10
O
0 M to WDE. This disables
W O M.T
W O WW .100Y. C
WW • Bits Y.C
002:0 .TW WW .100Y.C M.TW M .TW
. 1 M W O W O
WW .100Y.C M.TW
W – WDP2,
O WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 WDP2,OWDP1,
WThe C
M and WDP0 bitsW W.1 Ythe
determine .CO
M
Watchdog Timer prescaling when the Watch-
W W 0 0 Y . .T W W . 1 0 0 M .TW
W W.1 Y.COM W
dog Timer is enabled. The different prescaling
W W
0 Y
values
.CO and their
W
corresponding Timeout Periods
W W 0 .T
M.T W 100 in Table
W are .shown
OM
.T10-1. W.1 Y.COM W
.C O W .C W W
00Y .TW 00Y Watchdog
W Table.110-1. M.T Timer Prescale
W Select .100 OM
.T
W.1 Y.COM W W C O W W .C W
00 .T WW .100Y. M .TW W
Number ofW .100
WDT
Y
M.T Time-out
Typical Typical Time-out
W . 1 O M W O WCycles00Y .C O
Y.C W W W
WDP2 Y
WDP1
0 .C WDP0 .T W W
Oscillator at V.CCT W= 3.0V at VCC = 5.0V
. 1 00 M.T . 10 M W . 1 O M
W O .C 17.1
WW 00Y.CO .TW WW0 .1000Y.C M 0 W
.T 16K W W
(16,384)
. 1 00Y M
W
.Tms 16.3 ms
. 1 O M W O W . C O
W
WW .100Y.C M.TW W0W .1000Y.C 1M.TW WW .100Y
32K (32,768) 34.3 T
M.
msW 32.5 ms
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
0 1 0 WW .100Y.C 68.5Mms
64K (65,536)
.TW 65 ms
W O
W O 0 WW 1 .CO 1 128K (131,072)
WW .100Y.C 0.14Ms .TW 0.13 s
WW .100Y.C M.TW W . 100Y M .TW O s
W O W0 0O 256K (262,144)WW .C0.27
WW .100Y.C M.TW
1 0.26 s
WW .100Y.C M.TW W . 1 00Y M .TW
W O 1 W0 1 O 512K (524,288) W W 0.55O
.C s .TW 0.52 s
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M
W O 1 1W 0 O 1,024K (1,048,576) WW .CsO .TW
1.1 1.0 s
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M
1 1 W 1 O 2,048K (2,097,152) WW 2.2.C O
W O
WW .100Y.C M.TW Ys W 2.1 s
WW .100Y.C M.TW W 1 0 0
W. C function M .T
W W .C O The following code WWexample Y
O
.Cshows oneW assembly and
W Wone 0 Y .CO for turning
.TW off the WDT.
W 00 Y .T W W 1 0 0 .T
M are controlled (forW .1 0 M
W.1 OM The example assumes W. that Y interrupts
.CO execution W
example O
by disabling
0Y.C M.TW
interrupts globally)
WW .100Y.C M.TsoWthat no interrupts WW will.1occur 00 during M .T W of W functions.
these . 1 0
W W .C O
W 00 Y W
.TAssembly Code Example .1 M
W W 00 .T W
W
W .100 O M.T WDT_off: W.1 Y.COM W W W.1 Y.COM W
.C W
WW .100Y M .TW; reset WDT W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C M.TW
wdr
W O and WDE W O
W O
; Write logical one to WDTOE
WW .100Y.C M.TinW r16, WDTCR
W W .C O
W W W Y .CO .TW W WW 00Y.CO .TW
W 00 Y W
.T r16, (1<<WDTOE)|(1<<WDE)
ori 10 0 .1 M
W W.1 Y.COMout WWDTCR, r16 WW. 0Y.COM W W WW 00Y.CO .TW
W .T
W
W .100 O M .T W .10
.C OM W W.1 Y.COM W
C ; Turn off WDT W W
WW .100Y. W
M.Tr16, (0<<WDE) WW.10
W 0Y M.T
W 00
W.1 Y.COM W
.T
W O ldi
.C O W
WW .100Y.C out M .T W
WDTCR, r16 W . 100
Y
M .TW W
W .100 O M.T
W O W O W .C
WW .100Y.C retM.TW WW .100Y.C M.TW W .100
Y
M.T
W
W O W C O
W
WW .1C00Code
O
Y.C Example .TW WW .100Y.C M.TW WW .100Y. M .TW
M W O W O
W
WW .100void
O
Y.C WDT_off(void) .T W WW .100Y.C M.TW WW .100Y.C M.TW
OM W O W O
W
WW .10{0Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .10_WDR();
/* reset
0Y.C M.TW
O WDT */
W W .C O
Y W
W 00 Write M
/*
W.1WDTCR
.T
logical one to WDTOE and
O (1<<WDTOE) | (1<<WDE); W.1 Y.COM W
WDE */
W W.1 Y.COM W
.C W
W W
.1 00Y |=
M .TW W
W . 100 O M .T W
W .100 OM.T
W /* Turn off WDT */ O WW .100Y .C
W
W O W O
W O
WDTCR = 0x00;
WW} .100Y.C M.TW
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
11. M .TW
Interrupts W
W . 100 O M .T W
W .100 O M.T
.CO .TW .C WofW Y. C
00Y WWThis section1 00Y describes M .TW . 100 handling M .TasWperformed in ATmega32A. For a
. 1 O M W . O the specifics the Winterrupt
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W
0 Y.C .T W WW 0Y.C Mof
general1explanation
0 .TtheW AVR interrupt WW handling, .1 00Y refer M TW and Interrupt Handling” on
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. 1 0 M W . O W .C O
W .CO .TW W 13. 00Y.C
Wpage .TW WW .100Y .TW
. 1 00Y M W . 1 O M W O M
WW 00Y.CO .TW WWin ATmega32A 0 0Y.C M.TW WW .100Y.C M.TW
11.1 Interrupt Vectors . 1
W W. 1
.C OM
W 00 Y .T W 1 M
W.1 Y.COM W W W.1 Reset .C OMInterrupt Vectors WW. Y .CO .TW
W Table
W 11-1.
00 Y and .T W W 0 0
W
W .100 O M.T W.1 Program .C OM W W.1 Y.COM W
.C W W
WW .100Y M .TW W
Vector No. W . 0 Y
10Address (2) M.T
O Source
W
W .100 Definition
Interrupt OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 0$000
.
0Y (1) M.TWRESET W External . 0
10Pin,
Y
M .TW
1 . W O
Power-on Reset, Brown-out Reset,
W .C O WW 00Y.CO .TW W W 0 Y.C and JTAG W
W W
.1 00 Y
M.T W W
W . 1 O M Watchdog
W . 1 0 Reset,
O M T AVR Reset
.
W O .C W Y. C
WW .100Y.C M.TW 2 WW 00Y
$002
1 M .TW INT0 WExternal . 100 Request
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M .T0W
. W O
W O 3 WW $004
W .CO .TINT1 W Interrupt .C
00Y Request W
WW .100Y.C M.TW . 1 00Y M
W W
External
W . 1 O M.1T
O W O .C
W
WW .100Y.C M.TW 4 W $006
W 00Y
.C .TW
INT2 WW Interrupt
External
.
Y
100 Request M2 .TW
W . 1 O M W O
W
WW .100Y.C M.TW 5
O
WW $008.100Y.CTIMER2 W
.TCOMP WW .10Compare
Timer/Counter2 0Y.C Match M .TW
O W O M W .C O
W
WW .100Y.C M.TW
6
WW $00A
00Y
.CTIMER2 .TOVFW WW .1Overflow
Timer/Counter2 00Y M.T
W
W . 1 O M W O
W O W .C WW Capture Y.C Event .TW
WW .100Y.C M.TW
7
W$00C 00Y
TIMER1 CAPT
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Timer/Counter1
100
W O W . 1
C
M
O COMPA Timer/Counter1 W W .
.C OMA
.C 8 $00EW Y .
TIMER1 W W Compare 0 Y Match W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O WW Compare .C
WW .100Y.C M.TW .TW
9 $010 TIMER1 COMPB Timer/Counter1 YMatch B
WW .100Y.C M.TW W . 100 O M
W O 10 $012WW TIMER1 .COOVF .TWTimer/Counter1 WWOverflow 00Y
.C W
WW .100Y.C M.TW W . 100Y M W .1 O M.T
W O C
W
WW .100Y.C M.TW
O 11 $014
WW .100Y.C M.TW
TIMER0 COMP Timer/Counter0
WW .100Y.
Compare Match
M .TW
W O W O
WW .100Y.C M.TW
W O 12 $016 TIMER0 OVF Timer/Counter0 Overflow
WW .100Y.C 13 .T W WW .100Y.C M.TW
W W .C OM
W
$018
WW SPI,00STC Y .CO .Serial W
Transfer Complete
W WW 00Y.CO .TW
W 00 Y T W T
.1 RXC OM USART, Rx CompleteWW.1 M
W.1 Y.CO 14M. $01A WUSART, .CO .TW
W W W Y . C W W 0 0 Y
W .100 15OM.T
W 00 .T W.1 Y.COM W
W .C
$01C
W W.1 UDRE
USART,
.C OMUSART Data Register W
W
Empty
0
WW .100Y 16 M.TW $01E W USART, .10TXC 0Y M.T Tx Complete WW.10
W .T
W O W C O USART,
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WW .100Y17 .C .TW$020 W ADCW
1 00Y ADC
.
M TW
.Conversion W . 100
Y
M .TW
M W . O Complete W O
W
WW .10018 Y.C
O
.T W WW 0 0Y.C EEPROM .TW WW .100Y.C M.TW
$022 EE_RDY . 1 M Ready W O
W OM W O
WW .100Y.C M.TW
WW .1019 0Y.C M.T$024 W WW .100Y.CAnalog
ANA_COMP M .T W
Comparator
W .CO $026 WW 00Y.CO .TW W WW 00Y.CO .TW
WW .120 0 0 Y
M. T W W TWI .1 Two-wire W.1 Y.COM W
W C O W W .C OMSerial Interface W
WW .21 Y. .TW Y W W 0 .T
W 100 O M$028 W
SPM_RDY
W .100 Store Program O M.T Memory Ready WW.10 .C OM
W Y.C the BOOTRST W fuse isW W .C
Y device will
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Tjump W Loader.address00Y at M.TW
WNotes: 1.00When .T programmed,
. 10 M . 1
W
1
W. reset, .C OM“Boot Loader Support W
see
W
W
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on page
W
W
Y W 0 .T
W 00 the IVSEL
W2..1 When
.T
OM bit in GICR is set,W interrupt
0
W.1 vectors . C O Mbe moved to the start W
will W.1Boot Y.COM
of the
. C Y W W 00
W W Y section. The
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Flash W
M.T of the Boot FlashWsection.
address of each W Interrupt
W
0 will then
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table
W O M.T
W .C Y.C W Y.C
WW .1shows 00Y Reset M TWInterrupt W
.and . 100 M .TW W
W .100of
Table 11-2 W O Vectors W placement O for the various combinations
W
WW and
BOOTRST 0Y.C settings.
0IVSEL .TWIf the program WWnever . 1 0Y.C anMinterrupt
0enables .TW source,Wthe Interrupt
. 1 M O
W O
Y.Cand regular WW Y.C at these .TW locations. This is also
Vectors WW are not used,
. 1 0 0 M .T W program W code can be
. 1 0 0placed M
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10case if O MReset Vector is in the .1 M
W Wthe Y . C the
W W WW Application
0 Y .CO section while
.TW
the Interrupt Vectors are in the
W .1
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vice versa. . 1 0 M
W
O M.T W .1
.C OM W W.1 Y.COM W
.C W W
00Y .TW W Table.111-2. 00Y Reset M.Tand Interrupt Vectors
W .100
Placement (1)
OM
.T
W.1 Y.COM W W Y. C O W W Y .C
.TW Vectors Start Address
00 .T WW BOOTRST . 100 M .TW Reset W
IVSEL address .100 MInterrupt
. 1 M W O W .C O
W .CO .TW WW .1100Y.C M0.TW $0000 W
W
100
Y .TW
. 1 00Y M W O W . O
$0002
M
WW 00Y.CO .TW WW 1 .100Y.C M 1 .TW $0000 WW .100Y.C Boot M .TW Address + $0002
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WW .100Y.C M.TW WW 0 .100Y.C 0M.TWBoot Reset W Address 100Y $0002 .TW
. M
W W .C O W W Y .C O
W W WW 00Y.Boot CO ResetTW
W .100
Y
M.T
W W 0
W .100
1
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W .1 O M. Address + $0002
W O Note:WW C Address
Y.Reset W on Y .C W
WW .100Y.C M.TW .TW .1 0
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M.T
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.
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W 100unprogrammed O M while “0” means W
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W O
WWtypical 0Y.C
W Y. .TW Vector Addresses in
WW .100Y.C M.TW The most . 10and general M TW
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Wfor the W . 100 andOInterrupt
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W O
W O
WW .100Y.C M.TW ATmega32A WW is: .100Y.C M.TW WW .100Y.C M.TW
W O W .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW WWLabels 0 YCode W
0 W.1 Y.COM W
Address Comments
W. 1 M
ORESET
W .C O W .C W W
W Y W .100 M.T
$000 jmp ; Reset Handler
W . 1 00Y M .TW W
W . 100jmp O M .T W C O
W O WW .100Y .
0Y.C EXT_INT1
$002 EXT_INT0 ; IRQ0 Handler
WW .100Y.C M.TW $004 W
W
10jmp M .TW M .TW
W . O ; IRQ1 W
Handler O
W O
WW .1jmp .C WWHandler Y.C .TW
WW .100Y.C M.TW $006 00Y EXT_INT2 M .TW ; IRQ2
W . 100 O M
W O
WW .jmp
W .CO .TW WW Compare .C
00YHandler W
WW .100Y.C M.TW$008 1 00YTIM2_COMP M
; Timer2
W . 1 O M.T
O W O C
Y.Handler
W
WW .100Y.C M.TW
$00A
WW jmp 00Y
.C
TIM2_OVF
.TW
; Timer2 WWOverflow .100 M .TW
. 1
Wjmp TIM1_CAPT O M W O
W O $00C
Y.C
; Timer1 W Capture Handler .C W
WW .100Y.C M.T W WW jmp.100TIM1_COMPA M .TW ; Timer1 W . 1 00Y M.T
$00E W O W
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C O
W O
WWjmp .10TIM1_COMPB 0Y.C M.TW ; Timer1WCompareB
W Y. .TW
WW .100Y.C M$010 .TW W . 100Handler O M
W O $012
WW
W .CO .TW; Timer1 W W 0Y.C M.TW
WW .100Y.C M .TW jmp TIM1_OVF
. 1 00Y M
Overflow
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O
W W .C O $014
W WW TIM0_COMP
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W 00 Y .T W . 1 0 0 M . 1 M
. 1 M O W O
W O $016 jmp
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WWComplete
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00YHandler W
WW .100Y.C $018 M .T W W
jmp .1
SPI_STC M .T;
W
SPI Transfer W . 1 O M.T
O W O .C
W
WW .100Y.C$01AM.TW WW USART_RXC
jmp 00Y
.C W RX Complete
;.TUSART WW .Handler 100
Y
M .TW
W . 1 O M W O
W
WW .100Y.C
O
$01C
.T W jmp WWUSART_UDRE 0 0Y.C M ; UDR
.TW Empty Handler WW .100Y.C M.TW
. 1 HandlerY.CO
W $01E
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W TX Complete WW W
W W
.1
Y
00 $020 M.T W W
W . 1 O M .T W
W .100Handler O M.T
W O jmp ADC ;
Y.C ; EEPROM
ADC Conversion Complete
WW .100Y. C
WW .100$022 Y.C .TW jmp W
W
EE_RDY .100 M .TW Ready Handler M .TW
O M W O W .C O
W
WW .10$024 0Y.C M.TW jmp ANA_COMP WW .100Y.C; Analog .TWComparator WW Handler.1 00Y M.T
W
W O M W C O
W $026 O
WW .100Y.C M.TW
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W 00Y
.C; Two-wire
.TW Serial Interface WW .10Handler 0Y. M .TW
W . 1 O M W O
W $028 O
WW ;.100Y.C M.TW
jmp SPM_RDY
WW .100Y.C M.TW
; Store Program MemoryW
0Y.C M.TW
W Ready.10Handler
W W . C O
Y W 0
W
W .100 RESET:
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OM out SPH,r16 WW. ; YSet
10
.
MainMprogram start
C O W W.1 Y.COM W
.C W
W W $02B
.1 00Y M .TW W
W . 100 Stack
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.100
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W O M.T
W O WW .100Y .C
WW$02D.100Y.C M.T
$02C ldi r16,low(RAMEND)
W WW .100Y.C M.TW M.T
W
W O W O
O WW .100Y.C M.T
W out SPL,r16
WW $02E .100
Y.C .TW WW ;.10Enable 0Y.C interrupts M .TW
WW 00Y.CO
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W W Y .C O
W W WW 00Y.CO .TW W
W $02F
.100 M.T
<instr> xxx
W.1 Y.COM W .1
:.WW :. Y.CO :. W W W WW
W 00 .T W 0 0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 the BOOTRST OM .1 OM
W WWhen Y .C W W WW 00Y.C
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.
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W IVSEL
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W O
WW Y .CO setup W W W 0 Y.CVector .Addresses W
M .T W W general0program
W . 1 0
O M .T for the Reset and Interrupt
W . 1 0
O MT is:
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Address
.C Labels Code
WW .100Y. C
Comments
00Y WW $000 1 00Y RESET: M .TWldi r16,high(RAMEND); M .TW start
. 1 O M W . O W Main
.C O program
W
0 Y.C .T W WW $001 0 0Y.C M.TW out SPH,r16 WW .100;YSet Stack
W
M.T Pointer to top of RAM
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00Y WW$002.100Y.C Mldi .TW r16,low(RAMEND) M .TW
. 1 M W O W .C O
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W . 1 00Y M .TW
W. 1 OM W O
$004 sei ; Enable interrupts
WW .100Y.C M.TW W$005 . 1 M <instr> xxx W O
W O
W
WW .100Y.C M.TW
O
W ;W 0 0 Y.C .T W WW .100Y.C M.TW
.1 OM WW 00Y.CO .TW
W W Y .C O
W .org
W WW $3802 0Y.C
.T W W
W 00 .T W.1 Y.CO
0 M .1 M
W W.1 Y.COM W $3802 W jmp EXT_INT0
W W W; W IRQ0 Handler
0 Y .CO .TW
W 00 .T W
$3804 W.10
0 .T .1 0 M
W.1 Y.COM W W . C OM EXT_INT1
jmp
WW Handler
; IRQ1
Y .CO .TW
W Y W W 0 0
W
W .100 O M.T :. W :..
W .100 : OM.T ;
W W.1 Y.COM W
C W .C W
WW .100Y. W $3828
M.T When the BOOTRST
W .100
Yjmp SPM_RDY
M.T
W . 00
; Store 1Program
W
.T Ready Handler
Memory
OM
W O W C O W .C to W
WW .100Y.C M.TWtypical andW
W Y. is programmed
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program O
setup M for the Reset and W
Interrupt C O
Addresses
W O WW .100Y .
W O W O
W O
Address Labels Code Comments
WW .100Y.C M.TW .org $002
W W .C O
W WW jmp Y .CO .TW W WW 00Y.CO .TW
Y W .10 0 .1
W
W .100 O M.T $002
W W
EXT_INT0
.C O M ; IRQ0 Handler
WW 00Y.CO .TW
M
W Y .C W
$004 W jmp 00 YEXT_INT1 .T W ; IRQ1 W Handler
W
W .100 O M.T:. W:.1 Y.COM W ; W W.1 Y.COM W
.C :.. W W 0
WW .100Y M .T W W
W . 100SPM_RDY O M .T W .10Memory O M.T Handler
W O $028 jmp ; Store
WW .100Y.
Program C Ready
WW .100Y.C M;.TW WW .100Y.C M.TW M .TW
W O W O
W
WW .100Y.C M
O
.org.TW$3800 WW .100Y.C M.TW WW .100Y.C M.TW
WWstart O
W W Y.C O $3800 RESET: ldi
W W WW r16,high(RAMEND);
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W . 1 00 M .T . 1 0 M W .1 to top Oof M
W O $3801
WW 00Y.C
out SPH,r16 O ; Set Stack Pointer
W Y.C RAM
W
WW .100Y.C $3802 M .T W W .1
ldi r16,low(RAMEND) M .T W W
W . 1 00
O M.T
O W O .C
W
WW .100Y.C$3803 .TW WW SPL,r16
out 00Y
M W . 1 O M W O
W
WW .100Y.C
O
$3804
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. WW .100Y.C M.TW
W W $3805
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W
<instr> WWxxx 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W Fuse is W 00 the Boot section .T W
W 100 the O
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W.1 Y.COM W
size set to 4K bytes
W W.1 andY.theCO
M
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W
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W W
.1
in
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the GICR
M
Register
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W
any
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interrupts
O M
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W .10 and
M.T
general
O
W O for the Reset and Interrupt WW .100Y. C
WW .100Y.C M.TW
program setup Vector Addresses is:
W O W O
W Address
WW .org 0 Y.C
OLabels Code
Comments WW .100Y.C M.TW
0
W W. 1 $3800
. C OM
W W W Y . CO W W WW 00Y.CO .TW
Y W 0 .T
W
W .100
$3800 .T jmp RESET
OM jmp EXT_INT0WW.; IRQ0
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.C OM W W.1 Y.COM W
$3802 .C Handler W
W
W $3804 .1 00Y M
W
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W . 1IRQ1
Y
00 Handler
O M .T W
W .100 O M.T
W O EXT_INT1 ;
WW .100Y .C
WW:. .100Y:.. .C .T W WW ; .100Y.C M.TW M.T
W
W O M :
W O W W .CO
WW $3828 00Y.C .TW SPM_RDY W ; W
W Store Y.C TW ReadyWHandler.100Y OM.T
. 1 M
jmp
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W
W;W .100Y.C M.TW
O
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WW RESET:
$382A
Y .CO ldi.TW r16,high(RAMEND);
W WW Main 0 0 Y.program .T
start
W WW
W$382B W.10
0 M SPH,r16 .1 Stack Pointer M
Oout WW 00Y.CO .TW
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W W 0 Y .C W W
$382C 0 ldi .T r16,low(RAMEND) .1 M
W 00 .T W
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 47
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 $382D OM .1 M
W Y .C W
out SPL,r16
W WW 00Y.CO .TW
W 00 .T W.1 Y.;CEnable OM interrupts
W W.1$382E Y . C OM
W
sei
W 0 W
.TW .T <instr> xxx W.10 W M.T
M
W
W . 100
$382F
O M C O
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00Y Application .TW and Boot WW .100Y. .TW
. 1 00Y 11.1.1M.TW Moving Interrupts . 1 M Space W O M
W Y.C
O
WW
W CO
0Y.Interrupt W WW .C
0Yplacement W
. 1 0 0 M .T W The General
W . 1 0
O M .TControl Register controlsW .1 0the
O M.Tof the Interrupt Vector table.
W .CO .TW WW .100Y .C
. 1 M W O W O
WW 011.2 0
O
Y.C Register.T WW .100Y.C M.TW
W Description WW .100Y.C M.TW
W W. 1
.C OM
W 00 Y
11.2.1 GICR W
.T – General Interrupt 0 0
Control Register .1 M
W W 00 .T W
W
W .100 O M.T Bit
W.1 7Y.COM6 W 5 4
W W.1 3 Y.CO2M W1 0
W Y .C W W W 0 .T W 0 0 .T
W .100 M.T .10R/W W.1R Y.CROM R/W
INT1 INT0 INT2 – – – IVSEL IVCE GICR
W O W O M W
W . C W
WW .100Y.C M.TW .TW 0
Read/Write R/W R/W R R/W
W .1000
Y
0M
W
W 0.
100 0 OM.T 0
W C O Initial Value
W W .C O 0
W Y.C W
0
W W 0 Y . .T W W 0 0 Y . T W W . 1 0 0 M .T
0
W.1 Y.COM W • Bit 1 – IVSEL: .1 M WW 00Y.CO .TW
W W WW Interrupt 0 Y .CO VectorTSelect
. W W
W 00 .T .10is cleared OM .1 M the start of the Flash
W W.1 Y.COM WWhen the IVSEL W Wbit Y .C (zero), the Interrupt Vectors
W W WW are 0 Y .CO at.T
placed W
W 00 .T memory. When W this .bit 100is set (one), M .Tthe interrupt vectors W are 0
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W . 1 O M W O W .C
WW .C actual Y .TWsection is deter-
WW .100Y.C M.TW Loader section of the 1Flash.
. 00Y The M .TWaddress ofWthe start W .1of00the Boot O MFlash
W O WW fuses. O W Loader .C
WW .100Y.C M.TSelf-Programming”
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W by theW BOOTSZ
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. 1 00Y Support
M
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W O
W O Won W page Y .CO
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WW the
changes of Interrupt Vector
0Y.C bit: M.TW
WW .100Y.C Mtables, .TW a special Wwrite . 1 00
procedure must M .TW
be followed to changeW . 10IVSEL O
W O
W
WW .100Y.C M1.
O
.TWWrite the Interrupt WW Vector 0 0 Y.C .T W WW .100Y.C M.TW
.1 Change MEnable (IVCE) bit toWone. W .CO .TW
W W Y.C O
W W WWwrite0the 0 Y .CO .TW W 0 0 Yzero
W
W .100 O M.T
2. Within four cycles,
W .1 desired
. C OM
value to IVSEL while
W W.1 Y.COtoMIVCE.W
writing a
C W W sequence
WW .100Y. Interrupts M .TW will automatically W .1 0
Y
be 0disabled
M.T
while this Wis executed.
W .100 Interrupts .T
are disabled
OM the write to
W O W C O W .C W
WW .100Y.CIVSEL.
in the cycle
.TIfW
IVCE is
WW .100Y.
set, and they remain disabled
M
until after
.TWdisabled forWfour cycles.
the instruction Y following
.100 The I-bit Min.Tthe Status
M IVSEL is not written, W interrupts O remain W C O
W
WW .100Y.C
O
Register.TisW unaffected W
W
by the automatic
.C
00Y disabling. .TW WW .100Y. M .TW
M . 1 O M W O
W .CO If.T WW 00Y.C TWsection and W
W 0Y.C is programmed, W
WW .100YNote: M
W VectorsWare
Interrupt placed
W .1 in the Boot Loader
O M . Boot Lock W . 1
bit 0BLB02
O M.T
W O .C the.TApplication WWIf Interrupt . C
0YVectors M W
WW .100Y.C M interrupts
.TW
are disabled WW . 1 00YLockfrom
while executing
M
W section.
. 10are are.Tplaced
O in the Application section W
and Boot O
bit BLB12 is programed, W
interrupts O
disabled
.C while
W
WW .100Y.C executing .T W from the Boot WW 0
Loader1section. 0Y.CReferMto.Tthe Wsection “Boot WW 1
Loader .Support00Y – Read-While-
M .TW
W M Self-Programming” W
OWrite onW
. O on Boot Lock bits. W W .C O
page 252Yfor .Cdetails 00Y W
WW .100Y.C M.TW W . 1 00 M .TW W
W .1 O M.T
W O C
W
WW .•10Bit
O
0Y0.C– IVCE: W
.TInterrupt VectorWWChange Y.C
00Enable .TW WW .100Y. M .TW
M .1 M W O
WThe IVCE O WW .CO change WW .C
00isYclearedMby .TW
WW .100Y.C M.TW .TWof the IVSEL
bit must be written toW logic one to0enable bit. IVCE
. 1 0 Y M W .1 O
hardware four cycles after it is written Wor when IVSEL O is written. Setting the IVCE bit C
will
Y. disable
W
WW interrupts, .CO .TW WWdescription .C
00Y above. .TWCode Example WWbelow.’ 100 .TW
. 1 00Y as explained M in the IVSEL
W . 1 O M See W . O M
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 Code
Assembly
O M .T
Example W
W .100 O M.T
00Y WW .Move_interrupts:
100Y M .TW M .TW
. 1 O M W O W .C O
W
0 Y.C .T W WW .1;00Enable Y.C change .TW of interrupt WW vectors .1 00Y M.T
W
. 1 0 M W O M W .C O
W .CO .TW WW .100Y
ldi r16,
.C (1<<IVCE)
00Y WW out 100Y M .TW M .TW
. 1 M W . GICR, O r16 W .C O
WW 00Y.CO .TW WW ; .Move 10
C
0Y.interrupts .TWto boot W
W
Flash section . 1 00Y M .TW
W. 1 OM M W O
W
WW ldi.1r16, .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW 00Y (1<<IVSEL) M W O
W GICR, r16 O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
out WW .100Y.C M.TW
W W .C O
W Wret W Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W.1 Y.COM W C Code Example
W W 0 0 .T W .1
W W.1 Y.COM W void Move_interrupts(void)
W W WW 00Y.CO .TW
W
W .100 O M.T { W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W /*WEnable change
.100
Y of interrupt
M.T
W */ .100
vectors
W OM
.T
W O W C O W .C W
WW .100Y.C M.TW
GICR WW = (1<<IVCE); Y. .TW W .100
Y
M.T
W . 100 O M W C O
W O WW .100Y .
WW .100Y.C M.TW
/* Move interrupts to boot Flash section */
GICR = (1<<IVSEL); W O W O
W
WW .100Y.C M.TW }
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
12. M .TWPorts W W.100
I/O O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Overview
1 0 O
W. .C OM
W WAVR
All
W portsYhave .CO true.TRead-Modify-Write
W W WW 0
functionality
0 Y.C when.T W as general digital I/O ports.
used
00 Y .T W . 1 0 0 M . 1 M
. 1 M W O W .C O
WW 00Y.CO .TW This
WW
means
10
that.C the direction of one port W
0ofYany other .TpinW W pin can.10be0Ychanged M
without
.T W unintentionally changing
W. 1 OM the direction . M with the SBI and W CBI instructions. O The same applies when chang-
W Y .C W W WWvalue 0 Y CO
.configured T W W W 0 0 Y.C of pull-up .T W resistors (if configured as
W 00 .T ing drive 0 (if . as output) or enabling/disabling
.1 M
W.1 Y.COM W W.1output C OM has symmetrical drive WWcharacteristics .CO with
W W 00 .T
input).
W W Each
1 0 0 Y . buffer
M .T W W . 1 0 0 Y
M .TW both high sink and source
.1 M . W O
W O capability.W
WW
The pin driver .CO is strong enough to drive LED displays
WW .100Yinvariant .C directly. .TW
All port pins have indi-
WW .100Y.C M.TW vidually selectable . 1 00Ypull-up M .TW with a supply-voltage
resistors M resistance. All I/O pins have
W W . C O W W Y .C O
W W WW in00Figure Y .CO12-1..TRefer W
Y W W
protection diodes
.10
to0 both V CC .T and Ground as indicated .1 to “Electrical Char-
W
W .100 O M.T W C O M W W .C OM
W
WW .100Y.C M.TW
acteristics”
WW .100Y.
on page 296 for a complete
M .TW
list of parameters.
W .100
Y
M.T
W O W C O
W O
WW .100Y.C M.TW Figure 12-1. WW I/O .Pin Y.C
00Equivalent TW
.Schematic WW .100Y. M .TW
W 1 O M W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .R100 M.T
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW W pu Y
.100 M.T
W
W O W C O
W O
WW .100Y.C M.TW WW .100Logic Y. .TW
WW .100Y.C M.TW Pxn
W O M
W O
W
WW .100Y.C M.TW
O
W O
W W Y .C O
W W WW 0C 0 Y .CO .TW
pin W WSee Figure
0 0 Y23.C .TW
W . 1 00 M .T . 1 M W .1 O M
O W O "General Digital I/O"Yfor.C
W
WW .100Y.C M.TW WW .100Y.C M.TW WW Details. 1 00 M.T
W
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W All Y registers
.C O and bit references W in W this section
Y
O written in general form.
.Care W W WW A lower Y
0 .CO“x” repre-
case W
W W
.1 00 the numbering
sents M .T W W
letter for the port, W . 1and0
0 a lowerM
O
.T
case “n” represents theW 0
bit.1number. However,
O M.T
W .CO .T WWbe used. Y. C
WW .when 00Yusing the W or bit defines
register WW in.1a0program, 0Y.C the M
W form must
.Tprecise . 100 i.e., PORTB3 M .TW
1 M W O W O
Wfor bit Yno.
WW bit.1locations .CO 3 in PortW B, here documented
WW .1generally 0 0Y.C asMPORTxn. .TW The physical WW I/O 1 0Y.C M
0Registers .TW
and
00 areM .T
listed in “Register W
Description” on O
page 66. W .
C O
W
WW .100Y.C M.TW
O
Wallocated Oeach port, one each for W O
WW .100Y.C M.TW
Three
W I/OYmemory
WW– PORTx, 0 .CO address .T W RegisterW
locationsW are
0 0Ythe .Cfor .TWPins – PINx.
the Data Register
0 Data Direction – DDRx, . 1
and Port M Input The Port Input Pins
W
.1
Wlocation .C OM W
WRegister Y .CtheO
W W WWare read/write.
0 Y .CO .TW
W I/O 00 Y is read only,
.T W while the W
Data
.10 0 and Data .T Direction Register .1 0
W.1 the OM Disable – PUD bit WSFIOR C OM the pull-up functionWfor Wall OM
.Call
In
W addition,
Wports when 0 0 Y .C Pull-up
. T W W W in
1 0 0 Y .
disables
M .T W W . 1
pins
0 0 Y in
M.TW
1
W. set. OM W . O W O
W O as General DigitalWI/O” W on page O
0Y.C M.T
Using W the I/O portCas
W W 0 Y . O General .T W
Digital I/O isWdescribed
W 0 0 Y.C
in “Ports
. T W W . 1 0
51. Most port .10 pins are OM
multiplexed with alternate .1 functionsOfor M the peripheral features WW 0Port
on the O
device. W WHow each Y .C alternate W
function W
interferes WWwith 0the 0 Y .C pin is.Tdescribed
port W in W“Alternate 1 0Y.C
W .1 0 0 . T
M to the individualWmodule . 1 M W .
ORefer W sections O
W WWon page
Functions”
0 Y .C55.
.T W W 0 0 Y.C for .aTfull W description WW of the alter-
0
W.1 Y.COM W .1 M
nate functions.
W W WW 00Y.CO .TW
W 0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 that enabling OM the alternate function .1 M
W WNote Y .C W W WW of0some 0 Y .CO of the port
.TW
pins does not affect the use of the
W .1
other 0 0
pins in theM .T
port as general digital I/O.. 1 M
W
O M.T W .1
. C O M W W.1 Y.COM W
C
. 12.2 .Ports W
00Y TW as General W Digital Y I/O .TW
.100 are bi-directionalM
W .100 .T
OM pull-ups. Figure 12-2 shows a func-
W.1 Y.COM W The W ports Y. C O I/O ports W
with W optional Y .C
internal
.TW
00 .T WW . 100 M .TW W .100 called MPxn.
. 1 M tional W description Oof one I/O-port pin, here W
generically .C O
. 1 00Y M W O W O M
WW 00Y.CO .TW WW 12-2.
Figure
0
.C
0YGeneral Digital
.TW I/O
(1)
WW .100Y.C M.TW
. 1 M
W W. 1
.C OM
W 00 Y .T W .1 M
W W
W .100 M.T
W .100 M.T .1 PUD
W O W O M
W O W .C
Y
M.T
W
W O W C Q
O D
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. DDxn
M .TW
W O W O
Q CLR
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C RESET M.T
W WDx
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M .TW RDx
W O W O
W
WW .100Y.C M.TW
O
DATA BUS
W W .C O
W 00 Y .T Pxn
W .1
Q D
M
PORTxn
W W W 00 .T W Q CLR
W
W .100 O M.T W.1 Y.COM W W W.1 RESET .C OM WPx
WW .100Y .C
.TW W W
100 M .T W .100
Y
MRRx.TW
M W . O W O
W O
SLEEP
WW .100Y.C M.TW
W W .C O
W WW 00Y.CO .TW W
SYNCHRONIZERWW 00Y.CO .TW
Y W
W
W .100 O M.T W .1
C OM W W.1 Y.CORPx M
W W 00 Y .C
.T W W W
1 0 0 Y .
M .T W D Q D
WQ
PINxn
. 1 0 0 M .TW
. 1 M W . O W O
W
WW .100Y.C M.TW
O
L Q Q
W W .C O
W WW 00Y.CO .TW W WW 00Y.CclkO .TW
W 00 Y .T W .1
I/O
M
W W
W .100 M.T
W 100
.DISABLE OM
.T WDx: WRITE DDRxW.1 M
W W .C O PUD: PULLUP
W W Y .C W
RDx:
W W
READ DDRx
0 Y .CO .TW
W 00 Y .T W SLEEP:
W SLEEP CONTROL
I/O CLOCK 10 0 T
. RRx: WPx: WRITE PORTx
.1 0 M
W. OM RPx:
clk : READ PORTx REGISTER
I/O
READ PORTx PIN
W W Y .C W W
W .100 M.T
W 00 .T W.1 Y.COM W
W .C O W W.1RDx are . C OM to all pins within the
W W
WW .100Y Y W same .100 .T
Note: 1. WPx, WWDx, RRx, RPx, and common port. clkI/O, SLEEP,
M
and .TPUD are common
W
to W
all . 100
ports. O M .T W C OM
W O W .C W Y . .TW
WW .100Y.C M.TW W .1 00Y M .TW W
W . 100 O M
W O
12.2.1 Configuring W
WW .100Y.C M.TW
the Pin O
O WW O
W Each portC O consists of three register
pin
Y. on page WWbits:0DDxn, Y.C PORTxn, Wand PINxn. WAs 0 .C M.TW
shown inY“Register
WW Description” 0 0 . T W W 1 0
are. accessedOat .T
Mthe DDRx I/O address, .1 0
Obits
W.1 Y.COM W
66, the DDxn bits W the PORTxn
W bits0at Y .C PINx .I/O W W WW 0 Y.C W
WWat the .1 PORTx
0 0 I/O
M
address,
.T and the W PINxn
W . 1 0 the
O M T address.
W . 1 0
O M.T
W .CO .TW RegisterW WisWwritten .C
WW The DDxn 00Ybit in theMDDRx
W
selects the . 1 0Y.C of
0direction M .TWpin. If DDxn
this . 0Y one, M.TW
10logic
. 1
WWis configured .CO as an WWis written Y
O
.Clogic zero, W W
W
W as 0an 0 .CO .TW
Yinput
WPxn 0 Y
M. T Woutput pin. IfWDDxn
0 0 .T Pxn is configured
. 1 OM
pin. W.1
0
.C O W W.1 Y.COM W W W Y.C W
WW .100Y M .TW W
W .100 O M .T W
W .100 OM.T
If PORTxn W is written Ologic one when the pin is configured Y.C as an .input pin, the pull-up W resistor .C
is
WW .To Y.C the pull-up
00switch .TW resistor off, WW .1 00has M TW logic zeroW . 00Y
1has M.T
activated.
W 1 O M PORTxnW to be
O written or the
W Wpin to.C O
W .C W The portWpins W are tri-stated Y.C when .TW W becomes .100
Y
beW configured
.1 00asY an output M .Tpin. W . 100 O M a reset condition
W
active,W W
W even if.1no .CO are .running.
clocks
TW WW .100Y.C M.TW WW
00Y M W O
W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WIf.1PORTxn . C is M
O written logic one when Wthe W.1pin isYconfigured
.CO .Tas
M
Wan output pin, the port pin is driven
W W 0 0 Y .T W W 1 0 0
W.1 Y.COM W
high (one). If PORTxn is written logic zero. when the M
pin is configured as an output pin, the port
W W W W
0 Y . CO T W
M .TW W pin .is10driven
W
0 low (zero).
O M .T W .10 O M.
.CO .TW .C between WW PORTxn} C
Y. 0b00) W output high ({DDxn, PORTxn}
00Y WWWhen.1switching00Y M .TW tri-state ({DDxn, . 100 = O M .Tand
W . 1 O M W anYintermediate O W
W pull-up .C
00 Y.C .T W WW = 0b11),
. 10 0 .C M.TWstate with W either
.1 00Y enabled
M .TW PORTxn} = 0b01) or output
({DDxn,
W . 1 O M low W
({DDxn, PORTxn} O = 0b10) must occur.
W W Normally, .C O
the pull-up enabled state is fully accept-
0 Y.C .T W W
Wable, 0 0 Y.C .T W W . 1 0 0Ythe difference
M .TW between a strong high driver
.1 0 as
W. 1
a high-impedant M environment will not notice
CO
WW 00Y.CO .TW
M CO is notTthe
If .this
WWbit in0the 0Y.SFIOR .TW can be set to disable all
WWa pull-up.
and
. 10 0 Y
M . W case, theWPUD . 1 M Register
W. 1 OM W O
pull-ups W ports.
WW in .all .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW 1 00Y M O
W O W O
Y.Cinput with WW low00generates Y.C .TWsame problem. The user
WW .100Y.C M.TW WW between
Switching
. 10 0 M .T W pull-up andW output
. 1 M
the
W O
W O must use either
WW
W theYtri-state .CO ({DDxn, PORTxn} =
WW .100Y.C M.TW
0b00) or the output high state ({DDxn, PORTxn}
WW .100Y.C M.TW = 0b11) as an.1 00
intermediate M .TW
step. W O
WW .100Y.C M.TW Table W 12-1 summarizes .1 the M control signals for the pin value.
W W . CO
Y W
W
W .100
O M.T Table 12-1. WW Port .1 Pin Configurations
WW .100Y. C W
M.T
W W
W
Y
.100 PUDOM.T
W
W .100 OM
.T
W O W .C W Y .C W
WW .100Y.C M.TW DDxn W PORTxn .10(in 0YSFIOR) M .TW I/O W
Pull-up .100
Comment
W O M.T
W O W O W .C
WW .100Y.C M.TW 0 W0W .100YX.C M.TInput W NoW Tri-state .
Y
100(Hi-Z) OM.T
W
W O W
W
WW .100Y.C M.TW0
O
W1W 000Y
.C .TW
Input
W
Yes W Pxn will . 0Y.Ccurrent
10source M .T W
if ext. pulled low.
. 1 M W O
W O
1WW
W .CO Input W 00Y
.C W
WW .100Y.C M.TW 0
. 1 010Y M .TW No WTri-state W . (Hi-Z)
1 O M.T
W O
W
WW .100Y.C M.T1W
O 0 WW X00Y.
C OutputTW No W
.
W
Output Low . 0Y.C M.TW
10(Sink)
. 1 M W O
W .C O WW X 00Y.CO W W W High (Source) 0 Y.C W
W W
. 1 00 Y
M
1
.T W 1 W
W . 1 Output
O M .T No Output
W .1 0
O M.T
WW 00Y.CO .TW WW .100Y. C
12.2.2 W Reading
. 1 the Pin Value
M W O
W O WW 00Y.CO .TW W .C
00Ybe read .TW the
WW .100Y.CIndependent M .T W of the W setting of.1Data Direction M bit DDxn, the Wport pin
W .1 can O Mthrough
O Register bit. As shown W O .C
W
WW .100Y.C PINxn
.TW WW in.1Figure .C
00Y 12-2,M the W Register
.TPINxn WW bit and1the
. 00Y preceding
M TW con-
.latch
M WneededY.to O W O
.Cchanges
W
WW .100Ynear .CO a synchronizer.
stitute
.T W of the internal
This
WWclock,
is
0 0 it C
avoid metastability
.TW a delay. WWphysical
if the
. 1 00Y
pin
M .TW
value
.1 M O
W W .C
the
OM edge
W
W
Wwhen
but
Y
also
.CO
introduces
W W WW 00Y.C
Figure 12-3 shows a timing
.T W
dia-
Y W 0 .T
W 00 gram
W.1 minimum
of the .T synchronization
OMpropagation delays W .10
reading
Wdenoted . C
an externally
OMand t
applied pin
W W.1 Y.COM W
value. The maximum and
.C are t W respectively.
W W
. 1 00Y M .TW W
W . 100
Y pd,max
O M .T pd,min W
W .100 O M.T
W O W .C
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 12-3. OMSynchronization when .1 OM
W WFigure Y .C W W WW Reading an
0 0 Y .CExternally .TW
Applied Pin Value
W .1 0 0 M .T . 1 M
W
O M.T W .1
.C OM W W.1 Y.COM W
.C W CLK .TW
00Y .TW W .100
Y
SYSTEM
M
W .100 OM
.T
00 .T WW .100Y. M .TW W Y
.100XXX OM.T in r17, PINx
. 1 M W INSTRUCTIONS O XXX W .C
. 1 00Y M W O W O M
WW 00Y.CO .TW WW SYNC 0 Y.C
0LATCH . TW WW .100Y.C M.TW
. 1 M
W W. 1
.C OM
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 PINxn Y .C OM
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T W.1 r17Y.COM W W W.1 Y.COM W
.C W
WW .100Y W .100 M.T
0x00 0xFF
M .TW W
W . 100 O M .T W C O
W
WW .100Y.C M.TW
O
tpd, max
M .TW
O W O W .C O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW tpd, .min 1 00Y M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O WWperiod Y .CO shortly W W W W
0 Y .CO .TW
Y W
Consider the W clock
.10 0 starting
M. T after the first falling 0
edge
.1 of the system clock. The latch
W
W .100 O M.T is closed when the W .C O W Wthe .C
M
Ohigh,
W
WW .100Y.C M.Tshaded W WW .100Y clock is low, and
M
goes
.TW transparent W when
. 1 00Y
clock is
M
as
.T indicated by the
W O
W O region of theW
W “SYNC .CO signal.
LATCH” The signal W value is latched .C when.T
00Y positive
theWsystem clock
WW .100Y.C Mgoes .TW low. It isW clocked.1 00Ythe PINxn
into M
W
.TRegister W
at the succeeding . 1 M clock edge. As
W W .C O indicated by the twoWarrows W Y .C O
W W
W
Wtransition 0 Y .CO .T W
Y W W t 0
.10clock
and t .T , a single signal .10 on the pin will be delayed
W .100 .T M
pd,max
W O M W O Mpd,min W W .C O
WW .100Y.C M.TW W
between ½ and 1½ system period depending upon the time of assertion.
Y
WW .100Y.C M.TW W
W .100 O M.T
W OWhen reading back aW W .C O W C
Y. be inserted
WW .100Y.C cated .TinWFigure 12-4. W software 1
assigned
00Y M
pin value,
.TW
a nopW instruction
.
must
100 at theOpositive
M .TW as indi-
M . W
W O WW 00Y.CO .TW
The out instruction sets the “SYNC LATCH”W signal
Y.C Wedge of
WW .100Y.Cthe M T W
. In this case, the delay
clock. W .1 tpd throughMthe synchronizer is one
W . 1
system0 0 M .
clock period.
T
W W .C O
W 00 Y .T W 1 Reading .1 M
W.1 YFigure C OM12-4. Synchronization W W.when . C OMa Software Assigned W Pin ValueY.CO
W W
W . .TW Y W W .10 0 M.T
W . 1 00 M
W
W .100 O M .T W CO
W O WW .100Y .
W O W O
W
WW .100Y.C SYSTEM
O
.T W CLK WW .100Y.C M.TW WW .100Y.C M.TW
W W .C OM
W 00 Y .T W .1 M
W.1 Y.COM r16 W W.1 Y.COM 0xFFW WW 00Y.CO .TW
W W W
W 00
W.1 INSTRUCTIONS OM
.T W
.C W .C W
W Y W .100 M.T
nop in r17, PINx
.TW
out PORTx, r16
W .1 00Y M
W
W . 100 O M .T W C O
W
WW .100SYNC
O
Y.C LATCH .TW WW .100Y.C M.TW WW .100Y. M .TW
M W O W O
W
WW .100Y.C M.TW
O
W W . C O
PINxn
Y W
W 00
W.1 Y.COM W
W W 0xFF100
W W
.1 00 r17 .T
M
W
W . 0
100x00 O M .T W . O M.T
W O WW .100Y .C
WW .100Y.C M.TW WW .10tpd 0Y.C M.TW M.T
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
WThe.10 following
C OM code example showsW W.1to setYport
how
M 0 and 1 high, 2 and 3 low, and define
.COB pins
W W
the.1port Y .
00 pins from M
W
.T4 to 7 as input with W W . 1 0
pull-ups 0 assigned M .TtoWport pins 6 and 7. The resulting pin
W O O
W WW values Y.C
0are read back . TW again, but as W
Wpreviously Y.C
00discussed, W instruction is included to be able
a.Tnop
M .T . 1 0 M W . 1 O Mpins.
toW read back O
the value recently assigned to some ofC the
. 1 00Y M W O M
W Y.C
O
W
W
WWAssembly 0YCode.CO Example .TW(1) WW .100Y.C M.TW
0 0 .T . 1 0 M
W. 1
.C OM
W WW :. 00Y.CO .TW W WW 00Y.CO .TW
Y W .1
.100 M.T W;.1Define O M WW high .CO .TW
M
WW 00Y.CO .TW W W
100
Y .C pull-ups
.T W and set W outputs
0 0 Y
W .1 O M W ; .Define .C OM
directions for port pins W W.1 Y.COM W
.C W 0Y W W 00 .T
WW .100Y M.T
W W ldi.10r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
M.T W.1 Y.COM W
W O W . C O W
WW .100Y.C M.TW WWldi .1r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
00Y M.T
W W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW WW Y.C .TW W .100
Y
M.T
W
100
out PORTB,r16
W . O M W C O
W
WW .100Y.C M.TW
O
Wout W DDRB,r17 0 0Y.C M.TW WW .100Y. M .TW
. 1
W nop forO synchronization W W O
W O ; Insert .C
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M.T
W
nop
W O W C O
W
WW .100Y.C M.TW
O
;W
W
Read port Y.C
00pins .TW WW .100Y. M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O in WW r16,PINB0Y.C
0 .TW WW .100Y.C M.TW
. 1 M
W W .C O
W
:. WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM W C Code Example W W.1 Y.COM W
(1)
WW 00Y.CO .TW
W W
W
W .100 O M.T unsigned char
W
Wi; .100 OM
.T
W W.1 Y.COM W
.C W Y .C W W 00 .T
WW .100Y M.T
W O :. W .C O W
WW .100Y.C M.TW /* Define WW pull-ups
Y
.100 and set .TW
Moutputs high */
W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW/* DefineWdirections
W Y.C port.Tpins W */ W .100
Y
M.T
W
W . 100 for O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); WW .100Y. M .TW
W O W O
W O Y.C WW .100Y.C M.TW
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
WW .100Y.C M.T/*WInsert nop WW . 100 M .TW
W W .C O
W
forWsynchronization*/
Y W 0
W 00
W.1 Y.COM/* Read
.T
_NOP(); 0
W
W W
. 1 00 M .TW port W
pins */
W .100 O M .T W
W .100 O M.T
W O WW .100Y .C
WW .100Y.C :.
i = PINB;
.TW WW .100Y.C M.TW M .TW
M W O W O
W
WW .100Y.C M.TW
O
WW the O
W W Note: Y .C O1. For the assembly program,
W W WW two0temporary
0 Y .CO registers .T W are used to minimize
W 0 0 Y.Cfrom pull-
time
.T3W
W .1 00 Mups .Tare set on pins 0, 1, 6,W and
. 1 7, until the O Mdirection bits are correctly set, W .1defining bitO2M and
W O as low and redefining bits .C high.Tdrivers. WW .100Y. C
WW .100Y.C M.TW WW0 and.1100asYstrong M
W M .TW
W O W O
12.2.3 Digital Input
W
WW Enable 0 and
O
Y.C Sleep.T W
Modes WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 Y.CinOFigure M W
0Y.Ccan M
O W
WW at the Y.C of the.TW
WW As.1shown 00 .T W12-2, the digital WWinput.1signal 0 be.T W
clamped to ground
.1 00input M
W W
schmitt-trigger. .C OM The signal denoted SLEEP W W in the Y .C O is set by the MCUWSleep
figure, W W
W Controller
0 Y .CO in .TW
Y mode,.TPower-save W W Standby .100 mode, .T .10 to avoid
W Power-down
W .100 O M mode, W
W .C OMand Extended Standby W Wmode Y
M
.CO .TW
W Y .C W W 0 Y
0are left floating, .T W W
or have an analog.1 0 0
W high power
W.to 100 consumption OM
.T if some input signals W.1 Y.COM W W W signalYlevel M
.CO .TW
W
close VCCY /2..C W W W 00 .T W 0 0
W
W is 0overridden
SLEEP .C for port
W pins enabled W
W as .External Interrupt.T pins. If theW External 1 00
Interrupt .T
W 0Y
1 not
.is M.TSLEEP is active also W 100 O MSLEEP W. by vari- C OM
Request W O
enabled, for these .Cpins. is also W
overridden Y.
WW Y.C functions W WW“Alternate Y
.100 PortOFunctions” M.T
W W
on page 55. W.1
00 M.T
ous
W 100
other .alternate O M.T as described inW W W .C O
WW high 0Y.C(“one”) W Y.C .TW W Y
.100as
If a logic W .10level M .Tis present on
W
an . 100
Asynchronous
W O M
External Interrupt pin W
configured
WW on .Rising .CO .TW Edge, orWAny W 0Y.C on .TWwhile the ExternalWW Inter-
“Interrupt 1 00Y Edge,MFalling Logic
W . 1 0Change
O M Pin”
rupt isW not W
Wenabled, 0 .CO
Ythe corresponding
.T W External WW Interrupt0Flag 0Y.Cwill be .TW
set when resuming from the
.1 0 M W .1 O M
W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 mentioned OM sleep modes, asW .1 M
W Wabove Y .C W W
theWclamping
0 Y .CinOthese.Tsleep W modes produces the requested
W .1
logic 0 0
change. M .T . 1 0 M
W
O M.T UnconnectedW
12.2.4 pinsW .1
.C OM W W.1 Y.COM W
.C 0Y W W 0 .T
00Y .TW W .10pins M.T it is recommended 10ensure
.to OMthese pins have a defined level. Even
W.1 Y.COM W If some
W are
.C O unused, W W .C that
00Ydeep sleep W
00 .T WW though.1most 00Yof the M .TWinputs are disabled
digital W .1the
in M.Tmodes as described above, float-
. 1 M W O W .C O
W .CO .TW WingWinputs 0should 0Y.C be M .TW to reduceWcurrent
avoided W consumption
100
Y allWother modes where the digital
in.T
. 1 00Y M W . 1 O W .
.C O M
inputs are enabled (Reset, Active mode and
WW Idle.mode). 1 00Y M .TW
W. 1 OM W method O ensure a defined level W O
WW .100Y.C M.TW
The W
W simplest 0 0Y.C toM .TW WW of an .1 0Y.C pin,
0unused is W to enable the internal pullup.
M.Tconsumption during reset is
In this case,
W . 1 the pullup O will be disabled during Wreset. If low O
power
W O
WW it .is 0Y.C M.TW WW pullup Y.C .TWConnecting unused pins
WW .100Y.C M.TW important, 1 0recommended to use an external W . 100 or pulldown. O M
W O W O W this may .C excessive
WW .100Y.C M.TW WW
directly to VCC or00 Y.Cis not recommended,
GND .TW W since
. 1 00YcauseM .TW currents if the pin is
W . 1 O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
accidentally configured as an output.
WW .100Y. M .TW
W O W O
W Y.C
WW12.3.100Alternate
O
.T W Functions
Port WW .100Y.C M.TW WW .100Y.C M.TW
W OM WW 0alternate O
Y.C functions
W
WWto being 0Y .CO .TW
WW .100Y.C M.TW Most portWpins have . 1 0 M .T W in addition
W . 1 0 GeneralM
O Digital I/Os. Figure 12-5
W O W C O W .C
WW .100Y.C M.TWalternate functions.
shows how WtheW port pin 00Y
.
control signals
.TW from theW simplified 0Figure Y 12-2 .can
.1 0 in all M TWbe overridden by
W . 1The O M
overriding signals may not be Wpresent C O port pins, but the figure
W O W Y.C applicable W Y . TW family.
WW .100Y.C M.TW serves as a W 1
generic description 0 0 .T W
to all port
Wpins in .1
the 0 0AVR M .
microcontroller
W. OM W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y.CO .TW W
.10 12-5. OMAlternate Port Functions .1 M
WW 00Y.CO .TW
(1)
W WFigure Y .C W
W 00 .T W
W.1 Y.COM W W W.1 PUOExnY.COM W
W W 00
M .TW W
W . 100 O M .T W .1PUOVxn O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C M.TW 1
M .TW PUD
W . 1 O M W C O 0
W W .C O
.C W Y . W W 0 Y .T W
00Y .TW W 00
W.1 Y.COM W
.T .10 OM
W.1 Y.COM W W W W DDOExn
Y . C
.TW
. 1 00 M .T W . 100 M .T W
W . 100 O M
W O
DDOVxn
WW .100Y.C M.TW
1
W. 1 OM WW 00Y.CO .TW
0 Q D
WW 00Y.CO .TW
DDxn
W Y .C W W W
W 00 .T W.1 Y.COM W .1 M Q CLR
W W.1 Y.COM W W W WW 00Y.CO RESET

PVOExn
.TW
WDx
W 00 .T W .1 0 0 M .T . 1 M
W.1 Y.COM W PVOVxn W O
W W WW 00Y.CO .TW W W 0 0 Y.C .T W RDx
W 00 .T W.1 Y.COM W .1 M
DATA BUS
W W.1 Y.COM W W 1
W WW 00Y.CO .TW
W 00 .T W Pxn
0 0 .T .1 M
W.1 Y.COM W
0 Q D

PORTxn
W W W
W .100 .T
Q CLR
DIEOExn
W
W .100 O M.T W .C OM DIEOVxn W
W.1 Y.CRESET OM WPx
W
C W .TW
WW .100Y. M .TW W . 100Y M
1 W
W . 100 O M .TRRx
W O
W O
0 SLEEP
WW .100Y.C M.TW
W W . CO
W WW 00Y.CO .TW W WW 00Y.CO RPx
SYNCHRONIZER
.TW
W 00 Y .T W . 1 M
SET
.1 M
. 1 M W O
D Q D
W
Q
O
W O
PINxn
WW .100Y.C M.TW L CLR Q CLR Q
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO clk .TW
W 00 Y .T W .1
I/O
M
W W 00 .T W
W
W .100 O M.T W.1 Y.COM W W W.1 Y.CDIxn OM
W
.C W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O WW .100Y. C
WW .100Y.C M.TW
AIOxn

W O W ENABLE O W
WDISABLE 0Y.C O
WW .100Y.C M.TW PUOVxn: WWOVERRIDE
PUOExn: Pxn PULL-UP
Pxn PULL-UP
. 1
OVERRIDE 0 0Y.C M.TW PUD:
VALUE WDx:
W
WRITE DDRx .10
PULLUP
M.T
W
W O READ DDRxW C O
W O DDOExn: Pxn DATA DIRECTION
WW OVERRIDE .C
OVERRIDE ENABLE RDx:
W REGISTER Y. .TW
WW .100Y.C M.TWDDOVxn: Pxn DATA DIRECTION
PVOExn: Pxn PORT VALUE OVERRIDE . 1
YVALUE
00ENABLE M .TW RRx:WPx:
WPORTx
READ
WRITE PORTx
W . 100 O M
WW OVERRIDE O
W
WW .100Y.C M.TDIEOExn:
O PVOVxn: Pxn PORT VALUE OVERRIDE
W Pxn DIGITAL WINPUT-ENABLE
VALUE C
00Y VALUE
. ENABLE .TWRPx: clk : WW PIN .100Y.C M.TW
READ PORTx
I/O CLOCK
.1 M I/O
O
.CO .TW WW PIN
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE
SLEEP CONTROLWW
DIxn: DIGITAL INPUT PIN n ON PORTx
W O ON.C
W W 00 Y .C SLEEP:
.T W W 1 0 0 Y
M
AIOxn:
W
ANALOG INPUT/OUTPUT
. 1 0 0nY PORTx
M .TW
. 1 M . O W O
W O WW RDx .C WW Y.C .TW
WW .10Note: 0Y.C 1.MWPx, .TWWDx, RRx,WRPx, and . 1 00Yare common M .TW to all pins within the same
W .100port. clkOI/OM
, SLEEP,
W O and PUD are commonWtoW O signals are unique forW
.Cother .C W
WW .100Y.C M.TW W all ports. . 1 00Y
All
M .TW W each pin. .1 00Y M.T
W O W C O
. from Fig-
WW .ure
W TableY.12-2 CO summarizes W in the W
the function W of the00overriding Y.C signals. The pin and
TW
.overriding WW port.1indexes 00Y internally .TW
1 0012-5 areM not.Tshown succeeding W .1 tables. The
O M signals are Wgenerated O M
W
WW in.1the .CO having W the alternate WWfunction. 0Y.C M.TW WW .100Y.C M.TW
00Y modules .T . 10 W O
W OM W O
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-2. OM
Table
W
.T Description of Overriding
Generic
W W.1 YSignals .CO for
M Alternate Functions
W Y .C W W 0 W
M .TW W
W .
Signal 100Name OMFull .T Name W .10
Description O M.T
.CO .TW .C W C
0Y. is set,Mthe W
00Y WW PUOE . 1 00Y M .TWOverride W IfW
Pull-up .
this 10signal .Tpull-up enable is controlled by the
W . 1 O M W C O Enable W O
.CIf this signal
.C W Y . W W PUOV 0 Y
signal. T W is cleared, the pull-up is enabled
. 1 00Y M.TW W
W . 100 O M .T W
0
.1{DDxn, O M. PUD} = 0b010.
W .CO .TW
when
WW .100Y .C
PORTxn,
. 1 M PUOV W O
Pull-up Override Value If PUOEW is set, the
.C O pull-up is enabled/disabled when PUOV
WW 00Y.CO .TW WW .100Y.C M.TW WisW set/cleared,
. 1 00Yregardless M TW
.of the setting of the DDxn,
W .1 O M W C O W W and PUD .C O
.C W 0Y . W PORTxn,
W 00 Y Register W
.Tbits.
WW .100Y M .T W W . 1 0 M .T
W .1 O M
W O DDOE W O
.C Direction
Data If thisW C OutputTDriver
Y.the
WW .100Y.C M.TW WW .100YOverride .TW W signalsignal. .
is set,
100 If thisO M
Enable is controlled by
. isWcleared, the Output driver
W O M Enable the DDOV W signal
W O
WW .100Y.C M.TW WW by .the Y.C Register W
WW .100Y.C M.TW is enabled
W 1 00DDxn
O M.T bit.
O W O C
Y. Driver.TisW
W
WW .100Y.C M.TW DDOV WW .10Data 0Y.C Direction TW
. If DDOE WW is set, the
100Output enabled/disabled when
W O W Override
C O M
Value DDOV is W .
set/cleared,
W OM of the setting of the DDxn
regardless
.C
WW .100Y. Wbit. .100Y W
WW .100Y.C M.TW M .TW Register W O M.T
O W O Y. C
W
WW .100Y.C M.TW PVOE W
W Port00Value Y.C Override .TW If this signal WWis set and . 100the Output M .TWis enabled, the port
Driver
. 1
WEnable O M W O
W O WWDriver .C signal.
WW .100Y.C M.TW and the Output
value is controlled by the Y PVOV If
WPVOE is cleared,
WW .100Y.C M.TW . 1 0is0enabled, the
O M .Tport Value is
W W .C O
W WW 00Y.CO .TWcontrolled by W WW
the PORTxn 0 0 Y.C bit..TW
Register
W 00 Y .T W .1
W.1 Y.COM W W.1Value Y C OM WW OM
.Cset
W W 0 0 .T PVOV W W Port
1 0 0 .
Override
M .T WIf PVOE is set,W the port
. 1 00
value Y is .TWregardless of
to PVOV,
M
W. 1 OM W
Value . O the setting of the PORTxnW Register O bit.
WW .100Y.C M.TDIEOE W WW .100Y.C M.TW WW .100Y.C M.TW
Digital Input EnableO If this bit is set, the Digital
WW Input Enable O is controlled by the
W O WW Enable Y.C 0Y.C theMDigital .TWInput
WW .100Y.C M.TW WOverride . 10 0 M .T
DIEOVW signal. IfW this signal.1
W
is0cleared,
O
W O W O Enable is determinedW .C
WW .100Y.C Mmodes). W by MCU-state .TW sleep
(Normal Mode,
WW .100Y.C M.TW .TW . 1 00Y M
W O W O
Y.C If DIEOE WW 00Y.CO .TW
WW .100Y.C DIEOV W WWInput.Enable 0 .T W is set, the W
W OM
.T Digital
W 1 0
.C
M
ODIEOV Digital
W W.1 is enabled/disabled
Input
Y .C OM
W
when
W .C W Override W Value Y W
is set/cleared, W regardless of 0 the MCU T
state
. (Normal
W
W .100
Y
O M.T
W
W .100 O M.Tsleep modes). WW.10
Mode, . C OM
C W . C W Y .TW
WW .100Y. DI M.TW W . 100Y ThisMis.T W
W . 0
10functions. O M
W O Digital Input W O the Digital Input to alternate
W In the
Y.Cschmitt trigger
figure,
WW .100Y.C M.TW WW .100Y.Cthe signal M .T Wconnected toWthe
is output. 1 0
of0the M . T W
W O W O
C before T W
W the0Digital .C O
WW .100Y.as
but the Wsynchronizer. WUnless 0Y InputMis.Tused W
WW .100Y.C M.TW aO M
clock .source, the module withW the. 1alternate function
O will
W .C O W W Y . C W W 0 Y .C W
W W 0 Y .T W W 0 0 use its own .synchronizer.
T W .1 0 M .T
1 0 . 1 M W O
W. OM WW 00This O
Y.Cis the Analog W .C .TW
WW .10AIO 0Y.C M.TWAnalog Input/ Woutput . 1 M .TWInput/outputWto/fromWalternate .1 00Y functions. M
W The O
signal is connected directly to the pad, and canC O
be used
W
WW .100Y.C M.TW
O
WW .10bi-directionally.0Y.C M.TW WW .100Y. M .TW
W O W O
W
WW The following
0
O
Y.C subsections .T W WW
shortly describe00the Y.Calternate . W
Tfunctions forW
W
each port, .1 0Y.C
0and relateM the.TW
.1 0 M W . 1 O M W C O
W overriding.Csignals O to the alternate function. .Cto the alternate WW . further.TW
WW details. 00Y .TW WW .1Refer 00Y M .TW
function description
.100
Yfor
M
W W . 1
.C O M W W Y .C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
W .100 O M.T W . C OM W W.1 Y.COM W
C W .TW
12.3.1
WW .100Y.
Alternate Functions of Port A W
M.T function as analog
W Y
.100 for the M
W
W .100 OM
.T
PortWA has an.C O
alternate W input C O ADC as shown in W
Table 12-3. If .C
some
W
WPort 0 0 Y configured .T W WitW 1 0
.
0Ythat these M .Tdo W W . 1 00Y M .TW
A pins
W. 1 are M as outputs, is .
essential
W O not switch when Wa conversion O
Wis Win progress. 0 .COmight
YThis .T W
corrupt WWof the
the result 0 0Y.C M.TW
conversion. WW .100Y.C M.TW
0 .1 O
W.1 OM W O W
WW .100Y.C M.T
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y.CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-3. OM
Table
W
.TA Pins Alternate Functions
Port
W W.1 Y.COM W
W .C W
M .TW W
W .
Y
100 Port Pin O M .T W
Alternate Function W .100 O M.T
.CO .TW .C WWinput channel Y. C W
00Y WW .100YPA7 M .TW ADC7 (ADC . 100 7) OM.T
W . 1 O M W O W W .C
0 Y.C .T W WW .100PA6 Y.C .TW ADC6 (ADC Winput .1 00Y6) M.T
W
. 1 0 M W O M W channel
.C O
W .CO .TW WW .10PA5 0Y.C M.TWADC5 (ADCW
W Y
1005) OM.T
W
. 1 00Y M W O
input channel
W .
WW 00Y.CO .TW WW .1PA4 0 0Y.C M.TW ADC4 (ADC input WWchannel . 1 0Y.C M.TW
04)
W. 1 OM W O
.C WW PA3 Y .CO .TADC3 W W W 0 Y.C W
W W
.1 00 Y
M .T W W
W . 10 0
O M (ADC input channel
W .1 0
3)
O M.T
W O .C W 2)00Y.C .TW
WW .100Y.C M.TW WW PA2 . 100Y M .TW (ADC inputWchannel
ADC2 . 1 M
W O W O W W .C O
WW .100Y.C M.TW WW PA1.100Y.C M ADC1.TW(ADC input W channel 1).100Y M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WWPA0 .100Y.C ADC0 .TW
(ADC input channel WW 0) .100Y. M .TW
M W O
W O W
WWand .Table .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW Table 12-4 1 00Y 12-5 relate M
W W .C O W W Y .CO the
W
alternate
W WW 0of
functions
0 Y .COA to.T
Port the overriding signals
W
W 00 Y W W
.T shown in FigureW 12-5
. 0
10 on pageO56. M.T .1 M
. 1 M W O
W O
WW .100Y.C M.TWTable 12-4.W Overriding
W .C
00YSignalsMfor W
.TAlternate WW .100Y.C M.TW
. 1 Functions in PA7:PA4 O
W W .C O
W WW 00Y.CO .TW W WW 0 0 Y.C .TW
W 00 Y .T Signal Name W . 1 M .1 M
. 1 M PA7/ADC7 O PA6/ADC6 WPA5/ADC5 O PA4/ADC4
W O WW 00Y.C WW .100Y.C M.TW
WW .100Y.C M.TW PUOE W .1 0 M .T W
0 0 0
W W .C O
W 00 Y .TPUOV W .1 0 M
W.1 Y.COM W W W.1 0 Y.COM W 0 WW 00Y.CO .TW
0
W W 000 .T W
W
W .100 O
.T
MDDOE W.1 Y.COM W
0
W W.1 0 Y.COM W0
.C W
WW .100Y M .TW
DDOV W
W . 1000 O M .T 0 W
W .10 00 O M.T 0
W O WW 0.100Y. C
WW .100Y.C PVOE .TW WW 0.100Y.C M.TW0 M .TW 0
W . 1 00Y PVOV M .TW W
W
0 100
. O M .T0 W
0 .10
O M. 0
W O WW 0 .100Y. C
WW .100Y.CDIEOE .TW WW 0 .100Y.C M.T 0W M .0TW
M W O W O
W
WW .100Y.C
O
DIEOV .TW WW0 .100Y.C M0.TW WW0 .100Y.C M0.TW
W W .C OM
W W W Y .CO – .TW W WW 00Y.CO – .TW
Y DI W – 0 –
W 00
W.1 AIO OM
.T 0
W.1 YADC6 .C OM W W.1 Y.COM W
.C W W
W W
. 1 00Y M .TW ADC7 W INPUT
W . 100 O
INPUT
M .T ADC5 W INPUT
W .100 ADC4OINPUT M.T
W O W .C
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-5. OM
Table
W
.T
Overriding W.1 Functions
Signals for Alternate
W
M
.CO in.TPA3:PA0
W Y .C W W 0 Y W
M .TW W
W . 100Name OM.TPA3/ADC3
Signal .10
PA2/ADC2
W C O M PA1/ADC1 PA0/ADC0
.C O W Y .C W W W 0 Y . .T W
00 Y .T W W 0 0 .T .1 00 M
W.1 Y.COM W W W.1 Y.COM W 0
PUOE
WW 00Y.CO .TW
0 0
W PUOV.100 .T 0 W
00
W.1 Y.COM W
.T W . C OM W W.10 Y.COM W0 0
W W 0 Y .T W W 0 0 .T
.100 M.T DDOE .10
OM
0 .01 M 0 0
WW 00Y.CO .TW W W Y .C W W WW 00Y.CO .TW
W DDOV .100 .T 0
W .1 O M W .C OM W W0.1 Y.COM 0W 0
.C W Y W W 0 .100 .T
WW .100Y M.T
W W
PVOE
.100 M.T0 W OM 0 0
W O W .C O W Y .C W
WW .100Y.C M.TW WW .100Y
PVOV
M.T 0W W 0 .100 M.0T 0
W O W O W W . C O
WW .100Y.C M.TW DIEOEWW .100Y.C M0.TW W 0 .100Y M0 .T
W 0
W O W C O W W .C O
W . Y W
WW .100Y.C M.TW DIEOV W .100
Y
M.T
0 W W0
W .100 OM
0 .T 0
W O W C O W . C
Y – .TW
WW .100Y.C M.TW DI W
W Y. – .TW W –
.100 –
W . 100 O M W C O M
W O W Y.C INPUT WW .100ADC1 Y. INPUT.TW ADC0 INPUT
WW .100Y.C M.TW AIO W . 1 00ADC3 M .TW ADC2 INPUT M
W W .C O W W Y .C O
W W W W
0 Y .CO .TW
Y
W12.3.2 .100Alternate .TW
MFunctions of Port W B .100
W OM
.T 0
W.1 Y.COM W
W C O W .C W W
WW .100Y. M.T
W
The Port B pins W with alternate .100
Y functions
M.T are shown in Table
W 00
W.1 Y.COM W
12-6. .T
W O W W .C O W
WW .100Y.C M.TTable W 12-6. WPort BW .
Pins
Y
100Alternate M .TW
Functions
W
W .100 O M.T
O O .C
W
WW .100Y.C M.TWPort Pin W Alternate
W 0Y.C M.TW WW .100Y M.T
W
W . 10Functions O W O
W
WW .100Y.C M.TWPB7
O
WSCK W .C
00YSerial Clock)
(SPI.1Bus .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T PB6 MISO (SPI.1Bus Master Input/Slave M Output) .1 M
W 00 .TPB5 W .1 M
W.1 Y.COM W
MOSI (SPI Bus Master Output/Slave Input)
W .100 M.PB4 T SS W (SPI Slave.1Select 00 Input)M.T W.1 Y.COM W
W C O W W .C O W
WW .100Y. .TW Y Negative W W .100 .T
W O MPB3
AIN1W
W .100
(Analog Comparator
O M.T Input) W W .C OM
WW .100Y .C Y W
WW .100Y.C M.TW .TW Match Output) W .100 M.T
OC0 (Timer/Counter0 Output Compare
O W O M W .C O
W
WW .100Y.C PB2
AIN0 (Analog
.TW INT2 (External WWComparator .C
00Y2 Input) M.TW
Positive Input) WW .100Y M .TW
M W . 1 O W O
WW .100Y.C M.TW
W O Interrupt
WW .100Y.C PB1M.TW T1 (Timer/Counter1 WW .100Y.C M.TW
W W .C O
W WW External Y CO Input)
.Counter W W WW 00Y.CO .TW
W 00 Y W
.T T0 (Timer/Counter0WExternal 0
.10 Counter .T .1 M
W.1 Y.PB0 C OM W .C OMInput) WW 00Y.CO .TW
W W
.T XCK (USARTW Y
00 Input/Output) .T W W .1
W 00 External .Clock
W 1 Y.COM W M
W
W
0
.10alternate O M .T W
W .100 OM
.T
W W.1 Y.COM W
The C pin configuration is as W follows: .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW• SCK .C
00–YPort B,M Bit.T7W WW .100Y. M .TW W .100
Y
M.T
.1
W Master O W O W W .C O
WWinput.1pin .C Y .TW
WWSCK:
. 1 0 0Y.CClockMoutput, .TW Slave Clock 00Yfor SPI.MWhen .TW the SPI isWenabled W . 1as00a Slave, O M
thisW pin is configured CO asTan input regardless Wof the setting O
.C of DDB7. Y.Cas .TW
WaWMaster, 0 Y.data W of this pinWisWcontrolled 0 0Yby .T W When the WSPI
W is enabled
1 00the
W .1 0the
O M .
direction W . 1
C
DDB7.
O M When the pin is forced
W W .by SPI
.C OM
.C W . W Y W
to W
W be an input,
.1 00Ythe pull-up M .TW W
can still be controlled
W .by Y
100the PORTB7 O M .Tbit. W
W .100 O M.T
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.T
•WMISOW –.1 M WW 00Y.CO
WW 00Y.CO .TW
Port B, Bit O 6
W Y .C W W W
W Master
MISO: 0 input,
0Data .T Data output pinW
Slave .1SPI. When
for
OM the SPI is enabled as aW .1
Master,
pinW
W.1 Y.Cas OM
W W 0 Y .C W W W
this W is configured an input regardless W of the setting
.10
of DDB6.
M.T
When the SPI is enabled as
.100direction
Wdata O Mof.Tthis pin is controlled W C O
a Slave,W
W
the
0 0 Y.C .T W WW .100Y. by DDB6. When
M
the
.TW pin is forced by the SPI to
be an input, W the.1pull-up can OM still be controlled by theW PORTB6 bit.O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1MOSIY.–CPort OM B, Bit 5 .1 M
W W W WW 00Y.CO .TW
W
W .100 SPI Master
MOSI: .T
OM Data output, Slave W
Data
W .1 input forOSPI.
.C
M When the SPI is enabled as a Slave,
W Y . C W W 0 Y TW
M .TW W this.pin
W 100is configured O M .T as an input regardless W .1of0 the setting
O M.of DDB5. When the SPI is enabled as
O C W . C
00Y
.C
.TW W W a Master,
1
Y the
00input,
. data
M
direction
.TW of this Wpin is controlled
.
Y
100by the O
by DDB5.
M .TW When the pin is forced by the SPI
. 1 M . W
to be an the pull-up can still be controlled
WW .100Y.C M.TW
PORTB5 bit.
0
0
W.1 Y.COM W W W–.1Port Y .CBitOM
W WW 00Y.CO .TW
W • SS 0 0 B, 4 .T W .1
.100 M.T W.1 Select OM When the SPI is enabled WW 0as0Ya.C OM
WW 00Y.CO .TW SS:W
W
Slave
1 0 0 Y .C input.
.T W W . 1
Slave, this
M .TW pin is configured as an input
W. 1 OM regardless . of the setting M of DDB4. As a Slave, W the SPI is O
activated when this pin is driven low.
W Y .C W W W W
0 Y .CO .TW W W 0 0 Y.C .T W
W 00
W.1 Y.COM W
.T When the SPI
W .10 is enabled
C OM
as a Master, the data direction
W.1 Yof.Cthis
Wpull-up OM pin is controlled by DDB4. When
W W 00 .T the Wpin W is forced
1 00 Y
by . the SPI
M
to
.T Wbe an input, Wthe
. 10 0
can still be
M .TW by the PORTB4 bit.
controlled
.1 M . W O
W O
WW –.1Port
WW .100Y.C M.TW • AIN1/OC0 00YB, BitM 3
W O WWComparator O
Y.C Negative
W
WW the.1port 0Y.pinCO
WW .100Y.C M.TW AIN1, W Analog 1 0 0 M .T W Input. Configure 0 as M .TW
input with the internal pull-up
W O W . Odigital port function from W W O
.Cwith the
W .C switched W
off to avoid Y .
theC W W interfering
0 Y T W
function of the analog
W .1 00Y M .TW comparator. W
W . 100 O M .T W .10 O M.
W O WW .100Y. C
W O
W O OC0, OutputW W
Compare .CO output:
Match The PB3 pin
WWcan .serve 00Y
C an external
.as .TW
output for the
WW .100Y.C M.TWTimer/Counter0 W Compare . 100Y Match. M TWPB3 pin has
.The to be 1configured O M
as an output (DDB3 set
W W .C O
W Wthis W Y .COThe .OC0 W W WW 00Y.C .T W mode timer
Y W 0 T
00 0 W.1 Y.COM W
W .T (one)) to serve function. pin is also the output pin for the PWM
W.1 Y.COM function. W W.1 Y.COM W W
W W
. 1 00 M .TW W
W . 100 O M .T W
W .100 O M.T
W O W Y.C WW .100Y .C W
WW .100Y.C M•.TAIN0/INT2 W –W Port B, Bit . 1020 M .TW W O M.T
W O
W
WW .100Y.C M
O AIN0, Analog Comparator
.TW WW .1Positive .C
00Y input. .T W
Configure the W
W
port pin as . 0Y.Cwith M
10input
W
the.Tinternal pull-up
W O W O M W W .C O
switched off to avoid
WWthe digital .C function
Yport from interfering with the Y function.T ofW the Analog
WW .100Y.C Comparator. M .TW . 100 M .TW W
W .100 O M
W O C
W
WW .100Y.C M.TW
O
W 2: Y The O W O
WW .100Y.C M.TW
W INT2, External InterruptW
O Source PB2 pin can serve as an external interrupt source to the
WW .100Y.CMCU. .T W W . 10 0 .C M.TW
W W .C OM
Y W
W 00
W.1 Y•.CT1 OM
.T
– Port B, Bit 1 W.1 Y.COM W W W.1 Y.COM W
W
W W
. 1 00 T1, Timer/Counter1
M .TW W
Counter .
Source.
W 100 O M .T W
W .100 O M.T
W O WW .100Y .C
W O W O
W
WW .10•0YT0/XCK .CO –.TPort W B, Bit 0 WW .100Y.C M.TW WW .100Y.C M.TW
W W T0,YTimer/Counter0
.C OM
W Counter Source. WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 .1 M
W.1XCK,YUSART C OM External Clock. The W W
Data Direction .C OM Register (DDB0) controls WWwhether Y COclockTisW
.the
W . W Y W W 0 0 .
W
W 100 (DDB0
.output O Mset).T or input (DDB0 W .100 The XCK
cleared).
W O M.T pin is active only when W W 1 USART
.the
.C OMoper-
.C W .C Y W
WW ates .1 00inYSynchronous M .TWmode. W W.100Y OM.TW W
W .100
C O M.T
W O
Y.C and Table WW .C .TW
W Y. .TW
WW Table . 1 0012-7 M .TW 12-8 relate . 1
the alternate00Y functions M of Port B
Wthe
to .100 signals
overriding
W O M
WW O .C
WWshown
W in
0 .CO 12-5
YFigure .T W
on page 56.WSPI MSTR 0 Y.C and.TSPI
0INPUT W SLAVE OUTPUT WW constitute . 1 00Y theM.TW
1 0 . 1 M W O
W W. signal,
MISO .C OM MOSI is divided into
while WSPIW MSTR Y CO
.OUTPUT and
W SPI SLAVE W W INPUT. 0Y.C .TW
W 00 Y .T W W . 1 0 0 M .T . 1 0 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-7. OM
Table
W
.T
Overriding W.1 Functions
Signals for Alternate
W
M
.CO in.TPB7:PB4
W Y .C W W 0 Y W
M .TW W
W . 100
Signal
O M .T W .10
C O M
.CO .TW WW Name .C
00YPB7/SCK .TW WW .100Y. PB5/MOSI
PB6/MISO .TW PB4/SS
. 1 00Y M W . 1 O M W .C O M
W O C
. • MSTR W Y SPE • .MSTR W
00Y
.C .TW WWPUOE.100Y SPE
M .TW SPE • W MSTR
.100 MT
SPE • MSTR
. 1 M W O W .C O
W .CO .TW W
WPUOV Y.C • PUD
00PORTB7
W
.TW PORTB6W• PUDW.100Y PORTB5 .T• WPUD PORTB4 • PUD
. 1 00Y M . 1 O M O M
WW 00Y.CO .TW W WW SPE
DDOE
0 0Y.•CMSTRM.TW SPE • MSTR WW .100Y.SPE C • MSTR
.TW SPE • MSTR
. 1 M W . 1 O W O M
W O WW .100Y .C
WW .100Y.C M.TW WW .0100Y.C M.TW0
DDOV 0
M.T
W 0
W O W O
W O
WW .100Y.C M.TW
PVOE SPE • MSTR SPE • MSTRWW Y.C• MSTR.TW
SPE 0
WW .100Y.C M.TW W . 100 O M
W O PVOV WW SCK OUTPUT .CO .TSPI W SLAVE OUTPUT WW .10SPI .C OUTPUT
0YMSTR .TW 0
WW .100Y.C M.TW W . 1 00Y M W O M
W O 0
W
WW .100Y.C M.TW
O DIEOE W0
W 0 0 Y.C .T W WW .10 00Y.C M.TW 0
0 W.
1 M
W W .C O
W
DIEOV
W Y .CO 0 .TW W WW 0 00Y.CO .TW 0
W 0 Y W 0 0 .1 SLAVE INPUT
W .10 O M.T DI SCK
W W .1
INPUT .C OMSPI MSTR INPUT WWSPI Y
M
.CO .TW SPI SS
W Y .C W W 0 0 Y .T W W 1 00
W 00 .T W.1 Y.CO–M W – . M
.CO .TW–
W W.1 Y.COM W AIO –
W W WW 0 0 Y
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W
Table 12-8. W Overriding Y
.100Signals for.T
M Alternate W in PB3:PB0
Functions 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW Signal WW .100Y M .TW W .100 M.T
O W O W .C O
W
WW .100Y.C M.TW
Name
WW .100Y.C M.TW
PB3/OC0/AIN1 PB2/INT2/AIN0
WW .100Y
PB1/T1 PB0/T0/XCK
M.T
W
W O PUOE 0 W 0 O 0 W W 0Y.C O
WW .100Y.C M.TW WW .100Y.C M.TW W .100 M .TW
W 0 O W O
O PUOV WW .100Y.C M.TW
W 0 0 0
WW .100Y.C M .T W WW .100Y.C M.TW
W O W 0 O
O DDOE WW .100Y.C M.TW
W 0 0 0
WW .100Y.C DDOV .T W WW .100Y.C M.TW
W OM 0
WW 00Y.CO .TW
0 0 WW 0 00Y.CO .TW
WW .100Y.C PVOE M. T W W
OC0 ENABLE W.1 0
W .1 M
W C O W . C OM 0
W WUMSEL Y .CO .TW
W Y . W W 0 0 Y .T W W 0 0
.1 OUTPUTOM
W 00 PVOV .T OC0 W.10 Y.COM W 0
W.1 Y.C OM W W W W
XCK
00Y
.C W
W W
. 1 0 0 DIEOE M .T W0
W
W .1 0
INT2
0 ENABLEM.T 0
O 0 W . 1 O M.T
W O WW .100Y .C
WW .100YDIEOV .C .T0W WW 1 .100Y.C M.TW0 0 W M .TW
O M W O .CO
W
WW .100DI Y.C .T W WW INT2 0 0Y.C M.TW WW .1 00Y INPUTM.TW
– . 1 INPUT T1 INPUT XCK WINPUT/T0 O
W . C OM WW 00Y.CO .TW W W 0 Y.C W
W W
.1 0 Y
0AIO M AIN1 W
.T INPUT W AIN0.1
W
INPUT
O M – – W .1 0
O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 ofY.Port OM .1 M
12.3.3 Alternate Functions
W C C
W W WW 00Y.CO .TW
W 0 C pins .T
The
W .10Port
.C OM with alternate functions W W.1 are Y shown M
.CO in .Table 12-9. If the JTAG interface is
W and PC2(TCK) will be activated
W W W enabled, 0 0 Y the pull-up .T W resistors on W pins PC5(TDI),
1 0 0 PC3(TMS) T
.T W.1if a reset M . M
.C OM
W Weven Y .COoccurs. W W WW 00Y.CO .TW
Y W 0 .T
00
W.1 Y.COM W
.T 0
W T Alternate Functions.100 W
. 1 00 M .T WTable 12-9.
W . 100 Port O MC .Pins
W O M.T
W .CO .TW .C Alternate W .C
1 00Y M
WW Port.1Pin 00Y M .TW FunctionW W.100Y OM.TW
. W O .C
WW 00Y.CO .TW WW PC7 1 0 0Y.C TOSC2 . W Oscillator
T(Timer WW Pin 2) 100Y
. M .TW
W. 1 OM W . O M W
W1) 00Y.C O
WW .100Y.C M.TW WW PC6.100Y.CTOSC1 M .T W OscillatorWPin
(Timer
.1 M.T
W
W O W O W W .C O
WW .100Y.C M.TW WWPC5 .100Y.C TDI (JTAGTTest
M . W Data In) W W.100Y OM.TW
W O WW 00YTDO .CO(JTAG.TTest W Data Out)WW .100Y.C M.TW
WW .100Y.C M.TW WPC4 . 1 M W O
WW 00TMS O
W
WW .100Y.C M.TW
O
W PC3 Y.C (JTAG .Test T WMode Select) WW .100Y.C M.TW
.1 OMTest Clock) WW 00Y.CO .TW
W W .C O PC2WW TCK Y .C(JTAG W W
Y W W 0 .T
W
W .10 0
O M.T PC1 W
0
.1 SDA (Two-wire
. C OM Serial Bus Data Input/Output W W.1 Line) Y
M
.CO .TW
W Y .C W W W 0 Y .T W W 1 00
W 00
W.1 Y.COM W
.T
PC0 WW SCL (Two-wire
.10 OM Serial Bus Clock Line)WW. M
.CO .TW
W Y .C W W 0 0 Y
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. W W
M.T The alternate pinWconfiguration .100
Y is as .follows:
MT
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW W . 1700
Y
M .TW W
W .100 O M.T
O • TOSC2 – Port C, W
Bit O .C
W
WW .100Y.C MTOSC2, .TW Timer W
W 00Y
.C .TW WW .100Y W
M.T asynchronous
Oscillator W . 1pin 2: When O M the AS2 bit in ASSR isW set (one) C toO enable
W O
WW .10pin 0Y.C WWthe port, Y. .TWthe inverting
WW .100Y.C M .TW of Timer/Counter2,
clocking PC7 is M .TW
disconnected from
W .100and becomesO M
O output of the Oscillator W O mode, a Crystal Oscillator Y.C
W
WW .100Y.C the .T W WW amplifier. 0 0Y.InC thisM .TW WW .1is00connected M.T
W pin, and
to this
M pin can not be used W
as .
an1 I/O pin. O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C• TOSC1
O
.T W– Port C, Bit WW 6 0 0Y.C M.TW WW .100Y.C M.TW
. 1
W W .C OM Timer OscillatorW
TOSC1, pinW1: When Y COAS2 T
.the bitW in ASSR isW set
W to enable
W(one) 0 Y .CO asynchronous
.TW
W Y
00 clocking W
.Tof Timer/Counter2, pin W . 1 0
0 is disconnected M . . 0
1becomes O M
. 1 M W PC6 O from the port, W
and the input of the
W .CO .Oscillator WW In this Y.C a Crystal WOscillatorW W 0 Y.C T W
WW .100Yinverting T W amplifier. .1 0 0
mode, .T is W.
connected 1 0 to this OM pin, . and the
W C O M W W .C OM W Y .C W
WW .100pin Y. can not.TbeWused as anWI/O pin. .100Y W W 00 .T
W O M W O M.T W W.1 Y.COM W
.C WW .100Y . C
WW .10•0YTDI – Port
M .TC,WBit 5 M .TW W
W .100 O M.T
W O W O W .C
WW .1TDI, .C Test .TW WW Y.C .TinWto the InstructionW Y
.100 or Data .TW
00YJTAG M Data In: Serial input data
W . 100to be shifted O M Register
W C O MReg-
W .CO chains). W interface .C .TW notWbe used00as Y.an I/O pin. .TW
WW .ister 1 00Y
(scan
M .TW
When the W JTAG
.1 00Yis enabled, M
this pin can W
W . 1 O M
W O
W
WW • .1TDO .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y– PortM C, Bit 4
W O WW data .COInstruction WW 00Y.CO .TW
WW TDO, Y.C Test Data
JTAG
0 T W Out: Serial Woutput 0 0 Yfrom .T W RegisterW or Data Register.
.1 When
W . 1 0
O M . W . 1
C O M W W .C OM
the JTAGYinterface .C is enabled, this pinW can not be Y .
used as an WI/O pin. W 0 Y W
W W
.1 00 M .TW W
W . 100 O M .T W .10 O M.T
W TD0 pin isO Y.C out data are entered.WW .C
WW The
00Y
.C tri-statedWunless TAPWstates
.T
W that00shifts
1 M .TW . 100
Y
M .TW
. 1 M W . O W O
W
W•WTMS.1–0Port
O
0Y.CC, BitM3.TW WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
W Wused W Y .CO .T W W WW 00Y.CO .TW
TMS, JTAG Y
Test Mode Select: This W
pin is for 0 navigating through the TAP-controller state
W
W
00
.1When O M.Tinterface is enabled, W .10
.C O M W W.1 Y.COM
WW .100Y.C M.TW
machine. the JTAG WW .100Y this pin can not be
M.T
used
W as an I/O
W pin.
.100 M.T
W O W O W W .CO
• W TCK W – Port0C, 0YBit.C 2 .TW WW .100Y.C M.TW W .100
Y
.1 M W O W
WW Test .CO JTAG .TW
W .C
00Yto TCK. TW the JTAG WW
TCK, WJTAG . 1 00Y Clock:
M
operation is Wsynchronous
W . 1 O M .When interface is
W pin can O C
enabled,W
W
this
00Y
not
.C be used
.TW
as an I/O
WW .100Y.
pin.
M .TW
W .1 O M W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1SDAY–.C OMC, Bit 1 .1 M
W Port
W W WW 00Y.CO .TW
W .100Two-wire
SDA,
W
.T
OMSerial Interface Data: W
.1 the TWEN
When
W .CO bit
M in TWCR is set (one) to enable the
W Y .C W W 0 Y .TWport and becomes the Serial Data
M .TW W Two-wire
W . 100 Serial O M .T
Interface, pin PC1 is disconnected
W .10
C
from
O Mthe
.CO .TW .C Two-wire WW In.1this . .TW
00Y WWI/O pin . 1
for the
00Y shorter M .TWSerial Interface. 00Y mode, there
M
is a spike filter on the pin to sup-
. 1 M W O
press spikes than 50 ns on the
W
input
W signal,
1 0 0 Y.Cand the pin
.T Wis driven by an open drain driver
0 W. by the M Serial Interface, the pull-up can
0
W.1 Y.COM W Wbe W.1 Y.limitation.
with slew-rate
CO
M When this pin isWused
W 0 Y
Two-wire
.CO .TW
W still 0 0
controlled by the .TPORTC1 bit. W .1 0
M
WW 00Y.CO .TW W W
100 C, BitO0M.T
W
W .1 O M • SCLW – .Port
.C W W.1 Y.COM W
.C W Y W W the TWEN 00 .T is set (one) to enable the
WW .100Y M.T
W W Two-wire
SCL, .100 SerialOInterface M.T Clock: WhenW W.1 Ybit OM
in TWCR
W O W C .C
WW .100Y.C M.TW WW Serial
Two-wire
1
Y .
00Interface, M .TW
pin W
PC0 is disconnected
. 100 the port
from
M .TW
and becomes the Serial Clock
W O I/O pin forW the. Two-wire O Serial Interface. In W
this W
mode, there.C O
is a spike filter on the pin to sup-
WW shorter .C Y .TW
WW .100Y.C M.TW . 1 00Y than 50 M TW
.ns W . 1 00the M
W W .C O
W
press spikes
W W Y .C O on
W
the input
W WW 00Y.CO .TW
signal, and pin is driven by an open drain driver
W 00 Y .T W
with slew-rate 0 0
limitation. When .Tthis pin is used by the 1
.Two-wire Serial
M Interface, the pull-up can
W.1 Y.COM W still be controlled W W.1 by the Y . C OM bit.
PORTC0 W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C Wthe alternate
WW .100Y. W Table 12-10
M.T shown in Figure
W and Table Y12-11 relate
.100on pageO56. M.T
W functions
W .100of PortOCMto.Tthe overriding signals
W O W12-5 C W .C W
WW .100Y.C M.TW WW .100Y. M .TW W . 1 00Y M.T
O W O W .C O
W
WW .100Y.C M.TW Table 12-10.WW
0 Y
Overriding0Signals .C for.T W
Alternate WW in PC7:PC4
Functions
.100
Y
M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O Signal WW .100Y.C M.TW WW .100Y.C M.TW
W .C O Name PC7/TOSC2
WW 00Y.CO .TW
PC6/TOSC1
W W W
PC5/TDI
0 CO
Y.PC4/TDO W
W W
. 1 00 Y
M
W
.TPUOE AS2
W
W . 1 O M
AS2 JTAGEN W .1 0
O
JTAGEN M.T
W
WW .100Y.C MPUOV
O
.TW WW .100Y.C 0 M.TW WW .100Y.C M.TW
W W .C O
W
0
WW 00Y.CO .TW
1
W WW 000Y.CO .TW
W 00 Y .T W .1 AS2M .1 JTAGEN M
DDOE AS2 JTAGEN
W W WW 00Y.CO .TW W
W 00 DDOV .T 0
W.1 Y0.COM W 0 .1 SHIFT_IR +MSHIFT_DR
W
W .100 PVOE
O M.T 0
W
W .100 0 OM.T 0
W W.1JTAGEN M
.CO .TW
W Y .C W W W 0 Y .C T W W 0 0 Y
W 00 PVOV .T 0 00 . .1 M
W.1 Y.COM W
0 TDO
W 0
.10AS2 .T .1
W
W .100 DIEOE O M.T AS2 W W .C OM
JTAGEN
W WJTAGEN
Y
M
.CO .TW
W Y .C W W 00 0 Y .T W W 0 .1 0 0
W 00 DIEOV .T0 W.1 Y.COM W
0 M
W – 00 .T –
W .100 M.T W.1 Y.COM W
DI – –
WW .10AIO 0Y T/C2W OSC OUTPUT W T/C200
.1 OSC INPUT M.T TDI
W– 00 .T
W
WW .100Y.C M.TW W .100
Y
M.T
W W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-11.OM
Table
W
.T
Overriding Signals for Alternate
W W.1 Functions M
.CO in.TPC3:PC0
(1)
W W Y .C W W 0 0 Y W
O M.T
W .100
Signal
W OM
.T
W W.1 Y.COM W
.C W .C W
00Y .TW W Name .100
Y PC3/TMS
M.T
W
PC2/TCK
.100PC1/SDA OM
.T PC0/SCL
00 .T WWPUOE.100Y. JTAGEN M .TW JTAGEN W .100
TWENY
M.T
TWEN
. 1 M W O W .C O
W .CO .TW W
WPUOV 00Y 1
.C .TW 1 WW .1PORTC1 00Y • PUD .TW PORTC0 • PUD
. 1 00Y M . 1 O M W O M
WW 00Y.CO .TW W WW 00YJTAGEN
DDOE .C .TW JTAGENW
W TWEN
1 00Y
.C .TW TWEN
1 . 1 M W . O M
W. OM W O
WW SDA_OUT .C
WW .100Y.C M.TW WW .1000Y.C M.TW 0
DDOV
.1 00Y M.T
W SCL_OUT
W O W O
W O
WW .100Y.C M.TW
PVOE 0 0 WW TWEN Y.C .TW TWEN
WW .100Y.C M.TW W . 100 O M
W O PVOV WW 0 .CO .TW 0
WW0 .100Y.C M.TW0
WW .100Y.C M.TW W . 1 00Y M O
DIEOE WW JTAGEN.CO 0 W
W
WW .100Y.C M.TW
O
W 0 0 Y .T
JTAGEN
W WW . 1 00Y.C M.TW 0
DIEOV WW0 . 1 O 0M W O
O WW .100Y.C M.TW
W 0 0
WW .100Y.C M.TW DI W . 10 0Y.C M.TW
W O
W O WW – .CO – .TW WW .100Y.C M.TW
– –
WW .100Y.C M.TW AIO W TMS.100Y M W O SCL INPUT
W O WW 00Y.CO TCK.TW SDAW INPUT
Y.C W
WW .100Y.C M.TWNote: 1. W When W . 1 the Two-wire
enabled, M Serial Interface enables
W
W 1 0 0
. slew-rate controls
O M.Ton the output pins
O O .C
W
WW .100Y.C M.TW WWand PC1.
PC0 Y.Cis not shown
00This .TWin the figure. WInWaddition, .
Y
100spike filters M .TW
are connected between
W . 1 O M W C O
W O the AIO outputs shown.C in the port figure and the W
digital logic of
Y .
the TWI module.
.TW
WW .100Y.C M.TW WW .100Y M .TW W . 100 M
W O W O
W
WW Alternate
12.3.4 0
O
Y.C Functions
.T W of Port DWW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 OMThe Port D pins withWalternate W .CO are
functions shown in Table WW12-12.
W
0Y.C M.TW
WW .100Y.C M.TW W 0 0 Y .T W .1 0
W .C O Table 12-12. Port DWPins W.1 Y.COM W WW 00Y.CO .TW
W Y W W 0
Alternate Functions .T W .1
W 00
W.1 Y.COM PortWPin
.T .10 M WW 00Y.CO .TW
M
W W
AlternateWWFunction 0 Y .CO .TW W
W 00 .T .10 OM .1 M
W W.1 Y.COM PD7W OC2W WW 00Y.C
(Timer/Counter2 Output Compare W Match W
Output)WW 00Y.CO .TW
.T W.1 Y.COM W
W
W .100 O M.T W W .1
.C OM W
WW .100Y. C W
Y W .100 .T
PD6 ICP1 (Timer/Counter1 Input Capture Pin)
M .TW W
W .100 O M.T W C OM
W O .C W Y . W
WW .100Y.C M.TW
PD5 WW .100YOutput
OC1A (Timer/Counter1
.TW A Match Output)
Compare
M
W .100 M.T
O W O W .C O
W
WW .100Y.C M.TW
PD4
WW .100Output
OC1B (Timer/Counter1 Y.C Compare .TWB Match Output) WW .100Y M .TW
W O M W O
W
WW .100Y.C M.TW
O
PD3 INT1 (External
WWInterrupt .C
1 Input)
00Y .TW WW .100Y.C M.TW
. 1 M
W W .C O
PD2
W INT0 (External W W 0 Input)
Interrupt Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 .1 M
W.1 YPD1 C OM TXD (USART Output W WPin) .C OM WW 00Y.CO .TW
W . W W 00 Y .T W W
W 00
W.1 PD0
.T
OM RXD (USART InputWPin) W.1 Y.COM W W W.1 Y.COM W
.C
W W
.1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W .CO pin configuration .C WW .100Y. C
WW The.1alternate
00Y .TW isW
W
as follows: 1 00Y M .TW M .TW
M W . O W O
W
WW• OC2 0 Y.C
O
0
W
1
W. – Port .C D,M
O Bit 7
Y W .1
W 100
W OC2, .Timer/Counter2
OM
.TOutput Compare Match W.1output: C
TheOM PD7 pin can serve as an
W Wexternal .out-
CO
M
W
Wput for .the Y .C
00Timer/Counter2 .T W Output Compare. W W The
. 1 0 Y .
0pin has to M . W W
T configured as an output
be . 1 0 (DDD7 M.TW
0 Y
1 OM O output pin for the PWM W O
W to Y
setW(one)) .C
serve this function. The OC2 WW pin is also Y .Cthe W W W mode 0 Y.C
timer W
Wfunction. .1 00 M .T W W
W .10 0
O M .T
W .1 0
O M.T
W
WW .100Y.C M.TW
O
• W ICP1WW – Port 0D,Y.Bit CO6 W WW 00Y.CO .TW W WW 00Y.CO
0 .T W 1 .1
ICP1 –W W.1Capture
Input C OMThe PD6 pin can act
Pin: W W.an
as Input .C OM pin for Timer/Counter1.
Capture WW
Y . W W 0 0 Y .T W W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
• OC1A W – Port.1D,
W
00Bit 5 M.T
O
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Output
WOC1A, C OMCompare Match A W W.1 TheYPD5
output:
M
.CO pin can serve as an external output for the
W W 0 0 Y . .T W W . 1 0 0 M .TW
W W.1 Y.COM W
Timer/Counter1 Output Compare A. The
W W pin has
0 Y
to
.CO be configured
W
as an output (DDD5 set (one))
W W T
0 output pin. for the PWM mode timer function.
W to serve .100 .T The OC1A pin is also
this function. the
.C W .TW
00Y .TW W • OC1B Y
.100– PortOD,MBit
W .100 OM
.T
W.1 Y.COM W W .C 4
W W .C
00Y pin can .TW as an external output for the
00 .T WW OC1B,.1Output 00Y Compare M .TWMatch B output: W The.1PD4 Mserve
. 1 M W O W .C O
W .CO .TW W
WTimer/Counter1 .C
00Y Output W
Compare WW
B. The pin has1to 00be Y configured .TW as an output (DDD4 set (one))
. 1 00Y M W . 1 O M .T W .
.C O M
W O to serve this .C
function. The OC1B pin is also W the output pin for the
.TW mode timer function.
PWM
W 00 Y.C .T W WW .100Y M .TW W . 1 00Y M
W. 1 OM CO3 TW W O
WW Y.Bit WW .100Y.C M.TW
WW .100Y.C M.TW •W INT1 – Port
. 1 00D, M .
W O W Interrupt Y.C Source
O WW 0Y.as COan external
WW .100Y.C M.TW INT1, WW External
10 0 M .T W1: The PD3Wpin can serve
. 1 0 M .TW interrupt source.
W . O W O
W
WW .100Y.C M.TW
O
• INT0 WW – Port.1D, 00Bit Y.C2 .TW WW .100Y.C M.TW
O M W CO
W O WW Interrupt Y.CSource.T0:WThe PD2 pin WW Y.an .TW
WW .100Y.C M.TW INT0, W External
. 1 0 0 M can serve
W . 1 0 0as external
O M interrupt source.
W O W C O W .C W
WW .100Y.C M.TW • TXD W
W Y. .TW W .100
Y
M.T
– Port WD, . 1001
Bit O M W C O
W O
WW Data 0Y.Coutput WW When Y. TW
WW .100Y.C M.TW TXD, Transmit . 1 0(Data M TWfor the USART).
.pin W . 100the USART O M .Transmitter is enabled,
W . Wthis pin is configured as Y
an output W
regardless of theW value of 0 0
DDD1. .T
W
W .100
Y
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
O W O W . C O
W
WW .100Y.C M•.TRXD W WW .100Y.C M.TW WW .100Y M.T
W
W O W O
WW .100Y.C M.TW
W O – Port D, Bit 0 .C
WW .100Y.C M .TWReceive Data
RXD, WW(Data.1input 00Ypin forMthe .TW USART). When the USART Receiver
WW O is enabled this
W .C O WW Y .CO of.T W W 0 Y.C W this pin
W W
. 1 00 Y pin
M
is
.T Wconfigured W
as an input
W . 10 0
regardless
O M the value of DDD0. When
W .1 0 the USART
O M.Tforces
W Oto be an input, the pull-up .Ccontrolled WW bit..100Y. C
WW .100Y.C M.TW WW can.1still 00Y
be
M .TW
by the PORTD0
M .TW
W O W relate O W W O
.Coverriding
WW .100Y.CTable .
12-13
T W and Table WW 12-14
. 10 0Y.C the alternate
M .TW functionsWof Port D .1 0to0Y the
M.T
Wsignals
shown M in Figure 12-5 on pageW 56. O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
Table O 12-13. Overriding Signals
WW .1for 00Y
.C
Alternate Functions
.TW PD7:PD4 WW .100Y.C M.TW
M WW 0PD4/OC1B O
W W Y .C O Name
Signal W PD7/OC2WW
W 0 .CO .TW PD5/OC1A
PD6/ICP1
Y W 0 Y.C .TW
W . 1 00 M .T . 1 0 M W . 1 O M
W O
W
WW .100Y.C M.TW
PUOE O 0
WW .1000Y.C M.TW0 WW .1000Y.C M.TW
W W PUOV .C O
W 0 WW 000Y.CO .TW 0 W WW 0 00Y.CO .TW
W 00 Y .T W .1 M
W.1 DDOE . C OM 0 W W.10 Y.COM 0W WW0 00Y.CO .TW
W W 00 W
W 00Y .T W
W.01 Y.COM 0 W
.T .1 M
.CO .TW
W W.1DDOVY.COM W 0 W 0 W WW 0
0 0 Y
W .T
W
W 100
.PVOE O M.T OC2 ENABLE WW0.10 .C OMOC1A ENABLE W W.1 ENABLE
OC1B Y
M
.CO .TW
W Y .C W W 0 Y .T W W 0 0
W
W .100
PVOV OM OC2
.T 0 .1
W
0
.C OM OC1A W.1 Y.COM W
OC1B
W
.C W W
W
W DIEOE .1 00Y M .0TW W
W .100
Y
O M .T W
W .100 O M.T
W .CO .TW
0 0 0
WW .100Y .C
WWDIEOV 00Y WW .100Y.C M.TW M.TW
. 1 M 0 0 O
0 0 W O
W Y.C – .TW
O WW 00Y.C TW WW .100Y.C M.TW
WW 0 0 WICP1 . 1 M .
DI
W W. 1
.C OM
W
INPUT
WW 00Y.CO .TW
– –
W WW 00Y.CO .TW
WAIO .100 Y .T W .1 M
W .C O– M –
W W.1 Y–.COM W –
WW 00Y.CO .T
W Y W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10012-14.OM
Table
W
.T
Overriding Signals for Alternate
W W.1 Functions M
.CO in.TPD3:PD0
W Y .C W W 0 Y W
M .TW W
W .
Signal 100Name OM.TPD3/INT1 .10
PD2/INT0
W C O M PD1/TXD PD0/RXD
.C O W Y .C W W W 0 Y . .T W
00 Y .T W W 0 0 .T 0 .1 0 M TXEN
W.1 Y.COM W W W.1 Y.COM 0 W
PUOE
WW 00Y.CO .TW
RXEN
W PUOV.100 .T W 0 W.1
00 .T OM0 .CO .TW
M0 PORTD0 • PUD
W.1 Y.COM W W W
0 Y.C W W W 0 0 Y
W DDOE .10 0 . T .1
.100 M.T W OM
0
WW 00Y.CO .TW
MTXEN RXEN
WW 00Y.CO .TW W W
DDOV .100 Y . C
0 .T W W
W .1 O M W .C OM
0
W W.1 Y.CO1M W 0
.C W Y 0 W W 00 .T
WW .100Y M.T
W W
PVOE
.100 M.T 0
W.1 Y.COM W
TXEN 0
W O W .C O W
WW .100Y.C M.TW PVOVWW .100Y 0 M.TW 0W .100 TXD M.T 0
W O W O
C ENABLE W W . C O
WW .100Y.C M.TW DIEOE WW .100Y.INT1 .TW INT0 WENABLE.100Y 0 M.TW 0
W O M W O
W
WW .100Y.C M.TW
O DIEOV WW .100Y 1 .C .T W 1 WW .100Y.0C M.TW 0
WW 00INT1 OM WW 00Y CO
W .C O Y .CINPUT W W –. W
W W
.1 0 0 Y
M .TW DI W
W . 1 O M .T INT0 INPUT
W . 1 O M.T RXD
W O .C WW .100–Y. C
WW .100Y.C M.TW AIO W
W
10–0Y M .TW – M .TW –
W O W . O W W .C O
.C WW .100Y. C Y W
W
W12.4 1 00Y M .TW M .TW W
W .100 O M.T
. Register O Description W O .C
W
O W O
W .C–OSpecial WW 00Y.C TW WW .100Y.C M.TW
WW .SFIOR
12.4.1
00Y .T W Function I/O WRegister . 1 M .
W W 1
.C OM
W WW 600Y.CO 5 .TW 4 W WW 00Y.CO .TW
Y W .12
W .100 M.T
Bit 7 3 1 M 0
W O W .1 O M W WPUD .C O PSR10
WW .100Y . C Y W SFIOR
WW .100Y.C MRead/Write .TWR W 100 R/W OM.T
ADTS2 ADTS1 ADTS0 – ACME PSR2
.TW M W .
WW0 00Y.C0O .TW Y.C
R/W R/W R/W R/W R/W R/W
W O W W
WW .100Y.C M Initial W
.TValue 0 W
. 1 M 0 0W
W
0 .100 0
O M.0T
W O C
W
WW .100Y.C • M
O
.T2W WW .100Y.C M.TW WW .100Y. M .TW
W O
W O Bit – PUD: Pull-up
WW
W
disable .CO .TW W 00Y
.C .TW
WW .100Y.CWhen M .T Wbit is written
this to one, . 1 0
the0Ypull-ups M in the I/O ports
Ware .1
disabled
W even if M
O the DDxn and
O W O Y.C
W
WW .100Y.C PORTxn W
.TRegisters areW W
configured .C
00toYenableMthe W
.Tpull-ups WWPORTxn}
({DDxn, .100 = 0b01). M .TW“Con-
See
M W . 1 O W O
W O the Pin” on page 51 .C about this feature.WW .C W
WW .100Y.C M.TW
figuring
WWfor more .1 00Y
details
M .TW . 1 00Y M.T
O W O W .C O
W
WW – Port .C .TW WW .100Y.C M.TW WW .100Y .TW
12.4.2 PORTA
. 1 00AYData Register M W O W O M
W
WW .100Bit Y.C
O
.T W7 WW 5.100Y.C4 M.TW WW .100Y.C M.TW
OM PORTA7 PORTA6 WPORTA5 W1W 0PORTA0 O
.CO PORTA3
6 3 2 0
W .C W Y W 0 Y.C PORTA W
W Y W W 0 .T W .1 M.T
W .1 00 M .T W . 10 PORTA4
O M PORTA2 PORTA1
W C O
W Read/Write .CO R/W R/W
WW 0 .100Y0.C M0.TW 0
R/W R/W R/W R/W
WR/W W R/W Y. .TW
WW .1Initial 00YValue M.T0W W . 1000 O M
0
W O 0
W
WW .100Y.C M.TW
O
W O W O
12.4.3 DDRA – Port AWData Direction
WW .100Y.C M.TW
O Register
W O 5W
W
4 0Y.
CO3 WW 0 00Y.CO .TW
WW Bit .100Y.C 7M.TW 6 W .1 0 .T W2 1W
.1 M
W C O
DDA7 DDA6 DDA5 WWDDA4 . C OM DDA2
DDA3 DDA1 WW DDA0 Y .CO .TW
DDRA
W Y . W W 0 Y T W W 00
W Read/Write 00 R/WM.T R/W .10 R/W M. R/W W.1 Y.COM W
W.1
R/W R/W R/W R/W
O W W . C O W
Initial Value 0Y.C 0 W
W W
.1 0 M .TW 0 0 W
W
0
. 100
Y 0
O M .T 0 0 W 0
W .100 O M.T
WW 00Y.C O WW .100Y .C
PINA – Port A W AddressOM.T
W WW .100Y.C M.TW M.T
W
12.4.4 Input Pins . 1 W O W O
W
0 WW O
Bit
W W Y
7
.C O 6
W
5
W
4 W
W 3
0 Y .CO 2 .TW 1 W 0 0 Y.C
W 0
0PINA7 .T PINA5 W.1PINA3
0 M .1
W.1 R Y.COMR W R WW
PINA6 PINA4 PINA2 PINA1 PINA0 PINA
W . C O
W
Read/Write W R R
0 0 Y R .T W R W
R
W
Initial Value W.1 N/A
00 M.T N/A W.1N/A Y.CN/A OM N/A
C ON/A N/A
W N/A
W W 0 0 Y . .T W W .1 0 0 M .TW
W.1 OM W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W OM.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
B.1Data Register OM .1 M
12.4.5 PORTB – PortW
W 00 .T W.1 4 Y.CO3M W2
W WBit.1 Y.COM7 W 6 5W 1 0
.T W W . 10 0 M .T PORTB6 PORTB5 PORTB4 W . 1 00 PORTB3 M .T
.C OM
W WW Y .COR/W .TWR/W
PORTB7
W WW 00Y.CO .TW PORTB2 PORTB1 PORTB0 PORTB
00 Y .T W 10
Read/Write 0 R/W .1
W.1 Y.COM W W W.Value .C O0 M WW0 00Y.C0O .T0W
0 .T W Initial
0 0 Y .T W 0 0
W .1 M
0 0
1 0 . 1 M W O
W. OM WWDirection O
Y.CRegister WW .100Y.C M.TW
0 0 Y.C
12.4.6 T
DDRB
. W – Port BWData . 1 0 0 M .T W
.1 M W O
W.1 Y.COM W
Bit .1 7 M 6 5
WW DDB3
4 3 O 2 1 0
W W WW 00DDB7 Y .CO DDB6 . T W W 0 0 Y.C DDB2.TW DDB1
W .100 M.T W.1 R/W Y.COR/W
DDB5 DDB4 DDB0 DDRB
W .1 R/W OMR/W M
W O . C W W
Read/Write R/W R/W R/W R/W
M .TW 0 W
W .100 0 O 0M
.T 0
W C O Initial Value
W W .C O 0 0
W Y .C W
0
W Y . W W 0 0 Y .T W W .1 0 0 .T
W
W .100
12.4.7
.T
OM – Port B Input Pins
PINB W W.1 Y.COM W
Address WW 00Y.CO .TW
M
W Y . C W W 0 .T W
W 00 .T 0
W.1 Y.COM W .1 OM
W.1 Y.COM W Bit W W WW3 00Y.C W
W W
.1 00 M .T W
W
7
. 100 PINB6OM.TPINB5
6 5 4
W .1 2
O M.T1 0
W O WW .100Y. C
W 0Y.C TW R
PINB7 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
WW .100Y.C M.TW Read/WriteW R .10 R M .T R
W
R R W R O M R
.
W O WW .CO N/A W N/A WW Y.C N/A.TW N/A
WW .100Y.C M.TW Initial Value W N/A .100Y N/A
M .T N/A
. 1 0 0
N/A
M
W W .C O
Y W
W12.4.8 .1PORTC
W
00 .T
OM C Data RegisterWW.
– Port 1
. COM W W.1 Y.COM W
.C W
W W
. 1 00Y M .TW W
W . 1060
Y
O M .T W
W .1200 O M.T 0
W O Bit 7
Y.C
5 4 3
WW PORTC2 Y .C 1
TW
WW .100Y.C M.TW WW PORTC6 . 100 PORTC5 M .TW .100 PORTC1 M.PORTC0
W O Read/Write
PORTC7
W C O PORTC4 PORTC3
W
W R/W 00Y.R/W C O PORTC
W .C W W Y . W W .T W
W .100
Y .T Value W
R/W R/W
00 R/W
.T R/W R/W
.1 M R/W
W O MInitial W.01 Y.C0 OM 0W W W 0.CO

.TW
0 0 0 0
.C W W 0 Y
WW .100Y M .T W W . 10 0 M .T
W . 1 0
O M
12.4.9 WW
W
DDRC – 0Port Y .CCOData.TDirection W W
Register WW 00Y.CO .TW WW .100Y.C M.TW
W.1
0
OM W.1 .CO .TW
M W Y.C
O
WW .100Y.C Bit M.TW WW6 .100Y WW .1 0 0 0M.
TW
7
W
5
O M 4 3 2
W 1
C O
W O W 0Y.C DDC4 WW DDC1 Y. DDC0 .TW
WW .100Y.CRead/Write M .TW R/W WR/W W.10R/W
DDC7 DDC6 DDC5
M .TW DDC3 DDC2
W 100
.R/W O M
DDRC
O
W O
W0W .100 0Y.C 0 M.TW 0
W 0Y.C 0 M.TW
R/W R/W R/W R/W
WW .100Y.C Initial Value.TW 0
W
0 010
.
W W .C OM
Y W
W
12.4.10 PINC – Port
00
W.1C Input OM Address
Pins
. C W
W W
. 1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W Bit O W .C
WW .100Y.C M.TPINC7 W7 6
WW 5 .100Y.4C M.T3 W 2 W 1 .100Y0 M.T
W
W PINC4 O PINC3 W PINC0.CO PINC
.CO .TRW
PINC6 PINC5 PINC2 PINC1
W
WW .1Read/Write WW R .100YR.C MR.TW R WW 100R
Y .TW
00Y M R
W O
R
W .
.CO M
W Initial Value O N/A 0Y.C N/A WN/AW .1N/A 00Y W
WW .100Y.C M.TW
N/A
WW N/A
. 10N/A M .TW N/A M.T
W O W C O
12.4.11 PORTD –W
WW 00Y
Port D Data
.CO .TW
Register WW .100Y.C M.TW WW .100Y. M .TW
. 1 M W O
WW Bit .100Y.C 7M.TW 6 W . 1 M
W W .C O
W
5
WW
4
Y CO 3
.PORTD3 W
2 1
W WW0 00Y.CO .TW
Y W 0 M. T
W .100 M.T R/W .10 W.1 Y.COM W
PORTD7 PORTD6 PORTD5 PORTD4 PORTD2 PORTD1 PORTD0 PORTD
W O W .C O W
WW
Read/Write .C
00Y 0 M.TW
R/W R/W
WW .100Y R/W R/W
.TW
R/W R/W W R/W
.100 M.T
.
Initial Value1 0 0 W0 0 OM 0 0 0W C O
W O WW .100Y .
W
W O W O
12.4.12 DDRD – Port D Data
WWDirection
W CO
.Register .TW WW .100Y.C M.TW WW .100Y.C M.T
00Y
W W . 1
.C O M
W W W Y .CO 2 .TW 1 W WW 00Y.CO
Y W 0
W 00 .T 0 W.1
Bit 7 6 5 4 3 0
W.1 DDD7Y.COM DDD6 DDD5 DDD4 W W.1DDD3 Y.CO M
DDD2
W DDD1 DDD0 W DDRD
W W W 0 .T W
W
Read/Write
0
.10R/W M.T R/W 10
W.R/W OM R/W
W W .C OR/W R/W
W Y .C R/W
W
R/W
Initial W 0 0Y W W 0 0 .T
M.T
Value 0 0 0 0 0 0 0
W .10 O W .1 OM
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Pins Address OM .1 M
12.4.13 PIND – Port DW
W Input
W 00 .T W.1 4 Y.CO3M W2
.T W W . 10 0 M .T PIND6 W . 1 00 M .T
.C OM
W WW Y .CO R .TW R
PIND7 PIND5
W WW 00Y.CO .TW
PIND4 PIND3 PIND2 PIND1 PIND0 PIND
Y W 0
00 .T 10 W.1 Y.C OM N/A
Read/Write R R R R R R
W.1 Y.COM W W.Value O M
C N/A W N/A
00 .T W W Initial
10 0 Y . N/A
M .T WN/A
W .1 0 0 N/A
M .TW N/A N/A
W. 1 OM W . O W O
.1 0 M W O W O
W 00 .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
100Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W . CO
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
13. M .TW
External W
Interrupts
W . 100 O M .T W
W .100 O M.T
.CO .TW .C W Y. C W
00Y WWThe External. 1 00Y Interrupts M .TW are triggered
Wby the . 100 INT1,Oand
INT0, M .TINT2 pins. Observe that, if enabled,
W . 1 O M W C O W W .C
.C W Y . W W 0 Y T W
. as outputs. This feature provides
00Y .TW Wthe interrupts 00 will trigger
W.of1 generating
.T even if the INT0:2 W
OMa software interrupt.W
pins .10are configured OM
W.1 Y.COM W aW way . C The external Y .C interrupts .TW can be triggered by a falling or
1 00 M .T W . 1 00orYa low level M .TW W
W . 00
1triggered O M
. rising Wedge O (INT2 is only an edge interrupt). This is set up as indicated in
WW 00Y.CO .TW WW
the specification 0 0 Y.C for the .T
MCU
W Control Register WW – .MCUCR 1 0 0Y.C – and M .TW Control and Status Regis-
MCU
W.1 Y.COM W W W.1 Y.COM W W W
0 .COis configured
Yand W as level triggered (only
W terW – MCUCSR. 0 When the . external
T interrupt W is enabled
.1 0 M.T
W .1 00 M .T W . 10 O M W O
W O Wthe pin0is0Y .C low. Note
0Y.C M
INT0/INT1), the interrupt will trigger
W as longWas held
WW .100Y.C M.TW WW edge 1 0interrupts .T . 1the presence M .TWthat recognition of falling
or rising . on INT0 and INT1 requires W O of an I/O clock, described in
W .C O W W Y .CO .TW W W 0 Y .C W
W W
.1 00 Y
M .T W “Clock W Systems
W . 10 0
and their
O MDistribution” on page 25.
W .1
Low 0 level M.T on INT0/INT1 and the
interrupts
O
W O WW .This Y. C
WW .100Y.C M.TW edge interrupt WW on . 1 0Y.Care M
0INT2 .TW asynchronously.
detected
100 implies M
that.TW these interrupts can be
W O used for waking W the part C O
also from sleep modes other
W W than Idle .C O
mode. The I/O clock is halted in
WW .100Y.C M.TW all sleepWmodes except
W
1
.
00Y Idle mode. M .TW W . 1 00Y M .TW
. W O
WW .100Y.C M.TW Note thatW 1
W O if a level
WW 0some
.triggered interrupt OM is used for wake-up WW from O
Power-down
Y.C the MCU
mode, the changed
WW .100Y.C M.TWlevel mustW be held for 0 Y.C time to .T W up theW
wake MCU. This1 0 0
makes .T W
less sensitive to
W O W .1
C OM twice by the Watchdog W W. .C OM
C W . .TW Y W
WW .100Y. M .TW
noise. The changed
W level
. 1 00Y is sampled
M
W
W .100
Oscillator
O
.T
clock.
M
The period of the
O Watchdog Oscillator WWis 1 0µs0Y(nominal) O at 5.0V and 25°C.W Y.C of the.T
W
WW .100Y.C M.Ttor Wis voltageW .C W
.T“Electrical W The frequency . 100 on page M
Watchdog
W Oscilla-
dependent . 1 as shown M in Characteristics”W O 296. The MCU will
W W Y .C O
wake W up if the W
input WW has the 0 Y .CO level
required .T W during this W W
sampling or 0 0
if Yit
.C
is held .T
until
Wthe end of the
W 00 .T 0
W.1 timeYis OM by the SUT fuses .1 M
W W.1 Y.COMstart-up time. The W
start-up .C defined W W WW as described0 Y .COin “System .TW Clock and
W 00 .T W W . 1 0 0 M .T .10 M
. 1 M O is sampled twice byWthe Watchdog W O
W O Clock Options” on page WW25. If00the .Clevel Y.C Oscillator clock but
.TW will be
WW .100Y.C disappears .T W beforeW the end of
. 1 the
Ystart-up
M .TWthe MCU will
time,
W still wake
W . 1 00up, but OnoM interrupt
W OM W COheld long WMCU Y.C .TW
WW .100Y.C generated. .T W The required WW level.1must 0 0Y.be M .T Wenough forWthe . 1 0
to 0complete M the wake up to
W O M W C O W W . C O
trigger the level
WW .100Y.
interrupt. Y W
W .100 O M.T
W O C
W
WW .1Description .CO .TW WW .100Y.C M.TW WW .100Y. .TW
13.1 Register 00Y M W O W O M
W
WW .100Y.C M.TW
O
13.1.1 MCUCR W W– MCUYControl
. C O Register
W
W 00
W.1 The MCU .T
OM Control Register contains W.1 control C
M for interrupt senseWcontrol
Obits W.1 and OM MCU
general
.C
W W 0 0 Y . C
functions. .T W W W
1 0 0 Y .
M .T W W .1 0 0 Y
M .TW
W. 1 OM . W O
WW 00Y.CO .TW WW1 .1000Y.C M.TW
WW .10Bit0Y.C M.TW7 6W 5 .1 4 M 3 2
O
W .CO .TSE WSM1W Y.C ISC11
O
W ISC10 WISC01 WW ISC00 0Y.C MCUCR .TW
WW .1Read/Write
0 0 Y
M
W SM2
W .1 0 0 SM0
M .T
W . 1 0
O M
W O R/W
W O R/W
WW0 .1000Y.C M W0 W .1000Y.C M.TW
R/W R/W R/W R/W R/W R/W
WW Initial 0 0 Y.C
Value . T0W 0 0 .T
W 0
W.1 OM W O W O
and Bit 0 WWW O
•WBit 3, 2 – O
.CISC11, ISC10: InterruptW W Control
Sense Y .CO1 Bit.T 1W 0 Y.C W
WWThe .External
1 0 0 Y
M
Interrupt T W
. 1 is activated by W W
the . 0 0
1external O pin M INT1 if the SREG I-bitW 1
and
0
. the corre- O M.T
W O .C WW INT1 .C
WW sponding Y.C mask
00interrupt .TWin the GICR Ware W
set..1The 00Ylevel and M TW on the external
.edges .
Y
100 pin that M .TW
. 1 M O W O
WW the .CO are WW13-1.00The Y.Cvalue on TW the INT1 pinWisW Y.C
00before .TW
Wactivate 1 0 0 Yinterrupt .T Wdefined in W Table
. 1 M . sampled
W . 1 O M
.
.CO If M WW O
WW Y.C
W WW edges.
detecting
0 Y
edge or toggle interrupt
T W W
is selected,
0 0 Y.C pulses.Tthat W last longer than one0clock
1 0 .TW
period will .1 0generateOan M .interrupt. Shorter pulses W . 1are not guaranteedO M to generate anW interrupt. .IfCOM
.
W
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 level interrupt 1
W.level M
Wlow C OM is selected, theW low must .CObe held until the completion of the currently
W W 0 0 Y . .T W W . 1 0 0 Y
M .TW
.1
executing instruction
M to generate an interrupt.
WW 00Y.CO .TW
W W WW 00Y.CO .TW W
O M.T Table
W .1 13-1. O
.C
M
Interrupt 1 Sense Control W W.1 Y.COM W
.C W Y W W 0 .T
00Y .TW W .100 ISC10 M.T Description WW.10 OM
W.1 Y.COM W W
ISC11 C O .C W
00 .T WW .100Y. M .TTheW W Y
.100 an interrupt M.T request.
. 1 M W0 0O low level of INT1 W
generates .C O
W .CO .TW WW 0 .100Y.C1 M.Any TWlogical change WW .100Y .TW
. 1 00Y M W O on W
INT1 generates O an M interrupt request.
WW 00Y.CO .TW WW1 .100Y.0C MThe .TW WW .100Y.C M.TW
W.1 Y.COM W WW 00Yan.Cinterrupt
falling edge of INT1 generates O request.
W W WW 00Y.CO .TW W .T W
W .1 00 M .T 1
W . 1 1 OThe M rising edge of INT1 generates W .1 an interrupt O M request.
W
WW .100Y.C M.TW
O
WW 00Bit O
W W Y .C O
W • BitW 1,W 0W – ISC01, 0 Y .CO Interrupt
ISC00:
.T W SenseW Control 0 Y1.Cand Bit.T0W
W 00 .T .10 .1 M
W.1 Y.COM W The External WInterrupt 0O isM activated by the external WW pin0INT0 .CifOthe SREG
W W 0 .T W W 0 0 Y .C
.T W W . 1 0 Y
M .TW I-flag and the corre-
0
W.1 Y.COM W interrupt are
sponding interrupt .1 mask are OMset. The level and edges on the external INT0 pin that activate the
WW 00Y.CO .TW
W W WW defined 0 Y .CTable
in .T W
13-2. The value W on the
W .10 0 M.T W .1 0
OM is selected, pulses W .1INT0 pin O is M sampled before detecting
W O C W .C
WW .100Y. C edges.
.TW generateW
If edge W or toggle
1 00Y
.interrupt
M .TW W that
.
last Ylonger
10to0generate
than
M .TW one clock period will
M . W O
W O an
WW 00Y.CO .TW
interrupt. Shorter pulses are not guaranteed
W Y.C an interrupt.
W If low level
WW .100Y.C M.TWinterrupt isW selected,.1the low level M must be held until W
W . 1 0
theWcompletion
0 .T
OofMthe currently executing
W W Y.C O
W
instruction toW WW an
generate 0 Y .CO .TW
interrupt. W 0 0 Y.C .TW
W . 1 00 M .T . 1 0 M W .1 O M
W O
W
WW .100Y.C M.TW
O
W W . CO Table 13-2. Interrupt
W WW 0 Sense Y
O
.CControl W W WW 00Y.CO .TW
W 00 Y .T W .10 0 .T .1 M
W.1 Y.COM ISC01 W WDescription . C OM WW 00Y.CO .TW
W W ISC00 Y W W
W
W .100 O M.T 0
W
W .100 M.T
OINT0 W
.1
Wrequest. .C OM
.C 0 W The low .C
level
Y of generates
W an interrupt
W 0 Y W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O .C on .INT0 an W Y. C
WW .100Y.C M.TW
0 1
WWAny logical 1 00Y
change
M TW generates W interrupt request.
. 100 M .TW
O 1 TheW
. OINT0 generates an interrupt W .C O
W
WW .100Y.C M.TW
0
WW .100Y.C M.TW
falling edge of WW request. .1 00Y M.T
W
W O W CO
W O 1 1
WW .100Y.C M.TW
The rising edge of INT0 generates an interrupt
WWrequest. Y. .TW
WW .100Y.C M.TW W .100 O M
W O
13.1.2 MCUCSR
W
WW .1–0MCU
O
0Y.CControl .T W Status Register
and WW .100Y.C M.TW WW .100Y.C M.TW
W W .C OM
W Y
00 Bit .T W 1 .1 0 OM
W.1 Y.COM WJTD
7 6
W.15 Y.C4OM W 3 2 W
WEXTRF .C MCUCSR
W W 00 .T W
ISC2 W –
1 0 0 JTRF
M .TWDRF BORF W .1 0 0 Y
PORF
M .TW
1
W. Read/Write M R/W WWR
. R/WO W R/W.C
O
CO
0Y.Value
R/W
0Y.C M.TWSee Bit Description
R/W R/W
WW R/W
00Y W
WW .10Initial M . T W0 0
W
W 0 . 1 0
O W .1 O M.T
W O WW .100Y. C
W 2 O W O
WW The
W• Bit Y
0
O Interrupt Sense Control
6 .–CISC2:
0 O and
W.1 Asynchronous M External Interrupt
.CO .Tinterrupt W2Wis activated .CO
Yset.
by the external pin INT2W
W
if Wthe SREG.C
Wzero, a .falling
I-bit
0Y edge M TW
WW the.1corresponding
00Y M
W mask Win GICR . 1 0 0
are If ISC2
M .T is written to W 1 0
O on.
W .CO the interrupt. WW
W .COa rising
toYone, TWedge on INT2 WWactivates Y.Cinter- .TW
00the
WWINT2.1activates
00Y .T W If ISC2 is written00
. 1 M . . 1 M
W W Edges
rupt. . on
C
M are registered asynchronously.
OINT2 WW 00Y.COPulses on
W INT2 wider W W W the minimum
than 0 Y .CO .TW
W pulse .width Y
00 given M .T W W .T .1 0
W1 Y Oin Table 13-3 will generate W.1an interrupt. C OMShorter pulses are not W Wguaranteed .CtoOM
W
Wgenerate 0 0
an . C
interrupt. .When T W changing W
Wthe ISC2 . 1 0 Y
bit,
.
0 an interrupt M . W
T can occur. Therefore, W . 1 0it is rec- M.TW
0 Y
W. 1 M W O
.C Odisable WW Y .CO W W WRegister.00 Y.C W
W W
ommended
. 1 00
toYfirst
M .T W INT2 by clearing W its Interrupt
W .10 0 Enable.Tbit
O M
in the GICR
W .1 Then,
OM.T
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10ISC2 bitOcan M be changed. Finally, .1 M
W Wthe Y .C W W WW the INT2 Interrupt
0 Y .CO Flag .
should be cleared by writing a logi-
TWbefore the interrupt is re-enabled.
W cal.1one00 to its Interrupt M .T Flag bit (INTF2) in . 1
the 0 GIFR M
Register
W
O M.T Table
W .1 13-3. O
.C
M
Asynchronous ExternalW W.1 Characteristics
Interrupt
Y .CO .TW
M
Y .C W W W 0 Y .T W W 0 0
00 .T 0
W.1 YParameter OM .1 OM
W.1 Y.COM W W Symbol
0 .C W W WW 00Y.C Condition
.T W Min Typ Max Units
0 0 .T W 0
.1 Minimum .T
Mpulse width for asynchronous .1 M
W.1 Y.COM W WtW Y .CO interrupt W W WW 00Y.CO .TW 50 ns
00 .T W INT
. 1 0 0 external
M .T . 1 M
. 1 M W O W O
W
1
W. 13.1.3 .C OM GICR – General Interrupt
W WW Control Y .CO Register
W W WW 00Y.CO .TW
Y W 0 .T
W 00
W.1 Y.COM W
.T 0
W.1 Y7 .COM 6 W 5 W W.1 3 Y.COM
W W 00 .T
Bit
W W
1 00INT1 M .T W 4
. 10–0
2
M .TWIVSEL 1 0
.1 M . W O
.CO R/W .TW R/W
INT0 INT2 – – IVCE GICR
W W Y .C O
W W WW 0R/W 0 Y W W 0 0 Y.C R .TW
W 00 .T W.10 Y.C0OM W
Read/Write R R R/W R/W
W.1 Y.COM W Initial ValueWW
.1 0 OM 0 W
. C 0
W 0
.T 0 0
W W
.1 00 M .T W . 1 0 0 Y
M .T W
W . 100 O M
W O WW 00Y.CInterrupt O W Y.C W
WW .100Y.C M.TW • Bit 7 W – INT1: External . 1 M .TWRequest 1W Enable .100
W O M.T
W O W O
C andTthe W Y. C
WW .100Y.C M.TW When theWINT1 bit.is
W
1 0Y.(one)
0set M . W I-bit in theWStatusWRegister . 100 (SREG) M .TisWset (one), the exter-
O W O Interrupt Sense Control1 C O
1/0 .(ISC11
W
WW .100Y.C M.TWGeneral Control
nal pin interrupt
WW Register
is enabled..CThe
00Y(MCUCR) W
.Tdefine WW bits . 1 00Y Interrupt M
andW
.T
ISC10) in the MCU
. 1 M whether the External O is activated on rising
W W .C O
W WW of the Y .CO pin .or W W WW 00Y.C .T W an interrupt
W 00 Y .T and/or falling W edge . 1 0 0 INT1 M T level sensed. Activity .1 on the pin Mwill cause
. 1 M O W O
W O WWis configured .C as an WW .100Yinterrupt .C W
WW .100Y.C M.TW .TW
request even W if INT1 output. The corresponding of
.TExternal Interrupt
. 1 00Y M W O M
O Request 1 is executed W from the O
INT1 interrupt Vector. .C
W
W
W O • Bit 6 – INT0: External W O W W .C O
WW .Interrupt .C .TW0 Enable W W.100Y OM.TW
WW .100Y.C M .TW 1 00Y Request M
O When the INT0 bit isW W O .C
W
WW .100Y.C nal .T W W set (one) 0 Y.Cthe I-bit.TinW
0and the Status RegisterWW (SREG) . 1 00Y is setM(one), .TW the exter-
M pin interrupt is enabled. W . 1
The Interrupt O M Sense Control0 bits W
1/0 (ISC01 andC O ISC00) in the MCU
W
WW .100Y.C General
O
. T WControl Register WW (MCUCR) 0 0 Y.Cdefine .whether T W the External WW Interrupt . 1 0 0Y. is activated M .TWon rising
OM falling edge of the .1 M WW O
W WW CO
.or Y.Ccause an W
WW .100Y.Cand/or M .T W W INT0 0pin
. 1 0 Y level sensed.
M .T W Activity W on the pin
W .1 0 0 will
O M.T interrupt
O W O C
Yof. External.TInterrupt
W
WW .100Y.C
request even if INT0 is configured
.T0W W W as an .Coutput..TThe
00Yinterrupt W corresponding WW interrupt .100 M
W
Request M is executed from the
W . 1
INT0 O M vector. W O
W
WW .100Y.C M.TW
O
W W •Y.CBitO5 – INT2: W ExternalW WW Request
Interrupt Y .CO2 Enable W W WW 00Y.CO .TW
W 00 .T 0
10 I-bit inOthe .T 1 M
W.1 When Othe MINT2 bit is set (one)W W.the
and C
MStatus Register (SREG) W W.is set Y .CO the .exter-
(one),
W W 0 . C
Y pin interrupt .T Wis enabled. WThe Interrupt 0 Y .
0 Sense .T W W .1 0
0MCU Control M TW
1 0nal . 1 M Control2 bit (ISC2) in
W the O and
W W. .C OM WWwhether Y .C O
W W W 0 Y .C .T W
W 00 Y
Status Register .T W(MCUCSR) W
defines
. 10 0 the M .
External T Interrupt is activated .1 0
on rising orM falling
.1 M W O W C O
W edgeYof.Cthe O INT2 pin. Activity on W
W the pin.1will .C an interrupt
cause
.TW requestWevenW
W if INT2 Yis. configured .TW
WW .as 1 0an0 M .T W 00Y M . 100 O M
W output. O The corresponding W W ofYExternal
interrupt O Interrupt Request W 2 is executed .Cfrom the
WW INT2 0 0 Y.C
Interrupt . T
Vector. W W . 1 0 0 .C M.TW W .1 00Y M.T
W
.1 M W O W C O
W
WW .100Y.C M.TW
O
W O W O
13.1.4 GIFR – General WInterrupt Flag
WW .100Y.C M.TW
O Register
W W . C O7 5 W
W 4 Y.CO W 1 WW 0
W
0 Y .CO .TW
W Bit
00 Y W
.T INTF0
6
W 0 0 3
.T 2 0
.1 GIFR OM
W.1 Y.CINTF1 OM INTF2 W.–1 Y.C– OM –W – W W
– .C
W
W Read/Write 0 0 R/W .T WR/W R/W W W
R .100 R M .TR R
W R . 1 00Y M.TW
.1 OM W O W .C O
WW
WInitial Value
0 Y.C 0 .T W0 0 WW 0
0 0Y.0C M.0TW 0 WW0 . 1 00Y M.T
W
. 1 0 M W .1 O W O
WW 00Y.C O
W W1W .100Y.C M.TW WW .100Y.C M.T
•WBit 7 – INTF1: External .TInterrupt Flag
W W . 1
.C O M
W WW Y
O
.Cinterrupt W W WW 00Y.CO
When an edge orY logic change on the INT1 W pin triggers 0 an .T request, INTF1 becomes set
W
W.I-bit100 O Mand.T W .10
.C O M W W.1
(one). W If the inYSREG.C the
W INT1 bit in W
GICR are setY (one), the MCU
W will jump W to the corre-
W
sponding W .100 Vector.
Interrupt M.TThe flag is cleared
W
W 100 theOinterrupt
.when M.T routine is executed.
O C
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OM .1 M one to it. This flag is always cleared
W WAlternatively,
Y .C the flag can be cleared
W W WWby writing 0 Y .CaOlogical .TW
W when
. 100INT1 is configured
M .T as a level interrupt. . 1 0 M
W O W O
OM •W O External Interrupt Flag W O
Bit 6 – INTF0: WW 0 .100Y.C M.TW
0 O
W.1 Y.COM W When an edge or logic change on the INT0
WW 00Y.CO .TW W WWpin triggers0 0 Y.C an interrupt .T W request, INTF0 becomes set
0 T W 1
0
W.1 Y.COM W
. (one).
W
If
.1 the I-bit
C
in
OM
SREG and the INT0 bit
W W.
in GICR are
.C OM
set (one), the MCU will jump to the corre-
W Y . .TW The flag Wis cleared Y
00 when the W
.100 M.T
Wsponding
W
interrupt
.100 the flag O
vector.
Mcan W.1 a logical OoneM.Tinterrupt routine is executed.
W O Alternatively, C be cleared by W
writing .C to it.
W 00 Y.C .T W WW INT0 1 0 Y .
0configured M .TW W . 1 00Y M .TWThis flag is always cleared
W. 1 OM when W . is O as a level interrupt. W O
W O
W O
WW 5 –W .CO Interrupt 2 W 0Y.C M.TW
WW .100Y.C M.TW
• Bit INTF2: 0 YExternal T W Flag W 0
0 . . 1
W . C O When an WeventW.1 onYthe .CO
M pin triggers an interrupt
INT2
W WW request, 0
O
Y.CINTF2.T becomes
W set (one). If the I-
W W 0 Y .T W W 0 0 .T W . 1 0 M
0 bit in SREG .
and1 the INT2 M bit in GICR are set (one), the MCU will jump to the corresponding
W W.1 Y.COM W Interrupt W W Y .C O
W W WW routine 0 Y .CO .TW
W Vector.
.10 0
The flag is
M.T
cleared when the interrupt .1 0 is executed. Alternatively, the flag
W
W .100 O M.T W C O
. a logical W W Y .C O M
someW
WW .100Y.C M.TW INT2 interrupt WW by.1writing
can be cleared
00Y the M .TW one to it. Note W that when .10be0entering M.T
sleep modes with the
O W disabled, O input buffer on this pin Wwill O
disabled.
.C This may cause a logic
W
WW .100Y.C M.TW change inWinternal.1signals
W .C
00Y which .T
will
Wset the INTF2 WWFlag..1See 0 0Y“Digital M .TWEnable and Sleep
Input
WW OM W O
W O
WW .100Y.C M.TWModes” onW page Y.C information.
54 for00more .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y.C O
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W .100 M.T
W 00 .T W.1 Y.COM W
WW .100Y W W .100 M.T
W 00 .T
W W .100 M.T
W O W O W W . C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W . C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
14. M .TW Timer/Counter0
8-bit W
W . 100 with O M .T
PWM
W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Features
0
W. 1
.COM
W •W W Compare
Single Y .COUnit Counter W W WW 00Y.CO .TW
Y W 0
.10 on Compare .T .1
.100 M.T • Clear WTimer OM Match (Auto Reload) WW 00Y.CO .TW
M
WW 00Y.CO .TW W Y .C W W
W .1 O M •WGlitch-free,
W .100Phase O M.T Pulse Width Modulator
Correct
W W.1(PWM) .C OM
.C W .C W Y W
WW .100Y M .TW •W
W . 1 00Y
Frequency Generator
O M .T W
W .100 O M.T
W
WW .100Y.C M.TW
O • External Event Counter
WW .1Prescaler 00Y
• 10-bit Clock M WW 00Y.CO .TW
W W Y .C O
W W WWand Compare 0 Y .COMatch .T W W
W .100 M.T
• Overflow
W .10 O M Interrupt Sources
W.1 and Y
(TOV0 OCF0)M
O
W
WW .100Y.C M.TW
O
W W 0 0 Y . C
.T W W W
. 1 0 0 .C M.TW
.1 M WW 00Y.CO .TW
W W
14.2 Y . O
Overview
C W W WW 00Y.CO .TW W
W .10 0 M.T .1a generalOpurpose, M .1 M
W W .C O Timer/Counter0 W W is
Y .C W single compare
W W W
0 CO
unit, 8-bitY.Timer/Counter
TW
module. A simpli-
W 0 0 Y .T W W 1 0 0 .T . 1 0 M .
fied
W.1 Y.COM Wof I/O pins, refer
block diagram
W W. of the 8-bit
.C OM Timer/Counter is shown
W Win Figure
Y
14-1.
.CO .TW
For the actual placement
W Y W W .10 0
W
W .100 O M.T bits and I/O pins,
W to “Pinout
W .100 ATmega32A” M.T on page 2. CPU
Obold. W W
accessible
.C
I/OM
O
Registers, including I/O
C W are shown .Cin The device-specific I/O Y
Register and bit W
.Tlocations are listed
WW .100Y. M .TW W . 100Y on page M .TW W
W .100 O M
in the “Register Description”
W O 84.
W
WW .100Y.C M.TW
O
W W .C O Figure 14-1. 8-bit
W
W
WTimer/Counter Y .COBlock.TDiagramW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W W 00 .T W
W
W .100 O M.T W.1 Y.COM TCCRn W W.1 Y.COM W
. C W W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O
W O
WW count
W .CO .TW WW .100Y.C M.TTOVn W
WW .100Y.C M.TW . 1 00Y M W O (Int.Req.)
W O W clear O
.C Control Logic W Clock Select Y. C
WW .100Y.C M.TW WW direction 100Y M .TW clk Tn W
.100 M .TW
W . O W O
O Edge 0Y.C
W
WW .100Y.C M.TW WW .100Y.C M.TW WW Detector .10 MTn.T
W
O W O W .C O
W
BOTTOM TOP
WW .100Y M .TW
O W O
W O WW 00Y.C WW Y.C .TW
WW .100Y.C M.TW Timer/CounterW 1 .TW 100)
( From Prescaler
. M
DATABUS
. M W O
W O W
WW =.10 00Y .CO WW .100Y.C M.TW
WW .100Y.C M.TW W
TCNTn
= 0xFF M.T O
W O W
WW .100Y.C
OCn
W O
WW .100Y.C M.TW WW .100Y.C M.TW (Int.Req.) .TW
M
W W .C O W W Y .C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0 OCn M
W .100 M.T = W OM
Waveform
W.1 Y O
W O C W 0 .C M.TW
Generation
C W . W
WW .100Y. .T W W 1 0 0 Y .T W .1 0
OM W. OM W O
W
W W .C O OCRn
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
14.2.1 Registers WW .100Y.C M.TW WW .100Y M.T
W W .100 M.T
W O W O W W .CO
The W
WTimer/Counter .C(TCNT0) .TW and Output Compare WW .Register Y.C (OCR0) .TW W
are 8-bit registers.
.100
Interrupt Y
.1 00Y M W 100 O M W
request W
(abbreviated O Int.Req. in the figure)Wsignals are
to C visibleTinWthe Timer W
Y.all W
Interrupt Flag
WW (TIFR). 00All Y.Cinterrupts .TW W masked . 100with M . Interrupt Mask Register
Register
W . 1 O M are individually W the
O Timer
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10
W(TIMSK). C OMand TIMSK are notW
TIFR W.1 in the
shown .C OMsince these registers are shared by other
figure
W W
timer 1
Y .
00units. M.T W W . 1 0 0 Y
M .TW
W . O W O
.T W 0 0Y.C M.T
WW The.1Timer/Counter W WW .100Y.C M.TW
can be clocked internally, via the prescaler, or by an external clock source on
.C OM
W WtheW Y .COClock.TSelect W W WW 00Y.CO .TW
00 Y .T W T0
.10 0
pin. The
M logic block controls.1 which O clock
M source and edge the Timer/Counter
W.1 Y.COM W W Y. C O W W Y . C W
00 .T WW uses to increment
. 100 The output
(or decrement)
M .TW itsW value. The0Timer/Counter
1 0 is referred
.logic
is inactive when no clock source
M.Tto as the timer clock (clk ).
. 1 M is W
selected. O from the Clock SelectW . C O
W .CO .TW WW .100Y.C M.TW WW .100Y .TW T0
. 1 00Y M W O W O M
WW 00Y.CO .TW TheWdouble
W at all.1times. 0
buffered
0Y.CThe M
Output Compare Register
.TWof the compare WW .1(OCR0) 0Y.C is compared
0used M TW with the Timer/Counter
.waveform
1 value result can W be by O the generator to generate
W W. .C OM WW Y
O
.Cfrequency W W W 0 Y.C Pin.T W See “Output Compare
W 00 Y .T W a W
PWM or
.10 0
variable
M .T output on the Output .1 0
Compare M (OC0).
W W.1 Y.COM W Unit” W
on W
page 75. Y .C
for Odetails. The
W compare W WW event
match 0 Y .CO
will also .TW
set the Compare Flag (OCF0)
W 00 .T W . 10 0 M .T . 1 0 M
.1 M which canW O W O
WW .100Y.C M.TW
W O be used to generate an output compare interrupt request.
W O
W O
.CDefinitions WW 00Y.CO .TW WW .100Y.C M.TW
WW 14.2.2 0 0 Y .T W W .1 M
W.1 Y.COM W Many register WWand 0bit0Yreferences .CO .TinWthis document Ware W writtenY.in CO generalTW
W W 0 0 .T W 1 M
W . 1 0 0 M . form. A lower case “n”
W.1 OM replaces the Timer/Counter . number, in this caseW 0.W However,.C O using the register or bit
when
WW 00Y.CO .TW 0Y for accessing .TW Timer/Counter0
WW .100Y.C M.TW defines inWa program, . 1 the precise M form must be W
used i.e.,
W . 1 0
TCNT0 O M
W O
WW
WW .100Y.C M.TWcounter value and so on.
. 1 00Y M
W O W O
.Care W
Wthroughout CO
.the
W W 00 Y .C
.T W
The definitions W Win Table
1 0 0 Y
14-1 also
M .T W
used extensively W .1 0 0 Y .TW
document.
M
. 1 M . O W O
WW .100Y.C M.TTable W 14-1. WDefinitions . 1 M .TW
W W . C O BOTTOM The W
Wcounter .CO the.T
reaches
Y BOTTOM
W when W W W
it becomes 0 Y .CO .TW
0x00.
Y W W 0 0
W 00
W.1 Y.COM MAX
.T 0
W.1 reaches C OitsM W W.1 0xFF .CO
M
W W 00 .T W The
W Wcounter
1 00 Y .
M
MAXimum
.T W when W it becomes
.10 0 Y (decimal
M .TW 255).
. 1 M . W O
W O TOP WW reaches .CO WW equal .C highest.Tvalue
0Ythe W in the
WW .100Y.C M.TW
The Wcounter the TOP when it becomes 0to
. 1 00Y M .TW W . 1 O M value 0xFF
O count W
sequence. The OTOP value can be assigned to be C
the
. fixed
W
WW .100Y.C M.TW WW .C
00YstoredM TWOCR0 Register.
.the WW The.1assignment 00Y M
W
.Tdependent
(MAX) or the .value 1 in W O is
W O WWof operation. .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW on theW mode
. 1 00Y M
W W .C O
Y W
W
14.3 Timer/Counter
00
W.1 Y.Clock
.T
OM Sources W.1 Y.COM W W W.1 Y.COM W
C W
W W
. 1 00 The Timer/Counter
M .TW W
W .10by 0
O M .T W
W .100 O M.T
W O can be clocked an internal or an external clock
WW .100Y source. .C
The clock source
WW .100is C
Y.selected .Tby
Wthe clock select WW logic.1which 0 0Y.Cis controlled
M .T W
by the clock select (CS02:0) M
bits
.TW
located
M O W O
W .CO WW 0(TCCR0). 0Y.C M W on clock WW C
0Y.prescaler, W
.Tsee
WW .10in 0Ythe Timer/Counter
.T W Control WRegister . 1 For.Tdetails sources
W .1 0and
O M
W “Timer/Counter0 OM W .CO on.T WW .100Y.C M.TW
WW .100Y.C M.TW
and Timer/Counter1 WW .Prescalers” 1 00Y M
page
W 88.
W O
14.4 Counter UnitW.1 W .1 M
W .C OM
Y W
W
W
The
.10main0 partM
O
of.Tthe 8-bit Timer/Counter.1is the programmable
W .C OM bi-directional counter
W W.1 unit. Y
M
Figure
.CO .TW
W 14-2 shows
Y .C a block W
diagram of the
W W
counter and 0 Yits surroundings. .T W W 0 0
W 00 .T 0
W.1 Y.COM W .1 M
W Figure
W .10014-2. O M.T Unit Block Diagram
Counter
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M .TW W Y
.100 TOVn (Int. O M.T
W 00
W.1 Y.COM W
.T
W DATA O BUS W .C Req.) W
O W O W .CO
W
WW .100Y.C M.TW WW .100Y.C M.TClock W Select WW .100Y M.T
W
W O W O
W
WW .100Y.C M.TW clear W
O count W 00clkY
.C W Edge
.TDetector WW Tn.100Y.C M.T
.1 M
W W .C
TCNTn O
W WW
Control Logic
Tn
Y .CO .TW W WW 00Y.CO
W 00 Y .T direction W 0 0 .1
W W 0 0 .T Prescaler ) W
W 00 .T W.1 Y.COM W
( From
W W.1 Y.COM W W
W TOP .100 .T
W
W .100 O M.T BOTTOM W W .C OM
WW .100Y. C W Y
W O M.T
W
W .100
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 description 1 M
W WSignal .C OM (internal signals):WW. Y .CO .TW
W 00 Y .T W W 1 0 0 M
W.1 count C OM Increment W W.or decrement .CO TCNT0 by 1.
.T W W W
1 0 0 Y .
M .T W W . 1 0 0 Y
M .TW
OM .
W direction O W increment .CO and
Select WW between
. 1 00Y M .TW decrement.
. 1 0 M W O W O
C to zero).
W O W (set00allY.bits
0 0 Y.C .T W WW clear . 1 0 0Y.C M.TW Clear W TCNT0
.1 M.T
W
. 1 M W O W .C O
W .CO .TW WW clk.1Tn00Y.C M.TW Timer/Counter WW clock, 100
Y
referred to.T asWclkT0 in the following.
. 1 00Y M W O W . O M
WW 00Y.CO .TW WW TOP.100Y.C M.TW SignalizeWthat TCNT0
W 00hasY.Creached W
.Tmaximum value.
. 1 M W . 1 O M
O W O .C
W
WW .100Y.C M.TW WWBOTTOM Y.C .TWSignalize that WWTCNT0 .10has0Y reached M.T
W
minimum value (zero).
W . 100 O M W C O
W O . C W Y . W
WW .100Y.C M.TW WW of.1the
Depending 00Ymode ofMoperation .TW used,W the counter .100is cleared, .T
Mincremented, or decremented
W O W O
C T0). clk W W . C O
at eachW
W timer .clock 0Y.(clk Wcan be generated from
00Yan external W
or internal clock source,
WW .100Y.C M.TW 10Clock M TT0
.bits W
W .1clock O Mis.Tselected (CS02:0 = 0) the
selected by W the O
Select (CS02:0). When no source
C
W
WW .100Y.C M.TW timer W
O W
is stopped. Y.C
00However, .TW
the TCNT0 value WW canWbe . 0Y.
10accessed M
W
by.Tthe CPU, regardless of
. 1 O M O
W O WW 00Y.Cor W .C
00YpriorityMover) .TW all counter clear or
WW .100Y.C M.TW whetherWclkT0 is .present 1 not..T
M
AW CPU write W overrides
W . 1(has
O
W O C
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
count operations. WW .100Y. M .TW
O W CO W .C O
W The countingW
WW .100Y.C M.TWthe Timer/Counter W sequence 0 Y.determined
0is .TWby the setting WW of the WGM01
. 1 00Y andMWGM00 .TW bits located in
. 1 M Wclose Y O
W O WControlY.Register
WW (counts) CO (TCCR0). ThereW are connections between how the
0on.C .TWCompare output
WW .100Y.C M.TW counter behaves . 1 0 0 and howM .T W
waveforms are Wgenerated
W .1 0 theO M
Output
W O C
W
WW .100Y.C M.TOC0.
O
W For more WW details about .C
00Y advanced .TWcounting sequences WW .10and 0Y.waveform M .TW generation, see
W . 1 O M W C O
W O WW .100Y .
WW .100Y.C M.TW
“Modes of Operation” on page 78. W
O The Timer/CounterW W O Y.C
W
WW .100Y.C M W
.TWGM01:0 W Overflow 00beY.C Flag.TisWset according
(TOV0) WW to the mode
.100
of operation
M .TWselected by
the bits. TOV0 W . 1
can used O Mfor generating a CPU W
interrupt. O
W
WW .100Y.C M.TW
O
W O
WW Compare
14.5 WOutput Y.CO Unit W W WW 00Y.CO .TW WW .100Y.C M.TW
0 .T
W.1
0
OM W W.1 Y.Ccompares OM W W CO
Y.Compare W
WW .100Y.CTheM8-bit .T W comparator W continuously
. 0 0
1 OCR0, M .T W TCNT0 with W the Output
W .1 0 0
O M.T Register
W O C
W
WW .100Y.C
O
(OCR0).
.T
Whenever
W
TCNT0
W W equals
0 0 Y.C the
.
comparator
T W WW .100Y.
signals a match. A match
M
will
.TW set the
1
. the nextOtimer M clock cycle. If enabled
W Output MCompare Flag (OCF0)
.CO .Flag
at
WWthe Output Y.CCompare WFlag generates
W (OCIE0
WWan output 0 .C=O1 and
Ycompare T
Global
W
WW .100YInterrupt M T Win SREG is Wset), .1 0 0 M .T
W . 1 0
O M .
interrupt.
O W O .C
W
WW .100Y.C M.TW
The OCF0 Flag is automatically WW cleared .C
00Ywhen the W
.Tinterrupt WW Alternatively,
is executed.
. 100
Y W
the.TOCF0
M
. 1 O M W O
W Flag can
O be cleared by software WW 00Y.C
by writing a logical one to its I/O bit location.
W The Y.C
waveform gen-
W
WW .10erator0Y.C uses . T W
the match W
signal to . 1
generate an M
output .T W
according
W
to operating
W .1 0 0
mode set
O M .
by
T the
W W WGM01:0 . C OMbits and Compare Output WW mode Y .C O
W W Wand bottom 0 Y.Csignals.Tare W
W 00 Y .T W W . 10 0 (COM01:0)
M .T bits. The max .1 0 M
.1 M W O W C O
W usedYby .CO the waveform generatorWfor handling .Cthe special .TW
cases of the WW extreme values Y. in some .TW
WW .modes 1 00 of operation M .TW(See “Modes W .1 00Y on page M W . 100 O M
of Operation”
W O 78.).
W
WW .100Y.C M.TW
O
ofW O W O
WW .100Y.C M.TW
WFigure 14-3 O shows a block diagramW the output.C compare unit.
WW .100Y.C M.TW W 1 0 0 Y .T W
W. OM W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W . C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 14-3. OMOutput Compare Unit, .1 M
W WFigure Y .C W W WW Block Diagram
0 Y .CO .TW
W 00 .T 0
W.1 Y.COM W W W.1 BUS
DATA Y .CO .TW
M
W W W 0 0
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
.C W . C W
00Y .TW W .100
Y
M.T
W .100 OM
.T
00 .T WW .100Y. M .TW W .100
Y
M.T
. 1 M W O W .C O
W .CO .TW WW .100Y.C M OCRnW WW .100Y .TW
TCNTn
. 1 00Y M W O
.T W O M
W W. 1
.COM
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 Y.COM W WW ) 00Y.CO .TW
W W 00 .T = (8-bit WComparator
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O W . C W Y . C TW
OCFn (Int.Req.)
WW .100Y.C M.TW W .1 0 0 Y
M .T W W . 1 00 M .
W W .C O
Y W
W
W .10 0
O M.T W
top .1
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W bottom .100Y M.TWaveform GeneratorWW.10
W 0
OM
.T
W O W C O .C
WW .100Y.C M.TW WFOCnW
1 00Y
.
M .TW W . 100Y M .TW OCn
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W WW 00Y.COWGMn1:0 W COMn1:0
W WW 00Y.CO .TW
W 00 Y .T W .T .1 M
W W
W
W .100 O
The
M .T OCR0 Register W is double
W .100 buffered OM
.T using any of theWPulse
when
W
.1 WidthOModulation
. C
M (PWM)
.C W Y .C W W 0 Y T W
WW .100Y modes.
M .TW For the normal
W and
.
Clear
100 Timer
M
on .TCompare (CTC) modes
W
of
.10 operation,
O M. the double buff-
Oering is disabled. The W W O C
Y. Compare
W
WW .100Y.C to M .TWtop or bottom
double buffering
W of the.1counting .C synchronizes
00Y sequence. .TW The synchronization WW of the
the update
.
OCR0
100prevents M .TW
Register
either W O M W O the occurrence
W O
WW .1PWM 0Y.Cpulses,
W Y.C W
WW .100Y.Cof odd-length,M .T W non-symmetrical 0 M .T W making
thereby Wthe output
W .1 00glitch-free.
O M.T
W O W .C O W Y.C W
WW .100Y.C The OCR0 .TWRegister access WW may.1seem 00Y complex, M .TW but this is not Wcase. .100 the double
When M .Tbuffering
M O W O
W O WW to 0the .C Buffer WWif double Y.C TW
WW .100Yis.Cenabled, M .T Wthe CPU hasW access
.1 0YOCR0 M .TWRegister, and
W . 1 00buffering
O Mis .disabled
O W O .C
W
WW .100Y.C M.TW
the CPU will access the
WW .100Y.C M.TW
OCR0 directly.
WW .100Y M .TW
W O W O
14.5.1 ForceWW
W Compare
Output 0 0 Y.C
O
1
W. In non-PWM OM waveform generation WW 0can O
W Y .C W W WWmodes, 0 Y .CO
the matchToutput
. W of the W comparator 0 Y.C be forced W
.Tby
W .1 00 M T
.to W . 10 (FOC0) O M W .1 will not O M
W writing a one
.CO .TW the Force Output Compare .C bit. Forcing compare
WW .100Y.
match C set the
WW .OCF0 00Y Flag orMreload/clear theW
W 00YOC0 pin
1the M .TW M .TW
1 timer,W but. will be updated as if a real
W compare O match
W Y.C
O W settings .CO whether
0Ydefine TW the OC0 WW .C
00YclearedMor.TW
WW had .1 0 occurred
0 M
(the
. T WCOM0[1:0]Wbits . 10 M . pin is .1
W
set,
O
W O
Wtoggled). O
W .CbyOTCNT0 WW 00Y.CO .TW W WW 00Y.CO .TW
14.5.2 WW Blocking
Compare Match
.10 0 Y
M. T W Write W .1 W.1 Y.COM W
W C O W W .C OM W
WW All CPU write Y. operations Wto the TCNT0 W Register Y block any
00will .TW compare match W that .occur100 in the .T
nextW .100 clock O
timer M.Teven when the timer
cycle, W is
.1stopped.
C O
This
Mfeature allows OCR0W Wbe
to . C OM
initialized
WtoWthe same 0 0 Y.C .T W WW .100Y .
M .TW W . 1 00Y M .TW
.1 value M
as TCNT0 without triggering
W an interrupt
O when the Timer/Counter W clock isO
W WW 00Y.CO .TW
enabled. WW .100Y.C M.TW WW .100Y.C M.TW
W.1 OM W O W O
14.5.3 Using the Output Compare
W W Unit .C O
Y W
W writing.1TCNT0
Since
W
00 in any .T
OM mode of operationW will .1 all compare
Wblock .C OM matches for oneW W.1clock
timer
cycle, W
Wthere are Y .C
risks involved W W TCNT0.1when 0 Y W W
.T output compare unit, inde-
.100 .Twhen changing 0 usingMthe
pendently W
of whether C theOM Timer/Counter is W
running Wor not.YIf.Cthe O value written to TCNT0 equals
W W
1 00Y
.
M .TW W . 100 M .TW
W . O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10OCR0 value, OM the compare match .1 M
W Wthe Y .C W W WW will be missed,
0 Y .CO resulting .TW
in incorrect waveform generation.
W 0 0 .T . 1 0 M
W W.1 Y.COM W
Similarly, do not write the TCNT0 value
W W equal to
0 Y
BOTTOM
.CO .TW
when the counter is downcounting.
W W The.1setup 00 of theM .T W 0
O M.T W .C O OC0 should be performed W W.1beforeYsetting .CO the
M Data Direction Register for the port
W
Y .C W W Wpin to 0 Y
output.
0 The .T
easiestW way of W
setting the 1 0 0
OC0 value is.Tto use the Force Output Compare
. 1 00 M .T . 1
W strobe M
O in Normal mode. The W . O M
W
0 Y.C
O
.T W WW(FOC0)
0 0Y.C bitsM .TW WW OC0 .1 0Y.C keeps
0Register M.T
Wits value even when changing
. 1 0 M W
between . 1 waveform O generation modes. W C O
. 1 M W thatYthe O W O
WW 00Y.CO .TW BeW
W
aware .C COM0[1:0]
0COM0[1:0] . W bits areW
Tbits
notWdouble00buffered Y.C together .TW
with the compare value.
1 Changing . 1 0
the M will take effect . 1
immediately.
W O M
W. OM W O
WW .100Y.C M.TW
O W O
W O
.CCompare WW Unit Y.C W WW .100Y.C M.TW
WW .14.6 00 Y .T W Match Output
W .1 0 0 .T
W 1 Y.COM W The Compare WW Output OM (COM0[1:0]) bits have
.Cmode WWtwo functions. O
Y.C The.TWaveform W Generator uses
W W 0 Y . T W W 0 0
.1(OC0) state
W .1 00 M .T the COM0[1:0] W . 10bits for definingO M the Output Compare W C O Mat the next compare match.
W O .C WW . W
WW .100Y.C M.TW Also, the WWCOM0[1:0] . 1 00Y bits control M .TWthe OC0 pin output . 00Y Figure
1source. M .T14-4 shows a simplified
W O W C O W W O
.C I/O Registers,
W .1 00Y M .TW schematic W of the
W .
logic
100
affected
O M
by
.T the COM0[1:0] bit setting.
W .10 The
O M. I/O bits, and I/O
W O pins in the figure W are00shown Y.C in bold. WOnly the parts WW of the Y. C
general I/O port
WW .100Y.C M.TW (DDR andWPORT) .that 1 M .Tby . 100shown.OWhen M .TW Control Registers
O W are affected
CO the COM0[1:0] W
bits are
Y.Cpin. If a.T
referring to the OC0
W
WW .100Y.C M.TWstate, the reference WW .1is0for 0Y.the .
internalT W OC0 Register, WWnot the . 1 0 0
OC0 M
W
System Reset occur,
W O W O M W W .CO
C W . C W Y W
WW .100Y. M.T
the
W OC0 Register
W is reset
.100
Yto “0”.
M.T
W 00
W.1 Y.COM W
.T
W O W W .C O W
WW .100Y.C M.TFigure W 14-4. WCompare . 00Y Output
1Match M
W
.TUnit, Schematic
W
W .100 O M.T
O W O .C
W
W
W O W O
W
WW .100Y.C M.TW
O
WW 00Y.CO .TW
COMn1
W W Y .C O
W COMn0 W
W
W Waveform
0 Y .CO .TDW Q W
W 00 .T 0
1Generator .1 M
W W.1 Y.COM W FOCn WW. 0Y.COM W W WW 00Y.CO .TW
W .T
W 00
W.1 Y.COM W
.T 0
W.1 Y.COM W
1
W W.1 Y.COCn OM
W
W W 0
W W
. 1 00 M .T W
W . 100 O M T
.OCn 0
W .10 Pin
O M.T
W O WW .100Y. C
WW .100Y.C M.TW WW .100Y.C M .TQW M .TW
W O D W O
W
WW .100Y.C M.TW
O
W C O WW 00Y.CO .TW WW 00Y.CO .TW
DATA BUS
W Y. W W W .1
W 00 .T W.1 Y.CPORT OM M
W W.1 Y.COM W W W W WW 00Y.CO .TW
W .100 M.T
W 00 .T W.1 Y.COM W
W .C O W W.1 Y.DCOQM W W
WW .100Y W W .100 M.T
W 00 .T
W
WW .100Y.C M.TW W Y
.100 DDR OM.T
W W
W .100 OM
.T
W O W C W .C W
WW .100Y.C M clk.TW WW .100Y. M .TW W .100
Y
M.T
I/O
W O W C O
W
WW .100Y.C M.TW
O
O W O W .C O
W general
The
WWGenerator 0 Y.CI/O port .T
function is overridden
W WW .1by 0 Y.COutput.T
0the Compare
W (OC0)WW 00Y
from the Waveform
. 1 M.T
W
.1 0 if either M of the COM0[1:0] bits Ware set. O
However, M the OC0 pin W
direction (input or
.C O
out-
WW
W .CO .T byWthe Data Direction WW Register .C
00Y (DDR) TWthe port pin.
W
WThe 0Y
10Direction .TW
. 00Ycontrolled
put) is1still M W . 1 O M .for Data
W . O M
WW 0bit0Y .Cthe O OC0 pin (DDR_OC0)
WWmust.1be Y.Cas output TW WWvalue.10is0visible Y.C .TW
WRegister 1
for
.T W 0 0set M . before the OC0
W O M
Wpin.. The port OM W O Waveform Generation
WWmode. .C
WW .100Y.C M.TW
on the override function is independent of the W
WW .100Y.C M.TW . 1 00Y M.T
W O W O
TheW W of the
design O
.Coutput compare pin logicWallows initialization .C of the
.TW
OC0 state W the00out-
Wbefore Y.C
W is enabled. . 1 00Y Note M .TW W .1 00Y areMreserved W . 1 of OM.T
put that some COM01:0 bit
W settings O for certain modes
WW See
operation.
W
0 Y.C
“Register
O
.T W
Description” on WW 84. .100Y.C M.TW
page WW .100Y.C
0
W.1 OM W O
WW
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1Mode OM .1 M
14.6.1 Compare Output
W Y .and
C Waveform Generation
W W WW 00Y.CO .TW
W 0 .T
The
W .10Waveform
.C OM Generator uses the COM0[1:0]
W W.1 bits Y
OM
.Cdifferently W
in normal, CTC, and PWM modes.
W W W For all0 0 Y
modes, setting .T Wthe COM0[1:0] W = 0 tells
1 0 0
the waveform .T generator that no action on the OC0
O M.T W W .1
.C OM W W. Y . C OM
W
.C Register is to be
00Y referMto.TTable
performed W on the next
W compare 0 match. For .T compare output actions in the non-
. 1 00Y M .TW W . 1 W . 10For O M
PWM modes 14-3 on page
W W 85.
1 0 0
fast
Y.C PWM
.
mode,
T W refer to Table 14-4 on page
0 0 85, and.1for phase correct M PWM refer to Table .14-5 on pageM86.
W .1 at theOfirst
.100 M.T A change W.1 of the OM
COM0[1:0] bits state will have Weffect .C
M compare match after the bits are
WW 00Y.CO .TW W W
written. For 1 0 0 Y
non-PWM.C
. T
modes,W W W
the action can be.1forced 0 0 Y to have M
W
.Timmediate effect by using the
W . 1 O M .
W bits. O M W W .C O
.C FOC0 W strobe Y .C W W 00 Y .T W
WW .100Y M.T
W O W . C O W
WW .14.7 Y.C W WW 0Y M.T
W W .100 M.T
W 100 Modes O M.Tof OperationWW.10 O W W .C O
WW .100Y.C M.TW Y.C i.e., the .TW behavior ofW .100
Y .TW
W of operation,
The mode
W . 100 O M the Timer/Counter
W C
and
O Mthe Output Compare pins, is
W W .C O defined W
by the combinationY .C of the W Waveform W W
Generation 0
mode Y . (WGM01:0) .T W and Compare Output
W 00 Y .TW W . 1 0 0 M .T . 1 0 M
.1 M O W O
W O mode (COM0[1:0]) WW 0bits. Y.CThe Compare W OutputW W bits 0do
mode 0Ynot .C affect.T the
Wcounting sequence,
WW .100Y.C M.TW while the WWaveform . 1 0Generation M .Tmode . 1 M
W W .C O
W W W Y . CO W
bits do.
W
The
WW 00Y.CO .TWwhether the PWM
COM0[1:0] bits control
W 00 Y .T output generated W 0
should0 be inverted .T or not (inverted or .1non-inverted
W.1 Y.COM Wmodes the COM0[1:0] W.1 bits C OM whether the output WWshould OM PWM). For non-PWM
.Cset,
W Y . control W W 0 Y
be W or toggled at a
cleared,
W W
. 1 00 M .T compare match W
W . 00
1“Compare O M .T W .10 O M.T
W O (See Match Output Unit” on
WW .100Y page 77.). .C
W O W O
W O For detailed timing
WWTiming
information
0Y.C Mon
refer to Figure W 14-8, Figure WW 14-9, Y.C 14-10.Tand
Figure W Figure 14-11
WW .100Y.C M.TinW “Timer/Counter . 1 0Diagrams” .Tpage 82. W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O
14.7.1 WW .CO .TW
NormalYMode W WW 00Y.CO .TW WW .100Y.C M.TW
W 0
0
W.1 Y.COM The simplest mode of W.1 Yis.Cthe
Woperation OM normal mode (WGM01:0 WW= 0). COmodeTthe
Y.this
In counting
W W 00 .T W W 1 0 0 M .T W W . 1 0 0 M . W simply
W.1 OMdirection is always up W .
(incrementing), O and no counter clear is performed.
WWand 0then
The
O counter
WW .100Y.C overruns . T Wwhen it passes WW its maximum 0 0 Y.C 8-bit .value T W (TOP = W 0xFF) . 1 0Y.C restarts
M TW the bot-
.from
M .1 M W O
W O WW 0the .CO .TW OverflowWFlag W (TOV0) Y.Cbe set .inTW
WW .100Y.Ctimer
tom (0x00). W In normalWoperation 0YTimer/Counter 00will the same
M .T . 1 M W .1 O M like a ninth
W O clock cycle as the TCNT0W becomes O zero. The TOV 0 Flag in
W this case C
behaves
.
WW .100Y.C bit, except .TWthat it is only WW set, not . 1 0Y.C However,
0cleared. M .TW combined Wwith the . 00Y overflow
1timer M
W
.Tinterrupt
M W O W O
.C by software.
W
WW .100Ythat .COautomatically
.T W clears WW the TOV000Flag, Y.C the timer .TWresolutionWcan be .increased
W
1 00Y M.T
W
M W . 1 O M W C O
W There O in.Cthe normalWmode, a new WW . W
Y.C are .no
WW .100anytime. TW
special cases W
W to consider . 1 00Y M .T
counter value
. 100
Y can be.T
M
written
M W O W O
W
WW .10The 0Y.Coutput
O
W .C OMcompare unit can be WusedW to generate Y .CO interrupts W
at some W
W
W time.YUsing
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0 .CO the.out- W
W W
.1put Y
00 compare M
W W
.Tgenerate waveformsWin.1Normal
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O M . Tis not recommended,W 0
.1 this willOoccupy
since MT
W O WW .100Y. C
WW .too Y.C of the.TCPU
00much W time. WW .100Y.C M.TW M .TW
1 M W O W O
W
WWon Compare 0
O
Y.C Match.T(CTC) W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
14.7.2 Clear Timer
W.1 Y.COM W Mode W O
Y.C = 2),
W
WW is .used 0Yto.Cmanip- .TW
WW In Clear 0 0 Timer on .T
Compare or CTCWW mode . 0 0
(WGM01:0
1 M .T W OCR0 Register
the 1 0 M
. 1 M O W O
W .CO resolution. WW the0counter 0Y.C isMcleared TW to zero when WW the .counter .C
00Y valueM.TW
WWulate.1the 0 0Y counter
. T W In CTC Wmode . 1 . 1
W W
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. C OMthe OCR0. The OCR0 WWdefines Y .COtop value
the W for the counter,
W WWhence 0 Y .COits .TW
also
Y W W 0 .T 0
W resolution.
W.1 This
00 mode .T
OM allows greater control Wof .10the compare
C OM match output frequency. W W.1It alsoY.sim- CO
M
W
Wplifies the 0 0 Y .C
operation W
of.counting
T external W
W events. 1 0 0 Y .
M . T W W . 1 0 0 M .TW
.1 OM . W O
WW Y.C for.T WshownW .CO .TW
0YFigure WW 00Y
.C W
W
The timing
. 1 0 0
diagram
M theWCTC mode Wis
W .1 0 in
O M14-5. The counter value
W . 1
(TCNT0) OM.T
W CO
a .compare W .C OCR0, .TW and then W
W (TCNT0) Y.C
WW .until
increases
1 0 0Y M .Tmatch
W occursW between
.1 00Y and M
TCNT0 counter
W . 100 O M.T
is cleared. W O W O W .C
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 14-5. OMCTC Mode, Timing Diagram .1 M
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
.TW 100
W .100 M.T
W OCn Interrupt Flag Set
M . M .T W O
W O C
. 1 00Y M W O W O M
W
0 Y.C
O
0
W. 1
.C OM
Y W .1
M
WW 00Y.CO .TW W W TCNTn
00 .T W
.C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .100Y.C M.TW
OCn W
W(Toggle)
W .100
Y
O M.T
W
W .100 O M.T (COMn1:0 = 1)
W O W . C
WW .100Y.C M.TW WW .100Y.C M.TW W 100 4 OM.T
Y W
Period W 1O 2 3W. C
W
WW .100Y.C M.TW
O
W O W O
W O
WWcan .be 0Y.C Meach WW value Y.C W
WW .100Y.C M.TW An interrupt 1 0generated .TWtime the counter W . 1 00reaches
O Mthe.TTOP value by using the
W O C
W O
WW .100Y.C M.TW OCF0 Flag. WW .C
00Y is enabled,
If the interrupt .TW the interrupt WW handler10routine
. 0Y. canMbe W for updating the
.Tused
. 1 M
O TOP to a value close W O
W O TOP value. However, WW 0changing 0Y.C value
Wto BOTTOM .Cwhen the
00Y the CTC .TWcounter is running
WW .100Y.C M.TWwith none W . 1 M TW be doneW
.must . 1 O M
W .C O or a
W
lowW prescaler
Y .CO W
with
W WW 00Y.C
care since mode does not have
W
W W
. 1 00 Y
M
W W
.T the double bufferingWfeature. . 10 0 If theM
O
new T
. value written to OCR0 W .1 is lowerOthan M.Tthe current value of
W O .C W .C have .toTW
WW .100Y.C M.TTCNT0, W WW will.1miss
the counter
00Y the compare M .TWmatch. The Wcounter . 00Y
1will then
M
count to its max-
O imum value (0xFF) W
and wrap O
around starting at 0x00 before W the compare .C O match can occur.
W
O W canYbe O to toggle its logical
W O For generating a waveform WW 0output Y.C in CTC.Tmode, W the OC0 WW output 0 .Cset M .TW
WW .100Y.C M .
levelT W
on each
W
compare . 1
match
0 by M
setting the Compare W
Output .1 0 mode O
bits to toggle mode
W C O W W .CnotO W Ythe.C W for the
W Y. W W 0 Y .T W W .1 0 0 .T
W . 1 00 M .T
(COM01:0 = 1). The OC0
W . 10
value will
O
be
M visible on the port pin
Wunless
C
data
O M direction
W O .C WW .1frequency . .TW= fclk_I/O/2
WW .100Y.C pinMis.Tset Wto output.W The W waveform
.1 00Y generated M .TW will have a maximum 00Y of fOC0
M
O
when OCR0 is set to zero W(0x00). The waveform O frequency is defined W O
the.Cfollowing equation:
W
WW .100Y.C M.TW WW .100Y.C M.TW f clk_I/O
WW .1by 00Y M.T
W
W O W C O
W O
WW .100fOCn - W
Y.C= ---------------------------------------------- Y. .TW
WW .100Y.C M.TW 2M ⋅ N.T⋅ W ( 1 + OCRn ) W
W .100 O M
W O .C
W
WW .100YThe .CON variable .T W represents WW 0
C
0Y.factor .T8,W64, 256, orW
W
. 1 00Y M.T
W
M the
W .1
prescale
O M(1, 1024). W C O
W O WW .100Y .
WW .100As Y.Cfor the Normal .TW mode ofWoperation,
W
. 1 0Y.C
0the TOV0 M .TW
Flag is set in the same timer clock cycleM .TWthe
that
M O W O
WW .10counter 0Y.C counts . T W from MAX to W0x00. . 1 M .TW
W W .C OM
00 Y W .1
14.7.3 Fast W W.1 Y.COM W
PWM Mode .T W.1 Y.COM W WW 00Y.CO .TW
M
W W
W or fast.1PWM 00 modeM(WGM01:0 .T W
W 100 fast Pulse
The
W.PWM O M.WidthT Modulation
W C O = 3) provides
W W.1a highY.frequency
CO
M
W W 00Y
.C
waveform .generation TW option. W
W The .fast Y
100PWM O
. differs
M
W
.T from the other PWM W .option0
10 by its M .TW
sin-
.1 M W W C O
W gle-slope.C
WW non-inverting
O
operation. The counter counts
.TW Output mode, WW from .C
BOTTOM
00Y Compare
to MAX then restarts
.TW(OC0) is cleared WW from 0Y.
BOTTOM.
10the
In TW
.
. 1 00Y M
Compare Wthe. 1 Output O M W on. compare
.C O M
W O C W W
WWmatch 0Y.C TCNT0
0between .TWand OCR0,Wand set
W
. 0Y.
10BOTTOM.
at M In.T W
inverting Compare W Output Y
.100mode, O theM.T
.1 M W O W .C
W is set
0Y.C onOcompare W at0BOTTOM. 0Y.C M .TW WW operation, 100
Y the .TW
WW output
0 .TWmatch andWcleared . 1
Due to the single-slope
. M
W W
operating . 1 frequency
.C
M
O of the fast PWM mode W W can be Y . C O
twice as high W as the phase
W W W correct Y
0 .CO .TW
PWM
Y W W high.1frequency 00 M.T the fast PWM mode 10 suitedOM
Wmode that
W .100use dual-slope O M.T operation. ThisW W . C Omakes W W.well Y.C W
.C 0Y High W W physically 00small
WforW power regulation,
. 1 0 0 Y
M . T W
rectification, and W DAC applications.
W .1 0
O M .T
frequency allows
W . 1 O M.T
W O
WW and.1therefore .C reduces WW cost. 00Y.C
WW .100Y.C M.TW .TWtotal system
sized external components (coils, capacitors),
00Y M W .1 O M.T
W O W .C O W Y . C
WWPWM.1mode,
In fast
0 0Y.Cthe M counter
.TW is incremented WW until . 1 0the0Ycounter M .TW matches W
value the MAX value.
.100
O W O W
The counter
WW is 0then cleared
0Y.Cin Figure
at the following W
.TW
timer clock cycle.
Y.C The.Ttiming W diagram WW for the fast
PWM Wmode is
. 1 shown M 14-6. The TCNT0 W
W .
value 100is in the M
timing diagram shown as a his-
W W Y .C O
W W W The 0 Y .CO includes .T W
togram W for illustrating
.10 0 the single-slope
M.T
operation. .1 0 diagram non-inverted and
W C O W W .C OM
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OMoutputs. The small horizontal .1 OM on the TCNT0 slopes represent compare
W Winverted Y
PWM
.C W W WW 0line 0 Y .Cmarks
.TW
W matches
. 1 00 between M .TOCR0 and TCNT0. W.1 O M
W O
OM W 14-6. O
WW Diagram
W .CO .TW
WW .100Y.C M.TW
Figure Fast PWM Mode, Timing
0 0 Y.C .T W . 1 00Y M
W.1 Y.COM W W W Y .C O
W W WW 00Y.CO .TW
. 1 00 M .T W
W . 100 O M .T W .1
C O M OCRn Interrupt Flag Set

. 1 M W O W O
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW OCRn Update and
W W. 1
.C OM
W WW 00Y.CO .TW W WW 00Y.CO .TW TOVn Interrupt Flag Set
W 00 Y .T W .1 M
W W 00 .T W
W
. C W
WW .100Y M .TW W TCNTn .100
W O M .T W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
. W O
W O OCnWW .CO .TW WW .100Y.C M.T(COMn1:0 W = 2)
WW .100Y.C M.TW W . 1 00Y M W O
W O
W
WW .100Y.C M.TW
O OCnWW .100Y.C M.TW WW .100Y.C M.(COMn1:0 TW = 3)
W O W O
W
WW .100Y.C M.TW
O
WW .1100Y.C .TW 4 WW .100Y.C M.TW
M W6W 070Y.CO .TW
WW 00Y.CO .TW
Period 2 3 5
W W .C O W
W 00 Y .T W W .1 M
W W Overflow 00 Flag (TOV0) .T is set each time the W 1
W .100 M.T
The Timer/Counter
W O W.1 Y .C OMroutine can be usedW W.counter Y .C
reaches
OM MAX. If the inter-
W value.
.C rupt is enabled, theW interrupt handler W for updating the compare
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O In fast PWM mode,W .C W waveforms Y.C on the .TW
WW .100Y.C M .TW W the compare . 1 00Y unit allows M .TW generation W of PWM
W .100 O M OC0 pin. Set-
W O W O W .C
0Y.C toM3.T(See
ting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
WW .100Y.C be .T W WW the.1COM01:0 0 W W . 1 0Y
085). M .TW
W W .C OM generated
W
by setting
W W Y . CO W
Table 14-4
W WW 00Y.CO .TW
on page The actual OC0 value
W 00 Y will only W
be visible on the port 0
0 if the data
.1pin T
. direction for the port W pin.1is set as output. M The PWM
W.1 Y.CO M.T W W .C OM the OC0 Register W Y .CO match W
W waveform W is generated W by setting 0(or
Y clearing)
.T W W at the
10 compare
0 between
M.Tthe coun-
W . 1 00 OCR0 M .Tand TCNT0, and W
clearing . 10(or O
setting) M the OC0 Register at W
the
.timer
C
clock O cycle
W
WW .100Y.C
O
.TW (changesWfrom MAX
W .C
0to0YBOTTOM). .TW WW .100Y. M .TW
ter is M cleared . 1 O M W O
W .CO .TW WW 00Y.C TW by the following WW .100Y.C M.TW
WW .100YThe W .1 M . equation: CO
W W .C
PWM
OM frequency
W
for the output
WW 00Y.CO .Tf W
can be calculated
W WW 0 0Y. .TW
W 00 Y . T W . 1 M clk_I/O . 1 M
. 1 M W O W O
WW .100Y.C M.TW
W O f = -----------------
-
WW .100Y.C M.TW WW .10OCnPWM 0Y.C MN.T⋅ W 256
W W TheYN .C O
W WW 0factor Y .C(1,O
W W WW 00Y.CO .TW
W 00 variable .T represents theW prescale 0 8, 64,
. T 256, or 1024). .1 M
W The W Register 00 represents W
.Tspecial cases whenWgenerating .1
W 100 extreme
W.waveform O
values for the OCR0
M.Tin the fast PWM W W.1 If theYOCR0 C OMis set equal to BOTTOM, W
aM PWM
.COwill be
W W .C
00Y spikeMfor
output W
.Teach W mode. 0
10cycle.
.
M .T W W the Y
output
0
.10will result M .TW
a .1
narrow MAX+1 timer W
clock. O
Setting the OCR0 equal to W
MAX C O in a W
W
WW constantly 0
O
Y.Chigh or.low T Woutput (depending WW on 0 0 Y.C . T W WbyWthe COM01:0
.1 0 0Y. M .T
.1 0 M W . 1 the polarityO M of the output set W Cbits.)
O
W O C W . W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W .C O
14.7.4 Phase CorrectW PWMW Mode .CO .TW WW .100Y.C M.TW WW .100Y .TW
W The phase . 1 00YcorrectM PWM mode (WGM0[1:0] W = 1) provides O a high resolution phase W correct PWM
.C O M
WW 00generation O WW .1operation.
Wwaveform Y.C .T W The phase
option. WW correct . 1 0
PWM0Y.CmodeMis.Tbased W on a dual-slope 00Y M .TW
The
W Wcounter 0 0 Y.C repeatedly
counts
.T W from BOTTOM WW to.1MAX 0 0Y.C and then
M . W MAX toW
Tfrom BOTTOM. . 1 0In0Ynon- M.TW
.1 M mode, the Output CO is T WW match O
WW Compare
inverting
Y .CO Output
W W WW CompareY.(OC0)
0 0 .
cleared
W on theWcompare 1 0 0Y.C M.T
W 0 0 .T .1 set on the M . O
between TCNT0
W W.1 Yand .C
M while upcounting,
OOCR0
W W Wand
0 Y .CO .TW
compare match whileW
W
W
downcount-
0 0 Y.C
ing. W In inverting 00 Output .T
Compare mode, W
the operation .10 is inverted. The dual-slope operation .1 has
W.1 operation C OM frequency than single W W .C OM However, due to the WW
lower maximum
W W 0 Y . .T W W slope
0 0 Y
operation. .T W W symmet-
ric featureWof .10the OM PWM modes, W
dual-slope
C theseW.1 modes .C OMpreferred for motor control
are
W
applications.
W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
WThe.10 PWM resolution
.C OM for the phase W.1 PWM
Wcorrect Y
M
.COmode.TisW fixed to eight bits. In phase correct
W W 0 0 Y . T W W 1 0 0
W.1 Y.COM W
PWM mode the counter is incremented .
until the counter M value matches MAX. When the counter
W W W W
0 Y .CO T W
W .10 The TCNT0 . value will be equal to MAX for one
W reaches .100 .T
MAX, it changes the count direction.
O M.T W C OMThe timing diagram W W .C OM PWM mode is shown on Figure 14-7.
00Y
.C
.TW W W timer clock
1
.
cycle.
00Y valueMis.TinWthe timing diagram W for the
.
phase Y correct
100 as aOhistogram M .TW
. 1 M The .
TCNT0 W shown
W Y .CO .TW W WW 00Y.CO .TW WW .1and 0
.C
0Yinverted .T W for illustrating the dual-slope
0 0 operation. .1 The diagram includes non-inverted OM PWM outputs. The small horizontal
W.1 Y.COM W W W . C OM W W Y .C W
Wline marks onYthe TCNT0 W
slopes represent W compare 00 matches between .T OCR0 and TCNT0.
W .100 O M.T W .100 O M.T W W.1 Y.COM W
.C WW 14-7. .C
W
1 00Y M .TW Figure .
Y
100 PhaseOCorrect M .TW PWM Mode, W
TimingW
00
.1Diagram O M.T
. O W .C
W
W
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C M.TW OCn Interrupt Flag Set
W W .C O
W 00 Y .T W .1 M
W W 0 0 .T W .1
W 00 .T W.1 Y.COM W M OCRn Update
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 .T
OM TOVn Interrupt Flag Set
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T TCNTn W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TOCnW W
W . 100 O M .T W
W .100 M.T= 2)
(COMn1:0
O
W O WW .100Y. (COMn1:0 C
WW .100Y.C M.OCn TW WW .100Y.C M.TW M .=T3)W
W O W O
W
WW .100Y.C M.TW
O
W W .C O Period
W WW Y .CO 2 .TW 3W
WW 00Y.CO .TW
W 00 Y .T W 1
0 0 .1 M
W W 00 W
W
W .100 The O M.T W .1(TOV0) OsetM.Teach time the counter W
1
W.reaches .C OM
W Y .C Timer/Counter
W Overflow
W W Flag
0 Y . C is
T W W 0 0 Y BOTTOM.
.TW The
W 1 00InterruptMFlag .T can be used to generate . 1 0 an interrupt M . each time the counter W . 1 O M
. W O reaches the BOTTOM
W
WW .10value. 0Y.C M.TW
O
W W .C O
W Y
00phase correct W .1waveforms
In
W.1OC0Ypin. M.T PWM mode, the
OSetting W .1
compare unit allows
C OM generation of PWM WW OM
.CPWM
on the
W W 00
.C
.T W
the COM01:0 W W
bits to 2
1will
00 Y .
produce
M
a W
non-inverted
.T W
PWM. An 0 0
inverted
. 1
Y
M .TW
out-
. 1
Wput can beO M W . to 3O(see Table 14-5 on W W
W 86). The .C O
WW .100Y.C M.TW .TW
generated by setting the COM01:0 page
WW value 0 0 Y.C .T W .1 00Yactual OC0 M
.1 will only Mbe visible on the port pin
W if the data direction
O for the port pin isW set as output.
C O The
W Y.C
O W Y.C the.TOC0 W RegisterWatWthe compare Y. .TW
WW PWM . 1 00waveform M
W
is.Tgenerated byW clearing.1(or 00setting) M W .100 match O M
W .CO and.TTCNT0 WW .CO .TW
0Yincrements, and settingW (orWclearing) 00Y
.COC0 .TW
WWbetween 1 0 0 YOCR0 W when Wthe counter
. 1 0 M W . 1 the
OM
W.
Register C OM match betweenW
at .compare W andYTCNT0
OCR0 .CO when W the counterW
W decrements.
0 Y .CThe W
W
W PWM .frequency 1 00 Y for M
W W
.T output when usingW
the .
phase
0
10 correct O MPWM
T
. can be calculatedWby.1the follow- 0
O M.T
Wing WW equation: 0 Y.C
O
0
W W. 1
.C OM
W WW 00fYclk_I/O .CO .TW W WW 00Y.CO .TW
W 00 Y .T W
f OCnPCPWM.1= ------------------ M .1 M
W W.1 Y.COM W W W NY ⋅ 510
.C O
W W WW 00Y.CO .T
W .100 represents M.Tthe prescale factor
W
W.8, 100 .T
OorM1024). W.1 Y.COM
The N W
variable .C O W (1, 64, .
256,C W W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100
W values for O the OCR0 Register represent Y.C cases WW a PWM
WW .100Y.C M.TW
The extreme WW .100special M .TWwhen generating
waveform output W in the phase O correct PWM mode. W If the OCR0O is set equal to BOTTOM, the out-
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10will be continuously
OM .1 M
W Wput Y . C W
low and if set
W WW equal to MAX
0 Y .COthe output .
will be continuously high for non-
TWthe opposite logic values.
W .1 0
inverted 0 PWM .
mode.
M T For inverted PWM .
the1 0 output will M have
W
O M.T AtWthe.1 very start
.C OM of period 2 in Figure 14-7
W W.1OCnYhas M
.COa transition W
from high to low even though
Y .C W W W 0 Y T W W 0 0 .T
00
W.1 Y.COM W
.T there
W
is
.10 no Compare
O M. Match. The point
W
of
W
this
.1 transition
.C OM
is to guarantee symmetry around BOT-
WWTOM. There Yare C
. two cases Y Compare W Match:
1 00 M .T . 100 M .TW that give W a transition0without
W .1 0 O M.T
. W O .C
W .CO .TW WW • OCR0A 0changes
0 Y
.C its.value TW from MAX, WW Y
100 14-7.
like in Figure .TWthe OCR0A value is MAX the
When
. 1 00Y M . 1
W pin value O M W .
.C O M
WW 00Y.CO .TW WW
OCn
1 0 Y.Cis the same
0around .
as the resultW
TW the OCnWvalue at.1MAX
of a down-counting
00Ymust correspondM
Compare Match. To ensure
.TW to the result of an up-
W. 1 OM symmetry . M
BOTTOM W O
WW Compare .CO Match. WW .100Y.C M.TW
WW .100Y.C M.TW Wcounting . 1 00Y M .TW
W O W
Wtimer Y.C
O
WW than
W
0Yone .COin OCR0A, .TW and for that reason
WW .100Y.C M.TW •WThe
.
starts
10 0 counting.Tfrom
M
W a value higher
W . 1 0the
O M
W O W OMatch and hence the W C would
.that
WW .100Y.C M.TW
misses the Compare W OCn change have happened on the
WW .100Y.C M.TW . 1 00Y M .TW
way up. W O W O
W
WW .100Y.C M.TW
O
W W
14.8 .C O
Timer/Counter W Timing W W
Diagrams Y .CO .TW W WW 00Y.CO .TW
Y W 0
W
W .100
O M.T W .1 0
C W .TW
WW .100Y. M
The Timer/Counter
.TW clock enable W . 1
is
00Y a synchronous
M
design and W timer.10clock
the
W
0 (clkT0M
O
) is
.Ttherefore shown as a
W in the O
WW .100Y.C M.TW
W O signal following figures. The figures include information on when Interrupt
WW .100Y.C M.TWFlags are W
W
set. Figure . 1 0Y.Ccontains
014-8 M
W
.Ttiming data for basic
W O W CO to the
.close W WTimer/CounterY .CO operation. W
The figure
W Y.C W
shows the W
count Wsequence 0 Y T W MAX value Win all modes 0 0 other than .T
phase correct PWM
W
W .100 O M.T mode. W .10 O M. W W.1 Y.COM W
WW .100Y .C
W .100 O M.T
O W O .C
W
WW .100Y.C MFigure .TW 14-8. Timer/Counter WW .100YTiming .C .TW no Prescaling
Diagram, WW .100Y M.T
W
W O M W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T clk W .1 M .1 M
W W.1 Y.COM WI/O WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM clkW W W.1 Y.COM W WW 00Y.CO .TW
W W
W
W .100 O
.T Tn/1)
M(clk
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. Y W .100 .T
I/O
W W .100 M.T
W O M.T W C O W W .C OM
W
WW .100Y.C TCNTn .TW WW- 1 .100Y.
MAX M
MAX .TW W
BOTTOMW.10 BOTTOM
0Y M+.T
1
O M W O .C O
W
W O W O
W
WW .100Y.CTOVn
O
W W .C OM
W 00 Y .T W .1 M
W W 00 .T W
W 100
W.Figure O M.T W.1 Y.COM W W W.1 Y.COM W
.C W
W W
.1 00Y14-9 shows M .TW the same timing W data,.1but
W
00 with theM
O
prescaler
.T enabled.W
W .100 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 14-9. OMTimer/Counter Timing .1 M
W WFigure Y . C W W WW Diagram, with
0 Y .COPrescaler .
(f
TW clk_I/O
/8)
W .1 0 0 M .T . 1 0 M
W
O M.T W .1 clk
.C OM W W.1 Y.COM W
.C W W
Y W .100 .T
I/O
00Y .TW W .100 M.T OM
W.1 Y.COM W W Y. C O W W Y .C W
00 .T WW clk . 10Tn0 M .TW W .100 M.T
. 1 M W O W .C O
W .CO .TW WW (clk.I/O1/8) 00Y
.C .TW WW .100Y .TW
. 1 00Y M W O M W O M
W. 1 OM W O
W Y .C W W W W
TCNTn
0 Y .CO MAX .T
-1
W W W MAX
0 0 Y.C BOTTOM .TW
BOTTOM + 1
W 00 .T . 1 0 M .1 O M
W.1 OM W O W
WW .100Y.C M.TW
W W .C O
W WW 00Y.CO .TW
TOVn W WW 00Y.CO .TW
W 00 Y .T W .1 M
W W 0 0 .T W .1
W
W .100 O M.T Figure 14-10W shows
W .100the setting .T
OMof OCF0 in all modes W
.1 CTC mode.
except
W M
.CO .TW
W Y .C W W W 0 Y .C T W W 0 0 Y
W 00 .T
W.1 Y.COM WFigure 14-10.WTimer/Counter
0
W.1 Y.COTiming M. Wof
1
W.OCF0, M
.COPrescaler
W W 00 .T W 10 0 M .T Diagram,
W Setting
W . 10 0 Ywith
M .TW (fclk_I/O/8)
W. 1 OM W . O W O
W O W O
W
WW .100Y.C M.TW
O clkI/O
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM WclkTn W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T
(clkI/O /8)
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O OCRn - 1 0Y.C WW OCRn + 100Y. C
WW .100Y.C M.TW
TCNTn WW 1 0 M TW
.OCRn . 1 M .TW
OCRn +2
W . O W O
W
WW .100Y.C M.TW
O
W O
W W Y .C O OCRn
W W WW 00Y.CO .TOCRn W Value WW
1 0 0 Y.C .TW
W . 1 00 M .T W . 1 O M W . O M
W
WW .100Y.C M.TW
O
W W .C OOCFn
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y TW
M.shows
W
W .100and theOclearing
M.T of TCNT0 in CTC
W .100
Wmode. OM
.T
W Figure 14-11 O the setting of OCF0 C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 14-11.
WFigure C OMTimer/Counter Timing W.1 YClear
WDiagram,
M
.CO Timer on Compare Match Mode, with Pres-
W W 0 0 Y . .
calerT W(f /8) W . 1 0 0 M .TW
.1 M WW 00Y.CO .TW
WW 00Y.CO .TW
clk_I/O
W W W
O M.T W .1
.C OM W W.1 Y.COM W
.C W W
00Y .TW W 00I/OY
.1clk M.T
W .100 OM
.T
00 .T WW .100Y. M .TW W .100
Y
M.T
. 1 M W O W .C O
W .CO .TW WW clk.1Tn00Y.C M.TW WW .100Y .TW
. 1 00Y M W /8) O W O M
WW 00Y.CO .TW WW I/O.100Y.C M.TW
(clk
WW .100Y.C M.TW
W W. 1
.COM
W W W
TCNTn Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W.1 Y.COM W W.1 Y.COMTOP -W
(CTC)
W
1
WW 00Y.CO .TW
TOP BOTTOM BOTTOM + 1
W W 00 .T W
W
.C W
WW .100Y M .TW W OCRnW.10
0
O M .T W
W .100
TOP OM
.T
W O C W .C
WW .100Y.C M.TW W W
100Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
OCFn W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00
14.9 Register Y .T
Description W .1 M
W W 00 .T W
W 100 – O
14.9.1 W.TCCR0 M.T
Timer/Counter ControlW W.1 Y.COM W
Register W W.1 Y.COM W
WW .100Y .C W W 00 .T
W O M.T
W
W .100 O M.T W W2.1 Y.C OM
WW .100Y .C .T0 W
WW .100Y.C M.TW W W 100 CS01 OMCS00
Bit 7 6 5 4 3 1
M .TCOM00 W .
W C O FOC0
WWR/W 00Y.C
WGM00 COM01O WGM01
W CS02
Y.C W TCCR0
W Y. W W .T W W .1 0 0 .T
W 00 .T
Read/Write W
.1 R/W
OM 0
R/W R/W R/W R/W MR/W
W W.1 Y.COM W
Initial Value 0 WW0 00Y.C 0 W 0 W W0W 000Y.CO 0 .TW
W 00 .T W . T .1 M
W W 0 .T W
W
W .100 • Bit
O M.7T– FOC0: Force Output W .10Compare
.C OM W W.1 Y.COM W
C W W
WW .100Y. The FOC0 Wbit is only W
M.Tcompatibility withWfuture
active when Y
.100the WGM00 M.Tbit specifies a non-PWM
W
W .100mode.OHowever, M.T for
W O W C O W .C W
WW .100Ywhen
ensuring
.C .TW in PWMWmode.WWhen Y.
devices, this bit
.TW
must be set W to zero when
00Y TCCR0 is written
M.T com-
M
operating .100 writing O M a logical one to the FOC0 W .1bit, an O
immediate
C
W O Y.C W . .TW to
WW .100pare Y.C match.TisW forced on the WW Waveform . 1 00Generation M
W The OC0W
.Tunit. outputW 00Y according
is.1changed M
M O O
W .CO .TW WW Y.C bit is.Timplemented W asW
W Y.C
00Therefore TW
WW .10its 0YCOM0[1:0] M
bits setting. W Note that the
. 10 0FOC0 M
a strobe.
W .1 O M it.is the
W O W O W .C
WW .100Y.C M.TW
value present in the COM0[1:0] bits that determines the effect of the forced compare.Y W
WW .100Y.C M.TW W
W .100 O M.T
W O .C
W A FOC0
WW .OCR0 .CO strobe will
.TW
not generate
WWany .interrupt, 00Y
.C nor will .TW
it clear theW W in CTC
timer
100
Ymode .TW
using
1 00Y as TOP. M W 1 O M W . O M
W
WW .100Y.C M.TW
O
W O W O
WW .100Y.C M.TW
W The FOC0 bit O is always read as zero.
W O
.CWGM0[1:0]: W W Y CO
.Mode W W WW 00Y.CO .TW
WW• Bit.16, 0 03Y– T W Waveform
M.the counting sequence
W Generation
.1 0 0 .T
W.1 Y(TOP) M
W
These bits O
control
C W W of the .C OM the source for theWmaximum
counter, .CO .TW
W Y . W W 0 Y .T W W 0 0
W counter 00
W.1 value,
.T
OMwhat type of Waveform
and
0
W.1Generation .C OM to be used. Modes of W W.1 Ysup-
operation M
.CO .TW
W Y .C W unit are: W
W Normal.10mode, 0 Y .T W W 0 0
Wported .by
W 100the Timer/Counter
O M.T W .C
Clear
OM Timer on Compare W W.1 (CTC)
Match
Y .C OM
W
.C W W
W W and0two
mode,
. 1 0Y typesM of T
.Pulse
W Width Modulation W
W . 00Y modes.
1(PWM) O M .TSee Table 14-2 W and “Modes
W .100 of OM.T
Operation” W on pageO78.
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .10014-2. OM
Table
W
.T
Waveform Generation Mode
W W.1 Bit Description
.CO .TW
M (1)
W W Y .C W W 0 0 Y
M.T
W
W .100 WGM01 .T
OM WGM00 Timer/Counter W.1 Mode OofM Update of TOV0 Flag
Y .C O
W W W .
Mode 0Y(CTC0) .TWC (PWM0) W W
Operation 0 0 Y.C .T
TOP W OCR0 Set-on
00 .T .10 M .1 OM
W.1 Y.COM W W C O W W .C 0xFFW Immediate
00 .T WW 0 .100Y. 0 M.TW0 W
Normal
.100
Y
M.T
MAX
. 1 M W O W .C O
W .CO .TW WW1 .100Y.0C M.TW 1 PWM, W Correct
WPhase 100
Y 0xFF .TW TOP BOTTOM
. 1 00Y M O W . O M
WW 00Y.CO .TW 2W 1 .C W .C .TWImmediate
WW . 1 0 0Y M .T0W CTC W . 1 00Y OCR0 M
MAX
. 1 O M W O W .C O
W
WW .100Y.C M.TW W3W .1001Y.C M.1TW Fast PWM WW .100Y 0xFFM.TW BOTTOM MAX
Note: W
1. The CTC0 Oand PWM0 bit definition names W are now O
obsolete. Use the WGM01:0 definitions.
W O
WW However, Y.Cthe functionality WWof these Y.Care compatible TW with previous versions of
WW .100Y.C M.TW .1 0 0 M .T W and location . 1 0 0bits M .
W W .C O
W WWthe timer. Y .CO .TW W WW 00Y.CO .TW
Y W 0
W 00 .T
W.1 Y.COM W • Bit 5:4W– W .10
.C OM W.1 Y.COM W
WMode
W W 0 Y W W .100 .T
W
W .100 O M.T
COM0[1:0]:
W .10 O M.T
Compare Match Output
W W .C OM
WW .C YIf one or both .TWof the COM01:0 bits
WW .100Y.C M.TW .TW pin (OC0)
These bits control the
. 00YOutputM
1output
Compare W behavior.
W .100 of O MI/O
are set, the OC0W O
overrides the normal port functionality C the pin it is connected to.
W O
WW .100Y.C M.TW However,Wnote that.1the
W .C
00YData Direction .T W WW .100Y. M .TW
W C O W W .C OM Register (DDR)
W
bit
W corresponding
Y .CO .TW
to the OC0 pin must be
W Y . Wset in orderWto enable Y
0 output M .T W W 0 0
W
W .100 O M.T W .10the O
driver.
W W.1 Y.COM W
C W . C W
WW .100Y. W
When OC0 W is connected
M.T bit setting. TableW14-3
Y pin, the
.100to the O M.T function of the COM01:0
W 00 bits depends
W.1 Y.COM W
.T on the WGM01:0
W O W .C W
WW .100Y.C M.TW .TW bit functionality
shows Y the COM01:0 when the WGM01:0 bits are set to a
W
W . 100 O M
W
W .100 O M.T
W O normal or CTC mode (non-PWM).
WW .100Y .C
WW .100Y.C MTable .TW 14-3. Compare WW .100Y.C M.TW M.T
W
W Output O
Mode, non-PWM Mode W O
W
WW .100Y.C M.TW
O
W W .C O COM01
W WW 00Y.CO .TW
COM00 Description
W WW 00Y.CO .TW
W 00 Y .T 0 W .1 Normal port M operation, OC0 disconnected. .1 M
W W.1 Y.COM W 0
W 00 .T W 1 M
W.1 Y.COM 0 W 1 W.1 Toggle OC0
W .C OMon compare match WW. Y .CO .TW
W W0 Y
0 OC0 on .T W W 0 0
W
W .100 O M.T1 W .10Clear
.C OM compare match W W.1 Y.COM W
C W W
WW .100Y. M1.T
W W1 00OC0
.1Set
Y on compare
M.T match
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
WW .100mode.
Table
Y.C
14-4
.T
shows
W
the
WW .100Y.C M.TW
COM01:0 bit functionality when the WGM01:0
WW .100Y bits are set to fast
M .TPWMW
M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW(1) WW .100Y.C M.TW
W W Table .C O
14-4. Compare OutputW
W
W Fast
Mode,
Y CO Mode
.PWM W W WW 00Y.CO .TW
W 00 Y .T COM00 W 0 0 .T .1 M
W.1 COM01 .C OM W.1 Y.COM W
Description
W WW 00Y.CO .TW
W W 0 W
W 00Y .T W .10operation, M.Tdisconnected. WW.1 .CO .TW
M
W W.1 Y0.COM W0 NormalW
W port
Y .C OOC0
W W 0 0 Y
W .100 0 OM.T 1
W
ReservedW.1
00 .T W.1 Y.COM W
W C W .C OM W
WW .1001Y. W W 00Y W W .100 .T
W O M.T 0 Clear OC0W on.1compareCmatch, O M.Tset OC0 at BOTTOM, W W .C OM
WW mode) Y. Y W
WW .100Y.C M.TW (nin-inverting
. 100 M .TW W
W .100 O M.T
O W O .C
W
WW .1100Y.C M.1TW Set OC0 WW on compare 00Y
.C
match, clear W at BOTTOM,
.TOC0 WW .100Y M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
(inverting mode)
WW .100Y.C M.TW
W TOP COCOM01 WW O
Note:
W W 1. A Y .C
special O case occurs when OCR0
W W Wequals 0 Y .and .T W is set. In thisWcase, the compare
0 0 Y.C .TW
W .1 0 is ignored,
0match M .T but the set or clear isWdone .10 at BOTTOM. O M See “Fast PWM Mode”W on.1page 79.COM
W O WW .100Y
WW .1for Y.C details..TW
00more WW .100Y.C M.TW M.T
W O M W O W W .C O
Y.C WW when .C WGM01:0 .TWbits are set Y
Ythe Wto phase .100
TableW
W 14-5 .shows 100
the COM0[1:0]
M .TW
bit functionality
. 100 M W
cor-
rect PWMW mode. O W O
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W
W .10014-5. OM
Table .T
Compare Output Mode, W
W
.1 Correct
Phase
.CO PWM
M Mode(1)
W Y .C W W 0 Y W
M .TW W
W .
COM01 100 COM00 O M .T Description W .10 O M.T
.CO .TW WW OC0 Y. C
00Y WW 0.100Y.C 0 M.TW Normal port operation, . 100disconnected. M .TW
. 1 M W O W O
W
0 Y.C
O
.T W WW 0 .100Y.C1 M.TReserved W WW .100Y.C M.TW
0
W. 1
.C OM
Y W 1 .10 0 1 when up-counting.
.100 M.T W
0
OMwhen downcounting. WW.
Clear OC0 on compare match
.CO .TW
M Set OC0 on compare match
WW 00Y.CO .TW W W 00 Y .C
.T W W 10 0 Y
W .1 O M W.1 1Y.COM W W.when .C OM Clear OC0 on compare match
.C W
1 Set OC0 W on compare
.Tdowncounting.W W.100
match Y
up-counting. W
WW .100Y M .TW W
W . 100 O M
when O M.T
W O
WW1. A.1special .C occurs W Y.C .isTW
WW .100Y.C M.TW Note: 00Y case M .TWwhen OCR0WequalsWTOP . 100and COM01 O M set. In this case, the compare
W O W Wmatch isYignored, .C O but the set or clear is W done at TOP. Y .C
See “Phase W PWM Mode” on page
WW .100Y .C
.T W W 80 .for 1 0 0 details. M .T W W . 1 0 0 M .TCorrect
OM W more O W O
W
W W .C O
W
• Bit 2:0 –WCS02:0: W Y .COSelect
Clock W W WW 00Y.CO .TW
Y W 0 .T
W
W .10 0
O M.T The three Clock W .1 0
Select bits
C O M the clock sourceW
select to W be.1used by OM
.Cthe Timer/Counter.
W W 00 Y .C
.T W W W
10 0 Y .
M .T W W . 1 0 0 Y
M .TW
. 1 M Table 14-6. Clock . Select Bit
O Description W O
W O WW 0Y.C Description WW .100Y.C M.TW
WW .100Y.C M.TW CS02 WCS01 .10CS00 M .TW
W W .C O
W 00 Y .T W .1stopped). M
W.1 Y.COM W
0 0
W W.1 0 Y.CNo OM clock source (Timer/Counter
W WW 00Y.CO .TW
W W 00 clkI/OM/(No .T prescaling) W
W
W .100 O M.T 0 0
W.11 Y.C O W W.1 Y.COM W
.C W W
.T prescaler)W W.100 .T
WW .100Y M.T 0
W 1W .0100 clkI/O /8
M(From OM
W O W C O W .C
WW .100Y.C M.TW 0 1W
W 1 00Yclk /64 (From
1
.
I/O M.
TWprescaler) W .100
Y
M .TW
. O W O
W O WW0 00clk Y.C .TWprescaler) W W.100Y OM.TW
W .C
WW .100Y.C M.T1W 0 W . 1 I/O/256 M (From
W O
W
WW .100Y.C M1.TW
O
0 WW1 .10clk 0YI/O .C/1024 .T
(From Wprescaler) WW .100Y.C M.TW
M WWon falling CO
W O W
WW0 .1External .CO source Y.edge. W
WW .100Y.C M 1 .TW 1 00Y clock M .T W on T0 pin.WClock
W .1 0 0
O M.T
W O W .C O W Y. C W
WW .100Y.C 1M.TW 1 W1W .External 1 00Y clockM .TWon T0 pin. W
source Clock on rising.100edge. OM.T
W O W
W
WW .100YIf.Cexternal
O
.T W modes are WW 0
C
0Y.Timer/Counter0, .TW transitions WW .100Y.C M.TW
.1 M
W W .C OM pin used for
WW 00asY.an
the
CO W W WonWthe 0T0 0 Y .CO
pin will clock the
.TofWthe
W 00 Y
counter even.T Wif the pin is W configured . 1 output.
M .T This feature allows 1
software
. control
M
. 1 M W O W O
W
WW .10counting. 0Y.C M.TW
O
W W .C O
00
W – Timer/Counter Y .T W .1 M
14.9.2 TCNT0
W.1 Y.COM W
Register
W W 00 4 .T W .1
W 00 .T 5W.1 OM3 M
W W.1Bit Y.COM 7 W 6
W Y .C W
2
W
1
WW 000Y.CO .TW
W
W .100 O M.R/W T W
W .100 TCNT0[7:0] OR/WM.T W
1
W.R/W .C OM
TCNT0
W Read/Write
Y . C W R/W
W W
R/W R/W
0 Y . C T W R/W W
R/W
0 0 Y .TW
W 1 0
0Value M .T . 1 00 M . W .1 O M
. W O
WW .100Y.C M.TW
Initial 0 0 0 0 0 0 0
W
WWThe .Timer/Counter .CO .TW WW .100Y.C M.TW
1 00Y W .CO
W W .C OM Register gives direct WWaccess, Y .CbothO for read and write W
W W
operations,
0 Y to the
.TW
W Timer/Counter 0 0 Y unit .T
8-bitW counter. W
Writing to the
. 1 0 0
TCNT0 .
Register
M T blocks (removes) .
the1 0 compare M
. 1 M W O W O
WW on0the
Wmatch 0 CO
Y.following .T W clock. Modifying
timer WW the 0 Y.C (TCNT0)
0counter .
W
TW while theWcounter .is10running, 0Y.C M.TW
1 M . 1 M W O
W. a risk
introduces .C Omissing
of a compare match WWbetween Y
O
.CTCNT0 andW the OCR0W W
Register. 0 Y.C W
W W
.1 00 Y
M .T W W
W .10 0
O M .T
W .1 0
O M.T
WW Register .CO .TW WW .100Y.C M.TW WW .100Y.C M.T
14.9.3 OCR0 – Output W Compare 00Y
W W . 1
. C O M
W 00 7 Y .6T W .1
Bit
W.1 Y.COM W
5 4
W W.1 3 Y.CO2M W1 0
WWOCR0
W W 0 .T W
W 100R/W OR/W .10
OCR0[7:0]
Read/Write W. M.T R/W R/W WW R/W . C OM R/W
W 0 Y . C W0 W 0 0 Y R/W
.TW
R/W
Initial W 0 .T . 1 M
W.1 Y.COM W
Value 0 0 0 0 0 0 0
W W WW 00Y.CO
W 00 .T W.1
W W.1 Y.COM W W
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OutputOCompare M .1 OM that is continuously compared with the
W WThe Y .C W
Register contains
W WW an008-bit Y .Cvalue .TWan output compare interrupt, or to
W . 1
counter 00 value M .T
(TCNT0). A match can W be.1used to generate O M
W O W pin.00Y.C
.T W WW generate . 1 0 0Ya.Cwaveform M .TW output on the WOC0 .1 M.T
W
M W O W .C O
.CO WW .100Y .C .TW RegisterW W.100Y OM.TW
W
. 1 00Y 14.9.4M.TW TIMSK – Timer/Counter
W Interrupt O M Mask
W
0 Y.C
O
0
W. 1
.C OM
W
Bit W
W Y .CO 7
W 6 5
W WW4 00Y.3CO .2TW 1 0
0 0 Y .T W 1 0 0 . T . 1 M
.1 M W. OCIE2
OM TOIE2 TICIE1 OCIE1A
W OCIE1B
.CO R/W.TW R/W
TOIE1 OCIE0 TOIE0 TIMSK
WW 00Y.CO .TW W W
Read/Write
00 Y .C
R/W .TR/WW R/W W WR/W
.10 0 Y
R/W
M R/W
W .1 O M W.1 Y.0COM 0 W 0 W 0 W 0 .CO 0
Y .TW
Initial Value 0 0
.C W W 00
WW .100Y .T W W . 1 0 0 M .T .1 O M
W OM W .CO .TW OutputWCompare WW 0Match 0Y.C Interrupt .TWEnable
WW .100Y.C M.TW • Bit WW 1 – OCIE0:
. 1 0 0 YTimer/Counter0
M . 1 M
W O
W O WW .CisOwritten W Y.CStatus.TRegister W
WW .100Y.C M.TW
When Wthe OCIE00Y bit
. 1 0 M .TWto one, andWthe I-bit W . 1
in
00the
O M
is set (one), the
W O Timer/Counter0 W Compare .C O Match interrupt is enabled.
W The C
corresponding
. W interrupt is executed if
WW .100Y.C M.TW a compare WWmatch 0 0 YTimer/Counter0 .T W W . 1 0 0Y M .Tset
.1 in OM occurs, i.e., when the
WW 00Y.CO .TW
OCF0 bit is in the Timer/Counter
W W Y . CO
W Interrupt W WW
Flag Register 0 Y .–CTIFR. .T W W
W
W .10 0
O M.T W .1 0
.C OM W W.1 Y.COM W
C W W
WW .100Y. W
M.T • Bit 0 – TOIE0:
W .100
Y
Timer/Counter0 M.TOverflow Interrupt
W
W .100
Enable OM
.T
W O W C O W .C W
WW .100Y.C M.TWWhen the W
W Y. TW and the W 0Y Register
.10Status M.T is set (one), the
TOIE0 bit
W . 10is0 written O Mto .one, I-bit inW the
C O
W O .C W .
Y interrupt .TW
WW .100Y.C M.TW Timer/Counter0 WWOverflow . 1 00Yinterrupt M .isTW enabled. The Wcorresponding .100 M is executed if an
W O overflow in Timer/Counter0 W C O
occurs, i.e., when the TOV0 W W
bit is set in .C
the O Timer/Counter Interrupt
WW .100Y.C M.TFlag W W W
1 00Y
.
M .TW W . 100
Y
M .TW
Register – TIFR. W . O W O
W
WW .100Y.C M.TW
O
O W O
14.9.5 WW TIFR – Y .CO .TW InterruptWFlag
Timer/Counter WWRegister 0 0 Y.C .T W WW .100Y.C M.TW
W 0
0
W.1 Y.COMBit W W.1 Y.COM W WW Y1.C
O
W
7WW 3 W 0
W W
. 1 00 M .T W
6 00
. 1 5
O M .T 4 2
W .1 0
O M0.T
W O OCF2 W TOV2 .C W 0Y. C TOV0 W TIFR
WW .100Y.C Read/Write
ICF1 OCF1A OCF1B TOV1 OCF0
M .TW R/W
W R/W.100YR/W M .TW R/W W R/W W.10R/W
R/W O M.T
R/W
W O W C O W .C W
WW .100Y.C InitialMValue .TW 0 WW 0 Y. W 0 W0 .1000
Y
M.T
W . 100 0 OM0.T W C O
0
W
WW .100Y.C
O
W
.–TOCF0: WW 00FlagY.C .TW WW .100Y. M .TW
• Bit M1 Output Compare
W . 1 0O M W O
W .COOCF0 WWthe Timer/Counter0 .C
WW .100YThe .T W is set (one)
bit WW when a
. 1 0 0Y.C match
compare M .TW occurs between . 1 00Y W
M.Tand the
W O M W O W W .C O
Y.C in OCR0 WW Register0. .C OCF0 .TW 0Y executing .TWthe
WW .100data M .TW– Output Compare . 1 00Y M
is cleared byWhardware
W . 10when O M
W CO
corresponding interrupt handling Wvector. Y .C O
Alternatively, OCF0 is cleared W by writing .Ca logic one
WW .10the 0Y.flag. .T W WW OCIE0 1 0 0(Timer/Counter0 M .TW CompareWMatch Interrupt . 1 00Y Enable), M .TWto
OM When the I-bit in SREG, . W O and
W W Y .C W W WW 00Compare Y .CO Match .T W W W 0 0 Y.C .T W
W .1 00
OCF0 are set
M .T(one), the Timer/Counter0
W . 1 O M Interrupt is executed.
W .1 O M
W O WW .100Y. C
WW .•10Bit 0Y.C M.TW WW .100Y.C M.TW M .TW
O W O
W 0 – TOV0:
.CO .TW
Timer/Counter0 Overflow
WW 00Flag Y.C TW WW .100Y.C M.TW
WW The 0 0 YTOV0
bit is set (one) when W an overflow . 1 occurs in M .
Timer/Counter0. TOV0 W is cleared by
W W.1 Y.COM W WW interrupt Y
O
.Chandling W W W 0 Y .COhard-.TW
ware when executing the correspondingW .10 0 M. T vector. Alternatively, TOV0
.1 0 is cleared
W
W . 100 O M .T W C O W W OM
.CInter-
by writingYa.Clogic one W to the flag. When W the SREG Y . I-bit, TOIE0 W (Timer/Counter0 W Overflow0 Y W
W
W rupt .Enable),
1 00 M .T are set (one), W
W . 00
1Timer/Counter0 O M .T W
0
.1executed. O M.T
W and
.CO .mode,
TOV0 the
Y.C
Overflow interrupt W is .C In
WW phase.1correct00Y PWM TW this bit W
W
is set when . 100Timer/Counter0 M .TW changes W counting . 00Y at M.TW
1direction
M W O W O
WW 00Y.CO .TW
W$00. WW .100Y.C M.TW WW .100Y.C M.TW
W 00 .T W .1 M
W W 00 .T W
W
. C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
15. M .TW
Timer/Counter0 W
W 100 Timer/Counter1
and
. O M .T W
Prescalers W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Overview
1 0 CO
W. .C OM
W WW 00Y.Cand
Timer/Counter1
O Timer/Counter0 share
W W WW the same0 0 Y .prescaler W
.Tmodule, but the Timer/Counters
00 Y .T W . 1 M .T . 1 M
. 1 M W different O W O
.C applies
WW 00Y.CO .TW canW
W
have
1 0 0Y.C M.TW
prescaler settings. The W
W description . 1 00Y
below
M .TW
to both Timer/Counter1 and
W. 1 OM Timer/Counter0.
W . O W O
W O
W O
.CInternal WW 00Y.CO .TW WW .100Y.C M.TW
WW .15.2 0 0 Y .T WClock Source W .1 M
W 1 Y.COM W WW 00Ycan
The Timer/Counter .CObe clocked W directly by W WW
the system0Y .CO(by setting
clock W the CSn2:0 = 1). This
W W
.1 00 M .T provides
W
the W . 1
fastest O
operation,M .T
with a maximum W .1
Timer/Counter
0
O M.Tfrequency equal to system
clock
W O W Y. C
WW .100Y.C M.TW clock W
W
frequency.1(f0CLK_I/O 0Y.C ). Alternatively,
M .TW one W of fourW .
taps 100from the M .TW can be used as a
prescaler
O
W O W
WW The.1prescaled .CO clock WWof either 00Y
.C W
WW .100Y.C M.TW clock source. 00Y M .TW has a frequency
W . 1 O M T /64, fCLK_I/O/256, or
fCLK_I/O/8, f.CLK_I/O
W O C
W
WW .100Y.C M.TW
O fCLK_I/O/1024.
W O W O
WW Prescaler
W15.3 0 Y.C
O
.T
Reset W WW .100Y.C M.TW WW .100Y.C M.TW
0
W W. 1
. COM
W W W Y .CO i.e.,.Toperates W W WW 00Y.CO .TW
Y W 0
.100 .10 W.1 Y.COM W
W The prescaler is free running, independently of the clock select logic of the
W OM.T Timer/Counter, and W . C O M W
WW .100Y.C M.TW WW it is.10shared 0Y by M .TW
Timer/Counter1 and
W Timer/Counter0. 0
.10prescaler
Since
M .T the prescaler is
O not affected by the W
Timer/Counter’s O clock select, the state W
of the .C O will have implications
W
WW .100Y.C Mfor .TW WW a prescaled .C
00Y clockMis.Tused. W WW .100Y M .TWoccurs when
situations where
W . 1 O One example Wof prescaling Oartifacts
W
WW .100Y.C M
O the timer is enabledWand
.TW W clocked
0 0 Y.C by the .T W (6 > CSn2:0
prescaler WW > 1). .1 0 0Y.Cnumber
The M ofW
.T system clock
W . 1 O M W C O
W O Y.C W .
Y from 1 to W system
WW .100Y.C clock
cyclesWfrom when the
.T cycles, where WWtimer.1is 0enabled
0the M
to the
.TW
first countW occurs can0be
.10 M.T
N+1
M N equals
W O
prescaler divisor (8, 64, 256, W
or 1024). C O
W
WW .100Y.C M.TW
O
W O
W It is possible to use the W
O W
Prescaler Reset.COfor synchronizing the Timer/Counter
WWthat shares .Cto program
00Y the same Wexecu-
WW .100Y.Ction.MHowever, .TW care W must be taken . 1 00Yif the other M .TW Timer/Counter .1 O M .Tprescaler
W O WW 0reset O
Y.Cwill affect WW for0all .C
0YTimer/Counters .TW it is
WW .100Y.C also uses
M .T Wprescaling. AWprescaler
. 1 0 M .T W the prescaler Wperiod
W .1 O M
W O
W
WW .100Y.C M.TW
O
connected to.
W W .C O
Y W
15.4 External W .100 Source
Clock
W OM
.C W
W W
. 1 0Y external
0An M
W sourceWapplied.1to00the T1/T0
.Tclock W O M
W
T can be used as Timer/Counter
.pin W .100 O
T
M.clock
W C O W .C system W Y .C W
WW .1(clk 0 0Y T1./clkT0). The
M .TWT1/T0 pin isWsampled . 1 00Y everyM
once .TW clock cycle W by the .pin
W 100synchronization
O M.T
W O C
Y.Figure 15-1
W logic.YThe
WW .shows .COsynchronized (sampled)
.TWequivalentWblockW
W signal0is0Ythen .C passed through the edge
.TW synchronization WW detector. .100edge detector M.T
W
1 00 a functional M .1
diagram of O the M T1/T0 W and
.C O
W O .C of the WW W
WW logic. 0 0 Y.C registers
The .T W are clockedW
W
at the positive . 1 0 0Yedge M .TW internal system 00I/OY). The latch
clock .(1clk M.T
.1 M W O W C O
W
WW is transparent .CO in the .TW
high period of W internal
Wthe 00Y
.C clock.
system
.TW WW .100Y. .TW
. 1 00Y M . 1 O M W OM
W CO WT1W 0Y.C for M TW WW = 7) 0or0Y
.C W
WWThe .edge 1 0 0Y.detector M .generates
T W oneW clk /clkT00pulse
. 1
each. positive (CSn2:0
W . 1 OM.T
negative
O W O .C
W
(CSn2:0
WW .100Y.C M.TW
= 6) edge it detects.
WW .100Y.C M.TW WW .100Y M.TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
. C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 15-1. 1 M
W WFigure .C OMT1/T0 Pin SamplingWW. Y.CO .TW
W 00 Y .T W W 0 0
W
M .TW W
W . 10Tn0 O M .T W
W .100 O M.T
O WW .100Y. C
WW .100Y.C M.TW
D Q D Q D Q Tn_sync
0 0 Y.C .T W M .TW (To Clock
W.1 Y.COM W W C O W W .C O Select Logic)

W Y . LE W W 0 0 Y .T W
00 .T W 00 .T W.1 Y.COM W
W.1 Y.COM W W W.1 Y.COM W W
W clk 00
M.T
W 00 .T
W .100 O M.T W .1 I/O
.C O W W.1 Y.COM W
W 00Y
Synchronization W .100 M.T Edge Detector
. 1 O M W O W .C O
W
W
O W O W .C O
W
WW .100Y.C M.TW
TheW W
synchronization
0 0Y.Cand M edge
.TW detector logic WW introduces
. 1 00aYdelay of M .TW
2.5 to 3.5 system clock cycles
. 1
W has beenOapplied to the T1/T0 pin W O
WW .100Y.C M.TW
W O from an edge to the counter is updated.
Wdisabling O W when O
W O
WW .100Y.C M.TW one system
EnablingW and
W clock 0 0 Y.Cof the clock .T W input mustWbe Wdone
. 1 0 0Y.CT1/T0Mhas .TW been stable for at least
.1 cycle, otherwise M it is a risk that aWfalse W Timer/Counter O clock pulse is generated.
W W Y .C O
W W WW 00Y.CO .TW W 1 0 0 Y.C .TW
W .1 0 0 M .T Each half period . 1of the external M clock applied must Wbe . longer than O M one system clock cycle to
W Y . W W 0 Y
0 The external .T W W 1 0 0 .T
W . 1 00 M .T ensure correct sampling. W . 1 O M clock must be guaranteed
W . to have
.C O M less than half the sys-
W O WW duty.1cycle.
WW .100Y.C M.TWtem clock frequency WW .1(f0ExtClk 0Y.C< fclk_I/O M TW
./2) given a 50/50% 00Y SinceMthe .TW edge detector uses
O sampling, the W
maximum O
frequency of an external clock W it can .
detectC O is half the sampling fre-
W
WW .100Y.C M.TW WW sampling 0 0 Y.C .T W WW .100Y M .TW
quency (Nyquist W. 1 OM
theorem). However, due to variation of the system clock frequency
W W .C O W Y .C W W W W
0 Y .CO .TW
Y W duty cycleWcaused.1by00OscillatorMsource
and .T (crystal, resonator, .10and capacitors) tolerances, it is
W
W .100 O M.Trecommended thatWmaximum W . C O W Wsource Y . C OM
W /2.5.
.C frequency of W an external clock is less than f
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T clk_I/O
W
WW .100Y.C M
O An external clock source
.TW WW can Y.Cbe prescaled.
00not .TW WW .100Y.C M.TW
. 1 M
W W .C O
W WW 00Y.CO .TW W WW(1) 00Y.CO .TW
W 00 Y .T 15-2. Prescaler W
Figure W for.1Timer/Counter0 M and Timer/Counter1 .1 M
W 00 .T W 0 0 .1 M
W.1 Y.COClear M
clk
I/O
W W W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. PSR10 W
M.T
W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W O
WW .100Y.C MSynchronization
T0
W W .C O
W 00 Y T1
.T W .1 M
W.1 Y.COM Synchronization
W W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
WW .100Y.C M.TW WWclk .100Y.C M.TW WclkW .100Y M .TW
W O W O
WW .100Y.C M.TW
T1 T0
W O
Note:
W W 1. The .C O
synchronization W logic on the W Wpins (T1/T0)
input Y .COis shown W in Figure 15-1. W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M
W
15.5 .TRegister W
Description
W . 100 O M .T W
W .100 O M.T
.CO WW .100Y. C
00Y 15.5.1M.TW WW .100Y.C M.TW M .TW
. 1 SFIOR – Special W
Function IO O
Register W O
W
0 Y.C
O
0
W. 1
.C OM
W WW 00Y.C7 O .TW
Bit 6 5
W WW4 00Y.C3O .T2W 1 0
00 Y .T W . 1 ADTS2OM ADTS1 –.
1 ACMEOM PUD
. 1 M ADTS0 W PSR2 PSR10 SFIOR
WW 00Y.CO .TW W WW
Read/Write 00Y
.C .T W R/W W
W R 00YR/W
1
.C .TW R/W
W.1 Y
R/W
M R/W . M R/W R/W
W W.1 Y.COM W InitialWValue 0 .CO 0 W 0

W W0W 00Y0.CO 0.TW 0 0
W 00 .T W . 10 0 M .T .1 M
.1 M W O W C O
W
WW .100Y.C M.TW
O
• BitWW 0 – PSR10:
.C
00YPrescaler W Timer/Counter1
.TReset WW .10and 0Y.Timer/Counter0
M .TW
. 1 O M W O
W O WW 0Y.C to M WW and Y.C W
WW .100Y.C M.TW When Wthis bit is 0written
. 1
one,.TW the Timer/Counter1
W . 1 00Timer/Counter0
O M.T prescaler will be reset.
W O C
W
WW .100Y.C M.TW have no
O The bit will
WW
be cleared.C by hardware
.TW
00Ythat Timer/Counter1 WW .is10performed.
after the operation
0Y. M
Writing
.TW a zero to this bit will
effect. . 1
Note M and W
Timer/Counter0 O
share the same prescaler and a
W W Y .C O
W W
W
Wprescaler 0 Y.CO .T W W W 00 Y.Cbe read.TasWzero.
W 0 0 .T reset of this .1 0 will affectM both timers. This bit will . 1
always M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
O W O W .C O
W
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M .1 M
W 00 .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
16-bit W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Features
0
W. 1
.COM
W •W True W 16-bit Y .CO (i.e.,.TAllows
Design W 16-bit W PWM) WW 00Y.CO .TW
Y W .10 0 M Compare Units WW.1
.100 M.T • TwoW Independent OOutput .CO .TW
M
WW 00Y.CO .TW W
100
•WDouble .Buffered Y .C W
.TCompare Registers W.10 W 0 Y
W .1 O M W C
Output
OM W .C OM
.C W . W Y W
WW .100Y M .TW •W One Input Capture
W . 1 00Y UnitM.T
O
W
W .100 O M.T
W
WW .100Y.C M.TW
O • Input
WW .1on
Capture Noise
Y.C Canceler
00Compare .TW (Auto Reload) WW .100Y.C M.TW
• Clear Timer M Match
WW 00Y.CO .TW
W W Y.C O
W W WW Phase 0 Y .CO Pulse .T W W
W .100 M.T
• Glitch-free, .10 Correct M Width Modulator .1
(PWM) M
W W . CO • Variable W W
PWM Period Y .C O
W W W W
0 Y .CO .TW
W 00 Y .T W W .10 0 .T .1 0 M
W.1 Y.COM W • Frequency W W
Generator .C OM WW 00Y.CO .TW
W Y W W
W
W .100 O M.T • External W Event Counter
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W • Four Independent
W 00Y Sources
.1Interrupt M.T (TOV1, OCF1A, W
W OCF1B,
W
0 ICF1) M.T
.10and O
W O W C O Y.C W
WW .100Y.C M.TW WW .100Y. M .T W W . 10 0 M.T
16.2W Overview O W O W .C O
The 16-bit Timer/Counter W unit O
allows accurate program W
execution O
timing (event management),
W O
WWand .signal C
Y.timing WWregister Y.C TW in this sec-
WW .100Y.C M.Twave W generation, 0 0 .T W . 1 0 0and M .
W 1 Y.COM W
measurement. Most bit
O references
W .C O tion are written inWgeneral W WWthe Timer/Counter
0 Y.C W
W W
. 1 00 Y
M .T W W
W . 10 form.
0 A
O
lower
M .T case "n" replaces
W .1 0
O M.T number, and a
W O lower case "x" replaces WW C register
Y.the
W the 0output 0Y.C M.TW
compare unit. However, when using or bit defines
WW .100Y.C M .T W Wprecise 1 .100 Timer/Counter1M .TW
in a program, the .form must be used i.e., TCNT1 for W
accessing O counter
W W Y .C O
W W WW 00Y.CO .TW W W 0 0 Y.C .TW
W 00 value .T and so on. .1 M .1 M
W 00 AM .T
simplified W
block diagram of.1the 16-bit Timer/Counter is shownW in.1Figure 16-1. MFor the actual
W.1 Y.CO W W .C OM W Y.CO including W I/O
W placement
.TW of I/O pins, refer to FigureY 1-1 on page W 2. CPU W
accessible I/O
.10 0
Registers, M.T
W . 1 00 M
W
W . 100 O M .T W C O
W O and I/O pins, are shown
bits
WW on .page
in bold.Y .C device-specific I/O Register
The WW and Y.locations.Tare
bit Wlisted
WW .100Y.C in the M .TW Description”
“Register 1 00 112. M.TW W .100 O M
W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W W . C O W
WW .100Y.C M.TW W .100
Y
M.T
W W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 16-1.
WFigure .C OM16-bit Timer/CounterWBlock W.1 Diagram Y
M
.CO(1) .TW
W W 00 Y .T W W 0 0
W.1 Y.COM W W
Count W.1 Y.COM W TOVn
W W 0
M .TW W
W . 100 O M .T Clear
W .10Logic O M.T (Int.Req.)
C O W .C W Control
Y .C W
1 00Y
.
M .TW W . 1 00Y M .TW W
Direction
W . 100 clk
Tn
O M .T Clock Select
. W O
W
0 Y.C
O
.T W WW .100Y.C M.TW WW .100Y.C M.TW Detector Edge
Tn
. 1 0 M W O W . C O
W .CO .TW WW .100Y.C M.TW WWTOP .BOTTOM 100
Y .TW
. 1 00Y M W O W O M
WW 00Y.CO .TW WW .100Y.C Timer/Counter .TW WW .100Y.C M.TW ( From Prescaler )
W. 1 OM W M
OTCNTn W .C O
WW .100Y.C M.TW WW .100Y.C M.TW WW = .1 0=0Y 0 M.T
W
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C MOCnA .TW
W O W O (Int.Req.)
W
WW .100Y.C M.TW
O
WW .100Y.C = M.TW WW .100Y.C MWaveform .TW
W O W C O W W .C O Generation
OCnA
W Y . C W W W 0 Y . .T W W 0 0 Y .T W
W 00 .T 0
W.1 OCRnA OM .1 M
W W.1 Y.COM W W Y .C W W WW 00Y.CO .TW
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COCnB OM
W Y .C W W W 0 Y . C T W W
Fixed
0 0 .TW
W 1 00 M .T . 1 0 M . TOP
W . 1 (Int.Req.)
O M
. O W O .CWaveform .TW
DATABUS
W Values W
WW .100Y.C M.TW WW .10=0Y.C M.TW W 1 00Y Generation
W O W C O W W .
. C OM OCnB
C W . W Y W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW WW .100Y OCRnB
M .TW W .100 .T( From Analog
MComparator
W O W O W W . C O Ouput )
W Y.C W W W 0 Y .C .T W ICFn (Int.Req.)
W 0 0 Y .T W
W 00 .T 0
W.1 Y.COM W .1 M
W W.1 Y.COM W W EdgeW WW 00Noise Y .CO .TW
W .100 M.T
W ICRn
00 .T W.1 Canceler OM
W.1 Y.COM W
Detector
W O W .C
W Y .TW
ICPn
WW .100Y .C T W W 0 0 .T W 1 0 0
. . 1 M W . O M
W OM WW 00Y.CO .TCCRnB WW .100Y.C M.TW
WW .100Y.C M.TW WTCCRnA T W
W.1 OM W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 Note:OM1..TRefer to Figure 1-1W
W
onW .1002, TableO12-6
page M.Ton page 59, and Table W W .1
12-12 onYpage
M
.CO64 for.TW
W Y .C W W 0 Y .C T W W 0 0
W 00 .T 0 and description. . .1 M
W.1 Y.COM W
Timer/Counter1 pin placement
W 0 M.T
W 00 .T W.1 Y.COM W
16.2.1 RegistersW.10
.C O W W.1 Y.COM W W
WW .1The 00YTimer/Counter W
M.T (TCNT1), Output
W
W 100
.Compare M.T (OCR1A/B), and
Registers
O
W
W .100Capture
Input OM
.T
Regis-
W O C W .C
WW .ter Y.C are all
00(ICR1) .TW 16-bit registers. W
W Special 1 0Y .
0procedures M TW be followed
.must W when .accessing100
Y the
M .TW
16-
1 M . O W O
Wbit registers. O
Y.C These Wprocedures WareWW described
0Y.Cin theMsection TW “Accessing WW16-bit 0Y.C Mon
0Registers” .TW
WW page .1 0 0 M .T . 1 0 . W .1 O
94. The Timer/Counter Control W
Registers O
(TCCR1A/B) are 8-bit registers and have .Cno CPU
W
WW access .CO .TInterrupt W WW (abbreviated .C
00Y to Int.Req. .TW in the figure) WW 10are 0Yall .TW
. 1 00Y restrictions. M requests . 1 O M signals
W . O M
visible
W O WW All00interrupts Y.C W with Y.CTimer .TW
WWin the.10Timer 0Y.CInterrupt .T W
Flag Register W(TIFR). . 1 M
are
.TW individually W masked . 1 00the M
W
Interrupt Mask O M
Register (TIMSK). TIFRW andW TIMSKY.are COnot shown in the figure W W theseY.regis-
since CO
W
W ters are 0 Y
0shared
.C W
.T timer units. W 1 0 0 M .T W W . 1 0 0 M .TW
. 1 by Mother W . O W O
WTheWW 00Y.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W. 1
Timer/Counter
.C
M be clocked internally,
Ocan WWvia the Y .CO .or
prescaler,
W
by an external W
W
W source
clock
0 CO
Y.on W
W W
the T1 pin. . 1 0The Y
0 ClockM W
.T logic block controls
Select W
W . 0
0 clock M
1which O
T
source and edge the Timer/Counter W .1 0
O M.T
W .CO .TW its value. WWThe Timer/Counter .C W Wclock source Y.C
WWto increment
uses
. 1 00Y (or decrement) M .1 00Y M
is.Tinactive whenW no
W . 100 O M.T
W O W O W .C
WW .100Y.C M.TW
is selected. The output from the clock select logic is referred to as the timer clock (clk
W T1 .100Y ).
WW .100Y.C M.TW
The double WW buffered O Compare Registers
.COutput W
W
W (OCR1A/B) O
Y.Care compared W with theWTimer/Coun- WW
W 0 Y .T W 0 0
.1 usedOby .T
ter value at Wall .10time. The OM result of the compare W
W can be .C
Mthe Waveform Generator to
W
W a PWM 0 Y .C W W 0 0 Y .TW
generate .1 0or variable M .T
frequency output on the .Output
W 1 Compare
O M pin (OC1A/B). See “Out-
W W .C O W Y .C
W 00 Y .T W W 0 0
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10Compare 1
W.compare OM event will also set the Compare Match
W Wput .C OM Units” on page 100.W The
Y .Cmatch W
W 0 Y
0(OCF1A/B) W
.T can be used to W W . 1 0 0 M .Tcompare
Flag
W . 1 O M which generate an output
O interrupt request.
W Y .C W W W 0 Y .C .T W
W W The.1Input 00 Capture .T .10Timer/Counter
O M.T W W .C OM Register can capture W Wthe
Y .C OM value at a given external (edge trig-
W
.C 0Y on either .TWthe Input Capture W 0 on.Tthe Analog Comparator pins (See
. 1 00Y M .TW W gered) . 1 0event
W Comparator” O M W
Pin
. 10(ICP1) orM
O
W O WInput Capture .C
0 0 Y.C .T W WW “Analog
. 10 0Y.C M.on TW page 205.) W The
.1 00Y unitMincludes .TW a digital filtering unit (Noise
. 1 M W
Canceler) for O
reducing the chance of capturing W noise C O
spikes.
.
. 1 00Y M W value, O W O M
can.Cin some modes
WW 00Y.CO .TW TheWTOP
W either .the 1 0 Y.C
0OCR1A
or maximum Timer/Counter
.TW the ICR1 WW value, . 1 00Yor by aMset .TW
of operation be defined
W. 1 OM by MRegister, Register,
W O of fixed values. When using
W Y .C W W
OCR1A WWas TOP 0 Y .CO in a.TPWM
value W mode, Wthe
W
OCR1A 0 0 Y.C can.Tnot
Register W be used for generating a
W 00
W.1 Y.COM W
.T 0
W.1 However, .C OMthe TOP value will W W.1caseYbe .CO
M
W
W PWM W W
output.
0 0 Y .T W W in this
1 0 0 double .Tbuffered allowing the TOP
W .1 00 M .T value to beWchanged.C. 1 in O M
run time. If a fixed TOPW W .
value is required, O M
.C the ICR1 Register can be used
W O
WW .100Y.C M.TW
W
as anWalternative, . 1
Y
00freeing the
M TW to be used
.OCR1A W as PWM . 1 00Youtput. M.TW
W O W O
W
WW .100Y.C M.TW
O
W W
16.2.2 O
Definitions
.C W WW 00Y.CO .TW W WW 00Y.CO .TW
Y W
W
W .10 0
O M.T The following definitionsW .1
.are
C
M extensively throughout
Oused W W.1the document:
Y .CO .TW
M
W Y .C W W W 0 Y .T W W 0 0
W 00 .T 0
W.1 Y.COM W .1 M
W W.1 Y.COM WTable 16-1. WDefinitions W WW 00Y.CO .TW
W
W .100 O M.T BOTTOM
W
W .100 reaches .T
OMthe BOTTOM when itW W.1 0x0000. .CO .TW
M
W Y .C W W W The counter
0 Y . C T W W becomes
0 0 Y
W 00 .T .10 . .1 M
W.1 Y.COM W W W .C OM WW 0xFFFF Y .CO W
W W 0 .T MAX W The counter
0 0 Y
reaches its
.T W
MAXimum when W
it becomes
. 1 0 0 (decimal
M .T65535).
1 0 . 1 M W O
W. OM W O
WWequal.1to00the C
Y.highest
WW .100Y.C M.TW W TheWcounter
. 1 0Y.C theMTOP
0reaches .TW when it becomes .TWin the count
Mvalue
O W O W O
.C values:
W
WW .100Y.C MTOP .TW
sequence.
WW or .0x03FF,
The TOP .Cvalue can
00Y or to the .T Wbe assigned to be
WWone of.1or theY fixed
00ICR1 Register.M .T0x00FF,
W
0x01FF,
W 1 M value stored in the OCR1A
O mode of operation. W W O The assign-
W W Y .C O
W mentW Wis dependent 0 Y .Cthe
of .T W W 0 0 Y.C .T W
W . 1 00 M .T W . 10 O M W .1 O M
W O WW .100Y. C
W O
16.2.3 Compatibility
W O W
WW has.1been .CO .TW WW .100Y.C M.TW
WW .100Y.CTheM .TWTimer/Counter 00Yupdated M
W W . C O 16-bit
WW Y
and improved
.CO .TWis fully compatible
from previous
W WW 00versions .CO of.T
Ythe
the 16-bit
W
W 00 Y AVR .T W
Timer/Counter. W
This 16-bit
. 10 0
Timer/Counter M .1with earlier
M version
WW .100Y. Y W
WW .100Y.C M.TW
regarding:
M .TW W
W .100 O M.T
O W O .C
W
WW .100Y•.CAll 16-bit .TW
Timer/Counter WW 0 Y
related I/O0Register.C .TW locations,
address WW 1 0
including0Timer
.
Y Interrupt
M .TW
M W . 1 O M W O
W
WW .100Y CO
.Registers. . T W WW .100Y.C M.TW WW .100Y.C M.TW
W .C OM inside all 16-bitW
• Bit locations W
Timer/Counter
Y .CORegisters, W
including Timer
W WWInterrupt 0 CO
Y.Registers. W
W W
.1
Y
0•0 InterruptMVectors. .T W W
W . 10 0
O M .T
W .1 0
O M.T
W .CO .TW .C WW .100Y. C
WW .The 00Y bits haveW
W
1 00Y but have M
W
.Tsame M .TW
1 followingMcontrol changed W . name, O functionality and
W register location:
O
W
WW .•10PWM10 0Y.C is M
O
.TW to WGM10. WW .100Y.C M.TW WW .100Y.C M.TW
changed W O W O
W
WW • .PWM11 0
O
Y.C is changed .T W to WGM11. WW .100Y.C M.TW WW .100Y.C M.TW
0
W 1 Y.COM W WW 00Y.CO .TW W WW 00Y.CO .TW
WW • CTC1 .10 0 is changed
M. T to WGM12. W .1 W.1 Y.COM W
W C O W W .C OM W
WW Y. bits are.Tadded W to the 16-bit Y W W 0 .T
The following
W .100 O M
W Timer/Counter
W .100 O M.T Registers: WW.10
Control
.C OM
Y.CFOC1B.Tare W . C TW 00Y .TW
WW • FOC1A 1 0 0and W added toW TCCR1A..100Y M . W . 1 OM
W. M W O W
W•WWGM13 0 .CO to .TCCR1B.
isYadded T W WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 Y.COM has WWthat 0will CO theTcompatibility
Y.affect W WinW
W
0Y.C M.T
WW16-bit.1Timer/Counter
The
0 0 . T W improvements W .1 0 M . some .special
1 0
cases. W W . C OM
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Registers OM .1 M
16.3 Accessing W 16-bit Y .C W W WW 00Y.CO .TW
W 0 M.T
The
W .10TCNT1,
.C O OCR1A/B, and ICR1 are W W.1 registers
16-bit
Y
M
.CO that .can Wbe accessed by the AVR CPU via
W W W 0 0 Y .T W W 1 0 0 T
O M.T the
W
8-bit
.1 data
C
bus.
O M The 16-bit register must
W W. be byte
. OM using two read or write operations.
accessed
C
.C
.TW
W
W Each.116-bit .
00Y timer M has .TW a single 8-bitWregister 1for Y
00temporary TW of the high byte of the 16-bit
.storing
. 1 00Y M W TheY.same O temporary register W W . O M
W Y.C
O
W WW
access.
0 C theMlow .TW W is shared 0readY.C all.T16-bit
0between W registers within each 16-bit
1 0 0 .T timer. . 1 0
Accessing byte triggers the 16-bit.1 or O M
write operation. When the low byte of a
W. .C OM
W WWregister Y
O
.isCwritten W W WW 00Y.C .T W
Y W 16-bit 0 M. Tby the CPU, the high byte stored in the temporary register, and the low
W .100 O M.T W .10
.C O W W.1 Y.COM W
W 00Y
.C .TW WWwritten
byte
.
areYboth copied
100 is read M .TWinto the 16-bit W register .1of0in0the sameMclock .T cycle. When the low byte of
. 1 O M a 16-bit W register O by the CPU, the high W
byte the .C O
16-bit register is copied into the tempo-
W
WW .100Y.C M.TW WW 00the Y.Csame clock .TWcycle as the WW . 1 0is0Y M .TW
rary register . 1 in M low byte
W read. O
WW .100Y.C M.TW W
Not all 16-bit .1accessesO M the temporary register
uses Obyte. Reading the OCR1A/B 16-
W .C O WWdoes00not Y .Cinvolve .using W W WW for 0the 0
high
Y.C W
W W
.1 00 Y
M .T W bit W
registers
W . 1 O M T the temporary register.
W .1 O M.T
W O W .C WWbefore C
0Y.low byte. W
WW .100Y.C M.TW To do W a 16-bit write, . 1 00Ythe highMbyte .TWmust be written W . 10the O M .TFor a 16-bit read, the low
W C O W W .C O W Y .C W
W . W byte must be read Y
before the high W
byte. W 0 0 . T
W
W .100
Y
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C
WW .100Y. W The following
M.T interrupts updates
W code.1examples 00Y show .TW
Mregister.
how to access W the 16-bit
W .100Timer O M.T assuming that no
Registers
W O W the C
temporary O The same W principle can .Cbe used directly
W for accessing
WW .100Y.C M.TWthe OCR1A/B WW .100Y. M
W
.TNote W . 1 00Y M .T
and ICR1 Registers. that when WW 00Y.C
using “C”, the O
compiler handles the 16-bit
W W Y.C O
W W W W
0 Y .CO .TW W .T W
W . 1 00 M .T access. . 1 0 M W .1 O M
W O
W
WW .100Y.C M.TW
O
WWExample 00(1)Y
Assembly Code . 1 M
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W ; Set TCNT1
:.
W W 0 .T W
W .100 M.T ldi r17,0x01WW.10 W.1 Y.COM W
to 0x01FF
W C O .C OM W
WW .100Y . .TW W 00 Y .T W W .100 M.T
M W . 1 O M W C O
W
WW .100Y.C M.TW
O ldi r16,0xFF W
W 0Y.C M.TW WW .100Y. .TW
out TCNT1H,r17 W.10 O W OM
W
WW .100Y.C M.Tout
O
W TCNT1L,r16 WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O ; Read TCNT1 into
W WWr17:r16 Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 .1 M
W.1 Y.COMin W r16,TCNT1L WW .C OM WW 00Y.CO .TW
W Y W W
W
W .100 O M .T W
W .100 OM
.T
W W.1 Y.COM W
C in r17,TCNT1H
W .C W
WW .100Y. M.T
:.
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100C C
Y.Code .TW (1) WW .100Y M .TW W .100 M.T
W O Example
M W O W W .C O
W .C Y W
WW .100Y.C unsigned M .TWint i; W W.100Y OM.TW W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C:. M.TW WW .100Y.C M.TW M .TW
W O W O
W
WW .100Y/* .COSet TCNT1 .T W to 0x01FF WW*/ .100Y.C M.TW WW .100Y.C M.TW
M W O W O
W
WW .100Y .CO = 0x1FF;
TCNT1
W /* Read OMTCNT1 into i */ WW .CO .TW WW 00Y.CO .TW
WW .10i0Y=.CTCNT1; M. T W W .1 0 0 Y W
W.1 Y.COM W
W C O W W .C OM W
WW .1:. . W Y W W 00 .T
W
00Y
O M.T
W
Y.C“About Code W . C
W
WNote: 11.00See M .TW Examples”W on page 6. . 100
Y
M .TW W
W .100 O M.T
. O W O .C
W
Wassembly .C .TW returns the
W .C
00Y in theM .TW register pair. WW .100Y M.T
W
WThe
. 1 00Ycode example M
WTCNT1
W .1value O
r17:r16
W O
W CO W .C .TWoperations. WW Y.C
ItWisW important 1 00Y to. notice that .TWaccessingW 16-bit registers
.1 00Y are M atomic . 100
If anWinterrupt O M.T
W . O M W O
.C register, W Y.C
WW between
occurs
0 0Ythe .C two instructions
.TW WW .1the
accessing 00Y 16-bit
M .TW and theW . 00
interrupt 1code
. 1 M W O W
WW temporary
updates the .COregister by accessingW
.TW outside W
the same or.C
Y any other
00will WW Regis-
of the 16-bit Timer
.TW Therefore,
ters,W then the.1result 00Y of theMaccess the interrupt . 1 be M
corrupted. when both
W W Y .C O
W W WW 00Y.CO .TW
W 0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10main code OMand the interrupt code .1 OM
W Wthe Y .C W W WW update the.C
0 0 Y temporary
.TW
register, the main code must disable
W 00
the.1interrupts during
M .T the 16-bit access. . 1 M
W to.1do an atomic
O M.T W
The
W .1following O
.C
code M examples show how W W Y .CO read
M
W
of the TCNT1 Register contents.
Y .C W W 0 Y T W W 0 0 .T
00
W.1 Y.COM W
.T Reading
W .10 any of
O
the
M. OCR1A/B or ICR1 Registers
W W .1 can
.C
be
OM
done by using the same principle.
WWAssembly Y. C Y W
1 00 M .T . 100 CodeOExample M .TW(1) W
W .100 O M.T
. W .C
W .CO .TW WW TIM16_ReadTCNT1:
00Y
.C .TW WW .100Y .TW
. 1 00Y M W . 1 O M W O M
WW 00Y.CO .TW WW ; .Save 0
C
0Y.global .TW
interrupt flagWW .100Y.C M.TW
1 M
W W. 1
.C OM
W WW in r18,SREG Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 .1 M
W.1 Y.COM W W ;W Disable
.C OM
interrupts WW 00Y.CO .TW
W W cli .100 Y .T W W
W
.C W W
WW .100Y M .TW W ; Read.10TCNT1
W
0 Y into
O M T
.r17:r16 W
W .100 OM
.T
W O C W .C
WW .100Y.C M.TW
W
Win r16,TCNT1L 1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O in W
W
r17,TCNT1H
. 1 Ointerrupt flag W O
W O WW global
; Restore
Y.C WW .100Y.C M.TW
WW .100Y.C M.TW WSREG,r18 1 0 0 .T W
out
W. OM W O
W
WW .100Y.C M.TW
O
retWW 0 0 Y.C .T W WW .100Y.C M.TW
.1 M WW 00Y.CO .TW
W W Y .C O
W C Code W
Example WW (1)
0 Y .CO .TW W
W 00 .T
W.1 Y.COM W unsigned W
0
W W
. 1 00 M .T W int TIM16_ReadTCNT1(
W . 100 O M .T void ) W
W .100 O M.T
W O WW .100Y .C
WW .100Y.C M.TW
{
WW .100Y.C M.TW M.T
W
W O W O
W O
WW .100Y.C M.TW unsignedWint i;.100Y
unsigned char W sreg; .C .TW WW .100Y.C M.TW
M WW 00Y.CO .TW
W W Y .C O
W W WWinterrupt 0 Y .CO .TW W
W 00 .T /* Save global .10 flag
M */ .1 M
W 00 .T sreg = SREG; W .1 M
W.1 Y.COM /*WDisable interrupts W W.1 */ Y .C OM
W WW 00Y.CO .TW
W W
W
W .100 O M.T_CLI();
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M/* .TW Read TCNT1 into i.1*/
W 00Y M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M i .T=W TCNT1; WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
WW .100Y.C /* TW
.Restore global WWinterrupt .C
00Y flag M */.TW WW .100Y M .TW
M W . 1 O W O
W
WW .100Y.C return
OSREG = sreg;
W W .C OM
W
i;
W Y
00 } .T W .1 M
W W 00 6. M.T W
W 100 1. OSee
W.Note: M.T “About Code Examples”W on.1page
.C O W W.1 Y.COM W
.C W W
W W
The
.1 0Y
0assembly M code.TWexample returns W the.1TCNT1
W
Y
00 value
O M in
W
.Tthe r17:r16 register W .100
pair. O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
WThe .10 following
C OM code examples showWhow W.1to doYan .CO
M
atomic write of the TCNT1 Register contents.
W W
Writing 0 0 Y .
any of the .T W
OCR1A/B or W
ICR1 . 1
Registers 0 0 can be M .
doneTWby using the same principle.
.1 M WW 00Y.CO .TW
W W WW 00Y.CO .TW (1) W
O M.T W .1
Assembly
.
CodeMExample
C O W W.1 Y.COM W
.C W W
00Y .TW W 100
Y
.TIM16_WriteTCNT1: M.T
W .100 OM
.T
W.1 Y.COM W W C
Y. global
O W W Y .C W
00 .T WW .1;00Save M .TW interrupt W flag .100 M.T
. 1 M W O W .C O
W .CO .TW WW in 00Y
.C
r18,SREG
.TW WW .100Y .TW
. 1 00Y M W . 1 O M W O M
WW 00Y.CO .TW 0Y.C M.TW WW .100Y.C M.TW
; Disable interrupts
WW cli . 1 0
W W. 1
.COM
W WW Y . CO W W WW 00Y.CO .TW
W 00 Y .T W ; Set 0
10 TCNT1 OtoMr17:r16 .T .1 M
W.1 Y.COM W W W.TCNT1H,r17 Y .C W WW 00Y.CO .TW
W W
W .100 .T
out
W
W .100 O M.T WTCNT1L,r16 .C OM W W.1 Y.COM W
.C Wout W
WW .100Y M .TW W
W .
Y
100 global O M .T W
W .100 OM
.T
W O ; Restore C interrupt flag W .C
WW .100Y.C M.TW
W
Wout SREG,r18 100Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
ret WW .100Y.C M.TW
W O
W O WW (1)00Y.CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW C CodeW Example
. 1 M W O
W O WW 00Y.CO ( unsigned Wi W Y.C W
WW .100Y.C M.TW void W TIM16_WriteTCNT1
. 1 M .T W int )
W . 10 0
O M.T
O W O .C
W
WW .100Y.C M.TW
{ WW .100Y.C M.TW WW .100Y M .TW
W sreg; O W O
W O
WW .100Y.C M.TW unsigned
unsigned
WWint .1i;00Y.C M.TW
char
WW .100Y.C M.TW
W W .C O
W 00 Y .T W
/* Save global.1interruptM .1 M
W.1 Y.COM W sreg = SREG; W W .C O flag */ WW 00Y.CO .TW
W W 00 Y .T W W
W
W .100 O M.T /* Disable W W.1 Y.C OM W W.1 Y.COM W
.C W W .100 M.T
interrupts */
WW .100Y M .TW_CLI(); W W.100 M .T W O
O C
W
WW .100Y.C M.TW
O
WW i .1*/00Y.C M.TW WW .100Y. M .TW
/* Set TCNT1 to W O W O
W
WW .100Y.C M.TTCNT1
O
W = i; WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O /* Restore global
W WWinterrupt Y .COflag.T*/W W WW 00Y.CO .TW
W 00 Y .T W 10 0 .1 M
W W.1 Y.COMSREGW= sreg; WW. 0Y.COM W W WW 00Y.CO .TW
W .T
W
W .100 O }M.
T
W .10
.C OM W W.1 Y.COM W
C W W
WW .100Y. .TW W Y
.100on pageO6.M.T
W 00
W.1 Y.COM W
.T
W Note: OM 1. See “About Code Examples” W .C W
WW .10The 0Y.Cassembly .TW WW .10that 0Y the r17:r16 M .TW W 00 value toMbe.Twrit-
.1the
M code example requires W O register pair contains W O
W . C O W Y .C W W W 0 Y.C W
W W
.1 00
ten Y to TCNT1.
M .T W W
W . 10 0
O M .T
W .1 0
O M.T
WW 00Y.CO .TW WW .100Y. C
W WW .100Y.C M.TW M .TW
. 1 M
O Byte Register WW O W O
WW .100Y.C M.TW
16.3.1 Reusing the W Temporary High
WW If.writing 0 0 Y.Cto more.T W one 16-bitWregister.1where
than 0 0Y.C the M
high .T W
byte is the same for all registers written,
W W 1 Y.COM W W
Wwritten Y .CO W W WW 00Y.CO .TW
then the high byte only needs toW be
.10 0
once.
M.
However, T note that the same .1rule of atomic
W
W . 100 O M .T W C O W W .CO .TW
M
W operationYdescribed .C previously
W also W
applies in thisY . case. W W 0 0 Y
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
Y. C W Y .C W W 00 .T
16.4 Timer/Counter WWClock .100Sources M.T
W O W W . C O W
W Timer/Counter .C can.Tbe Wclocked byWan Y .TW W The clock .100sourceOM.T
WThe .1 00Y M internal
W . 100or an external O M clock source. W
W O WW(CS12:0) .C
Wis W selected
0 0 Y.the
by C ClockTW
. Select logicW W is controlled
which
.1 0 0Y.C M by.T theWClock Select . 1 00Ybits M.TW
.1 Timer/Counter M O W O
locatedWWin the .CO .TWControl Register WWB (TCCR1B). Y.C For details
W WWsources
on clock Y.C
0and
W
prescaler, .see 0 Y
10 “Timer/Counter0 M
W
and Timer/Counter1 W
0 0
.1 Prescalers” O
.T
M on page 88. W . 1 0
O M.T
W O W .C
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
16.5 Counter Unit W W WW 00Y.CO .TW
W 0 .T 16-bit Timer/Counter
The
W .10main part
.C Oof Mthe W W.1is theYprogrammable M
.CO .TW 16-bit bi-directional counter unit.
W W Y W W 0
M.T
W Figure
W .10016-2 shows OM
.aTblock diagram of the .10
Wcounter and Msurroundings.
Oits
O C W .C
00Y
.C
.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
. 1 M .
W 16-2. Counter O W O
WW .100Y.C M.TW
W O Figure Unit Block Diagram
W. 1
.C OM
W WW 00Y.CDATA O BUS (8-bit)
W W WW 00Y.CO .TW
Y W .T .1
.100 M.T W.1 Y.COM W WW 00Y.C(Int.Req.) OM
TOVn
WW 00Y.CO .TW W W
10 0 (8-bit) M.T W . 1 M .TW
W. 1 OM W . TEMP
O W O
WW .100Y.C M.TW WW .100Y.C M.TW WW .100Y.C M.TWClock Select
W O W Y.C TCNTnL
O CountWW
0Yclk .CO .TWEdge
WW .100Y.C M.TW WW TCNTnH .1 0 0
(8-bit)
M .T W(8-bit)
W
Clear . 1 0 M Detector
Tn
W O W O W W
Control Logic
Tn
.C O
WW .1TCNTn .C Y W
WW .100Y.C M.TW 00Y(16-bit Counter) .TW W .100 M.T
Direction
W O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y. M .( T WPrescaler )
From
O W O W BOTTOM .C
O
W
WW .100Y.C M.TW WW .100Y.C M.TW WW TOP
.100
Y
M.T
W
W O W C O
W O
WW .100Y.C M.TW Signal description WW .(internal .C
00Y signals): .TW WW .100Y. M .TW
W 1 O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C Increment .TW or decrement WW .100Y.C M.TW
Count M WTCNT1W by 1.CO
W W Y .C O
W W WW 00Y.CO .TW W 1 0 0Y. .TW
W . 1 0 0 M .T Direction . 1 SelectM between increment W
and . decrement. O M
WW 00Y.C O
W
WW .100Y.C M.TW Clear W
O
.TW WW .100Y.C M.TW
. 1 M W O
W .C O WW 00Y.Clear CO TCNT1 W
(set all bits to
W Wzero). 0 Y.C W
W W
. 1 00 Y
M
W
.T clk W
W . 1 O M .T
W .1 0
O M.T
WW .100Y.C M.TW
W O Timer/Counter clock.
WW .100Y.C M.TW
T1
WW .100Y.C M.TW
WW maximum O
W W Y .C O
W
TOP
W WW 00Signalize Y .CO that .T WTCNT1 has reached
W 0 0 Y.C value..TW
W 00 .T .1 M .1 OM
W W.1 Y.COM BOTTOM W WW 0Signalize 0 Y .CO that.TTCNT1 W has reachedW WWminimum 0 0 Y.Cvalue (zero)..TW
W 00 .T W .1 M . 1 M
. 1 M O W O
W O WW into Y.C8-bit I/O WW Counter .C
00YHigh (TCNT1H) TW con-
WW .100Y.Ctaining
The 16-bit Wcounter isW mapped 0two
.T . 1 0 M .Tmemory
W locations:
. 1 O M.the
M the upper eight bits W of the counter, O and Counter Low (TCNT1L)W C
containing lower 8
W
WW .100Y.C
O
.T W WW can.only 0 0Ybe .C .T W Wthe W
.1 0 0Y. the CPU M . W
Tdoes
bits. The TCNT1H Register 1 indirectly
OM accessed by CPU.
W When O an
W W . C OM to the TCNT1H I/OW W Y . C W W W 0 Y .C T W
W Y access
.100 The O M.T
W W location,
W .100
the CPU
OM
accesses
.T the high byte temporary 0
W.1TCNT1L
register
O M. (TEMP).
W C W . C
WW .100TCNT1H Y. C temporary
W
.Tupdated
register is
W updated
W
1
with . the
00YregisterMvalue
TCNT1H value
.TW when TCNT1L
when
W the
.
Y is
100 ThisOallows
read,
M .TW and
M is with the temporary
W . O W
is written. the
W O W16-bit .C W Y.C W
WW .10CPU 0Y.Cto read .Tor W write the W
entire .1 0 0
counterY value .T W
within one clockW cycle .1
via 0 0
the 8-bit M
data .Tbus.
W It isYimportantC OM to notice that there WW OM
.Ccases WW Register O
Y.C when.Tthe W
W W 0 . .T W W are special
0 0 Y .of
T W writing to theW TCNT1
.1 0 0 M
.1 0 M W . 1 O M W C O
W counter .CisOcounting that will giveW unpredictable .C results. The special cases
WW are.1described . in theW
WW .sections 00Y where .T W W .1 00Y M .TW 00Y M.T
W 1 O M they are of importance. W C O W W . C O
.C WW .100Y. W Y W
WW Depending.1 00Y onM the
W
.Tmode of operation used,
W the counter
O M .isTcleared, W
incremented, W .1or00decremented O M.T
W .CO .T(clk W .C
WW at each 00Ytimer clock W T1). The clk WTW 1 can be . 1 0Y.C M
0generated from .TW an external W or internal . 00Y source,
1clock M .TW
. 1 M
O Clock Select bits (CS12:0). W O W .C O
W
WWselected 0 by.Cthe
Y . T W WW .1When 0 0Y.Cno clock . W is selected
Tsource WW (CS12:0 . 1 00Y= 0) theM.TW
1 0 M .COof .TW
W W. is stopped.
timer . C OMHowever, the TCNT1
W WW value can.C
Y beOaccessed by the CPU,
W W WW independent
0 0 Y
Y W 0 T
M. priority over) allW
W whether
W.1 clkY
00 T1 is present
OM
.T or not. A CPU write 0
W.1overrides C O(has W.1 clear
counter
.CorOM
W
Wcount operations. 0 0 .C
.T W W W
1 0 0 Y .
M .T W W . 1 0 0 Y
M.TW
.1 M W . O W .C O
W
The WW counting 0 .CO .TisWdeterminedWby
Ysequence Wthe 0
setting0Y.Cof theMWaveform .TW WW Mode
Generation . 1 00Ybits M.TW
0 .1 O
W.1 Y.COinMthe Timer/Counter W Y.C A and
O WW 0Y.C M.T
WW .10located
(WGM13:0) 0 .T W WW Control Registers
.1 0 0 M .T WB (TCCR1AWand TCCR1B).
. 1 0
OM W O
There are
W W closeYconnections.C W
between how W
W
theWcounter
0 Y .CO .(counts)
behaves
T W and how
W Wwaveforms 0 0 Y.C
areWgenerated 00 the Output .T 0
W.1 ForYmore OM .1
W W.1 on Y .C OM Compare outputsWOC1x.
W 0 . C details about advanced W
W W W counting
sequences
W 0
and0waveform generation,
.T see W “Modes of.1Operation” 0 on.T page 103.
W.1 Y.COM W W W .C OM
W W
1 00 M .T W .100
Y
M .TW
W . O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Timer/Counter OM Overflow (TOV1) .1 OM
W WThe Y .C W W WW Flag is set.C
0 0 Y according
.
to the mode of operation selected by
TWinterrupt.
W 00
the.1WGM13:0 M .T
bits. TOV1 can be used for . 1
generating M
a CPU
W
O M.T W .1
.C O M W W.1 Y.COM W
C
. 16.6 .Input W
00Y TW Capture W Unit.100Y .TW
Mincorporates
W .100 O M.T
W.1 Y.COM W The W Timer/Counter
0Y. C O an Input W W
Capture
00Y
.
unitC that can
.TW capture external events and give
00 .T WW . 1 0 M .TW time ofW .1 M
W. 1 OM them a time-stamp indicating
WW 00Y.C
occurrence. The O
external signal indicating an event, or mul-
Y .C W W W W
0 Y .CO .TW W .T W
.100 M.T tiple events, 0 can be M
W.1 Y.Ccan
applied via the ICP1 pin or .1 alternatively, M via the Analog Comparator unit.
WW 00Y.CO .TW The W time-stamps
O then be used to calculate
W W WW frequency, 0 Y .COduty-cycle, .TW and other features of the
W . 1 0 0 M .T . 1 0 M
W. 1 OM signal W
applied. O
Alternatively the time-stampsW W O
used.Cfor creating
WW .100Y.C M.TW WW .100Y.C M.TW W can be .1 00Y M .TW
a log of the events.
W O The Input WWCapture COis illustrated
Y.unit W by the W WW
block diagram 0Yshown.CO in .Figure TW 16-3. The elements of
WW .100Y.C M.TW the
W block . 1
diagram 0 0 that M
are
.Tnot directly a part of W the. 1 0
Input O
Capture M unit are gray shaded. The
W W Y.C O
W W WinWregister 0 Y .CO .TW W W 0 0 Y.C number. .T W
W .1 00 M .T small “n”
W . 10 and bit
O M names indicates the .1
Timer/Counter
W O M
W O WW .100Y. C
W O Figure 16-3. WInput Capture O Unit Block Diagram W W .C O
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW DATA BUS WW (8-bit).100Y. M .TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W W W
TEMP (8-bit) Y.C
O
W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W W 00 .T W
W
.C W
WW .100Y M.T
W W
W .100 O M.T
W .100
W(8-bit)
.T
OM (8-bit)
W O C W .C
ICRnH (8-bit) . ICRnL
.TW
(8-bit)
M
WTCNTnH
.100
Y TCNTnL
M .TW
W O
W O W W(16-bit Register).CO .TW WWTCNTn.1(16-bit .C
00YCounter)M.TW
WW .100Y.C M.TW WRITE W 00Y
ICRn
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 ACIC* Y .C OM ICNC
W WW 00Y.CO .TW
W ACO* W ICES
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. W Analog W
M.T Comparator WW.10
0Y M.T
W 00
W.1 Y.COM W
.T
W O .C O W
WW .100Y.C M.TW Y Canceler .TW W 00ICFn (Int.Req.)
M.T
Noise Edge
W
W . 100 O M Detector W.1
C O
W O W .
WW .100Y.C M.TW
ICPn
WW .100Y.C M.TW W .100
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
O W O
W Ya.C
O WW Y.C on the TW WpinW (ICP1), Y.C
00alternatively W
WW When .1 0 0 change .of
M T W
the logic level W(an event)
W . 1 0 0occurs
O M . Input Capture
W .1 O M.T
W on the Analog .CO Comparator output W (ACO), andYthis .C change confirms toW Wsetting00ofYthe
the C
. edge.TW
WW detector, 00Y a capture W
.Twill W . 1 00capture isMtriggered, .TW the 16-bit .1of the counter M
W W . 1
.C O M be triggered. When
W W a
Y .C O
W W W W
value
0 Y .CO .TW
Y W Input Capture W Register .100 (ICR1). .T Input Capture FlagW(ICF1) .10 is setOatM
W (TCNT1) .100 is written Mto .Tthe W OM
The
WW
W
the same0system Y. C O clockW
.T as the TCNT1 W
W value .is 0 copied .
0Y intoC ICR1
.T W Register.W W 0Y.C = M.TW
If enabled10(TICIE1
.
.1 0 1 M O
1), W
W the Input .CO Flag
Capture M
W
generates anW W Capture
Input
Y .CO interrupt. W The ICF1 Flag
W WisWautomatically
0 0 Y.C .TW
Wcleared 0 0 Y .T W . 1 0 0 M .T . 1 M
W. 1when the interrupt
OM is executed. Alternatively
W the O ICF1 Flag can be cleared W by software O
WbyW writing a00 Y.C one to
logical .T W I/O bit location.
its WW .100Y.C M.TW WW .100Y.C M.TW
W.1 Y.COM W WWRegister O
Y.C(ICR1) .isTdone W by firstWreading WW 00Y.CO .T
WW the
Reading 0
16-bit value .Tin the Input W
Capture 0 0
W.the1 low OM
0
W.1 andY.then OM W.1 theYlow .C
M
Obyte W .C
byte W
W (ICR1L)
0 0 C the high
.T W byte (ICR1H). W W When
. 1 0 0 M
is
.T W
read the highW byte is 00Y
copied
. 1
.1 M W the CPU O WW it will
W WW byte
into the high
0 Y .CO .register
temporary
T W
(TEMP). W
W
When
0 0 Y.C reads.T theWICR1H I/OW location
access the TEMP 0
W.1 Register. OM .1 M
W Y . C W W WW 00Y.CO .TW
W 0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 ICR1 RegisterOM can only be written .1 M
W WThe Y .C W W WW when 0 Y .CO a Waveform
using
. T W Generation mode that utilizes
W 00 Register
the.1ICR1 .T for defining the counter’s . 1 0 TOP value.M In these cases the Waveform Genera-
W W .C OM W W Y .CO W
W W tion.1mode Y
00 (WGM1[3:0]) W W 0 0 T
. value can be written to the ICR1
M.T
bits must be set.1before the M TOP
O M.T W C Owriting W Wthe highYbyte .C Omust be written to the ICR1H I/O location
00Y
.C
.TW W WRegister.
1
When.
00Ylow byte M
Wthe
.Twritten
ICR1 Register
W . 100 M .TW
. 1 M before
W . the O is to ICR1L. W O
W
0 Y.C
O
1 0 O
W. .C OM
W WW information
For more
Y .CO on.Thow W
to access the
W WW 16-bit registers
0 0 Y.C refer .TW
to “Accessing 16-bit Registers”
00 Y .T Won page 1 0
94. 0 . 1 M
.1 M W. OM W O
W W.1 16.6.1 .C OM Input Capture Pin Source
W 00 Y .T W .1 M
W.1 Y.COM W The main W.1trigger C OM for the Input Capture
source WW 0unit .CisOthe Input Capture pin (ICP1).
W W 0 .T W W
Timer/Counter1 0 0 Y
can
.
alternatively.T W use the W Analog . 1 0
Comparator
Y
M .TWas trigger source for the
output
0
W.1 Y.COM W .1 M W CO source
WW unit. Y .COAnalog W W W 0 Y.trigger W
W W
.1 00 M .T Input W Capture
W . 1 0 0 The
O M .T Comparator is selected
W .1 0 as
O M.T by setting the Analog
W O Comparator Input Capture
Y.C (ACIC) bit in the Analog
WW Comparator Y. C Control
WW .100Y.C M.TW (ACSR). WW 1 00that M .TWtrigger source . 100 a capture. M .TW and Status Register
Be aware . changing can W trigger O The Input Capture Flag
W W Y . CO
W W WWbe cleared 0 Y .COafter the .T W W W 0 0 Y.C .T W
W .1 00 M .T must therefore . 1 0 M change.
W . 1 O M
W O W .C O W Y. C
WW .100Y.C M.TW Both the W
W
Input Capture 1 00Ypin (ICP1) M .T W the Analog
and WComparator . 100 outputO(ACO) M .TWinputs are sampled
. W
W O
WW technique
W .CO the.TT1 W on page .C
00Y 89). The W
WW .100Y.C M.TWusing the same . 1 00Y as forM W pin (Figure W15-1
W . 1 O M.Tedge detector is also
O W O . C
W
WW .100Y.C M.TW
identical. However,
W W when
0 0 Y.C
the noise
.
canceler
T W is
WW .100Y
enabled, additional logic
M
is
.Tinserted
W before the
edge detector, which 1
.increases O the Mdelay by four system W cycles. O
W O WW Y.C is always Wclock 0Y.C M.TW
Note that the input of the
WW .100Y.C M.Tnoise W cancelerWand edge 1 0 0
detector .T W enabledW unless the
. 1 0Timer/Counter is set in a wave-
W C O W W.that .C OM to define TOP. WW Y .C O
W
WW .100Y . form
.TW
generation mode uses
Y ICR1 W W .100 M.T
M
W
W . 100 O M .T W O
W O An Input Capture can
WW be triggered .C WW the .port Y.C ICP1.Tpin. W
WW .100Y.C M .TW . 1 00Y by software M .TW by controlling W 100of theO M
W O
16.6.2W Noise Canceler
W.1 OM WW 0noise O
Y.Cimmunity WW 00Y.CO .TW
WW .100Y.C The noise
.T W cancelerWimproves 0 .T Wby using aW simple .1
Wdigital filtering Mscheme. The
W .C O M
noise canceler input is W W.1 over
monitored Y . C OMsamples, and all four
four W W must be 0 Y .COfor changing
equal W the
W W 0 W .10 M.T
W . 1 00Y output M .T
that in turn is
W
used by W .
the 10edge O M
detector.
.T W C O
W
WW .100Y.C M.TW
O
W by setting O W O
.C (ICNC1)
W .COnoise
The
WW .100YTimer/Counter .T
canceler is enabled
W Control Register WW B.1(TCCR1B). 0 0Y.C M
the Input
.
Capture Noise
TWenabled the WW Canceler . 1 00Y introduces M .TW
bit in
OM When
WW 00Y.C
noise canceler O addi-
W W Y .C W W WW 0 Y .COa change T W W .T W
W
W .100ICR1 O
tional four
M.T
system clock cycles of
W .10
delay from
O M. applied to the
W W.1 Y.COM W
input, to the update of the
W .C
WW .100Y.C Register. M .TW
The noise W canceler
.
uses
100
Ythe system
M .TW clock and isW therefore not
W .100
affected by
O M.T
the
W prescaler. O W O W .C
Y
M.T
W
W O W C O
W Capture
WInput .CO .TW WW .100Y.C M.TW WW .100Y. .TW
16.6.3 Using W the
. 1 00Y Unit M O W O M
WThe main O WW 0Y.C unit WW processor .C
00Y capacity .TW
0Y.C the
challenge Wwhen using
WW for.10handling .T Wthe Input Capture
. 1 0 M .TisW to assign enough
.1 M
M incoming events. The W time between O two events is critical. If Wthe processor C O has
W
WW not.1read .CO .TWvalue in the W .C
00Y before TWnext event W
W 0Y. will M
10ICR1 be.
TW
00Ythe captured M
WICR1 . 1
Register
O M .the occurs,Wthe . O
W Y.C
O WWthe 0result 0Y.Cof the TW will be W
W 00Y
.C W
WWoverwritten
.1 0 0 with a new
M .T Wvalue. In this Wcase
W . 1 O M
capture
. incorrect.
W . 1 O M.T
W .CO .TCapture .C W .C
0Y inter- M.TW
WW When using 00Y the Input W WW the .ICR1
interrupt, 1 00YRegister M TW be readWas early.1in0the
.should
.
WWhandler
1
.CO as
M W theY.Input O
C Capture W
W relatively CO
Y.high
rupt
Wpriority, 0 0 Y routine
.T
possible.
W EvenW
W though
1 0 0 M .T W interruptW has
. 1 0 0 M.TW
1
. the maximum OM interrupt responseWtime .
W is dependent O on the maximum number W of clock O
W WW 00Yto .Chandle .T W of the other W interrupt 0 0Y.C M.TW WW .100Y.C M.TW
cycles it .takes any .1 requests. O
W W 1 Y.COM W WW 00Y.CO .TW
W
WW .100Y.C M.T
W
Using the.1Input 0
0 Capture .T W
unit in any mode of operation .1 when M the TOP value (resolution) is
W W . C OM
actively
W changed 00 Y during operation,
.T is not W
recommended. .1
W .Tsignal’s duty W 0 .T edge is changed after W
Measurement
W 00an external
of
W.1Changing OM
cycle requires
W .10 that O the Mtrigger
each capture. . C the edge sensing must W be done .
asC early TW
W W
1 00Y M .TW W .100
Y
M .as possible after the ICR1
W . O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OM .1 OM the Input Capture Flag (ICF1) must be
W WRegister Y .Chas been read. After a change
W W WW of00the Y .Cedge, .TW For measuring frequency only,
W . 100 by software
cleared M .T (writing a logical one W . 1to the I/O O bitMlocation).
W O W Y.C
.T W WW the .clearing
1 0 0Y.Cof the M TW Flag is notWrequired.1(if
ICF1
. 00an interrupt W
M.Thandler is used).
M W O W C O
.CO WW Units 00Y
.C .TW WW .100Y. .TW
. 1 00Y 16.6.4M.TW Output Compare . 1 M W O M
W Y.C
O
W WW
W .CO .TW
0Ycomparator WW 00Y
.C .TW
. 1 0 0 M .T The 16-bit . 1 0 M continuously compares W .1 TCNT1 O Mwith the Output Compare Register
W O W C O W .C
00Y
.C
.TW
W
W(OCR1x). 1
Y
0If0TCNT
. equals
M .TW OCR1x theW comparator
.
Y
100signalsOaMmatch. .TW A match will set the Output
. 1 M .
W FlagY(OCF1x) O W
WW 00Y.CO .TW Compare
WWFlag.1generates 0 .C M
at the
.T W next timer WclockW cycle. 00TheYIf.Cenabled (OCIE1x
.TW = 1), the Output Com-
1 pare 0 an output compare W
interrupt. . 1 O
OCF1x M Flag is automatically cleared
W W. .C OM Wthe W Y .CisOexecuted. W W W 0 .C
YFlag .T W
Y W W 0 .T 0
W
W .100 O M.T
when
W .10
interrupt
. C O M Alternatively the
W W.1 Y.COM W
OCF1x can be cleared by software by writ-
aW
WW .100Y.C M.TW ingW logical one
00Yto its I/O
.1output
bitWlocation. The
M.T to operating W
W Waveform
W .10set 0 Generator
O
.T uses the match signal to
MWaveform
W O generate Wan O
according mode by .C the Generation mode
WW .100Y.C M.TW WW bits
(WGM13:0) . 1 0Y.C
0and Compare M .TW Output mode
W
(COM1x1:0) . 1 00Ybits. The M TW
.TOP
W W . C O W W Y .C O
W W WWthe special 0 Y .CO .TW BOTTOM signals and
Y W are usedW by the 0
Waveform
.10 M.T
Generator for handling .1 0 cases M of the extreme values in
W
W .100 O M.T W C O W W .C O
Y 103.) .TW
WW .100Y.C M.TW
some modes
WW of operation Y. (See “Modes .TW of Operation” W on page
.100
W . 100 O M W OM
W W .C O A specialW W of output
feature Y .Ccompare Wunit A allows W itW to define 0 Y
the .CTimer/Counter .TW TOP value (i.e.,
W 00 Y W
.T counter resolution). . 1 0 0 M .T . 1 0 M
. 1 M W O
W O W In addition
WWgenerated .CO to the counter resolution,
WW .100Y.C M.TW
the TOP value defines the period time
WW .100Y.C M.TWfor waveforms . 1 00Yby the M .TW Generator.
Waveform
W W .C O
W 00 Y .T W 1 diagram .1 The small M
W.1 Y.COM Figure 16-4 showsW
W
a .block
.C OMof the output compare W W unit.
Y .CO “n”.TinW the register and
W W 0 T W
bit names W
indicates the 0 0
deviceY number .T W
(n = 1 for W
Timer/Counter1), . 1 0 0 and theM “x” indicates output
W .10 O M. W W .1
.C Oof M W W Y .C O
W
.C compare unit (A/B). The elements the W
block diagram that are not directly a part of the output
WW .100Y M .TW unit are W
W . 100
Y
O M .T W
W .100 O M.T
WW .100Y.C M.TW
W O compare gray shaded.
W W .C O Figure 16-4. OutputWCompare
W
W Y .COBlock.TDiagram W W WW 00Y.CO .TW
W 00 Y .T W .10 0 Unit,
M .1 M
W W.1 Y.COM W WW 00Y.CODATA W
BUS (8-bit) W WW 00Y.CO .TW
W 00 .T W .T .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C TEMP
W (8-bit)
. C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W O W W .C O
W .C 00Y (8-bit) M.TW
WW .100Y.C M.TW OCRnxH W Buf. (8-bit)
. 00Y Buf. (8-bit)
OCRnxL
1 M .TW TCNTnHW (8-bit)
W . 1TCNTnL O
W Register) O
W
WW .100Y.C M.TW
O
WW (16-bit
OCRnx Buffer
0 0 Y.C .T W WW
TCNTn
0 0Y.C M.TW
(16-bit Counter)
.1
.1 M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W 00
W.1 Y.COM WOCRnxH (8-bit) WW
.T W .100
OCRnxL (8-bit).CO
M.T .1
WW 00Y.CO .TW
M
W Y W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C OCRnx (16-bit Register)
W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .1=00(16-bit Y. Comparator.T) W W .100
Y
M.T
O W O M W .C O
W
WW .100Y.C M.TW WW .100Y.C MOCFnx .TW
(Int.Req.)
WW .100Y M .TW
O W O W .C O
W
WW .100Y.C M.BOTTOM TW
TOP
WW Waveform .C
00Y Generator .TW WW .1OCnx 00Y M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
W O W O
O WW .100Y.C M.T
WGMn3:0 COMnx1:0
W
O W O
The W
OCR1x W Register Y .C Ois double buffered when
W W WW using Y
any
0 .C of the twelve
.T W Pulse W
Width WModulation0 0 Y.C
W 00 M.T and Clear Timer 10
W.Compare OM modes of operation, .1
(PWM)W W.1 ForY.the
modes. C Onormal
W W on
0 Y .C (CTC) W W WW the dou-
00 W 0 .T
ble W buffering W.is1 disabled. M.Tdouble buffering synchronizes
OThe W.1 Y.C the OM update of the OCR1x Compare
W .C W .TW
W . 1 00Y M .TW W
W . 100 O M
W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10
WRegister O M TOP or BOTTOMWofWthe .1 countingOsequence. M
W Y .to
C either
W W 0 Y .C . W The synchronization prevents the
Tthereby
W 0 0 .T . 1 0 M
W W.1 Y.COM W
occurrence of odd-length, non-symmetrical
W W PWM
0 Y
pulses,
.CO .TW
making the output glitch-free.
W W The.1OCR1x 00 Register .T W .10 but O
O M.T W W .C OM access may seem W
complex,
W Y
M not case. When the double buffering
.C this is.T W and if double buffering is dis-
Y .C W W is enabled,0 0 Y the CPU .T W
has access toW the OCR1x 1 0 0 Buffer Register,
. 1 00 M .T . 1
W the CPU M
O access the OCR1x W W . O M
W
0 Y.C
O
.T W WW abled
0 0Y.C will M .TW W directly. .1 0Y.C
0The content .of Wthe OCR1x (Buffer or Compare)
M T does not update this register
. 1 0 M W
Register . 1 is only O
changed by a write operation W (the C O
Timer/Counter
W .CO .TW W .C W 0Y . .TW is not read via the high byte
1 00Y M
Wautomatically . 1 00Yas the M .TW and ICR1WRegister).
TCNT1 W . 10Therefore O MOCR1x
. W O Y.C to .read
WW 00Y.CO .TW WW .1register
temporary 0 0Y.C (TEMP). . TWHowever,W
W
it is a good . 1 00practice M TW the low byte first as when
W. 1 OM M W O
accessing
WW other
W .CO registers.
0Y16-bit TW Writing the WW OCR1x Registers
00Y
.C must .TW be done via the TEMP Reg-
WW .100Y.C M.TW ister since . 1
the 0 compare M of
. all 16 bits is done W .1
continuously. O
The Mhigh byte (OCR1xH) has to be
O W O Y.C
W
WW .100Y.C M.TW WWfirst. .When
written 0 0 Y.theC
high .T W I/O location
byte WW is .
written 1 0 0by the M
CPU, .TW the TEMP Register will be
Wthe 1 OM W C O
W .C O W Y . C W W W 0 Y . W
WW .100Y M .TW updated
W by
W . 1
value
00 written.
O M .TThen when the low byte
W
(OCR1xL)
.10 O
is
M.T to the lower eight bits,
written
W O the high W byte will be copied .C into.Tthe W upper 8-bits WW of either the C
Y.OCR1x .buffer TW or OCR1x Compare
WW .100Y.C M.TW Register W in the same . 100YsystemMclock cycle. W . 100 O M
W O
W O
WW .100Y.C M.TW For more WW .100Y.C M.TW WW .100Y.C M.TW
information
W of how Oto access the 16-bit registers W refer toO“Accessing 16-bit Registers”
W O
WW .100Y.C M.TW on page 94. WW .100Y.C M.TW WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
16.6.5
W W Force .C O
Output Compare
W 00 Y .T non-PWM Waveform W .1 M can be forced by
W.1 Y.COM InW W W.1 GenerationY .C OMmodes, the match output
W WW of the 0 Y .CO .TW
comparator
W writing a one W 00Output Compare W 0
W
W .100 O M.T
to the Force
W.1 Y O M.T (FOC1x) bit. W W.1 compare
Forcing
.C OM match will not set the
.C OCF1x Flag or W
reload/clear the.C timer, but W the OC1x Wpin will be Y
updated
0 as if.TaW real compare
WW .100Y M .TW had occurred W . 00
1COM1x1:0 M .T W .10the O M is set, cleared or
W O
WW .100Y.C M.TW
W O match (the bits settings define whether OC1x pin
WW .100Y.C M .TW
toggled). WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M
16.6.6 W W.1 Y
Compare Match
.C OM Blocking by TCNT1W W.1 Y.COM W
Write WW 00Y.CO .TW
W W 0 . T W
W 00
W.1 Y.CO AllM .T writes to the TCNT1
CPU 10
W.Register . C OM
will block any compare match W W.1that occurs Y
M
.COin the.Tnext W timer
W W W W 0 0 Y .T W W 1 0 0
W 0 0 clock .T
cycle, even when the timer .1 is stopped. M This feature allowsWOCR1x W. to be O M
initialized to the
W W.1 Y.C OM value as TCNT1 without
same W WW triggering 0 Y .CO an interrupt W when the W Timer/Counter 0 0 Y .Cclock is.T W
enabled.
W 00 .T W 0 .T .1 M
W W
16.6.7 W the.1Output
Using
W
00 M.T Unit
Compare
O
W
W .100 OM
.T
W W.1 Y.COM W
C
Y. writing W 0Y .C W all compare W matches 00
WW .100Since W
M.T TCNT1 in any mode
W
W .10operation
of
O M.T
will block
W.1 forYone M.Tclock
Otimer
W O C W .C
WW .10cycle, 0Y.C there .TareWrisks involved WWwhen.1changing 0 0Y . TCNT1
M .TWwhen using W any of.1the 00 output compare M .TW
OM W O W O
.C to TCNT1
W units,
WW .1equals .Cindependent of whether the
.TW value, the WW
Timer/Counter
Y.C is running
00match .TW
or not. If the
WW value written
00Y waveform M.T
W
00Y theM OCR1x compare
W . 1 will
O M be missed, resulting in
W .1
incorrect
.C O
W
WW .generation. .CO Do.not TWwrite the TCNT1 WW equal .C
00toYTOP inM .TWmodes withWvariable
W 00Yvalues.MThe .TW
1 00Y M W .1 O
PWM
W . 1TOP
.C O
Wcompare match O for the TOP will be Y.Cthe counter WWto 0xFFFF. W
WW .100Y.C M.TW WWignored . 1 00and M .TW will continue .1 00Y Similarly, M.T
do not write the TCNT1 value equal to W BOTTOM O
when the counter is W
downcounting. C O
W
WW .100Y.C M.TW
O
W O
W setupY.of
The CO the OC1x should be performed
WW .10the
W before
0YOC1x.COsetting .TW
the Data Direction
WW Register 00Y
.C
for the W
WWport .pin 1 00to output.MThe .TW easiest way of setting W O M
value is to use the force W .
output1 O
compare M.T
W O .C W .C
WW (FOC1x)00strobe Y.C bits .inTW Normal mode. WW The OC1x 1 00Y RegisterMkeeps .TW its value W even when . 0Y
10changing M.TW
. 1 M
O generation modes. WW . O W O
W waveform
WW .100Y.C M.TW
between W 00Y
. 1 M O
W thatY.the C OCOM1x1:0 bits are not WW Y .CO together W W WW 0value. 0 Y.C W
WBeWaware
. 1 0 0 M .T W W double0buffered
W .1 0
O M .T with the compare
W .1 O M.T
Changing W the COM1x1:0
WW .100Y.C M.TW
O bits will take effect immediately.
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Output M .1 M
16.7 Compare Match W Y .C OUnit
W W WW 00Y.CO .TW
W 0
.10Compare M.T mode (COM1x1:0) .1 have two M
W
The
W Y .C OOutput
W W W Wbits
0 Y .CO functions. .T W The Waveform Generator uses
W W 0 0 .T 1 0
O M.T W
the
W
COM1x1:0
.1
.C O
bits
M for defining the Output
W W. Compare
Y .C OM(OC1x) state at the next compare match.
W
.C W Secondly Ythe COM1x1:0 Wbits controlWthe OC1x 0 outputM .T Figure 16-5 shows a simplified
00Y .TW .100 of theOlogic M.Taffected by the COM1x1:0 .10pin source.
O The I/O Registers, I/O bits, and I/O
W.1 Y.COM W W
schematic .C W W
0Ybit .Csetting.
.TW I/O Port Control Registers
00 .T WW in.1the00Y M .T W W .10parts Mgeneral
. 1 M pinsW figureOare shown in bold. Only W the of
.C Othe
W .CO .TW W and0PORT) 0Y.C that Waffected by WW 100
Y bits are .TW
. 1 00Y M
W(DDR
W . 1 O M .T are the COM1x1:0
W .
.C O M shown. When referring to the
W O .C W TWOC1x pin. If a System Reset
W 00 Y.C .T W WW state,
OC1x
. 1 0
the
0Y reference M .TisWfor the internal W OC1x.1Register, 00Y not .the
M
W. 1 OM occur, W OC1x Register
the O is reset to “0”. W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW W .1 00Y M.T
W
W O W O
W O
WW16-5..10Compare 0Y.C Match
W Y.C .TW
WW .100Y.C M.TW Figure
M .TWOutput Unit, WSchematic
W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW COMnx1 0 0 Y.C .T W WW .100Y.C M.TW
.1 M W O
W .C O WW COMnx0
Y .COWaveform W D W QW 0 Y.C W
W W
.1 00 Y
M .T W W FOCnx
W . 10 0
O
.T
Generator
M W . 1 0
O M.T
W O WW .1010Y. C
WW .100Y.C M.TW WW .100Y.C M.TW M .TWOCnx
W O W O OCnx WW
W .C O
WW .100Y.C M.TW WW .100Y.C M.TW . 1000Y
M .TWPin
W O W O WW 00Y.C O
WW .100Y.C M.TW WW .100Y.C M.TW D Q W .1 M .TW
W O W O
W
WW .100Y.C M.TW
O
W O WW 00Y.CO .TWPORT WW 00Y.CO .TW
DATABUS
W Y.C W W W
W 00 .T W.1 Y.COM W .1 M
W .100 M.T
W 00 .T W.1 Y.COM W
W .C O W W.1 Y.COM DW Q W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O DDR W O
W
WW .100Y.C M.TW clk
O
I/O WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O
W 00 Y W .1
W.1 YThe M.T I/O port function
Ogeneral W is.1overridden
W .C Oby M the Output Compare W W
(OC1x) from Y
M
.COthe Waveform W
.C Y W W 0
W W
. 1 00 Generator M .TifW either of the WCOM1x1:0
W .100bits areOset. M .THowever, the OC1x W pin 0
.1direction O M.Tor out-
(input
W O .C WW .C
WW .100put) Y.C is still .controlled
TW by theWW 00Y Register
Data Direction
1 M .TW(DDR) for the port pin.
.
Y
100The Data M .TW
Direction
M W . O W O
W
WW .10ble 0Y.on CO bit for
Register
.T W the OC1x pin W
W (DDR_OC1x) 0 0Y.CmustM be set
.TWas output W
W the 0OC1x
before
.1 0Y.Cvalue M
is W
.Tvisi-
the M pin. The port override . 1
function is generally independent of the W Waveform O
Generation
W .CO there WW 00Y.CO .TW WW Y.C
00Table W
WW .1mode, 00Y but M .TWare some W exceptions.
W . 1 Refer toM
O
Table 16-2, Table 16-3 W .1
and O M.Tfor
16-4
W .CO .TW WW .100Y. C
WW .details. 00Y WW .100Y.C M.TW M .TW
1 O M W O W O
.C out-
WW The
W Y.C of the.Toutput
design
0 W compare WW pin logic0allows 0Y.C initialization .TW of the OC1x WW state.1before 00Y the M .TW
.1 0 M W . 1 O M W C O
W put is enabled. .CO Note that some COM1x1:0 bit.Csettings are reserved Wfor W certain Y .
modes of.TW
WW operation. 00Y See M .TW Description” WW .100Y M .TW .100 M
. 1 “Register onW page 112. O W O
W
WWThe .COM1x1:0 .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
00Y
W W 1
. C
M have no effect on W
Obits
W
theW Input Capture
Y .CO unit..TW W WW 00Y.CO .TW
Y W 0
W 00
W.1 andY.Waveform OM
.T 0
C W
16.7.1 Compare Output W W Mode
.1 00 M .TW Generation W
W . 100 O M .T W
W .100 O M.T
The W
WWaveform O Y.C WPWM modes. .C W
Y.Generator
C
.TW
uses the COM1x1:0
WW bits differently
100Waveform
in normal,
TW CTC,W
.Generator
and
.10on 0Y M.T
WFor allW .100 setting
modes, M the COM1x1:0 = 0 tells
W .the O M that no W
action the
Y.C
O
WW Register .CO performed .TW on theW
W .C
00Ymatch.M W WW 10in0the OM.T
OC1x
. 1 00Yis to beM next compare . 1 .Tcompare
For output actions
W .
W CO to Table
Y.refer WW 0Yfast.COPWM.Tmode W refer toWTable W 16-300on Y.C
WW modes
non-PWM
0 0
.1 for phase .T W 16-2 on W page 112. For
. 1 0 M . 1
page 113,Wand
W
M
.CO correct W
and phase and WW frequency.Ccorrect
Y
O PWM
W refer to W WW
Table 16-4 on
W
page 113. .10 0 Y .T W . 1 0 0 M .T
W O M W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WA.1change M COM1x1:0 bits state .1 M
W Y .C ofOthe
W W WW will have effect
0 Y .CO at the .TtoW
first compare match after the bits are
W 0 0 .T . 1 0 M
W W.1 Y.COM W
written. For non-PWM modes, the action
W W can
0
be
Y .
forced
CO have immediate effect by using the
W
.TW W .10 M. T
M
W FOC1x
W . 100strobeObits. M .T W C O
.CO TW WW .100Y.C M.TW WW .100Y. .TW
. 1 00Y 16.8M.Modes of Operation W O W O M
W
0 Y.C
O
.T W WW 0 0Y.C M.TW WW .100Y.C M.TW
0 . 1
W. 1
.C OM The
W Wmode of
Y
operation,
.CO .TW
i.e., the behavior
W WofWthe Timer/Counter0 Y .CO .Tand W
the output compare pins, is
Y W W 0
10the combination .1 0
.100 M.T defined .by
W M
Obits.
of the Waveform Generation
WW mode
mode M (WGM13:0) and Compare Output
.COdo not.Taffect
WW 00Y.CO .TW mode
W W (COM1x1:0)
1 0 0 Y .C The
.T W Compare WOutput
. 1 0 0 Ybits
M
W the counting sequence,
W. 1 OM .
WWaveform O M W O
WW .100Y.C M.TW
whileW the
Wgenerated Y.C Generation
00should
mode bits do.
.TW or not W
W The COM1x1:0
.1 0Y.C bits
0non-inverted M
control
W whether the PWM out-
.TPWM).
. 1 M WW 00Y.CO .TW
put W Obe inverted (inverted or For non-PWM modes
W W .C O W Y .C W W
Y W theW COM1x1:0
.100bits control T
M.whether the output should 1 be set,Ocleared or toggle at a compare
W
W .100 O M.T W W“Compare .C O W W.102.) Y .C
M
W
WW .100Y .C W match (See Y Match Output
W Unit” onW page 0 0 .T
W O M.T
W
W .C
WW .100Y.C M.TW For detailed W timing .100
Y
information
M.T
W to “Timer/Counter
refer W
W .100
Timing Diagrams”
OM
.T on page 110.
W O W C O W .C W
WW16.8.1 .C
00YNormal .TW
Mode WW .100Y. M .TW W .100
Y
M.T
.1 M W O W C O
W O
WWmode.1of Y.C WW(WGM13:0 Y. TWmode the counting
WW .100Y.C M.TW The simplest 00operation M
W Normal mode
is.Tthe
W . 100 = 0). O In .this
M
O WW up00(incrementing), O .C
W
WW .100Y.C M.TWoverruns when
direction isWalways Y.C .TWand no counter WW clear . 1 0is0Yperformed. M.thenTTheW counter simply
it W .
passes 1 its O M
maximum 16-bit value (MAX W = 0xFFFF) C Oand restarts from the
W O Y.C operation WW .Overflow .
0Y Flag TW will be set in
WW .100Y.C M.TW BOTTOM (0x0000). WW In 1 0 0
normal .T W
the Timer/Counter 1 0 M .
(TOV1)
W O WW cycle
. OM
.Cthe WW 00Y.CFlag O
Wcase behaves
WW .100Y.C M.Tthe Wsame timer Wclock . 1 0 0 Yas TCNT1
M .T Wbecomes W zero. The.1TOV1
W O Min.T this
O like a 17th bit, except W it isY.only O .C
W
WW .100Y.C Minterrupt .TW that automatically WW that 0 C set,
0clears .TnotWcleared. However, WW combined . 1 00Y with .TW
the
Mincreased
timer overflow
W . 1 the
O M TOV1 Flag, the timer W
resolution can O be by soft-
W O W Y.Cto consider WW mode, 0Y .C TW
WW .100Y.C M .TWThere are W
ware. no special 0 0
cases .T W in the Normal .1 0 a new M
counter . value can be
0 Y .C O
W
WW .100Y written W anytime. W 0 .T
W O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W mode. However,
WW .100Y. The InputW Capture W
M.T between the external
unit is easy00toYuse in Normal
.1 M.T
W
W
00
.1observe thatMthe .T maximum
O If the interval
W O W C O W .C
WW .100Y.Cbetween
interval
.TW WW .100Y. events must not exceed the resolution
.TW interruptWor theWprescaler
of the
.100
Y counter.
M.be TW
M events are too long,
W the timer O M
overflow C O
must used to
W
WW .100Y.C
O
extend the .T W resolution for WW the capture 0 0 .C
Yunit. . T W WW .100Y. M . TW
. 1 M
W .COoutput
M WW 00Y.CO .TW W WW 00Y.CO .TW
WW .100YThe T W
M. compare units can
W be.1 used to generate .1 time. Using OM the out-
W O W C OM interrupts at some W Wgiven
.C
W Y
put .C compare W
to generate W W
waveforms 0in0 Y .
Normal mode .T W is not W
recommended, 1 0 0
since Y this will TW
.occupy
W . 1 00 M .T . 1 O M W . O M
W too much O of the CPU time. WW .C WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00Y M .TW
WW on 0Compare .C O
16.8.2 ClearWTimer 0 Y .T
Match (CTC) Mode W .1 .1 M
W.1In Clear OM on Compare or CTC Wmode C OM WW or00ICR1 .CO
W W 0 0Y .C Timer
.T W W W
1 00 Y .
(WGM13:0
M .T= W 4 or 12), the W OCR1A
. 1
Y Register
M .TW
. 1
Ware used M
toOmanipulate the counter W . O mode the counter W W O
.C when
Y.C value.T(TCNT1) WW either
resolution. .InCCTC
0YOCR1A TW Wis cleared toYzero
00(WGM13:0 W
WW the .1 0 0
counter M
W matches W . 1 0the O M .
(WGM13:0 = 4) or the W
ICR1.1 O M.=T
W CO W .C W C
Y. This.TW
WW 12)..10The 0Y.OCR1A M TW
.or ICR1 defineWthe top .value 1 00Yfor theMcounter, .TW hence W 100
also its resolution.
W . OM
W allows C O W W match . C O frequency. It also W Y .C W
W W mode
0Y . greater control of
.TW events. W W.100
the compare Y output .T W W simplifies
.10 0the opera-
M.T
tion .1
of 0counting M
external O M W .C O
W O WW .100Y
O for the CTC modeWisW O W O
TheWtiming diagram
W
Wincreases 0 Y.Ca compare .T Wmatch occurs W with either
shown in.C
0
Figure 16-6.
0YOCR1AMor.TICR1, W The counter WWvalue.1(TCNT1) 0Y.C M.TW
0(TCNT1)
1 0 until . 1 and then counter W O
W. .C OM WW 00Y.CO .TW W W 0 Y.C W
W
is W
cleared.
. 1 00 Y
M .T W W
W .1 O M W .1 0
O M.T
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
.100
W OCnA Interrupt Flag Set
M .TW W
W . 100 O M .T W O M.T or ICFn Interrupt Flag Set
.C O W Y .C W W W 0 Y . C T W (Interrupt on TOP)
00 Y .T W W 1 0 0 M .T . 1 0 M .
. 1 M W . O W O
W
0 Y.C
O
0
W. 1
.C OM
Y W .1
M
WW 00Y.CO .TW W
W TCNTn 00 .T W
.C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .100Y.C M.TW WOCnA .100
Y
M.T
W W
W .100 O M.T
W C O W
(Toggle) W .C O W Y . C W
(COMnA1:0 = 1)
W Y . W W 0 0 Y .T W W .1 0 0 .T
W 00 .T W.1 Y.C1OM W 2 M
W W.1 Y.COM W Period W W W3W 00Y4.CO .TW
W 00 .T W 0 0 .T .1 M
W W
W .100 M.T
W 100generated
.be .T
OMat each time the counter W.1valueYreaches M
W W .C O An interrupt can
W W Y .C W W W 0 .CO the . WTOP value by either
Tthe
W 0 0 Y .T W using the W OCF1A or
1 0 0
ICF1 Flag .T
according to the register . 1 0
used to M
define TOP value. If the
W.1 Y.COM Winterrupt is enabled, W W. the Y .C OM WbeWused00for Y CO
.updating W
W interrupt handlerW routine W
can T
M. TOP value. How-
the
W . 1 00 M .T W
W . 100to a value O M .T W .1
C O
W O ever, changing W the TOP
Y.C close to BOTTOM
WW .100Y
when the .
counter is running
TW with none or a
WW .100Y.C M.TW W 1 0 0 .T W M .
W O low prescaler valueW . be done
must OM with care since the CTCW
W mode00does O
not have the double buff-
Y.Cthan the
WW .100Y.C M.Tering W feature.WIfW the new 0 0 Y.C written
value .T W
to OCR1A WICR1
or is. 1lower M
W
.Tcurrent value of
W . 1 O M W C O
W .C O TCNT1, the counter W will miss .
theC compare W match. The W
counter will Y
then
0 . have to W
count to its max-
WW .100Y .TW value (0xFFFF) W . 0Y
10wrap M .T W .10the T
M.match
M W O W O
WW .100Y.C M.TW
W O imum and around starting at 0x0000 before compare can occur.
WW .100Y.C M .T W W W 0 0 Y.C .T W
In many cases this feature .1is not desirable. M An alternative willWthen W be toYuse .COthe fast PWM mode
W W Y . CO
using WOCR1A for W WW TOP
defining 0 Y .CO .T=W
(WGM13:0 15) since the W OCR1A 0
then 0 will be .T
double W buffered.
W 00 .T 0
W.1 Y.COM W .1 M
W 00 For generating W
a waveform output 0
.10 in CTC .T
mode, the OC1A output can .1 be set toOtoggleM its logical
W.1 Y.CO M.T W C OM the compare output WWmode .C to toggle
W level onW each compare W match by
Y . setting W W 0 Ybits
.10 the data TW mode
M.direction
W . 1 00 M
(COM1A1:0
.T = 1). TheWOC1AWvalue . 100 will not O Mbe
.T
visible on the port pin W unless C O for
W
WW .100Y.C
O
.T W W
W(DDR_OC1A 0 0 Y.C .T W WW .100Y. M .TW
the pin M is set to output W. 1 = 1). OM The waveform generated W will have a Omaximum fre-
W
WW .100Yquency .CO of.TfW OC1A = fclk_I/O W /2W when 1 0
OCR1A
0 Y.C is set.T toW zero (0x0000). WWThe .waveform 1 0 0Y.C frequencyM.T
W is
O M W . O M W .C O
W
WW .100Y.C M.TW
defined by the following equation:
W O f W O
W
WW .100Y.C M.TW
O
WW f OCnA .C
2 ⋅ NO⋅M
clk_I/O
( 1.T
W
00=Y --------------------------------------------------
+ OCRnA )
- WW .100Y.C M.TW
. 1
W W .C O
W WW 00Y.C W W WW 00Y.CO .TW
Y W . T
W 00 N variable .T W.1 factor OM 8, 64, 256, or 1024). WW.1 .CO .TW
M
W W.1The Y .C OM represents the prescaler
W W 0 Y .C (1,
W W 0 0 Y
W .10TOV1 .T .1 cycle O
W 100for the O
W.As M.T mode of operation,
Normal Wthe C OMis set in the same timer
Flag W Wclock M
.C that the
. C W Y . W W 0 Y W
W W 00Y countsMfrom
counter
.1 .TWMAX to 0x0000. W
W . 100 O M .T W .10 O M.T
W O WW .100Y. C
W O W O
16.8.3 Fast PWM Mode W
WWThe .fast .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
1 00Y PulseOWidth M Modulation or fast PWM mode (WGM13:0 = 5,6,7,14, orW 15) provides .COa .TW
W W Y .C W W W W
0 Y .CO .TW W W 0 0 Y
W high frequency 00 PWM.Twaveform generation .option. 10 The fast PWM differs from the.1 M
W.1 by its OM W .C OMfrom BOTTOM to TOP W W other YPWM .CO .TW
W
options Y .Csingle-slope W operation. W W
The counter
00 Y counts .T W W then 0 0
restarts
W
from W .100
BOTTOM. M.T
InOnon-inverting CompareW W.1 mode,
Output . C Othe MOutput Compare (OC1x) W W.1is cleared
Y .C OM
W
.C Y W W 100
W W
on the compare . 1 00Y matchMbetween .TW TCNT1Wand OCR1x, W .100 and set O M T
at. BOTTOM. In inverting W .Compare OM.T
W O
Y.C is set.Ton WW and.1cleared .C .TW Due toWthe single-slope
W Y.C
WW mode
Output
. 1 00output M
Wcompare match 00Y at BOTTOM. M W . 100 OM.T
W O W .C O W .C
WW .100Y.C M.TW
operation, the operating frequency of the fast WWPWM.1mode 00Y
can be twice
.TWas high asWthe phase 0Y
cor-
.10high
rect and W phase and frequency correct PWM W
modes that use O Mdual-slope operation. W
This
WW makes .CO .TW W 0Y.C regulation, .TW rectification, WWand DAC
frequency . 1 00Ythe fastMPWM mode wellWsuited for
W . 1 0power
O M
W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10
Wapplications. C OM High frequency allows W.1 Y.small
Wphysically CO sized
M external components (coils, capaci-
W W 0 0 Y . .T W W . 1 0 0 M .TW
.1
tors), hence reduces
M total system cost.
WW 00Y.CO .TW
W W WW 00Y.CO .TW W 1 to 8-,O9-,
O M.T The
W .1PWM resolution
C OM for fast PWM can W W.fixed
be
.C
M or 10-bit, or defined by either ICR1 or
00 Y .C
.T W W W OCR1A. 1 0 0 Y
The
. minimum
M .T W resolution W
allowed is . 0
2-bit
1 0 Y (ICR1 orM .TW set to 0x0003), and the max-
OCR1A
. 1 O M .
W resolution O 16-bit (ICR1 or OCR1A W .C O
W
0 Y.C .T W WW imum
0 0Y.C isM .TW WW set .1 00toYMAX).MThe .TW PWM resolution in bits can be
. 1 0 M W
calculated . 1 by using O the following equation: W C O
. 1 M W O W O
WW 00Y.CO .TW WW .100Y.C M.TW WW= log
R FPWM . 1 (0TOP0Y.C + 1)
- M.T
----------------------------------
W
W. 1 OM W O W log ( 2 ) O
W mode Ocounter is incremented W O
W O In fastW PWM
Y.C the
WWuntil .the Y.C value
0counter .TW
matches either one of the
WW .100Y.C M.TW W
fixed values . 1 0
0x00FF,
0 0x01FF, M .T W
or 0x03FF (WGM13:0 W 1=
0 5, 6, or O M
7), the value in ICR1 (WGM13:0 =
W W Y .C O
W W W W
0 Y .CO (WGM13:0 .T W W W 0 0 Y.isCthen cleared .T W at the following timer
W 00 .T 14), or the value .10 in OCR1A M = 15). The .1
counter
OM
W W.1 Y.COM W clock cycle. W WThe timing
0 Y . C Odiagram W for the fast W PWM WWmode 0 0 Y
is .C
shown in W
.TFigure 16-7. The figure
W 00 .T W . 1 0 M .T . 1 M
W .1 OM shows fast PWMW mode when
C O OCR1A or ICR1 is used
W W to define .C O
TOP. The TCNT1 value is in the
WW shown . 0Y W
WW .100Y.C M.TW timing diagram . 1 00Y as a histogram M .TW for illustrating W
the . 1 0single-slope M .T operation. The diagram
W W .C O WW 00and Y
O
.Cinverted W W WW 0 Y .CO .TW
Y W includes W
non-inverted
M. TPWM outputs. The small .1 0 horizontal line marks on the TCNT1
W
W .100 O M.T slopes represent W .1
C O W W . C O M
WInterrupt Flag will
WW .100Y.C M.TWbe set when WW compare Y. matches.Tbetween W OCR1x W and TCNT1. .100
Y The OC1x
M.T
a W
compare . 100matchOoccurs. M W C O
W O WW .100Y .
O W O
W O WW 0Y.C Timing WW .100Y.C M.TW
WW .100Y.C M.TFigure W 16-7. WFast PWM0Mode,
. 1 M .TW Diagram
W W .C O
Y W
W
W .100 O M.T W .1
.C O M W W.1 YOCRnx .C
TOVn
M / TOP Update and
OInterrupt
W Set
Flag and
WW .100Y.C M.TW WW .100Y M .TW W .100 OCnAO M .TFlag
Interrupt Set
O W O W .C Interrupt.T
W
OCnA Flag Set
W
WW .100Y.C M.TW W
(Interrupt on TOP)
O M
W O C
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W 00
W.1 Y.COM
.T
TCNTn W.1 Y.COM W W W.1 Y.COM W
W
W W
. 1 00 M .TW W
W .100 O M .T W
W .100 O M.T
W O WW .100Y .C
W O W O
W
WW .100Y.C M.TW
O
OCnx
WW .100Y.C M.TW WW .10(COMnx1:0 0Y.C = 2)M.TW
W O
W W Y .C O
W W WW 00Y.CO .TW W W 0 0 Y.C = 3) .TW
W 00 OCnx .T W.1 Y.COM W .1(COMnx1:0 M
W 00 .T W 00 .T W.1 Y.COM W
W.1 Period .C OM W W.1 4Y.CO5 M6 W7 8 W
W W .100 M.T
1 2 3
W .1 00Y M .TW W
W . 100 O M .T W C O
W
WW The.1Timer/Counter .CO .TW WW .1is0set 0Y.each C W WW .100Y. .TW
00Y M Overflow Flag (TOV1) M
time .Tthe counter reaches W TOP. In O M
addition
W CO
Y.or WW timer 0Y .CO .Tas WTOV1 is set WW .C
00YOCR1AM.TW
WWthe OC1A .1 0 0 ICF1 Flag . T Wis set at the
Mdefining the TOP value.
Wsame .1 0 clock cycle M when either
W . 1 O
orW Ofor WWIf one of.C
O Wthe .Chan-
W W ICR1 is Y
0 0 .
usedC
.T W W 1 0 0 Y the interrupts
M .T W are enabled, W interrupt
. 1 0 0 Y
M .TW
. 1 M .
W and compare values. O W O
WW .100Y.C M.TW
dlerW routine can O be used for updating the TOP
When Wchanging .C O TOP value the program
the WWmust00ensure .CO that.Tthe W new TOP value WWis higher Y.CorO W
W Y W W Y W 0 0
.1 of the OM.T
Wequal to .the 1 00value ofM all.Tof the Compare Registers. W .1 If theOTOP M value is lower thanW any
W .CO a compare Wnever occur .C .TW
W Y.C
WW .Registers,
Compare
1 00Y M .TW match W will .1 00Y between M the TCNT1 W and the OCR1x.
W . 100 O M.T
W O W O W .C
NoteW that when Y .C fixed.TTOP
using W values W theWunused 0 Y.Care masked
bits
.TW to zero when W any .of 0Y
10the
W
OCR1x Registers . 1 00 are written. M W . 10 O M W
W O WW
O ICR1 differs from updating W OCR1A Owhen used for defining the TOP
The procedure
WW for 0
updating
Y.C is not W WW This 0 0Y.C thatMif.TICR1 W
value.WThe ICR1 . 1 0 Register M .T double buffered. W . 1 means O is changed to a low
W W .C O W Y .C
W 00 Y .T W W 0 0
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 105
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 whenOthe Mcounter is running with .1 OM
W Wvalue Y .C W W WWnone00orYa.Clow prescaler
.
value, there is a risk that the new
TW The result will then be that the
W ICR1.1 0 0value written .T is lower than the .
current1 value ofM TCNT1.
WW .CmissOM W W .CO The.Tcounter
Yvalue. W
.T W W counter 0 0 Y
will the .T W
compare match W at the .TOP
1 0 0 M will then have to count to the
M W . 1 O M W C O
.C O WMAX value .C
(0xFFFF) and
W wrap around W starting at Y .
0x0000 before W the compare match can occur.
. 1 00Y M .TW W
The . 1
OCR1A00Y Register M .Thowever, is
W
double W . 100 This
buffered. O M .T
feature allows the OCR1A I/O location
W Y .CO .TW W WW 00Y.CO .TW WWI/O location 1 0 0 Y.C . T W
00 to be written
.1 anytime. When the OCR1A W. is OM
written the value written will be put into
W.1 Y.COM W W W .C OM W Y .C W
Wthe OCR1A Y
Buffer Register. W The OCR1A W Compare 00 RegisterMwill .T then be updated with the value
W .100 O M.T W .100Register O Mat.Tthe next timer clock W W.1 theYTCNT1 .C O matches TOP. The update is done
W Y.C W
in
Wthe
the
W Buffer .C
0Y clockMcycle TWas the TCNT1 W cycle
00 and theMTOV1 .TW
1 0 0 .T at same . 1 0 timer . isW . 1
cleared O Flag is set.
W W. .C OM WW 00Y.CO .TW W W 0 Y.C . T W
W 00 Y .T W W .1 Register .1 0 M
W.1 Y.COM W Using the
W WICR1 . C OMfor defining TOP works WW well00when Y .COusing.Tfixed W TOP values. By using
W W 0 .T ICR1,W the OCR1A 0 0 Y Register . T
is
W
free to be usedW for . 1
generating a PWMM output on OC1A. However,
W .10 O M WPWM .1 OM W W .C O
.C W Y . C W W 0 Y W
WW .100Y M .TW if the W base
W . 1 00 frequency
O M
is.T actively changed (by
W
changing
.10 the
O M.T
TOP value), using the OCR1A
W O WW buffer Y. C
WW .100Y.C M.TW
as TOP is clearly a better choice due to its double feature.
WW .100Y.C M.TW . 100 M .TW
O W O
W O In fast PWM WW mode, the
0Y.C compare
Tunits
W allow generation WW .1of00PWM Y.C waveforms .TW on the OC1x pins.
WW .100Y.C M.TW Setting W the COM1x1:0 . 1 0 bits O M .
to 2 will produce a non-inverted W PWM O M
and an inverted PWM output
O W 0Y.C
W
WW .100Y.C M.TW can be generated WW by 0 0 Y.C the COM1x1:0
setting .T W to 3 WWTable
(See . 1 016-2 on pageM .T W
112). The actual OC1x
. 1 M W O
W O Wbe W visibleY.on COthe port WWdirection 00Y
.Cthe port.Tpin W is set as output
WW .100Y.C M.TWvalue will W only
. 1 00 M .TW pin if the data
W . 1 for
O M
O W O .C
W
WW .100Y.C M.TW
(DDR_OC1x).
W
The
W PWM
0 0 Y.C
waveform is
.T
generated
W by
WW .100Y
seting (or clearing) the
M
OC1x
.TW Register at the
1
W. OCR1x M TCNT1, and clearing O
W O compare match between Oand
Y.isCcleared.T(changes WW(or setting) 0Y.C M.TW
the OC1x Register at the
WW .100Y.C M.Ttimer W clock cycle WW the counter .1 0 0 M
W from WTOP to . 1 0
BOTTOM).
W W .C O
W 00 Y .T PWM frequency for
The W the output can be calculated by the following .1 equation:M
W W 00 f OCnxPWM f W
.T = ----------------------------------- W.1
W .100 M.T
clk_I/O
W O W.1 Y.C OM ⋅ ( W ) .C OM
.C W W N 1 + TOP
W 0 Y W
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W OThe N variable represents .C divider WWor 1024). Y. C
WW .100Y.C M.TW WW the.1prescaler 00Y M .TW(1, 8, 64, 256, . 100 M .TW
W O
W O extreme values forW W .CO .represents WWcases.1when .C
00Y generating W
WW .100Y.CTheM .TW W the OCR1x . 1 00YRegister M TW special
W O M.T a PWM
W O C
W
WW .100Y.C
O
waveform
.T W
output in the
W
fast
W PWM
0
mode.
0 Y.C If the OCR1x
.T W is set
WW .100Y.
equal to BOTTOM (0x0000)
M .TW the out-
put will M be a narrow spike W forW 1
. TOP+1Otimer
each M clock cycle. Setting COequalTtoWTOP
W .COresult.TinWa constantW Y.C (depending W on theW WWthe 0OCR1x 0 Y.output
WW .100Ywill high or low .1 0 0output .T polarity
W. 1
of the .
OMset by the
W O M bits.) W C OM W .C
WW .100Y. C
COM1x1:0
.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
M . O W O
W .CO .T WW waveform 0Y.C output TinWfast PWM mode WW can.1be Y.C
00achieved W
.Tset-
WW .10A0Yfrequency M
(with
W 50% dutyWcycle) . 1 0 M . W O M by
Won each O This.C
W tingYOC1A
WW .1if00OCR1A .CO to .toggle TWto define the
its logical level
WW .C
00Y(WGM13:0
compare match (COM1A1:0
.T=W15). The waveform WW = 1). .1
applies only
00Y will .TW
Mhave
isMused TOP W . 1
value O M W generated C O
W O W 0Y.C OCR1A
W Y. .TisW
0Y.C M
WW .a10maximum .TW of fOC1W
frequency A = fclk_I/O.1 /20when M .TW is set to zero W(0x0000).
W . 100This feature
O M
Wsimilar to the O OC1A toggle in CTCW W .CO .TWbuffer feature WWof the.1output .C
00Y compare W
WW .100Y.C M.TW W mode,.1except 00Y the double M W O M.T
unit is enabled in the fast PWM mode. W O C
W
WW .100Y.C M.TW
O
W O W O
16.8.4 WWPWM
Phase Correct W Mode
0 Y.C
O
1 0 .CO .TW
WTheW.phaseYcorrect .C OMPulse Width Modulation
W WW or phase Y
O
.Ccorrect PWM
W mode (WGM13:0
W WW =001,2,3,10, Y
W 0 . T
W or 11).1provides
W
00
OaM high .T resolution phase correct W.1 PWM
0
.C OM
waveform generation option. W W.1The phase Y
M
.CO .TW
W Y .C Wthe phaseW W Y
00 correct PWM W
.T mode, based onW W 10 0
Wcorrect .PWM
W 100 mode O Mis,.T like
W.1 Y.COM W
and frequency
W
a .dual-slope
.C OM
W
operation. . C
.TW repeatedly
W .T to TOP andWthen from 0 to M.TW
Y
W . 1 0The
0Ycounter M
counts W from BOTTOM
W . 100 (0x0000)
O M W .10TOP
.CO .T
WW In00non-inverting
BOTTOM. O Compare Output W mode,00the Y.COutput .Compare (OC1x) WWis cleared 0Yon
W Y.C T W W T W 1 0
the compare .1 match O M
between . TCNT1 and OCR1x W.1 while OM
upcounting, and set on the W W compare .COM
.
W .C W Y .C W Winverted. 0Y
WWwhile.1downcounting.
match 00Y M .TIn Winverting Output W 100 mode,
Compare
. M T operation is
.the W .10The
O W O
WW operation
dual-slope W
0Y.Chas lower .TW
maximum operation WW frequency 00Y than
.C TW slope operation.
.single WW How-
. 1 0 M . 1
WPWM modes, M
O these modes are preferred for
ever, due to
WWthe symmetric O feature of the dual-slope
motorW 0 0 Y.C .T W WW .100Y.C M.TW
W.1
control applications.
OM W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
WThe.10 PWM resolution
C OM for the phase W W.1 PWM
correct .Cmode OMcan be fixed to 8-, 9-, or 10-bit, or defined
W W Y .
00 ICR1Mor.TOCR1A. The minimum
by.1either
W W . 0 0 Y
1 resolution M .TW is 2-bit (ICR1 or OCR1A set to
allowed
W O
W
W
WW 0x0003), 0Yand .COthe maximum .TW WWis 16-bit
resolution 00Y
.C
(ICR1 orMOCR1A .TW set to MAX). The PWM resolu-
M .T . 10 M W . 1 O
W O C
Y. equation:
.CO .TW WWtion in.1bits 00Y
.C be calculated
can
.TW
by using WW the following
100 .TW
. 1 00Y M W O M W .
.C O M
W O WW .1log
0 0 Y.C .T W WW .100Y.C M.TW 00Y ( TOP +M 1 ) .T
W
. 1 M W O R W = C O
----------------------------------
. -
W .CO .TW WW .100Y.C M.TW WW .100log
PCPWM Y (2) .TW
. 1 00Y M O W O M
WW 00Y.CO .TW WW correct
Wphase
In 0 0Y.CPWMMmode .TW the counter WW is incremented 1
.C
00Y untilMthe .TW counter value matches either
. 1 M W . 1 O 0x00FF, 0x01FF, orW0x03FF (WGM13:0 W . O
W .C O one W
of the fixed .C
values W Y . C = W2, or 3), the value in ICR1
1,
WW .100Y M .TW W
(WGM13:0 W . 0Y
1=010), or O
the M .T in OCR1AW(WGM13:0
value W .100= 11).OThe M.T counter has then reached the
W O W Y.theC W 0Ywill .C TW
WW .100Y.C M.TW TOP Wand changes 0 0 count .T W
direction. The W TCNT1 . 1
value 0 be M
equal . to TOP for one timer clock
0 Y .C O
W
WW .100Y W cycle. WThe timing diagram for.T the phase correct W PWM.1mode 0 is shown .Ton Figure 16-8. The figure
M.T W 100
.correct O Mmode when OCR1A W C OMto define TOP. The TCNT1
W O shows phase
W .CPWM W or ICR1 Yis . used
.TW
WW .100Y.C M.TW value is Win the timing . 1 00YdiagramMshown .TW as a histogram W
W for . 00
1illustrating O M
the dual-slope operation. The
W W .C O WW non-inverted Y .CO and W W W 0 Y .C TW
W .1 0 0 Y
M .T W diagram W includes
W . 1 0 0
O M .T inverted PWM outputs.
W . 1 0 The small
O M.horizontal line marks on
W C O W . C W matches W W Y .C W
WW .100Y. W the TCNT1
M.T rupt Flag will W
W slopes.1represent 00Y compare
M.T match occurs. WW.10
between OCR1x 0 andM
O
.T
TCNT1. The OC1x Inter-
W O be Wset when aC O
compare .C W
WW .100Y.C M.TW Y. .TW W .100
Y
M.T
W
W . 100 O M W C O
W O Figure 16-8.WW .C WW .100Y . .TW
WW .100Y.C M.TW Phase Correct
. 1 00Y PWM M .TW Timing Diagram
Mode,
W O M
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C OCRnx/TOP M .TWUpdate and
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.C OCnA M
or ICFn .TWFlag
Interrupt
Interrupt
Set
Flag Set
W O W O on TOP)
W O
(Interrupt
WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M .1 M Flag Set
W.1 Y.COM W .CO on Bottom)
TOVn Interrupt
W WW 00Y.CO .TW W WW 00Y (Interrupt
.TW
W 00 .T W .1 M . 1 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
W W .C O
Y W
W 00
W.1 Y.COM
W
W W
. 1 00 TCNTn
M .TW W
W .100 O M .T W
W .100 O M.T
W O WW .100Y .C
O W O W .C O
W
WW .100Y.COCnxM.TW WW .100Y.C M.TW WW .100Y(COMnx1:0 M .TW
= 2)
W O W O
W CO WW .100Y.C M.TW WW .100(COMnx1:0 Y.C .TW
WW .100Y.OCnx M .T W
W O =M3)
W O C
W
WW .100Y.C M.TW
O
W O W O W W .C O
WW .100Period Y.C .T W 1 WW 2.100Y.C 3 M.TW 4W
.1 00Y M.T
W
M W O W C O
W
WW The.1Timer/Counter .CO .TW WW .100Y.C M.TW WW .100Y. .TW
00Y M eachOtime the counter reaches W O M
W O
Y.C or ICR1
Overflow Flag (TOV1)
WW is set Y.Cvalue, .the TWOC1A or ICF1
BOTTOM.
WWFlag .is10set .CWhen .TW
0Yaccord-
WWeither 0 0
OCR1A . T Wis used for W defining the
. 1 0 0TOP M M
1
W. at theYsame OMtimer clock cycle asW W .CO .Tare Wthe W CO
Y.buffer
W W ingly
00
.C
.T W W the OCR1x
1 0 0 Y Registers
M
W updated W
with double
. 1 0 0 M .TW
. 1 M . O W O
WW (at 0TOP). O beWused toYgenerate WW .C
value
Wreaches 0 Y.C The Interrupt .T W Flags can WW . 1 0 0 .C M.an TW interrupt each
. 1 00Y
time the counter
M .TW
1
. the TOP orM BOTTOM value. W O W O
When W
W
.1
changing the TOP
.CO .TW
M value the program WW must ensure
Y .COthat the W
new TOP value
W WW is higherYor
0 .CO .T
W 0 Y W 0 0 .T 1 0
equal to the
W .10value ofOall M of the Compare Registers. W.1 If Y the O
C
TOP M value is lower than W
any .
W of the .C OM
.C W . W W the OCR1x. 0 Y
WW Registers,
Compare Y a compare
.100 usingOfixed
W match will
M.TTOP values, the W
W never .occur 100 between M.T
the TCNT1 and
W.of 10
Note that W when W
unused bits . C
are O masked to zero when W any the
WWRegisters .C W 00Y .TWillustrates,W
OCR1x . 1 00Yare written. M .TAs the third
W
period shown . 1 in Figure M 16-8 changing the
W W Y . C O
W W WW 00Y.CO .TW
TOP W actively while 0
0 the Timer/Counter .T is running in .the 1 phase correct M mode can result in an
W 00 .T W
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 107
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10
Wunsymmetrical OMoutput. The reason W forW
.1 OM in the time of update of the OCR1x Reg-
W Y .C W W
this can be
0 Y .Cfound .TW
W ister.
. 1 00Since theMOCR1x .T update occursW 0
at.1TOP, theOPWM M period starts and ends at TOP. This
W W .C O W Y .C W
.TW Y W W 0
10determined T
M.by the previous TOP value, while the
M
W implies
W . 100that the O
.T of the falling slope
length
M W .is
C O
.CO .TW WWlength.1of the.Crising slope
00Y of theM
is determined
.TW will differW
Wby the 0new 0Y.TOP value. .TWWhen these two values differ the
. 1 00Y M two slopes period in W
length. . 1The O
difference M in length gives the unsymmetrical
W Y.CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW
0 0 result on
.1 the output. M
W .1 correct
.100 M.T W.1 Y.COtoMuse the
It is recommended phase and frequency
WW .CO .is
Mmode instead of the phase correct
WW 00Y.CO .TW W
mode W when
1 0 0
changing the. T W
TOP value W
while the 0 0 Y
Timer/Counter
. 1 M TW running. When using a static
. 1 O M W . O M W . C O
W
WW .100Y.C M.TW
TOPW
W value .there .C practically
Yare .TW
no differences WW between .100
Ythe two modes
M.T
W of operation.
W 100 O M W O
W O .C mode, WW .C .TofWPWM waveforms on the
WW .100Y.C M.TW WW correct
In phase
. 1 0 0YPWM M .TW the compare units allow
. 1 00Ygeneration M
W O
W O OC1x pins.
WWSetting .COCOM1x1:0
the bits to 2 will Wproduce C
a .non-inverted
00toY3 (SeeM
PWM and an inverted
.TW16-2 on page 112). The
WW .100Y.C M.TW PWMWoutput can . 1 00beYgenerated M .TbyWsetting theWCOM1x1:0
W . 1 O Table
O WWvalue00will O Y.Cdirection
W
WW .100Y.C M.TW actualW OC1x Y.C only be .visibleT W on the port WWpin if .the 1 0 0data M .TW for the port pin is set as
W . 1 O M W C O
W O C W . .TW the OC1x Regis-
WW .100Y.C M.TW ter at the
output
WW .100Y.
(DDR_OC1x). The PWM
M .
waveform
TW is generated
W .
by
1 00Ysetting (or
M
clearing)
compareW match CO between OCR1x and W TCNT1 W when O counter increments, and
the
W O
WW .100Y.C M.TW clearing (or WW setting) 0 0
the Y.OC1x .T
Register W at compare W match . 1 0 0Y.C OCR1x
between M .TW and TCNT1 when
. 1 M W O
W O WW 00YThe .COPWM.T WW .C phase
00Y usingM .TWcorrect PWM can
WW .100Y.C M.TWthe counterWdecrements. . 1 M
W
frequency for the output1when
W . O
O W O . C
W
WW .100Y.C M.TW
be calculated
WW .100Y.C M.TW
by the following equation:
WW .100Y M .TW
W O f W O
W O
WW .100Y.C fM
clk_I/O
W - Y.C .TW
WW .100Y.C M.TW
= ---------------------------
.TW
OCnxPCPWM 2W ⋅ N ⋅ TOP.100
W O M
WW .100Y.C MThe .TWN variable W represents . 1 the prescaler M divider (1, 8, 64, 256,Wor 1024). O
W O W C O W Y.C
W W 00Y
.C W
.T extreme values
W
W for the 1 0 Y
0OCR1x
.
M
W
.T represent specialWcases W .100 whenOgenerating M .TW
. 1 M The . Register a PWM
W W Y .C O
W W WW 0 Y .CO PWM .T W W W 0 0 Y.C .T W
W
W .100 O
waveform output
M.T will be continuously
in the phase
W .10 correct
.C
M
Oset
mode. If the OCR1x
W W.1 Y.COM W
is set equal to BOTTOM the
C W .TW
WW .100Y.
output low and if equal to TOP the output will be continuously high for
M .TW W .1 00Y M
W
W . 100 O M .T
W non-inverted PWM mode.
O
WWthe TOP
W For inverted .COPWM.Tthe W output willWhave W the 0opposite 0Y.C M.TW
logic values. If
WW .100Y.COCR1A .T Wused to define
is . 1 0 0Yvalue M
(WGM13:0 = 11) and COM1A1:0 .1 = 1, the
O OC1A output
W W .C OM
W
W
Wcycle. Y .CO .TW W WW 00Y.C .TW
W 00 Y will toggle .T with a 50% W
duty
. 1 0 0 M .1 M
. 1 M W O W O
WW and
W
0 Y.C
O
0
16.8.5 Phase
W W. 1 Frequency
.C OM Correct
W
PWM Mode
W Y
00The phase W .1
W.1 mode O M.T and frequency correct Pulse
W.1 Width C OModulation,
M or phase andW
W
frequency OM PWM
correct
.CPWM
W W 0 0 Y .C (WGM13:0
.T W = 8 or 9) W W
provides a
1 0 0 Y
high . resolution
M .T W phase and W
frequency .1 0 Y
correct
0 M .TW
wave-
1
W. form M .
Wand frequency O correct PWM modeWis, like theYphase W O
.C correct
CO
.generation option. The phase
WW .100Y.C M.TW W 00 W
WW .1PWM 00Y mode, M .T
based
W
on a dual-slope W operation. OThe counter counts W
repeatedly .1 from O M.T
BOTTOM
W .CO .TW .C WW .Output Y. C
WW .(0x0000) 00Y to TOP and then from WW 00Y
TOP to.1BOTTOM. M TW
In .non-inverting Compare 100 mode, M .TW
the
1 M W O W O
W
WW Output 0 .CO .T(OC1x)
YCompare W is clearedWW on the 0 Y.C match
0compare .TWbetween TCNT1 WW and . 1 0Y.C while
0OCR1x M.T
W
.1 0 M W . 1 O M W C O
WW mode,
W upcounting, O and
Y.Coperation
set
.TW
on the compare match
WW .100Yoperation
while
.C downcounting.
W
.Tgives
In
WW .100Y.
inverting Compare Output
.TW
. 1 00the M is inverted. The dual-slope M a lower maximum W operation O M
fre-
W Y.C
O W
WWoperation. CO
0Y.However, W to the symmetric WW .feature .C
00Y of theM.TW
WWquency 0 0compared to
.T W single-slope
the . 1 0 M . Tdue 1
W W. 1
dual-slope PWM
. C OM modes, W these modes WareWpreferred Y .Cfor O motor control applications.
W W WW 00Y.CO .TW
Y W 0 M. T
W
Wmain.100 .T
OM between the phase W .10
. C O W W.1 Y.COM W
. C W W
W W
The
00Y
difference
.TW W correct,
.10by 0 Y
and the phase and
M.T Buffer Register,W
W
frequency
.100 PWMOM.T
correct
modeWis.1the timeCthe O MOCR1x Register is updated W the O
OCR1x (seeW FigureY16- .C
W W 0 0 Y . .T W WW .100Y.C M.TW W . 1 00 M.T
W
8 and Figure . 1 16-9). M W O W O
WW
W .CO .TW W 00Y PWM
.C W WW .100Y.C M.T
PWM.1 00Y W . 1 M .T O
The
W W resolution
.C O M
for the phase
W
and frequency
WW is02-bit
correct
Y .CO .TW
mode can be defined
W WWby either 0 0 Y.C
ICR1W or OCR1A. 00 Y The minimum .T resolution W allowed 0 (ICR1 or OCR1A set to 0x0003), .1 and
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10maximum OM .1 M
W Wthe Y .C resolution is 16-bit (ICR1
W W WW or OCR1A 0 Y .COset to.TMAX). W The PWM resolution in bits can
W 00
be.1calculated using
M .T the following equation: . 1 0 M
W
O M.T W .1
C OM W W.1 log .C OM )
( TOP + 1T
00 Y .C
.T W W W
1 0 0 Y . .T W W
R . 1=0 0 Y . -W
----------------------------------
M
. 1 M W . O M PFCPWM W log (
O 2 )
W
0 Y.C
O
1 0 O
W. .C OM
W
InW W andYfrequency
phase .CO .Tcorrect W
PWM mode
W WWthe 0counter 0 Y.C is incremented .
until the counter value
TinWOCR1A (WGM13:0 = 9). The
0 0 Y .T W 1 0 0 . 1 M
.1 M matches
W. either the OMvalue in ICR1 (WGM13:0
WW the
= 8), or the
.CO .TW
value
WW 00Y.CO .TW WW has
counter 0 0 Y.Creached
then .T W TOP andWchanges
the . 1 0 0Ycount direction.
M The TCNT1 value will be
W .1 O M WTOP .1 M
Otimer W W diagram . C Ofor
.C equal W to forY . C
one clock
W cycle. The timing 0 Y the W
phase correct and frequency
WW .100Y M .TW W
correct PWM . 100mode isOshown M .T on FigureW 16-9. W
The .10figure O
shows M.Tphase and frequency correct
W O W .C W .C
WW .100Y.C M.TW PWM WW mode .when 1 00YOCR1AMor W is usedW
.TICR1 to define . 00Y The TCNT1
1TOP. M .TWvalue is in the timing dia-
O W O
W O WW as 0a0histogram Y.C WW .C
00Yoperation. W diagram includes non-
WW .100Y.C M.TW gramW shown
. 1 M .TW
for illustrating the dual-slope
W . 1 O M.T The
W O inverted and W invertedYPWM O
.C outputs. W C
Y.marks on.Tthe
WW .100Y.C M.TW sent compare WW matches 00 between W The smallWhorizontal
.TOCR1x .
line
100OC1x Interrupt M
W TCNT1 slopes repre-
. 1 M and TCNT1. W The O Flag will be set when a
W W Y . C O
W W WW occurs. 0 Y .CO .TW W W 0 0 Y.C .T W
W .1 00 M .T compare match . 1 0 M W . 1 O M
W O C
W O
WW .100Y.C M.TW Figure 16-9. WW .100Y.C M.TW WW .100Y. M .TW
W and Frequency O W O
WW .100Y.C M.TW
W O Phase Correct PWM Mode, Timing Diagram
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO OCnA . W
TInterrupt Flag Set
W 0 0 Y .T W 1 .1 M
or ICFn Interrupt Flag Set
W.1 OM W. OM W O (Interrupt on TOP)
W W .C O
W WW 00Y.CO .TW W WW 00Y.COOCRnx ./ T W
W 00 Y .T W . 1 M .1 M TOP Update
. 1 M W O W O
and
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .100Y.CTOVn .TW
Interrupt
M
Flag Set
W O W O
(Interrupt on Bottom)
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O TCNTn
W W .C O
Y W
W 00
W.1 Y.COM OCnx
.T W.1 Y.COM W W W.1 (COMnx1:0 Y .CO
M
= 2)
W
W W 0
W W
. 1 00 M .TW W
W .100 O M .T W .10 O M.T
W O WW (COMnx1:0 .C
WW .100Y.C M.TW
OCnx
WW .100Y.C M.TW . 100
Y = 3)
M .TW
W O W O
W
WW .100Y.CPeriodM.TW 1
O
WW 2.100Y.C 3 M.TW 4 WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M
W.1The Y OM W.1 Y.COM W WW CO
.the
W W 00
.C
Timer/Counter .T W Overflow W W
Flag (TOV1)
1 00 is set at
M the.T same timer Wclock cycle
. 1 0 0
asY OCR1x
M .TW
. 1 M . W O
WRegisters .CO are updated with the double
WW buffer
W .CO (at BOTTOM).
0Yvalue TW WhenWW either OCR1A .C
00Y or ICR1 W
WW is.1used 00Yfor defining M .T W
the TOP value, the
W . 1
OC1A
0 or ICF1 O M .
Flag set when TCNT1 Whas. 1 reached O M.T
TOP.
W .CO .Tcan .C W Y. C
WW The.1Interrupt00Y Flags W then be used WWto generate 1 00Y an interrupt M .TWeach timeW the counter .100reachesOthe M .TW
M W . O W
W
WWTOP.1or00BOTTOM Y.C
O value.
W W changing .C OM WW must Y CO that
.ensure W W W W
0 Y .COor .TW
When Y the TOP W value the W program 0 M. T the new TOP value is0 higher
W 00
W.1to theYvalue
.T
OMof all of the Compare W .10
CIf O W W.1any Y of.C
OM
equal
W
WCompare 0 0 .C
.T W W W Registers.
1 0 0 Y . the TOPW
M .T value is lower W than
. 1 0 0 the
M.TW
1
. Registers,M a compare match will never .
W occur between O the TCNT1 and W W
the OCR1x. .C O
W WW 00Y.CO .TW WW .100Y.C M.TW W .100
Y
M.T
W
. 1 M W O W O
0Y.C M.T
As Figure 16-9 shows the output generated is, in contrast to the phase correct mode, symmetri-
WW
W .CO .TW WW are.1updated 00Y at M
.C .TW the length WWof the 10rising
cal in all periods.
. 1 00Y SinceMthe OCR1x Registers BOTTOM, W . O
and W
the
Wfalling Y
slopes .C Owill always be equal. This
W W WW gives 0 Y .CO .T
symmetrical W
output pulses W
and
Wis therefore 0 0 Y.C
W .100 .T W.1 Y.COM W
0 .1
frequency W Wcorrect. . C OM
W W W WW
W 00 Y .T W 0 0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 the ICR1 OM Register for defining .1 M
W WUsing Y .C W W WW TOP works
0 Y .CO well when
.
using fixed TOP values. By using
TWa PWM output on OC1A. However,
W ICR1,.1 0 0 the OCR1A .T Register is free to be .
used1 0 for generating M
WW .C OM W
Wchanged Y.C
O
W
.T W W if the 0
base
0 Y PWM T
frequency
. W is W
actively . 1 0 0 by changing M.Tthe TOP value, using the OCR1A as
M W . 1 O M W C O
.CO .TW WWTOP .is10clearly 0Y.C a better .TW
choice due to WitsWdouble00buffer Y. feature. .TW
. 1 00Y M W and O M W . 1 O M
W Y.C
O
WWIn phase 0Y.C frequency TW correct PWM W the00compare
Wmode, Y.C units W
allow generation of PWM wave-
. 1 0 0 M .T W
W . 1 0
O M . W .1 O M.T
W O forms on the OC1x
Y.C output
pins. Setting the COM1x1:0
WW by .setting
bits to
.C 2
0Y the COM1x1:0
will produce a non-inverted PWM and
TW to 3 (See Table on page
0 0 Y.C .T W WanWinverted 1 0 0PWM .T W be generated
can 1 0 M .
.1 M W. OM W O
Y.Cport pin.T
WW 00Y.CO .TW WW The.1actual
113). 0 0Y.COC1xMvalue .TW will only be WW visible .on 1 00the M if Wthe data direction for the port
. 1 O M W O W . C O
W
WW .100Y.C M.TW
pin isWset as output Y.C(DDR_OC1x). .TW match between
The PWM WWwaveform .100 and
Yis generated .TWby setting (or clearing) the
OC1x
W
Register
W . 100 at theOcompare M W OCR1x O M
TCNT1 when the counter incre-
W O Y.C (or setting) W .C
0Ycompare TW between OCR1x and
WW .100Y.C M.TW ments,WWand .clearing 0 0 . T W the OC1x WRegister . 1 0 at M .
match
W .C O W W 1the counter Y
M
.CO decrements. W WWfrequency 0
O
Y.C for the.Toutput W when using phase
W Y W TCNT1 W when 0 0 .T The W PWM
.1 0
W .1 00 M .T W . 1 O M W C O M
W O
WW .100Y.C M.TW
and frequency correct PWM can be calculated by
WWthe following Y. equation: .TW
WW .100Y.C M.TW Wf . 100 O M
W O W O =W
clk_I/O .C
WW .100Y.C M.TW WW .100Y.C M.T f OCnxPFCPWM
W W 00-Y
---------------------------
2 ⋅ N ⋅.TOP 1 M.T
W
W O W C O
W O
WW .100Y.C M.TW The N variable WW represents .C
00Y the prescaler .TW divider (1, WW .100Y. M .TW
W . 1 O M 8, 64,W 256, or 1024).
O
W O
WW .100Y.C M.TWThe extreme WW 00theY.C W
.TRegister WW .100Y.C M.TW
. 1 M
W W .C O values
WW
for
Y
OCR1x
.COcorrect W
represents
W WW special cases
0 Y .COwhen.TgeneratingW
a PWM
Y W W 0 M. T 0
W
W .100 O M.T
waveform output in
W .10
the phase
. C O
PWM mode. If the
W W.1 Y.COM W
OCR1x is set equal to BOTTOM the
W
WW .100Y.C M.Toutput W will beW continuously
. 0Ylow andMif.Tset
10inverted
W equal to TOP W the output
W
0 will beMset
.10opposite O
.T to high for non-
O inverted PWM mode. W For O PWM the output will have the .C logic values.
W If OCR1A
W
WW .100Y.C Mis.Tused W to define WtheW .C
00Y (WGM13:0 .TW= 9) and COM1A1:0 WW .100Y M .T
TOP . 1value M = 1, the OC1A output will toggle
W W .C O
W W W Y .C O
W W WW 00Y.CO .TW
W .100
Y with
M.T
a 50% duty Wcycle. 00 .T W.1 Y.COM W
WW .100Y M .TW W
W . 1 00
O M .T W
W .100 O M.T
16.9 Timer/Counter
W O Timing DiagramsW .C WW .100Y. C
WW .100Y.C The TW
.Timer/Counter W 1 00Y design M .TandW M .TW
M is a .
synchronous the timer clock W
(clk ) is O
therefore shown as a
W O WW 00Y.CO .TW W T1 00Y.C W
WW .100Y.Cclock M .T
enableW signal W
in the following
. 1 figures. M The figures W
include .1
information
W onO M T Interrupt
when.
W O are set, and when W W .C O W OCR1x C
Y. value.T(only W for
WW .100Y.C Flags
M .TW W the OCR1x . 1 00YRegister M .isTWupdated withWthe
W .100buffer O M
O utilizing double buffering). O
W Figure 16-10 shows a timing diagram .C of.OCF1x.
W
WW .100Y.C M.TW
modes
WW .100Y.C M.TW WW for . 1
the setting
00Y MT
W
W O W O W W .C O
WW .100Figure Y.C 16-10. .TWTimer/Counter WWTiming . 1 0Y.C M
0Diagram, .TW of OCF1x,WNo Prescaling
Setting . 100
Y
M .TW
M W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y clk I/O .T W .1 M
W W 00 .T W
W 00
W.1 Yclk O M.T W.1 Y.COM W W W.1 Y.COM W
.C W
W W
.1 00(clkI/OTn/1) M.TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
O W O
W .CO .TW WW OCRnx 0Y.C M.TW OCRnx + 1 W
W 00+ Y
.C W
WW .1TCNTn 00Y M OCRnx - 1 W
W . 1 0
O
OCRnx
W . 1 2
O M.T
W O WW .100Y .C
W O W O
W
WW OCRnx 0 Y.C
O
.T W WW .OCRnx 0 0Y.C Value M.T
W WW .100Y.C M.TW
0 1
W W. 1
.C OM
W 00 Y .T W .1 M
W W 00 .T W
W OCFnx
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W shows theOsame timing data, but with W
WW the.1prescaler .CO enabled.
WW .100Y.C M.TW
Figure 16-11
00Y M .TW
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
W WFigure Y .C W W WW Diagram, Setting
0 Y .CO of.TOCF1x, W with Prescaler (fclk_I/O/8)
W .1 0 0 M .T . 1 0 M
W
O M.T W .1 clk
.C W W
Y W .100 .T
I/O
00Y .TW W .100 M.T OM
00 .T WW .clk 10Tn0 M .TW W .100 M.T
. 1 M W O W .C O
W .CO .TW WW (clk.I/O 0/8)0Y
.C .TW WW .100Y .TW
. 1 00Y M W 1 O M W O M
W. 1 OM W O
W Y.C W W W W
TCNTn
0 Y .CO OCRnx .T W -1
W W
OCRnx
0 0 Y.C OCRnx .TW
+1 OCRnx + 2
W 0 0 .T . 1 0 M .1 O M
W.1 OM W O W
WW .100Y.C M.TW
W ValueY.CO
W .C O WW 00Y.CO .TW
OCRnx WOCRnx W
W W
.1 00 Y
M .T W W
W . 1 O M
W
W .100 O M.T
W O WW .100Y. C
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
OCFnx WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O Figure 16-12W WW the0count
shows Y .CO sequence W close to TOPW W in
W
various 0 Y .CO When
modes. .TWusing phase and
W 00 Y W
.T frequency correct PWM . 1 0 M .T .1 0 M
. 1 M W mode O W O
W O
WWbut TOP Y.Cthe OCR1x Register is updated
WW .at Y.C
BOTTOM. TheW timing diagrams
WW .100Y.C M.Twill Wbe the same, . 1 00should M
be TW
.replaced by BOTTOM, W 100 by BOTTOM+1
TOP-1 O M .T and so on.
W C O WW O
.Cmodes W Y.C W
W Y. The W same renamingW applies 0 0 Y
for . T
thatW set the TOV1 W Flag at
.1 0 0
BOTTOM. .T
W .100 .T 16-12. Timer/Counter W 00 M.T no PrescalingWW.1 OM
W .C O MFigure
W W.1 Timing Y .C ODiagram,
W 0 Y.C W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W O
WW .100Y.C M.TW clkI/O W
W 00Y
.C .TW WW .100Y. M .TW
W .1 O M W O
W
WW .100Y.C M.TWclk
O
W W .C O
W
Tn
W 00 Y .T (clk /1) W .1 M
I/O
W W W
W
W .100 O M.T TCNTn
W
W .100 OM TOP
.T
W W.1 Y.COM W
C W .C
WW .100Y. (CTC M TWFPWM)
.and W TOP -
.
1
1 00Y M .TW W
BOTTOM
W . 100 BOTTOM O M
+ .1T
W O
W
WW .100Y.C M
O
W .C
TCNTn
Oand PFC PWM) WW
TOP -1
Y .CO TOP .TW TOP - W
W 1
W
0 .CO
YTOP -2 W
W W
.1 00 Y (PC
M .T W W
W . 10 0
O M W .1 0
O M.T
W CO (FPWM) WW .100Y. C
WW .100Y.TOVn .TW WW .100Y.C M.TW M .TW
M W O W O
W
WW .100Y.Cas TOP)
and ICFn O (if used
M W O
W CO WW 00Y.CO .TW WW .100Y.C M.TW
WW .100Y.OCRnx . T W W 1
at M
Old OCRnx W.Value OM W
New OCRnx Value O
W (Update O
WW .100Y.C M.TW
TOP)
W W .C O
Y W
W 00
W.116-13Yshows
.T
OMthe same timing data, W .1
.C OM W W.1 Y.COM W
Figure . C W but with the prescaler W enabled.
W W
.1 00 M .TW W
W . 100
Y
O M .T W
W .100 OM.T
W O WW .100Y .C
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
W WFigure Y .C W W WW Diagram, with
0 Y .COPrescaler .
(f
TW clk_I/O
/8)
W .1 0 0 M .T . 1 0 M
W
O M.T W .1 clkI/OOM
.C W W.1 Y.COM W
.C W W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W .C O W W Y .C W
00 .T WW .100clk YTn .TW W .100 M.T
. 1 M W (clk /8) OM W .C O
I/O
WW .100Y .TW
. 1 00Y M W O W .C O M
WW 00Y.CO .TW WW(CTCTCNTn 1 0 Y.C
0FPWM) .TW TOP - 1 W
W
. 1 00Y
TOP
M
W
.TBOTTOM BOTTOM + 1
. 1 O M W .and
O M W . C O
W
W
W O W O
W O TCNTn
Wand PFC0PWM) 0Y.C M.TW WW TOP Y.C .TW
WW .100Y.C M.TW W(PC . 1
TOP - 1
W . 100 O M
TOP -1 TOP - 2
W O W O W .C
WW .100Y.C M.TW
W (FPWM) Y.C .TW W .100
Y
M.T
W
WTOVn
W . 100 O M W C O
W
WW .100Y.C M.TW
O and W
W ICFnas TOP).10
(if used Y.C
0 .TW WW .100Y. M .TW
M W O
WW .100Y.C M.TW WOCRnx . 1 M W O New OCRnx Value
W O
W O WW .100Y.C M.TW
Old OCRnx Value
WW .100Y.C M.TW W at TOP).100Y.C M.TW
(UpdateW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W16.10 Register
00 Y Description
.T W 0 0 .1 M
W W
W 100
16.10.1 W.TCCR1A M.T
–OTimer/Counter1
W
Control .100 AOM.T
WRegister W W.1 Y.COM W
.C W Y .C W W 00 .T
WW .100Y M.T
W W .100 M.T W.21 Y.C1 OM 0W
W O W .C O W
WW .100Y.C M.TW
Bit
WW COM1A0
7 6 Y
.100 COM1B1
5 W 4
M.TCOM1B0 FOC1A WFOC1B
3 W .100 WGM11OMWGM10 .T
W O COM1A1 W O W . C TCCR1A
W Y .C W W W R/W 00Y.CR/W .T W W 0 0 YR/W .T W
W 00 .T
Read/Write R/W
.1 OM 0
R/W W W .1 OM 0 R/W
W W.1 Y.COM Initial Value

W 0 WW0 00Y.C 0 W 0 W W0W 00Y 0 .C
.TW
W 00 .T W .1 M .T . 1 M
. 1 M W O
W O
WWCompare
W .CO .TW WWunit A.100Y.C M.TW
WW .100Y.C• Bit . T
7:6 W– COM1A1:0: . 10 0YOutput MMode for Compare
W W .C OM
W 00 Y .T– COM1B1:0: Compare W .1 M
W.1 Y•.CBit OM 5:4
W W.1 Output Y .C
M for Compare unit
OMode
W W W B
0 Y .CO .TW
W W and COM1B1:0 W 00 the M .T W 0
W
W .100 The O M.T
COM1A1:0 W .1control
C OOutput Compare pinsW(OC1A W.1 and .COC1BOM respec-
W Y .C
tively) behavior. W If one W
or W
both of the
0 0 Y .
COM1A1:0 .T W bits are W
written to one,1 00 Y
the OC1A TW
.output
W . 1 00 M .T W . 1 O M W . O M
C both ofTW
W
WW .10COM1B1:0 0Y.C Mbit
overrides O the normal port functionality
.TW WW .100Y of.C the I/O pin
.TWit is connected WW to. .If10one 0Y.or M . the
are written to one, W M
O overrides the normal W O
W .CO connected WW note
the OC1B.C output
Y the Data .TW WW .100bit Y.C
port functionality of the
.TW
WW .1I/O 00Ypin it isM .TW to. However, . 1 00that M Direction Register (DDR) W M
correspond-
O
W O .C
WW .ing
W .CO .Tor WOC1B pin W W be set00inYorder .C to enable .TW the output WW driver. .100Y .TW
1 00toYthe OC1A M
must
.1 M W O M
W .CO WW .to
W CO the function
0Y.pin, TW of theW
W 0Y.C W
WW When .1 0 0 Ythe OC1A.T
M
orW OC1B is connected
W 1 0 the
O M . COM1x1:0
W .1 0bits
O M.T
is depen-
W .CO .C the.TCOM1x1:0 W .C
Ywhen the.TW
WW WGM13:0
dent of Y the
00 bits are
WGM13:0
.TsetWbits setting. WW Table 16-2
. 1 0Yshows
0mode M
W bit
Wfunctionality.100 M
W . 1 O M to a normal or a W
CTC O
(non-PWM).
C W W .C O
.C W Y . W W 0 Y W
W W
.1 00Y M .TW W
W . 100 O M .T W .10 O M.T
W 16-2. O .C WW .100Y .C
Table
WW .100Y.C M.TW
Compare Output Mode,W
W non-PWM 100Y M .TW M.TW
W . O W O
W
WW .100Y.C M.TW
COM1A1/COM1B1 O COM1A0/COM1B0
WW .10Description 0Y.C M.TW WW .100Y.C M.TW
O operation, OC1A/OC1BWdisconnected. W O
W 0 Y.CO 0 WW Normal Y .Cport W W 0 Y.C W
W W
. 1 000 M .T W W
W .1 0 0
O M .T
W .1 0
O M.T
W
WW .100Y.C M.TW
O 1
WW .100Y.C M.TW
Toggle OC1A/OC1B on compare match
WW .100Y.C M.T
.CO .on Woutput Y.CO
W 1 Y.CO 0 WWClear00OC1A/OC1B W compare matchW (Set
W W
. 1 00 M .T W W
W
Y
1 level) OM
to .low T W
W .100
W O .C W
WW 1 .100Y.C M.TW 1 WW Set .OC1A/OC1B 1 00Y on
M TW match W
.compare (Set output to
W O W
WWhigh level) .CO .TW
WW .100Y.C M.TW . 1 00Y M
W W Y .C O
W W WW 00Y.CO
W 00 .T W.1
W W.1 Y.COM W W
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 16-3Oshows M the COM1x1:0 W .1 M
W WTable Y .C W W
bitWfunctionality
0 Y .COwhen.Tthe W WGM13:0 bits are set to the fast
W PWM.1 0 0mode. M .T . 1 0 M
W
O M.T W .1
.C OM W W.1 Y.COM W
.C W 00Y Compare W W Fast .PWM 100 (1) OM.T
00Y .TW W Table.116-3. M.T Output Mode, W
W.1 Y.COM W W
0Y. C O W
00Y
.C W
0 0 .T WWCOM1A1/COM1B1
. 10 M . W
TCOM1A0/COM1B0 W .1
Description M.T
. 1 M W O W .C O
W .CO .TW WW .100Y.C M.TW 0 WW Normal Y
100port operation, .TW
. 1 00Y M W O W .
.C O M OC1A/OC1B
WW 00Y.CO .TW W W
1 0 0 Y .C
.T W W Wdisconnected.
. 1 0 0 Y
M .T W
W. 1 OM W . O M W O
.C Toggle.T
WW .100Y.C M.TW WW 0.100Y.C M.TW 1 WW WGM13:00=Y15:
.1 0 disconnected M
W on Compare
OC1A
W O W C O Match,
W W OC1B
.C O (normal port
W .C W W Y . W W 0 Y .T W
W .100
Y
M.T
W 00
W.1 Y.COM W
.T operation). .10
Wother OMsettings, normal port
W O W .C
WW .100Y .C
.TW W W
100 M .T WFor all
0 Y
WGM13:0
0
.1OC1A/OC1B M .TW
M W . O operation, W C O disconnected.
W
WW .100Y.C M.TW
O
WW1 .100Y.C M.T0W WW .100Y. on compare
Clear OC1A/OC1B M .TWmatch, set
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW WW .1at0BOTTOM,
OC1A/OC1B 0Y.C M.TW
W O W O
WW .mode)
W .CO .TW
WW .100Y.C M.TW
(non-inverting
WW .100Y.C M.TW 1 00Y M
W W .C O 1 WW
Y . C O1
W Set OC1A/OC1B
W W W on compare
0 Y .CO match, .TW
clear
W 0 0 Y .T W W . 1 0 0 M .T OC1A/OC1B W 1 0
at .BOTTOM, M
W. 1 OM W O W .C O
WW .100Y.C M.TW WW .100Y.C M.TW (inverting Wmode) .1 00Y M .TW
O W O W .C O
W
WW .100Y.C M.TNote: W 1. A special WW case 0Y.CwhenMOCR1A/OCR1B
0occurs .TW WW TOP.1and
equals 00YCOM1A1/COM1B1 M .TW is set. In
. 1
W compare O is ignored, but the setWor clear is done W O
W O this case Wthe match .C at BOTTOM. See “Fast
WW .100Y.C M.TW PWM WMode” on. 1 0Y.C
0page 104. forM .TWdetails. W W.100Y OM.TW
more
W O Table 16-4 shows the W O W Y.C are set
WW .100Y.C M .TW WW COM1x1:0 0 0 Y.Cbit functionality
.TW whenW the WGM13:0 .100 bits O M .TW to the phase
W . 1 O M W C
W O correct or the phase W Y.Ccorrect,.TPWM W Y . W
WW .100Y.C M.TW W and frequency . 100 M
W mode. W .100 M.T
W O W C O
W O
WWOutput Y.C Phase W and 0Frequency Y. .TW PWM
WW .100Y.C Table M .TW
16-4. Compare
(1) .1 00Mode, M .TW Correct and W Phase
W . 1 0 O MCorrect
W O
W O
WW .100Y.C COM1A1/COM1B1 .T W WW .100Y.C M.TW WW .100Y.C M.TW
W W .C OM
W WW 00Y.CO Description
COM1A0/COM1B0
W W WW 00Y.CO .TW
Y W .T
W 00
W.1 Y.COM 0 W
.T W.01 Y.COM Normal port operation, W W.1 Y.COM W
OC1A/OC1B
W W
W W
. 1 00 M .T W
W .100 O
.T
disconnected.
M
W
W .100 O M.T
W O WW OC1A .C
WW .100Y.C M0.TW WW 1 .100Y.C WGM13:0 M .TW= 9 or 14: Toggle . 10on0Y M .TW
W O W O
W O
WW .100Y.Cport M
Compare W Match, OC1BW W
disconnected Y.C
(normal
.TW
WW .100Y.C M.TW .T
operation). W .100 O M
O W O Y.C
W
WW .100Y.C M.TW WW .100Y.C For all other .TW WGM13:0 settings, WW normal .1 00port M.T
W
W O M W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
operation, OC1A/OC1B disconnected.
WW .100Y. M .TW
O W O W
match whenY.C O
W
WW .100Y.C M.TW
1 0
WW .100up-counting. Y.C OC1A/OC1B
Clear
.T W on compare WW .100 M.T
W
W O M Set OC1A/OC1B on compare W C O
W
WW .100Y.C M.TW
O
WW .10match 0Y.CwhenMdowncounting..TW WW .100Y. M .TW
W O
W 1 O 1 WWW Set0Y .CO .Ton WWwhen.1up- 00Y
.C W
WW .100Y.C M.TW Wcompare match
OC1A/OC1B
W .1 0
counting. O M
Clear OC1A/OC1B on compare W O M.T
W O .C WW .100Y .C
WW .100Y.C M.TW WW match 1 00Ywhen downcounting.
M .TW M.TW
. O W O
WW 1.00AYspecial .CO case W occurs whenW
WW 00Y.equals C
.TW WW .1is0set. 0Y.C SeeOM.T
W
WNote: 1 .T
M PWM Mode” on page OCR1A/OCR1B . 1 MTOP and COM1A1/COM1B1
W
W. “PhaseOCorrect W forYmore .COdetails. WW .100Y.C M.TW
WW .100Y.C M.TW WW 106. .1 00 M .TW
W O W O
W3W– FOC1A:
•WBit 0 Y
O
.CForce .T W
Output Compare W Wfor 0
Compare 0 Y.C unit A.TW WW .100Y.C M.T
0
W.1 Y.COM W .1 M WW 00Y.CO
W W WW 00Y.CO .TW W
W .100 Force .T W.1 Yunit OM .1
• Bit 2 –W
W
FOC1B:
.C OMOutput Compare for
W W Compare
. C B
W W WW
Y W the WGM13:0 0 0 .T
TheW FOC1A/FOC1B
W .100 bits O
are.Tonly active when
M W W.1 Y.CO bits
Mspecifies a non-PWM mode.
W .C W with future W
Y compatibility W devices, .100
However,
W for ensuring these bits.T must be set to zero when
W .100 O M.T W W . C OM
WW .100Y. C W Y
W O M.T
W
W .100
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OM .1 M When writing a logical one to the
W WTCCR1A Y .C is written when operating
W W WWin a00PWM Y .COmode. .TWon the Waveform Generation unit.
W . 1 00
FOC1A/FOC1B M .T an immediate compare
bit, W . 1 match O is Mforced
W O .C
.T W WW The.1OC1A/OC1B 0 0Y.C M.output TW is changed WW according . 1 00Y to itsMCOM1x1:0 .TW bits setting. Note that the
O M W C O W W .C O
.C W FOC1A/FOC1B . bits
.TW
are implemented as strobes.
0 Y Therefore W it is the value present in the
. 1 00Y M .TW W
COM1x1:0 . 1 00Ybits that M determine the
W
effect ofW .
the
10forced O M
compare.
.T
W O
W
0 Y.C
O
1 0 .CO
W. .C OM
W WW 00Y.COstrobe
A FOC1A/FOC1B will not generate
W W WW any interrupt
0 0 Y nor will itWclear the timer in Clear Timer
.T
0 Y T W . T 1
W .1 0
O M . on Compare
W . 1 match
C O (CTC)
M mode using OCR1A
W W .as TOP.
.C OM
W 0 0 Y.C .T W WWFOC1A/FOC1B 10 0Y .
M .TWalways read W . 1 00Y M .TW
W. 1 OM The W . Obits are as zero.
W O
W O W O
W
WW .100Y.C M.TW
O • Bit W
W 1:0 – WGM11:0: 0 0 Y.C Waveform .T W Generation WW Mode . 1 0 0Y.C M.TW
.1 M W O
W W Y .C O
W
CombinedW
W W with the 0 Y .CO .Tbits
WGM13:2
W
found in the W
W
TCCR1B
0 0 Y.C these
Register, bits control the counting
.TWand what type of wave-
W 0 0 .T sequence of the
. 1 0 counter, the
M source for maximum (TOP). 1 counter O Mvalue,
W.1 OM W CO seeTTable W
WW of operation 0Y.C supported .TW by the Timer/Counter
WW .100Y.C M.TW form generation WW .1to00beY.used, M . W 16-5. Modes . 1 0 M
CO W O
W O unit are: Normal WW mode .(counter), Clear Timer on WW Compare 0match
0 Y (CTC)
.C W and three types
.Tmode,
WW .100Y.C M.TW of PulseWWidth Modulation . 1 00Y (PWM) M .TW modes. (See “Modes . 1
W of Operation” M
O on page 103.)
W O
W
WW .100Y.C M.TW
O
WBit Description O (1) W O
W 16-5. Waveform
Table
WW .100Y.C M.TW
O Generation Mode
O of TOV1 Flag Set
W W Y .C OWGM12 WGM11 W
W W
W
WGM10
0 Y .CO .TWMode of WWW 00Y.C
Timer/Counter Update
.TW on
WMode .1WGM13 00 (CTC1)
M .T (PWM11) (PWM10) . 1 0 Operation M WTOP .1 OCR1 O M
x
O W O Y.C
W
W0W .1000Y.C M 0 .TW WW0 .100Normal Y.C .TW WW 0xFFFF . 100 Immediate M .TWMAX
0
W O M W O
W O
Y.C 0 .TW 0 WW 0Y.C TW8-bit WW0x00FF Y.C
00TOP W
W1W
. 0
1 0 0 M 1
W . 1 0
PWM, PhaseM
O
.
Correct,
W . 1 O M.T BOTTOM
2WW
W
0 00Y. 0
CO
.TW 1 W0W .PWM, .C
00YPhase Correct, .TW WW 0x01FF.10TOP 0Y.C M.TBOTTOM W
. 1 M 1 O M 9-bit
W O
W
3 WW 0 00Y. 0
CO W1 W WW PWM, 0 Y.C Correct,
0Phase . W
T10-bit
W
W0x03FF 1 00Y
.C .TW
. 1 M .T 1 . 1 O M W . TOP
O MBOTTOM
W .CO .TW W .C W Y. C
4 WW 0 00Y 1 0 0WW CTC100Y
M .TW W
OCR1A 100
Immediate
. MMAX.TW
. 1 M . W O
W O
1 WWFast PWM,
W .CO WW BOTTOM 00Y
.C W
5 WW0 .100Y1.C M.T0 W . 1 00Y8-bit M.TW 0x00FF
W .1 O M.T
TOP
W O C
Y. TOP .TW
WW
W .CO 1.TW 0 WW Y.C
009-bit .TW WW BOTTOM 100
6 0
001Y Fast PWM,
. 1 M
0x01FF
. M
. 1
W 1 Y.CO 1 W M W W Y . C O
W W WBOTTOM00Y.CO
W W
7 W 0 W
. 1 00 M .T 1 W Fast PWM,
W .100
10-bit
O M .T 0x03FF
W .1 TOP
O M.T
1 WW 0 Y.C 0 O .C W .C
8
W 00 .TW 0 W PWM,W Phase0and
1 0YFrequency M TW ICR1 W BOTTOM
.Correct .
Y
100 BOTTOM M .TW
. 1 O M W . O W W .C O
9 1 WW 0 Y.C 0 .TW 1 WWPhase.1and
PWM, 0Y .C
Frequency TW OCR1A WBOTTOM.100YBOTTOM
Correct .TW
W 1 00 M 0 M . W O M
W0. 1O PWM,W
W .CO .TW ICR1 W Y.C W
WW .100Y.C M.TW 00Y 00BOTTOM
10 1 0 W
W Phase Correct M.T
TOP
. 1 M W .1 O
W O C
11 1 W
WW .100Y.C M.TW
0 1O 1
WW Correct
PWM, Phase
00Y
.C .TW
OCR1A WW .10BOTTOM
TOP 0Y. M .TW
W .1 O M W O
1W 0 O WW .1MAX .C
12 1
WW .100Y.C M.TW
0 CTC
WW .100Y.C M.TW ICR1 Immediate
00Y M.T
W
W O W C O
13 1 1 W
WW .100Y.C M.TW
0 O 1 Reserved W
W 00Y
.C .TW
– –
WW .–100Y. M .TW
. 1 M W O
14 1 1 W 1 O 0 Fast PWM WW .CO .ICR1 BOTTOM W TOP Y.C W
WW .100Y.C M.TW W . 1 00Y M TW W
W .100 O M.T
W O .C
15 1 1
WW 00Y.CO .TW 1 1 .C W
Fast PWM OCR1A BOTTOM TOP Y W
WPWM11:0 WW the.1WGM 00Y 12:0 definitions. M .TW However,Wthe functionality .100 andOM.T
Note: 1. The CTC1 and . 1 bit definitionMnames are obsolete. UseW O W
location of these WW
Wbits are compatible
0
O
Y.C with previous.T W versionsWofW the timer.00Y.
C
.TW WW .100Y.C M.TW
0 . 1 M
W W. 1
.C OM
W Y
00Control Register .T W .1 M
16.10.2 TCCR1B – Timer/Counter1
W.1 Y.COM W
B
W W.1 Y.COM W WW 00Y.CO .T
W W
W .100 7 OM.T6
W
4 W.
100 3 OM2
.T
0 WW
.1
C OM
Bit W .C 5
W Y .C W
1
W 0 Y.
WW .100ICNC1 Y
M .TW –
ICES1 W WGM13 00
.1WGM12 CS12M.T CS11 CS10 .10
TCCR1B
W
W R/W.C
O W W .C O W
WW
Read/Write
000Y
R/W W R
.T W R/W R/W Y
.1000
R/W
.TW R/W R/W W
Initial Value W.1 O M0 0 0 W C 0 M
O 0 0
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1Bit 7Y–.CICNC1: OM Input Capture Noise .1 M
W W W WW Canceler 0 Y .CO .TW
W .100 this bit (to.T 0
Setting
W C OM one) activates the Input
W W.1Capture OM Canceler. When the Noise Canceler is
.CNoise
.TW
W
W activated, Y
100 the O
. input.T
M
W
from the Input Capture.1 W Pin 0 Y
0 (ICP1) isMfiltered. .TW The filter function requires four
M W . W C O
.CO .TW WWsuccessive C valued
Y.equal .TW samples W of W the ICP10pin Y.for changing .TWits output. The Input Capture is
. 1 00Y M . 1 00delayed M W . 1 0 the Noise O M
therefore by four Oscillator cycles when
WW .100Y.C M.TW
Canceler is enabled.
0
0
W.1 Y.COM W W W6.1– ICES1: Y
M
.COInput.T W WW 00Y.CO .TW
W • Bit 0 Capture Edge W Select
.100 M.T 10
W.selects OMedge on the Input W W.1 Pin .C OM
WW 00Y.CO .TW This
W W bit
1 0 0 Y .C
which
.T W W Capture
. 1 0 0 Y (ICP1) that
M .TWis used to trigger a capture
W. 1 OM event. When . the ICES1 M bit is written to zero, Wa falling O
(negative) edge is used as trigger, and
W Y.C W W W W
0 Y .CO .TW W W 0 0 Y.C .T W
W .1 00 M .T when the ICES1
W . 10 bit isOwritten M to one, a rising (positive)
W .1 edge O willMtrigger the capture.
W O .C WW .1setting, .C .TW value is copied into the
WW .100Y.C M.TW When WW a capture . 1 00isYtriggered M
W
.Taccording to the ICES1 00Y theM counter
W O
W O WW Register .CO .TW WW C
0Y.Input .TW Flag (ICF1), and this
WW .100Y.C M.TW InputW Capture
. 1 00Y (ICR1). M
The event will also set
W . 1 0the
O MCapture
O W O .C
W
WW .100Y.C M.TW
can be used
WW .100Y.C M.TW
to cause an Input Capture Interrupt, WWif this.1interrupt00Y is enabled. M .TW
O W O W O
.C WGM13:0
W
WW .100Y.C M.TW TCCR1A
When theW
W ICR1 .is10used 0Y.Cas TOP .TW value (see description WW .10of 0Ythe M.T
W bits located in the
and W
the TCCR1B O M
Register), the ICP1 is W
disconnected and
C O consequently the Input Cap-
W O
WW .100Y.C M.TW ture function WWis disabled. 0 0 Y.C .T W WW .100Y. M .TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W W .C O • Bit 5 – Reserved
W WW Bit00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W 1 futureOdevices, M
W.1 Y.COM This bit is reservedW for.1future use.
.C OM For ensuring compatibility W W.with Y .C Wthis bit must be
W W W W 0 0 Y .T W W 1 0 0 .T
W 0 0 .Twritten to zero when TCCR1B
.1 is written.
M . M
W 00 .T W .1 M .1 M
W W.1 Y.COM• BitW4:3 – WGM13:2: W WWaveform Y . C O
Generation
W Mode
W WW 00Y.CO .TW
W
W .100 O MSee.T TCCR1A Register W .100
description.
W OM
.T
W W.1 Y.COM W
.C W . C W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O• Bit 2:0 – CS12:0: Clock .C WW .100Y. C
WW .100Y.C M.TW WW Select 1 00Y M .TW M .TW
W The three Clock Select W
O .
bitsWselect the O source to be used W
clock W .C
by the Timer/Counter, O see Figure
WW .100Y.C16-10 .T
and WFigure 16-11. W . 10 0Y.C M.TW W .1 00Y M .TW
OM W O W O
W
WW .100Y.C .T W WW .100Y.C M.TW WW .100Y.C M.TW
W TableOM16-6. Clock SelectWBit WDescription .CO .TW WW 00Y.CO .TW
WW .100Y.C T
M. CS11
W W .1 0 0 Y W
W.1 Y.COM W
W CS12
C O CS10
W W Description
.C OM W
WW .100Y. 0 M.TW0 Y W W 00 .T
0
W
W
No 100 sourceO(Timer/Counter
.clock M.T stopped). W.1 Y.COM W
W O .C W
WW .100Y.C0 M.TW WW .100Y M .TW W .100 M.T
W O 0 1 clkW /1 (No prescaling)O W W .C O
WW
I/O
.C Y W
WW .100Y0.C M.T1 W 0 clkI/O /8.1 00Y prescaler)
(From M .TW W
W .100 O M.T
W O C
W
WW .1000Y.C M1.TW
O
Wclk W .C
00Yprescaler) .TW WW .100Y. M .TW
1 I/O/64 .1
(From M W O
WW .1010Y.C M 0 .T
W 0 WclkI/O/256 .(From 1 prescaler) M W O
W O
WI/OW
WW .1100Y.C 0M.TW 1 clk .
/1024 (From 1 0 0 Yprescaler)
M
W O WW 00Y.CO .TW WW 00Y.CO .TW
WW .1100Y.C 1 M.TW 0 W
External clock .1source onOT1Mpin. Clock on falling edge.
W
W.1 Y.COM W
W C O W W .C W W
WW 1.100Y. 1 M.TW1 ExternalW clock .source Y
100 on T1 Mpin..TClock on risingW edge. 00
W.1 Y.COM W
.T
W O W .C O W
O W O W .C O
W WW 00Y.C
If external pin modes are
.isTW
used for the Timer/Counter1,
WW .100Y .C transitions
.TW
on the T1 WW .100Y
pin will clock the
M.T
W
counter even .1 if theOpin M configured as an output. W This feature
O M allows software control W of the O
W
WW .100Y.C M.TW
counting. WW .100Y.C M.TW WW .100Y.C M.T
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 – Timer/Counter1
OM .1 M
16.10.3 TCNT1H and W
W TCNT1L
W 00 .T W.1 4 Y.CO3M W2
W WBit.1 Y.COM 7 W 6 5W
0 1 0
.T W W 0 0 .T W . 1 0TCNT1[15:8] M .T
. 1 M
.C OM
W WW 00Y.CO .TW W WW 00Y.CO .TW TCNT1H
00 Y .T W .1 OM R/W
TCNT1[7:0] TCNT1L
W.1 Y.COM W W .1 O M W W . C
WWInitial Value Y. C Y W
.TW0 W 100 0 OM.T0
. 1 00 M .T W . 100 O 0M 0 W 0. C 0 0
W .C O W Y .C W W W 0 Y . .T W
Y W W 0 0 .T .1 0
.100 M.T The two W.1Timer/Counter OM I/O locations (TCNT1H WW and
M
.CO .Tcombined
TCNT1L, TCNT1) give direct
WW 00Y.CO .TW W W
access, both 0 0 Y
for
.C
read .T
and
W for write W
operations, . 1 0
to
0 Y
the M
Timer/Counter
W
unit 16-bit counter. To
W .1
.C O M W W.1 Y.COM W W W Y .C O
0 writtenMsimultaneously W
WW .100Y W ensure
W that.1both 00 the high Tand low bytesWare read.10and
M.the .T when the CPU
W O M.T accesses W these C
registers,
. O access is performed W W usingYan .C O8-bit temporary
W High Byte Register
WW .100Y.C M.TW WW This.1temporary 00Y M .TW is shared W . 00
1other M .T
(TEMP). register by all W
the 16-bit O registers. See “Accessing 16-bit
W W Y .C O
W W WW 0 Y .CO .TW W W 0 0 Y.C .T W
W 00 .T Registers” on page0
W.1 Y.COM W
94. .1 M
W 00 .T Modifying W the counter 0
0 (TCNT1).Twhile the counter is W .1
running introduces M a risk of missing a com-
W.1 Y.COM W pare matchWbetween W.1 Y.COM W W Registers. 0 Y .CO .TW
W TCNT1 and one of the W
OCR1x 0
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C
WW .100Y. W Writing toW
M.T for all compare
the TCNT100Register
.1
Y .TW(removes)W
blocks
M the compare
W .100matchOon Mthe.T following timer clock
W O W C O W .C W
units.
M .TW W .100
Y
M.T
W O W .C O
WW OCR1AH .CO and.TOCR1AL W WW Compare .C
00Y Register .TW WW .100Y .TW
W16.10.4
. 1 00Y M – Output
W . 1 O M 1A
W O M
W
WW .100Y.C M.TW
O
WW7 .1006Y.C M .TW 4 WW .100Y.C M.TW
Bit 5 3 W 2 Y.C1O 0
W W Y .C O
W W WW 00Y.CO .TW OCR1A[15:8]WW 1 0 0 .T W OCR1AH
W 00 .T W.1 Y.COM WOCR1A[7:0] WW. 0Y.COM W OCR1AL
W W.1 Y.COM W W W .T
W .100 .T
MRead/Write
W
R/W
W .100 R/W
R/W O M.T R/W R/W W
R/W .10 R/W OMR/W
W O W 0 00Y.C0 W Y .C W
WW .100Y.C M Initial W
.TValue 0W
. 1 M .TW 0 0 W 0
W .100 0 OM0.T
W O C
WW 00Y.CO .TW WW .100Y.C M.TW WW .100Y. .TW
16.10.5W OCR1BH . 1 and OCR1BLM – Output Compare W Register 1
O B W O M
W
WW .100Y.C M.TW
O
2 WW
O
W W Y .C O
Bit
W
7
W W6W 005Y.CO 4 .TW 3 W 1
0 0 Y.C 0 .TW
W 00 .T W.1 Y.COM .1 M OCR1BH
W.1 Y.COM W WW 00Y.CO .OCR1BL
OCR1B[15:8]
W W W W
W W
. 1 00 Read/Write M .T W
W .100 O M .T
OCR1B[7:0]
W .1 O MT
W O WW .100Y .C
.C W0 W .1000Y.C 0 M.TW0 .TW
R/W R/W R/W R/W R/W R/W R/W R/W
WW .100YInitial Value M .TW 0 0 W
0 0 OM
W O
W
WW .10The 0Y.COutput
O
.T W WW contain 0 0Ya.C .TW that is continuously WW .100Y.C M.TW
. 1 M
W W .C OM Compare Registers
WW Y
16-bit value
.COto generate W W WW compared 0 Y .CO with.Tthe W
W 00 Y
counter value .T W
(TCNT1). A W
match can . 10
be 0 used M .T an output compare .1 0 interrupt,Mor to
.1 M W O W CO
W
WW .generate .COa waveform .TW
output on W OC1x00pin.
Wthe Y.C .TW WW .100Y. .TW
1 00Y M W .1 O M W O M
W O
Y.C Compare W16-bit Y.C To ensure TWthat both the WW Y.C
00low W
WW The .1 0
Output
0 M .T W RegistersW are
W . 1
in
0 0size.
O M . high and
W .1 O M.T
bytes are
W O
written simultaneously when the CPU writes to Y .C registers,
these the access W is performed C
0Y.using M an TW
WW 8-bit 0Y.C M
0temporary .TWByte Register WW(TEMP). . 1 00This temporary M .TWregister isWshared .10all .
W . 1 O High W C O W W by the
.C O
other
WWRegisters” Y. Y W
WW16-bit .1 0Y.C See
0registers. M
W
.T“Accessing 16-bit . 100 on page M TW
.94. W
W .100 O M.T
O W O .C
W
WW – Input Y.C .TW WW .100Y.C M.TW WW .100Y .TW
.100 Capture M W O W O M
WW .100Y.C M.TW
16.10.6 ICR1H and ICR1L W O Register 1
3.CO
W O
Bit W .C O
7 6 5 WW 4
Y 2 W 1
W W0
0 Y.C W
W W
. 1 00 Y
M .T W W
W .10 0
O M . T
W .1ICR1H OM.T
0
Y.C
ICR1[15:8]
W O .C WW .ICR1L
WW .100Y.C M.TW WW ICR1[7:0] .1 00Y M .TW 100 M.T
W O W R/WY.C R/W
O W W . CO
W Y
WW 0Y0.C M.0TW 0 .TW 0 W .100
Read/Write R/W R/W R/W
WR/W 1000
R/W R/W
Initial Value .10 0 W . O 0M 0 W
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Input Capture OM is updated with W .1 M
W WThe Y .C W W
theW counter (TCNT1)
0 Y .CO .value TW
each time an event occurs on the
W 0 0 .T . 1 0 M
W W.1 Y.COM W
ICP1 pin (or optionally on the analog
W
comparator
W
0 Y .
output
CO for Timer/Counter1).
W
The Input Capture
W W can.1be00used for M .T the counter TOPWvalue.
defining W .10 .T
O M.T W C O W .C OM
.C
.TW
W 00Y
. .TW is 16-bitWin size. Y
100ensure O TW the high and low bytes are read
.both
. 1 00Y M
W The Input
W . 1 Capture Register
M
O the CPU accesses W
To
. thatM
.C the.access
W O WWthese.1registers,
0 0 Y.C .T W WW simultaneously
. 1 0 0Y.C when M .TW 00Y W is performed using an 8-bit
M T is shared by all the other 16-bit
. 1 M temporaryW High O
Byte Register (TEMP). This W temporary .C O
register
W .CO .TW W .C
00Y“Accessing .TW WW page Y
100 94. OM.T
W
. 1 00Y M
Wregisters.
W . 1 See
O M 16-bit Registers” on W .
W
1
W. 16.10.7 .C OM TIMSK – Timer/Counter
W WWInterrupt Y
O Register
.CMask W
(1)
W WW 00Y.CO .TW
Y W 0 .T
W 00
W.1 Y.COM W
.T W.1 Y
0
OM 6 W.1 Y.COM W
W 7 .C W 4W
W W .100 M.T OCIE0
Bit 5 3 2 1 0
W .10OCIE20 M.T TICIE1 OCIE1A
W
W .100 O M.T W O W W OCIE1B .C O
0Y.C R/W
TOIE2 TOIE1 TOIE0 TIMSK
WW .100Y.C M.TW WW .10R/W
Read/Write M .TW R/W W
R/W .
R/W1 00Y R/W M.TW R/W R/W
W O W O 0WW
W .CO .T0W
WW .100Y.C M.TW WW .100 0Y.C 0 M.TW0
Initial Value 0 00Y 0
1 0
W O W C O W W .
. C OM
WW .100Y.C M.TW Note: W 1. W This register .
Ycontains .TW control bits
interrupt W for several Y
.100Timer/Counters, TW
M.respective
but only Timer1 bits are
W
described . 100in this section.
O M The remaining bits are W described Cin O their timer sections.
W
WW .100Y.C M.TW
O
W O WW 0Enable O
W O
WW Timer/Counter1, Y.C Y.C W
WW .100Y.C M.TW• Bit 5 – TICIE1: . 0 0
1 to one, M .T W Capture
Input WInterrupt
W . 1 0
O M.T
O W O . C
W
WW .100Y.C M.TW
When this bit
W
is
W written
0 0 Y.C and
.T
theW I-flag in the
WW .100Y
Status Register is set
M .T(interrupts
W globally
enabled), the Timer/Counter1 W. 1 InputM Capture Interrupt W W
is enabled. TheOcorresponding Interrupt
W O
WW .1on .CO is Y.C located.TinWTIFR, is set.
WW .100Y.C M.TVector W (See “Interrupts” 00Y page 45.) .T W
executed when W the ICF1 . 1 0 0Flag,
OM
W C O W W .C OM W W Y .C W
WW .100Y . W Y W W 0
.10Interrupt M.T
M .TBit W
W . 100 O M .T W O
WW .100Y.C M.TW
W O • 4 – OCIE1A: Timer/Counter1, .C Output Compare A Match Enable
W
WW .100Y.C M When.TWthis bit is W writtenW 00Y and the
to.1one, M TW in the Status
.I-flag Register is setO(interrupts globally
W W .C O W Y .COCompare W W WW is enabled. 00Y
.C TW
W . 1 00 Y enabled),
M .T W the W
Timer/Counter1
W . 1 0 0
Output
O M .T A match interrupt
W . 1 O M.corresponding
The
W OInterrupt Vector (See W .C page .45.) WW Y. C
WW .100Y.C TIFR, .TisWset. W “Interrupts” 1 00Y
on
M TWis executed when the 0OCF1A
. 10
Flag,
M .TWlocated in
M W . O W O
W
WW .100Y.C M.TW
O
W W .C• OBit 3 – OCIE1B: Timer/Counter1, WW 00YOutput .CO Compare W B W
Match
W
WInterrupt 0 Y .CO .TW
Enable
W 00 Y .T W W .T .1 0 M
W.1 YWhen .C OMthis bit is written toW one,W.1and the Y .C OM in the Status Register
I-flag W W Wis set0Y .CO .T
(interrupts W
globally
W W 0 .T W W 0 0 .T W . 1 0 M
. 1 0 enabled), M the Timer/Counter1 .
Output
W 1 Compare O M B match interrupt is W
enabled. The C O
corresponding
W O Y.C 45.) is.Texecuted WW Y . .TW in
WW .100Interrupt Y.C .TW (See “Interrupts”
Vector WW .on 1 00page M
W when the OCF1B . 100 Flag,Olocated
M
M W O W
W
WW .10TIFR, 0Y.C is set.
O
W W .C OM
W Y
•00Bit 2 – TOIE1: .T Timer/Counter1,W W .1 .1 M
W.1 Y.COM W W
Overflow
.C OM Enable
Interrupt
WW 00Y.CO .TW
W W Y
0 in the .T W W
W.1 Y.COM W
When
W 100 thisObitMis.Twritten to one, andW
W.enabled),
the.10I-flag
C
MStatus
Oenabled.
Register is set (interrupts
W
globally
.C the Timer/Counter1 W
Overflow Interrupt Y . is W The corresponding
W Interrupt
0 Vector
W W
.1
Y
00“Interrupts” M .T W W
W . 0
10when O M .T W .10is set. OM.T
W (See O on page 45.) is executed the TOV1 Flag, located in TIFR,
WW .100Y. C
W O W O
W
WW .100Interrupt
16.10.8 TIFR – Timer/Counter Y.C
O Flag Register
W W . C OM
W Bit .100 Y 7 .T W 4 0 0 0 .1 M
W.1 YOCF1B
6 5 3 2 1
W C OM ICF1 W OCF1A .C OM TOV1 OCF0 WW
W Y .CO .TW
W Y . OCF2
WTOV2
W 00 R/W M.R/W T W TOV0
.10 0TIFR
W Read/Write
W .100 R/WO M.T R/W R/W
W W.1 Y
R/W
. C O R/W R/WW
W Y .C OM
W
.C W
W Value 00Y 0
WInitial . 1 M .TW 0 0 W 0 .100 0
W O M .0T 0
W0
W .100 OM.T
W .CO contains W .C .TW WW described Y.C
WW 1. .1This
Note: 00YregisterM .TW flag bits for Wseveral . 1 00Y
Timer/Counters, M but only Timer1 bits are W . 100 OM.T
W O W O
C respective W .C
WW .100Y.C M.TW
in this section. The remaining bitsW are Wdescribed Y.their
in
.TW timer sections. W .100
Y
W . 100 O M W
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1Bit 5Y–.CICF1: OM Timer/Counter1, Input .1 OM
W W W WW Capture 0 0 Y .CFlag W
.Tpin.
W This. 1 0 is setM
0flag when.T a capture event occurs . 1 on theOICP1 M When the Input Capture Register
.CO W
W W WW (ICR1) 0 0isYset by the .T W
WGM13:0 to W
be
W
used as 1 0 0
the
.C
YTOP value, .T W
the ICF1 Flag is set when the coun-
O M.T W W .1
.C OTOP M W W. Y .C OM
W
.C ter reaches the value.
W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W
0Y. C O W W .C
0Y Interrupt W
00 .T WW ICF1 is automatically
. 10be M TW when the
.cleared W Input Capture .10bit M.T
Vector is executed. Alternatively,
. 1 M ICF1 W can cleared O by writing a logic one W
to its .C
location.O
. 1 00Y M O W O M
WW 00Y.CO .TW •WBit WW 4 – OCF1A:
0 0Y.C Timer/Counter1, .TW WW Compare
Output 1
.C
00Y A Match W
.TFlag
1 . 1 M W . O M
W. OM W O W the counter .C
WW .100Y.C M.TW
ThisW
W flag is.1set 0 0Yin.Cthe timer M .TW clock cycle W after
.1 00Y (TCNT1) M.T
Wvalue matches the Output
Compare W Register A O
(OCR1A). W O
W
WW .100Y.C M.TW
O
W will not O
W W Y .C O
W
Note that
W WaWForced 0 Y .CO Compare
Output
.T W (FOC1A) W
W
strobe
0 0 Y.Cset the .OCF1A TW
Flag.
W 0 0 .T . 1 0 M . 1 M
O A Interrupt Vector is exe-
W.1 OM OCF1A is W
Wautomatically O
Y.C cleared when the Output
WW Compare
W
0Y.CMatch .TW
WW .100Y.C M.TW cuted.W Alternatively,. 1 0 0 OCF1A Mcan . T W
be cleared by writing W .
a 1 0
logic one O M
to its bit location.
W .C O WW 00Y.CO .TW W W 0 Y.C W
W W
.1 00 Y
M .T W W
W . 1 O M W . 1 0
O MT .
W O W .C WW B .Match C
Y. Flag .TW
WW .100Y.C M.TW
• Bit 3 –W OCF1B: Timer/Counter1, Output Compare
. 1 00Y M .TW 100 M
W W .C O This flag is set W Win the timer
Y .C O
clock cycle after the counter
W W W W (TCNT1)
0 Y .COvalue.TmatchesW the Output
W 00 Y .T WCompare Register W B. 1 0 0
(OCR1B). M .T . 10 M
W. 1 OM W O
WW .100Y.C M.TW W 1
W O Note that a forced output W. compare OM(FOC1B) strobe will W notW set the OCF1B .CO Flag.
WW .100Y.C M.TOCF1B W WW .100Y.C M.TW W . 1 00Y M .TW
is automatically cleared when the Output Compare W Match B O
Interrupt Vector is exe-
W W Y .C O
W W WW 00Y.CO .TW W W 0 0 Y.C .T W
W 00 .T Alternatively, OCF1B
cuted.
W.1 Y.COM W
can be cleared by writing a logicW one.1 to its bitOlocation.
M
W W.1 Y.COM W W W W 0 Y .C .TW
W . 1 00 M .T W . 1 00 M .T W .10 O M
WW 00Y.COverflow O
W
WW .100Y.C The
O • Bit 2 – TOV1: Timer/Counter1,
.T W of thisW .TW
Flag
WW .100Y.C M.TW
setting flag is . 1
dependent of M
the WGM13:0 bits setting.WIn normal.C O CTC modes, the
and
W W . COM W W Y . CO W W W 0 Y W Flag
.TTOV1
W 00 Y TOV1 W W
.TFlag is set when theWtimer . 0
10 overflows. M T
.Refer to Table 16-5 on page
. 0
1 114 for M the
. 1 M O setting. W O
W
WW .100Y.Cbehavior
O
.T Wwhen usingW W WGM13:0
another
0 0Y.C bitM . TW WW .100Y.C M.TW
. 1
W W .C OM is automatically cleared
TOV1 WW when Y .COTimer/Counter1
the W W
Overflow WW interrupt 0 Y .CO is .executed.
vector TW
W Y
00 Alternatively, .T W W . 1 0 0 M .T .1 0 M
W . 1 O M W byYwriting O one to its bitW W .C O
TOV1 can beW cleared .C a logic W location. 00Y W
WW .100Y.C M.TW W .1 00 M .TW W . 1 O M.T
O W O .C
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W .1
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
8-bit W
W . 100 with O M .T
PWM and
W
Asynchronous
W .100 O
.T
MOperation
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Features
0
W. 1
.C OM
W •W W Compare
Single Y .COunit Counter W W WW 00Y.CO .TW
Y W 0
.10 on Compare .T .1
.100 M.T • Clear WTimer OM Match (Auto Reload) WW 00Y.CO .TW
M
WW 00Y.CO .TW W Y .C W W
W .1 O M •WGlitch-free,
W .100Phase O M.T Pulse Width Modulator
Correct
W W.1(PWM) .C OM
.C W .C W Y W
WW .100Y M .TW •W Frequency Generator
W . 1 00Y
O M .T W
W .100 O M.T
W
WW .100Y.C M.TW
O • 10-bit
WW and
Clock Prescaler
0Y.C Match .TWInterrupt Sources WW .100Y.C M.TW
• OverflowW . 10Compare M W andY.OCF2) CO
W W .C O
W Wclocking Y .CO W W W(TOV2 0 0 .TW
W 00 Y .T • W
Allows . 10 0 from External
M .T 32 kHz Watch Crystal .1
Independent of
Mthe I/O Clock
W .1 O M W C O W W . C O
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
W . O W O
W
17.2
WW .100Y.C M.TW
O
Overview WW .100Y.C M.TW WW .100Y.C M.TW
Opurpose, single compare W O
W O Timer/Counter2 WWis a general Y.C WW .100Y.C M.TW
unit, 8-bit Timer/Counter module. A simpli-
WW .100Y.C M.TW fied blockWdiagram.1of00the .T W
W C O W W 8-bit
.C OM Timer/Counter is shown
W Win Figure
Y
17-1.
.CO .TW
For the actual placement
W . Wof I/O pins,W Y W W .10 0
W
W .100
Y
O M.T bits and I/O pins,
refer to “Pinout
W .100 ATmega32A” M.T on page 2. CPU
Obold. W W
accessible
.C
I/OM
O
Registers, including I/O
C W are shown .Cin The device-specific I/O Y
Register and bit W
.Tlocations are listed
WW .100Y. M .TW W . 100Y on page M .TW W
W .100 O M
in the “Register Description”
W O 132.
W
WW .100Y.C M.TW
O
W W .C O Figure 17-1. 8-bit
W
W
WTimer/Counter Y .COBlock.TDiagram W W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W W 00 .T W
W
W .100 O M.T W.1 Y.COMTCCRnW W W.1 Y.COM W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O .C WW .100Y. C
WW .100Y.C M.TW WW .count 1 00Y M .TW M .TW
W clear Y.CO W O TOVn
W
WW .100Y.C M.TW
O
WW direction 00 .TW clk
Control Logic WW .100Y.C (Int.Req.) M.T
W
W . 1 O M W C O
W O
Tn
WW .100Y.C M.TW M TW
.TOSC1
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW Prescaler W
BOTTOM TOP W
. 1 0T/CY.C M.TW
0Oscillator
W W .C O
W WW 00Y.CO .TW W WW 00Y.CO TOSC2.TW
W 00 Y .T W .1 M
W.=10 =Y0xFF
Timer/Counter
W.1 Y.COM W TCNTn W . C OM WW 00Y.CO .TW

W W 00 W
.T OCn W
W
W .100 O M.T W.1 Y.COM W W W.1 clkY.COM W
I/O
.C W W 00 .T
WW .100Y W W .100 M.T Waveform
(Int.Req.)
M.T O W.1 OCnY.COM W

DATABUS
W O W W .C W
WW .100Y.C M.TW W .100
= Y W .T
W .100 M.T
Generation
W O W C O W W . C OM
WW .100Y. Y W
W .100 O M.T
W O C
W
WW .100Y.C M.TOCRn
O
W WW .100Y.C M.TW WW .100Y. M .TW
WStatus flags O W clk O
W O
WW .100Y.C Synchronization WW .100Y.C M.TW
I/O
Synchronized
WW .100Y.C M.TW M .TW Unit O

W W .C O
W WW 00Y.CO .TW W
ASY
WW clk
0 0 Y.C .TW
W Y
00 Status flagsM.T W . 1 M . 1 M
. 1 W O W O
W O Y.C WW .100Y.C M.TW
ASSRn
WW .100Y.C M.TW WWasynchronous

select1
. 00mode M .TW
WW 00Y.CO .TW
(ASn)
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W W.1 Y.COM W W W WW 00Y.CO .T
W .100 M.T
W 00 .T W.1 Y.COM
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
17.2.1 Registers
W W WW 00Y.CO .TW
W 0
.10Timer/Counter .T .1
The
W C OM (TCNT2) and Output W WCompare OM (OCR2) are 8-bit registers. Interrupt
.CRegister
W Y . W W 0 Y W Interrupt Flag Register (TIFR).
M .TW W request
W . 100(shorten O M .TInt.Req.) signals areWall
as .10visible inOthe M.T Timer
.CO .TW WW C
0Y. Interrupt
00Y WWAll interrupts. 1 0Y.Care individually
0are M .TW masked with the 0
.
Timer
1 registers M .TW Mask Register (TIMSK). TIFR and
. 1 M W O
TIMSK not shown in the figure since these
WW .100Y.C M.TW
are shared by other timer units.
0 0 .1 M be clocked internally,
W.1 Y.COM W WW
The Timer/Counter
Y .CO can.T W W WW via 0the 0 .CO .Tor
Yprescaler, Wasynchronously clocked from
0 0 .T W 1 0 0 . 1 M
.1 M the W.
TOSC1/2 pins, OM
as detailed later in this section.
W The
.CO .TW operation is controlled by
asynchronous
WW 00Y.CO .TW W Y .C W W W 0 0 Y
W .1 O M
W Asynchronous
the
W .100 Status .TRegister (ASSR). The
OM uses to incrementW .1Clock
Wdecrement)
Select
.C OM
logic block controls which clock
.C source W the .
Timer/CounterC W (or Y its .TWThe Timer/Counter is inac-
value.
WW .100Y M .TW W
tive when W no. 0Y
10clock O
source M .T
is selected. The
W
output W .100the Clock
from O MSelect logic is referred to as the
W
WW .100Y.C M.TW
O
WclockW 0 0 Y.C .T W WW .100Y.C M.TW
timer .1 T2
(clk ). M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T
W.1 Y.COM W value at all
The doubleW .1
buffered OM Compare RegisterW(OCR2)
Output
C W.1 isY.compared CO
M with the Timer/Counter
W W 00 .T W W times. 1 0 0
TheY . result
Mof .T
the W compare W
can be used . 1 0 0
by the waveform
M .TWgenerator to generate
.1 O M .
W frequency O output on the Output W .C O
W
WW .100Y.C M.TW Unit” onW
a PWM orW variable
0 0Y.C M .TW WW Compare . 1 00YPin (OC2). Mthe .TW See “Output Compare
page W
121. . 1 for details.O The compare match W
event will also C O
set Compare Flag (OCF2)
W O
WW .100Y.C M.TW which canWbe used.1to00generate
W Y.C an.Toutput W compare WW interrupt . 1 0 0Y.
request. M .TW
W OM W O
W
WW .100Y.C M.TW
O
W W Definitions
17.2.2 .C O
Y W
W 00
W.1 Y.COM Many
.T register and W bit.1references
.C Oin Mthis document are W W.1 in general
written
Y .CO form.
M A lower case “n”
W
W W the W
W 0 Y
0 number, . W
Tin this case 2. However, W 1 0
0 when using .Tthe
W . 1 00 M .Treplaces Timer/Counter . 1 M W . O M register or bit
W C O W Wthe precise .C O W Y .C W
WW .100Y . defines
.TW in a program,
W 0Y form mustW be used W
(i.e., TCNT2 00for accessing .TTimer/Counter2
W O Mcounter value and so W
on). .10The O
definitions M.Tin Table 17-1 areW W.1used Y
also .C OM throughout the
extensively
WW .100Y .C .TW
WW .100Y.C M .TW
document. M .TW W
W .100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C BOTTOM
OTable 17-1. Definitions
W OM The counter
WWreaches COBOTTOM
.the when it becomes WW zero .CO .TW
(0x00).
Y
WW .100Y.C MAX .T W W .1 0 0 Y .T W W .1 0 0 M
W OM The counterW
W reaches its OM
.CMAXimum when it becomes WW0xFF00(decimal .CO 255).
W W Y . C
00 TOPM.T W W 1 0 Y
0 the TOP M . T W W .1
Y
M .TW
. 1 . O W O
W O The counter
WW 00Y.C
reaches when it becomes equal
W to theY.C highest valueW in
WW .100Y.C M.TW the count Wsequence. .1 The TOP . T W W 1 0 0
. to be theOfixed .T
M value
W O WorWthe value OM value can be assigned
.Cstored WW The .C
W W 00 Y .C
.T W 0xFF (MAX) W 1 0 0 Y
M .TinW the OCR2 WRegister. . 1 0 0 Yassignment M .TWis
. 1 M W . O W O
W
WW .100Y.C M.TW
O dependent onW
W the mode 00Y
C
of .operation.
.TW WW .100Y.C M.TW
. 1 M
W W . C O
W 00 Y W .1
17.3 Timer/Counter W.1 Clock M.T
Sources
O W W.1 Y.COM W WW 00Y.CO .TW
M
W Y . C W W 00 internalM .T W
W 100 Timer/Counter
The
W.clock OM
.T can be clocked Wby.1an
.C O synchronous or an external W W.1 asynchronous
Y .CO .TW
M
W . C W sourceW W Y W W 0 0
W
W .1in
Y
00source.
O
The .Tclock
MRegister W . 0
clkT2 is by10default equal.T
O M to the MCU clock,W clkI/O.1
W
. When
.
the AS2
C OM
W bit the Y .C
ASSR W is written
W toW logic one, 0 Y the.C clock source
T W is taken W from the Y
Timer/Counter
0 0 .TW
W Oscillator 1 00 connected M .T to TOSC1 and TOSC2. . 1 0For detailsMon . W .1 see “‘ASSR OM
. O WW 00Y.CO .TW asynchronous operation, .C
W
WW– Asynchronous 0 Y.C Status .T WRegister” W WWand prescaler,
. 1 00Y seeM.TW
0 on page . 1
135. For detailsM on clock sources
W W. 1
“Timer/Counter .C
M
OPrescaler”
W on page 132.WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W W 00 .T W
17.4 Counter Unit
W
W .C W W W 0 .T
WThe main.1part 00Yof the 8-bit M.TTimer/Counter isW
W the programmable
W .100 O
T
M.bi-directional counter W .10Figure
unit. OM
W O .C W Y .C
WWshows Y.C diagram W W 00Y .TW W .100 M.T
.100 M.T of the counter and
17-2 a block its.1surrounding Menvironment.
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 17-2. OMCounter Unit Block Diagram .1 M
W 00 .T W.1 TOVn M
W W.1 YDATA .C OM BUS W W 0 Y .CO .TW
(Int.Req.)
W W 0
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
.C W .C W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W W
0 Y .C O
W W W W
0 0 Y .C
.T W TOSC1
00 .T W .1 0 M .T count
. 1 M
W.1 Y.COM W WW clk 00YPrescaler .CO .TW
T/C
W WW 00TCNTn Y .CO .TWclear ControlW Logic

Tn Oscillator
.100 M.T W.1 Y.COM direction .1 M

WW 00Y.CO .TW W W W WW 00Y.CO .TW TOSC2
W .1 0 0 M .T . 1 M
W
clk
W O W .1 O M bottom top
W
I/O
WW .100Y .C
WW .100Y.C M.TW M.T
W W
W .100 O M.T
W O W O W .C
WW .100Y.C M.TW
Signal W
Wdescription Y.C
(internal signals):
.TW W .100
Y
M.T
W
W . 100 O M W C O
W O .C WW .1TCNT2 .
WW .100Y.C M.TW W W
count
. 1 00Y M TW
.Increment or decrement 00Y by 1.M.TW
W O
W .C O WW 00Y.CO Selects W W W 0 Y.C W
W W
.1 00 Y
M .TW direction
W
W . 1 O M .T between increment
W . 1 0and decrement.
O M.T
W O W .C
WW .100Y.C M.TW clearWW .100Y.C Clear M .TW TCNT2 (setW 00Y
all bits to.1zero). M .TW
W O
W O
clkT2WW
WW .100Y.C M.TW . 100Y Timer/Counter M clock.
W W .C O
W 00 Y .T top W 0 0 Signalizes that TCNT2 has reached .1 maximum M value.
W bottomW 00 Signalizes .T that TCNT2 has reached W
W
W .100 O M.T W.1 Y.COM W W W.1 minimum Y .C OM value (zero).
W
.C W .T the counterWis cleared, 0
WW .100Y M .TW
Depending on the W mode.of
W
0
10operation O Mused, W .10incremented, O M.Tor decremented
W O at each timer clockW(clk ). clkY.Ccan be generated WW Y.C W source,
WW .100Y.C M .TW W T2.100 T2 M .TW from an external
W .100 or internal O M .Tclock
O selected by the ClockWSelect W bitsY.(CS22:0). O .C (CS22:0
W
WW .100Y.C timer .T W W 0 0 C M.TWhen W no clock WW . 1 0 Y
source is 0selected TW = 0) the
M.regardless
M is stopped. However, W . 1 the TCNT2 O value can be accessed W by the C O
CPU, of
W
WW .100Y.C whether
O
.T WclkT2 is present WW or not. 0 0 C
Y.CPU .T W WWpriority . 1 0 0Y. all counter M .TW clear or
OM operations. .1 A write
M overrides (has
WW 00Y.CO .TW
over)
W WW 00Y.CO .TW
WW .100Y.Ccount M. T W W .1
W
W.1 Y.COM W
W C O W W .C OM W
WW .100Y. The counting M.T
W sequence Wis determined Y
.100 by the .TW of the WGM21
Msetting
W
W
and 0
.10WGM20 OM how the
T
bits.located in
W O W C O W .C W
WW .100Ycounter
the
.C Timer/Counter
.TW (counts) WW .100Y.
Control Register (TCCR2).
M
There
.TW
are close W connections Y
.100 Compare
between
M.Toutput
O M behaves and W how waveforms O are generated on theW Output .C O
W
WW .100OC2. Y.C For .more TW details about WW advanced .C
00Y counting W
.Tsequences WW .100Ygeneration, M .TW
M W . 1 O M and waveform W O see
W W . C O of Operation” on pageW124. Y . C W W W 0 Y .C .T W
W 0“Modes
0 Y .T W W . 1 0 0 M .T . 1 0 M
W. 1 M O W O
.CO .TW OverflowW(TOV2) WW Flag 0Yis.C TW to the mode WWof operation .C
00Y selected W
WW .1The 00YTimer/Counter M W . 1 0 set according
O M . W .1 O M.Tby
W the WGM21:0 O bits. TOV2 can be W .C interrupt.WW Y. C
WW .100Y.C M.TW W used for 1
generating
00Y M
a CPU
.TW . 100 M .TW
W . O W O
W
WW .10Unit 0Y.C M.TW
O
17.5 Output Compare O W O W .CO .TW
W
WW The.108-bit 0Y.Ccomparator .T W continuously WW compares 0 0 Y.CTCNT2.Twith W the Output WWCompare .1 0 0YRegister M
1
W. the comparator OM W COthe TW
W W
(OCR2). .C
WheneverOM TCNT2 equals OCR2, W Y .C W
signals a match. W WA match 0 Y
will .set .
W Y
.100Compare M .TW W
W .100 clock O M.TIf enabled (OCIE2 W .10
COM
W
Output C O Flag (OCF2) at the next
W timer . C cycle. W = 1), the Y .
Output
.TW
WW Y. generates
00Flag .TW an outputW . 1 00Y M TW Flag is W
.OCF2 . 100 cleared O M
Compare . 1 O M compare W interrupt. OThe automatically
W W .C
WW the0interrupt
Wwhen 0 Y.C is executed. .T W Alternatively, WW the 1 0 0Y.C Flag
OCF2 .
canTWbe cleared W by software . 1 00byYwrit- M.TW
.1 OtoMits I/O bit location.W . M W O
ing aW logical Y one.C TheW waveform Y .COgenerator W uses the W W signal
match 0 Y.Cto W
W W
. 1 00output according M
W
.T to operating mode W
W . 0
1set 0
O M .T
W .1 Output OM.T
0
WW .100Y.C M.T
generate an by the WGM21:0 bits and Compare
W
WW (COM21:0) .CO .TW WWsignals .C
0Yused .TW
mode . 1 00Y bits. M The max and bottom .1 0are byM the waveform generator Wfor han- O
dling W the
WspecialYcases . C O
of the Wextreme W
values WinW some 0 Y
modes.COof operation .T W (“Modes W WOperation”
of 0 0 Y.C
W 00 .T 0
W.of1 the Y OM .1
on page W W.1 Figure
124).
Y .C OM shows a block diagram
17-3 W W 0 .C
output compare W unit. W WW
W 00 .T W 0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 17-3. OMOutput Compare Unit, .1 M
W WFigure Y .C W W WW Block Diagram
0 Y .CO .TW
W 00 .T 0
W.1 Y.COM W W W.1 BUSY.COM W
DATA
W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 Y.C
O
.T W WW .100Y.C M.TOCRn W WW .100Y.C M.TW
0
W. 1
.C OM
W WW 00Y.CO .TW W WW 00Y.CO TCNTn .TW
00 Y .T W . 1 M . 1 M
. 1 M W O W O
W W. 1
.C OM
W 00 Y .T W = (8-bit Comparator ).1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.TOCFn (Int.Req.)
W O C W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
. W O
W O
WW top
WW .100Y.C M.TW . 1 00Y M W O
W O
W O
WW FOCn.100Y.C M.TWaveform WW .100Y.C M.TW
bottom
WW .100Y.C M.TW W Generator OCxy
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 Y.COMWGMn1:0 W
COMn1:0
WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
.C W .C W
Y buffered.Twhen using any W of the .Pulse 00 WidthMModulation .T
WW .100Y The
.TWOCR2 Register
Mmodes.
W is double .100Clear Timer M on Compare (CTC)Wmodes W 1 of Y O
(PWM)
W O For the normalW W and .C O .C
operation, theW double buff-
WW .100Y.C M .TWis disabled.WThe double
ering . 1
Y
00buffering M .TW
synchronizes the
W
update W .10the
of
0
OCR2 O M .T
Compare Register
O W O .C
W
WW .100Y.C toMeither .TW top or bottom WW of the 0Y.C sequence.
0counting .TW The synchronization WW .100Yprevents Mthe.TW occurrence
W . 1 O M W C O
W C O W .C W W Y . .TW
WW .100Y. of M odd-length,
.TW
non-symmetrical
W .1 0Y pulses,
0PWM M .Tthereby making W the output
W . 100 glitch-free.O M
O OCR2 Register access W O .C
W
WW .100Y.CTheM .TW WW may 0Y.C complex,
0seem .TWbut this is not WW case. When
.1 00Y the double W
M.T buffering
W . 1 O M W C O
W isO enabled, the CPU has W access to the .COCR2 Buffer Register,W W if double
and .
Ybuffering isTdisabled
. W
WW .100Y.C theO CPUM
W
.Twill access the OCR2
W . 100Y
directly. M .TW W .100 O M
W O
W
17.5.1 ForceW W
Output C
Compare
. O
Y W
W 00
W.1 InYnon-PWM
.T
OM waveform generation W.1modes, .C OM
the match output of the comparator W W.1 can Y .CbeOM forcedW by
W .C Wthe Force W W 0 Y
0 (FOC2) . W W
Tbit. Forcing compare match 1 0
0 will notMset .T the
W 1 00
writing a one
M . Tto Output . 1
Compare M W . O
W. .CO or.T WW but00the Y.C
O
Wbe updated Was W Y.C
00compare .TW
WW .1OCF2 00Y FlagM W
reload/clear theWtimer, . 1 OC2 pin.T
M will if a real
W .1 O Mmatch
W had occurred O (the COM21:0 bitsW W O
.C whether isW C
Y.or toggled).
WW .100Y.C M.TW W settings 1
define
00Y M .TW the OC2 pinW set, cleared
. 100 M .TW
W . O W O
17.5.2 Compare WW Blocking
WMatch 0
O
Y.C by TCNT2 .T W Write WW .100Y.C M.TW WW .100Y.C M.TW
0 O
W.1 Ywrite M
.CO operations W COblockTany
Y.will WW 0occurs 0Y.C in the .TW
WW All .CPU 0 0 .T W to the TCNT2 WW Register . 1 0 0 M . W compare W match that .1 M
1 M W O W O
W timerYclock
next .CO cycle, even when theW
W timer .is10stopped.0Y.C This Tfeature
W allowsWOCR2 W to be Y.C
00initialized W
WWto the .1 0 0
same value M .T
as
W
TCNT2 without triggering
W an M
interrupt
O
. when the W
Timer/Counter . 1 clock O M.T
is
W .CO .TW WW .100Y .C
WW enabled. 00Y WW .100Y.C M.TW M .TW
. 1 M W O W O
W
WW .100Y.C M.TW
O
17.5.3 Using the Output Compare
W W Unit
.C O
W 00 Y .T mode of operationWwill W .1 block allOcompare M .1 M
W W.1 TCNT2
Since writing
. C OMin any
W Y .C W
matches for oneW
W W timer0clock 0 Y .CO .T
cycle,
W there 0Yrisks involved W W TCNT2 00 when using M.Tthe output compare .1 inde- OM
W 10are
.of O M.T
when changing
W.1 or not. C Othe W Wunit,
.C
pendently whether . C the Timer/Counter is W
running Y . If valueW written toW TCNT2 00Y
equals
WW .100Y .T W
M match will be missed,
W . 1 0 0 M .T
W . 1
the OCR2Wvalue, theCcompare WW resulting Oin incorrect waveform W generation.
W W 0 Y . O .TW W 0 0 Y.C .T W W
Similarly, do .not 0 write the TCNT2 value equal to BOTTOM
W 1 Y.COM W .1 when M the counter is downcounting.
W W WW 00Y.CO .TW
W 0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 setup ofOthe M OC2 should be performed .1 M
W WThe Y .C W W WW 0before 0 Y .CO setting the
.
Data Direction Register for the port
TisWto use the Force Output Compare
W 00output. The
pin.1to M .T easiest way of setting . 1the OC2 M
value
WW Y .CO bit .in W W
W
WThe 0 .CO keeps
YRegister W its value even when changing
M .T W W (FOC2)
W . 1 0 0 strobe
O M T Normal mode.
W
OC2
. 1 0
O M.T
00Y WWbetween 1 00Y
Waveform
M
Generation modes.
.TW M .TW
. 1 M . O W O
W Y.C
O
WW BeW aware0that Y.Cthe COM2[1:0] TW bits are WW not double .C
00Ybuffered W
together with the compare value.
. 1 0 0 M .T W
W . 10
O M . W .1 O M.T
W .CO .TW
Changing the COM2[1:0] bits will take effect
WW .100Y
immediately. .C
. 1 M O W O
WW 017.6 O
Y.C Compare W Match WW 0Unit
WOutput 0Y.C M.TW WW .100Y.C M.TW
1 0 .T . 1 W O
W W. .C OM The W W
Compare Y
Output.COmode W
(COM21:0) W
bits Whave two 0 Y.C
functions. .TWWaveform Generator uses
W .1 00 Y
M .T W W
W . 10 0
O M .T
W .1 0
O MThe
W O the COM2[1:0]
WW
bits.Cfor defining the Output Compare W Y.C state.T
(OC2) atW the next compare match.
WW .100Y.C M.TW Also, the . 1
COM2[1:0] 00Y bitsMcontrol .TW the OC2Wpin output W . 100source.OFigureM 17-4 shows a simplified
W W Y.C O
W W WW 0 Y .CO .TW W W 0 0 Y.CThe I/O.TRegisters,
W
W
W .100 O M.T schematic of
W .10
the logic
.
affected
C O M by the COM2[1:0]
W W.1 Y.COM W
bit setting. I/O bits, and I/O
W
WW .100Y.C M.TW pins inWthe figure 0Y shownMin.Tbold.
are
.10that
W Only the Wparts of.10the
W
0 generalMI/O .T Port Control Registers
O When referring to the OC2
W O (DDR and W
PORT) are
C Oaffected by the COM2[1:0] W bits are .C
shown. W
WW .100Y.C M.TW state, the
W Y. .TW OC2 Register, W Y
100OC2 pin. M.T
Wreference
W . 100is for the O M
internal not
W .the
C O
W
WW .100Y.C M.TW
O
W O
W O Figure 17-4. WCompare W .CO Output
Match Unit, Schematic WW .100Y.C M.TW
WW .100Y.C M.TW W . 100Y M .TW
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W
COMn1W.1 Y.COM W WW 00Y.CO .TW
W W COMn0 .100 Waveform .T W
W
W .100 O M.T W .C OM D Q
W W.1 Y.COM W
.C W Generator
Y W W 100 .T
WW .100Y
FOCn
W W .100 M.T
W O M.T W C O W 1W.
.C OM
WW .100Y.C M.TW WW .100Y .
M .TWOCn W .100
Y OCn
M
Pin .TW
W O W O
WW .100Y.C M.TW
0
W O
W O W O
WW .100Y.C M.TW
O D Q
W
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C MPORT .TW WW .100Y.C M.TW
DATA BUS
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 Y.COM D Q
W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W . C ODDR
W
WW .100Y.C M.TWclk I/O WW .100Y M .TW W .100 M.T
W O W O W W .C O
WW .1The .C
00Ygeneral .TW WW .100Y.C M.TW W .from
Y
100 the waveform M.T
W
M I/O port function is overridden
W by O
the Output Compare (OC2) W C O
W
WW .generator .CO .TW WW bits.1are 00Y
.C .TWthe OC2 pin
W
Wdirection 0Y. or output)
10(input .TW
1 00Y if either M of the COM2[1:0] set. However, M W . O M
W .CO .by W
WW Register CO forTthe
0Y.(DDR) W port pin. W WData Direction .C
00Y Regis- W
WW is.1still 00Y
controlled
M T Wthe Data Direction
W . 1 0
O M . The
W .1 O M.T
W ter bit for .theCOOC2 T pin (DDR_OC2) W must be setYas .C output.Tbefore W the OC2 WW value is visible C
Y. on the.TW
WW pin..1The 00Yport override . Wfunction isW . 1 00of the Waveform M .100 M
W W . C O M independent
W W Y .C O
W
Generation
W
mode.
W W
0 Y .CO .TW
W The .design Y
100 of the .TW compareW 00 initialization
.1allows OM
.T of the OC2 stateWbefore .10 the out- M
W W .C O Moutput pin logic
W W Y .C W W W 0 Y .CO .TW
Y W W 0 T
. reserved for certain 0
W put is.1enabled.
W
00 Note .Tthat some COM2[1:0]
OMDescription” on page
0bit settings are
W.1 Y.COM W W W.1 modes Y
of M
.CO .TW
W
operation. .C
“Register
Y W W W 132 00 .T W 0 0
W
.C W W 00 .T
17.6.1 Compare Output WW Mode .and
Y
100 Waveform
W
M.TGeneration
W .100 M.T W.1 Y.COM
W O W . C O W
WW Y .C TW the COM2[1:0] WW bits.1differently 00Y .TW CTC, and W PWM .modes. 100 M.T
.100
The waveform generator
W O M.uses W O
inMNormal,
W W .C O
For all
WWmodes, .C the .COM2[1:0]
setting
TW =0 WtellsW the Waveform Y.C Generator .TW that no Waction on .100
theY
.1 0is0Y M W . 100match.OFor M W
OC2 Register
WW modes
W to
.CO .TW
be performed on the next compare
WW133. .For Y.C
00fast
compare output
.TW refer to W
actions
W in the
non-PWM . 1 00Yrefer toM Table 17-3 on page 1 PWMO M mode, Table 17-4 on
page W 134,WW and for Y .COcorrect
phase W PWM refer W
to WW 17-5
Table 0 0 Y
on.Cpage .T
134. W
0 0 .T .1 M
W 00 .T W
W.1 Y.COM W W W.1
W W
W
W .100 O M.T 123
8155B–AVR–07/09
WW .100Y. C W
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WA.1change C ofOtheM COM21:0 bits state Wwill W.1have Y M first compare match after the bits are
.CO at the
effect
W W
1
written.
Y .
00 For non-PWM M
W
.T modes, the action W . 0 0
1can be forced M .TtoW have immediate effect by using the
W . O W W . C O
W Y .C W W 0 Y T W
M .TW W FOC2
W . 0
10strobe bits. .T
O M W .10 O M.
.CO WW .100Y. C
00Y 17.7M.Modes TW WW .100Y.C M.TW M .TW
. 1 of Operation W O W O
W
0 Y.C
O
.T W WW 0 0Y.C M.TW WW .100Y.C M.TW
0 . 1
W. 1
.C OM The
W Wmode of
Y
operation,
.CO .TW
i.e., the behavior
W WofWthe Timer/Counter0 Y .CO .Tand W
the output compare pins, is
Y W W 0
0the combination .1 0
.100 M.T defined .by
W 1 (COM2[1:0])
of the Waveform Generation
OM bits. The Compare WWOutput
mode
CO bits
.mode
M (WGM2[1:0]) and Compare Out-
WW 00Y.CO .TW put
W W mode
1 0 0 Y .C
. T W W . 1 0 0 Y
M .TW do not affect the counting
. 1 O M sequence, W . while the O M
Waveform Generation W
mode bits .
do.C OThe COM2[1:0] bits control whether
W
WW .100Y.C M.TW WPWM W .C
00Ygenerated W
.Tshould WW .100Y M
W
.Tnon-inverted
. 1 M WW 00Y.CO .TW
the W output O be inverted or not (inverted or PWM). For non-
W W .C O W Y .C W W
Y W PWM W modes.1the 00 COM2[1:0] M.Tbits control whether the output should
W
W .100 O M.T Wmatch (See C O“Compare W W.1 on page .C OM be set, cleared, or toggled at
.C a compare W Y . W Match Output W Unit” 0 Y 123.)..TW
WW .100Y M .TW W . 100 M .T W .10 OM
W O W C O W C
. Diagrams”
W W 00 Y . C
.TW For detailed
W W timing
1 0 0 Y .
information
M .T W
refer to W
“Timer/Counter
.
Timing
1 0 0 Y
M .TWon page 128.
.1 M W . O W O
WW17.7.1
W
0 .CO .TW
YNormal WW .100Y.C M.TW WW .100Y.C M.TW
0 Mode O
W.1 OM W Y.C
O W
WW(WGM2[1:0] 0Y.C= 0).M W
WW .100Y.C M.TW The simplest WWmode.1of00operation Mis.T WNormal mode
the . 1 0 In.T this mode the counting
O W O
W O WW up00(incrementing),
Y.C WW clear .C
0is0Yperformed. W counter simply
WW .100Y.C M.TWoverruns when
direction isWalways
. 1 M .TWand no counter W . 1 O M.T
The
W O it W
passes its .C O
maximum 8-bit value (TOP W = 0xFF) and.C then restarts
W from the bot-
WW .100Y.C M.TW tom (0x00). W
W
In normal.1operation00Y the .T W
Timer/Counter
WOverflow .1 0
Flag
0Y(TOV2)M will.Tbe set in the same
W C O W W .C OM W W Y
O
.Ccase W
W . .TW Y W W .10 0 .T
W . 1 00Y M
timer clock W
cycle as
W
the
. 100
TCNT2 becomes
O M .T zero. The TOV2 Flag
W
in this
C O M behaves like a ninth
W O bit, except that it W .C cleared. WW .with .
Ythe timer overflow.TW interrupt
WW .100Y.C Mthat .TWautomatically W is only.1set, Ynot
00TOV2 M TW
.the
However, combined
1be00increased Mby
clearsW the O
Flag, timer resolution W
can O software. There
W
WW .100Y.C M
O
are.TW no special cases WW to .consider 0 0 Y.C in the.Tnormal W mode, WW a new .1 0 0Y.C value
counter M .TcanW
be written
W 1 O M W C O
W .C O W Y .C W W W 0 Y . T W
WW .100Y anytime.
M.T
W W .100 .T 0
W.1 Y.COM W
.
W C O W W .C OM W
WW .100Y. The .TW Compare Wunit can.10be0Y W interrupts W at some 0 time.MUsing
.10given .T the out-
M.T
Output used to generate
W O Mcompare W C O W W . C O this will occupy
put to generate W waveforms Y. in normal mode is not recommended, Y since W
WW .100Y.Ctoo M much.TWof the CPUW time. . 100 M .TW W
W .100 O M.T
W O C
W
WW .100Y.C M.TW
O
O W O
W CO
Y.Compare WW 00Y.C TW WW .100Y.C M.TW
17.7.2
WW Timer
Clear
0
on
0 .T Match
W (CTC)WMode .1 M .
W W. 1 In.C OM Timer on CompareWor
Clear WCTC mode Y .CO(WGM2[1:0] W = 2), theWOCR2
W
W Register
0 Y .CO is used .TW to
W 0 0 Y .T W W 1 0 0
.In CTC mode .T
Mthe counter is cleared . 1 0 M
W.1 manipulate OM the counter resolution. WW to zero when Othe counter
WW The .CO defines Y.C hence.Talso W
WW .10value 0Y.C (TCNT2) . T W matches the W OCR2. . 1 0 0 Y
OCR2 M .T W the top valueW for the
W .1 0 0
counter,
O M
W OM This mode allowsWgreater W O
Y.C of the WWoutput.10frequency. 0Y.C M TW
WW .1its 0 Y.C
0resolution. .T W W . 1 0 0control M . W
Tcompare match It .also
M W O W C O
WW .100Y.
W simplifies O the operation of counting external events.
Odiagram for the CTC W W is shown Oin Figure 17-5. The counter W .C O
WThe timing
WW increases 0 Y.Cuntil a.compare T W
mode
Woccurs .between 0 0Y.C TCNT2 .TandW WW .1value (TCNT2) W
00Y (TCNT2) M.T
.1 0 M match W 1 O M OCR2, and then W counter C O
W
WW is cleared. .CO .TW WW .100Y.C M.TW WW .100Y. .TW
. 1 00Y M W O W O M
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W . C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W
W . 100 O M .T W
W .100 O M.T OCn Interrupt Flag Set
.C O W .C W W Y .C W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W C O W W . C W
00 .T WW .100Y. M .TW W .100
Y
M.T
. 1 M W O W .C O
. 1 00Y M W O W O M
WW 00Y.CO .TW WWTCNTn 0 0Y.C M.TW WW .100Y.C M.TW
. 1
W W. 1
.C OM
W 00 Y .T W .1 M
W W OCn
00 .T W
W
W .100 O M.T (Toggle) W.1 Y.COM W W W.1 Y.COM W (COMn1:0 = 1)
.C W W 0
WW .100Y M.T
W W .100 1 OM.T .10 M.T
W O Period W C 3 W
W 4Y.CO
. .TW
2
W
WW .100Y.C M.TW W . 1 00Y M .TW W
W . 100 O M
W O
W
WW .100Y.C M.TW
O
Wbe generated O each time the counter W Othe TOP value by using the
0Y.C canMbe
O An interruptW can value reaches
W
WW .100Y.C M.TW OCF2 Flag. W If the interrupt 0 0 Y.Cis enabled, .T W WW . 1 0 W
.Tused
W . 1 O M the interrupt handler W routine O for updating the
W W .C O W Y .C W W W 0 Y .C T W
. the counter is run-
Y WTOP value.WHowever, 0
.10changing the.TTOP to a value close to 0BOTTOM M when
W
W .100 O M.T ning with noneW W C OMvalue must be doneWwith W.1care Y .C O the CTC mode does not
WW .100Y. C
.TW W or a low
1
.
prescaler
00Yfeature. M .TtheW W .
since
1to00OCR2 O M .TW
M have the double W .
buffering O If new value written W is lower than the current
W
WW .100Y.C M.Tvalue
O
W of TCNT2, WW the counter 0 0 .C
Ywill miss . T
the
Wcompare match. WW The.1counter 0 0Y.C willM .
then TW have to count to
W .C O W W.1 Y.COM W W W Y .C O
W match can
WW .100Y M
its
.TW maximum value W (0xFF)
W . 100
and wrap around
O M .T startingW at 0x00 before
W .100 theOcompare M.T
W
WW .100Y.C M.TW
O occur.
WW can O
W W Y .C O For generating a waveform
W W WW output 0 Y .CinOCTC .mode, T W the OC2 W output
0 0 Y.C
be .TW its logical
set to toggle
W . 1 00 M
level.T on each compareW . 10 by setting
match O M the Compare Output W .1mode bits O Mto toggle mode
W O .C W C
0Y. the data W
WW .100Y.C (COM2[1:0] .T W = 1). The WW OC2 value
.1 0 0 Ywill not M be .T W on theW
visible port pin . 1 0
unless M .Tdirection for
W O M W C O W W C O
.frequency
W . 1 00Y
the
M
pin
.TW is set to output.W The
W
waveform
. 100 O
generated
M .T will have a maximum
W .10 O M. of f OC2 =
W O /2 when OCR2 is set WW is.1defined C
. by the.Tfollowing
WW .100Y.C M.TW
fclk_I/O to zero (0x00). The waveform frequency W
WW .100Y.C .TW 00Y M
equation:M W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.fTclk_I/O W WW .100Y.C M.TW
W W .C O
W WW fOCn Y
O
=.C----------------------------------------------
2 ⋅ N ⋅ ( 1 W
+ OCRn
-
) W WW 00Y.CO .TW
Y W 0 . T
W 00
W.1 The OM
.T 0
.C W
W W
. 1 00Y N variable M .TW represents W the prescale
W . 100factor (1, O M 8,.T 32, 64, 128, 256, or 1024). W
W .100 O M.T
W O Y.C W Y .C W
WW .1As 00Y for.Cthe Normal .TWmode of operation, WW .the 100TOV2 Flag M .isTW set in the same W timer .clock 100 cycleOthat M.Tthe
M W O W C
W
WW .counter
O
.Ccounts from MAX to 0x00.
.TW WW .100Y.C M.TW WW .100Y. .TW
1 00Y M W O W O M
17.7.3 Fast PWM WW
W
Mode.100Y
.CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W M
.CO .TWModulationW W O
Y.C (WGM2[1:0]
W
WW a .high .CO .TW
0Yfrequency
WW The.1fast 00YPulse Width orW fast PWM 0 0 mode .T W = 3) provides 1 0
W waveform OMgeneration option. The W . 1
C OM from the other PWM W W .C OM
W PWM .C W W fast PWM 0 Y . differs W W option 00 Y
by its sin- .TW
W gle-slope .1 00Yoperation. M .TThe counter
W
counts W
from. 10BOTTOM O M to
.T
MAX then restarts W
from
.1BOTTOM.
.C OInM
W .C O W Y .C W W W 0 Y W
W
W non-inverting . 1
Y
00 Compare M
W
.T Output mode, theWOutputW . 0
10 Compare O M T
. (OC2) is cleared onWthe 0
.1 compare O M.T
WW between O WW .C
Wmatch 0 0 Y.CTCNT2.Tand W OCR2, and WW set at BOTTOM.
. 1 0 0Y.C InM TW Compare
inverting
. Output.1 00Y the M.TW
mode,
output
W Wis 1
. set on compare
.C OM match and cleared WW at BOTTOM. Y .CODue .to Wthe single-slope W
W
Woperation, 0 .CO .TW
Ythe
Y W W 0 T 0
Woperating 00
W.1frequency OM
T fast PWM mode can
of .the 0
W.1 be twice . C Oas M high as the phaseW W.1 PWM
correct
Y
M
.CO .T
W Y .C W W W 00 makesY .T W W 0 0
W that.uses
mode
W 100 dual-slope O M.Toperation. This high frequency
W.1 Y.High C OM
the fast PWM mode well
W W.1suited Y .COM
.C W W W 0
WW .100Y
for power regulation, rectification,
M.T
W and DAC W applications.
100
.therefore
frequency allows
M.T total system cost.
physically
W.1
small
0
sized external W components O (coils, capacitors), W and W . C O
reduces W
WW .100Y.C M.TW W .1the00Y M .TW W
W O W C O
WW .100Y.
In fast PWM mode, the counter is incremented until counter value matches the MAX value.
W W 0 0 Y.C .T W M .TW
The counterW is.1then cleared OMat the following timer Wclock cycle. O The timing diagram for the fast
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 modeOisMshown in Figure 17-6. .1 OM is in the timing diagram shown as a his-
W WPWM Y .C W W WW The TCNT2
0 0 Y .Cvalue W
.Tdiagram
W togram
. 1 00 for illustrating M .T the single-slope W . 1operation.OThe M includes non-inverted and
W W .C O W Y .C W
W Y W W 0
0 marks on T
.the TCNT2 slopes represent compare
W inverted .100 .T The small horizontal1line
PWM outputs.
O M.T W C OMOCR2 and TCNT2.WW. .C OM
00Y
.C
.TW W W matches
1 00Y
.
between
M .TW W . 100
Y
M .TW
. 1 O M W . O W .C O
W
0 Y.C .T W WW Figure.117-6. 0 0Y.CFastM PWM.TWMode, Timing WWDiagram .1 00Y M.T
W
. 1 0 M W O W .C O
. 1 00Y M W O W O M
OCRn Interrupt Flag Set
WW .100Y.C M.TW
W 00 .T W .1 M
W.1 Y.COM W W W.1 Y.COM W WW 00Y.CO .TW OCRn Update and
W W 0 .T W 0 0 .T W . 1 M
TOVn Interrupt Flag Set
0
W.1 Y.COM W .1 M WW 00Y.CO .TW
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W 00 .T W 0 0 .T .1 M
TCNTnW.1 OM
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W OCnW .100
Y
M.T
W
W .100 .T
OM(COMn1:0 = 2)
W O W C O W .C
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y .TW
M(COMn1:0
W O OCn W O W W .C O = 3)
W Y . C W W W 0 Y .C .T W W 0 0 Y .T W
W 00
W.1 Y.COM W Period WW
.T .10 OM W W.1 Y.COM W
2Y.C W
W W
. 1 00 M .T W 1
W . 100 O
3
M .T 4 5 W 6
W .1700 O M.T
W O WW .100Y .C
W
W O W O
WW .100Y.C M.TW
W O The Timer/Counter Overflow Flag ( TOV2 ) is set each time the counter reaches MAX. If the inter-
WW .100Y.C M .T W W W 0 0 Y.C . T W
rupt is enabled, the interrupt .1 handler routine M can be used forWupdating W the compare
O value.
W W Y .C O
W W WW 00Y.CO .TW W 0 0 Y.C .T W
W . 1 00 In
M .T PWM mode, the compare
fast W . 1 unit allows O M generation of PWM W .1
waveforms on O M
the OC2 pin. Set-
W W .C O W Y .C W W W 0 Y .C T W
W 00 Y ting the W W
COM2[1:0] bits to 2 .will 0
0 produce M .T
a non-inverted PWM and an 0
.1 invertedOPWM .
M output can
W.1 Y.CO M.T W 1COM2[1:0] C O to 3 (see Table 17-4WonWpage .C The actual
W be generated
TW by setting
W W the
00 Y . .T W W 0 Y
134).
.10pin is setOas TW OC2
M.output.
W . 1 00 value M .will only be visible on W .
the 1port pin O
if M
the data direction for the Wport C The
W
WW .100Y.C
O
.TW WW by 0 0 Y.C .T W WW .100Y. M .TW
PWMM waveform is generated W. 1 setting OM
(or clearing) the OC2 Register at the compare
O match
W .CO .OCR2 WW at0the 0Y.C
WW .100Ybetween T W and TCNT2, WW and.1clearing 0 0Y.C (orM TW the OC2W
setting)
. Register.1 timer M clock.TWcycle
O M W O W .C O
W
WW .100Y.C M.TW
the counter is cleared (changes
WW from MAX
00Y
.Cto BOTTOM). .TW WW .100Y M .TW
. 1 O M W O
W O WW can00be C
Y.calculated WWequation: 00Y
.C .TW
WW .10The 0Y.CPWMMfrequency .TW
for the Woutput . 1 M .TW by the following
W .1 O M
W O W
WW .1f OCnPWM .CO -----------------
f clk_I/O
WW .100Y.C M.TW
WW .100Y.C M.TW 00Y = M N
W-
.⋅T256 W O
WW .The 0 0 Y W .1 8, M
W W 1 NYvariable .C OM represents the prescale
W WW factor Y .CO
(1, 32, 64, 128, 256, or 1024).
W W WW 00Y.CO .TW
W 0 .T
W
W The.100extremeOvalues M.T for the OCR2 W W
Register
0
.1 represent
. C OM special cases when W W.1 Y.Ca O
generating
M
PWM W
W Y .C W W 0 Y T W
. equal to BOTTOM,W W 0 0 .T
W waveform .100 output Min.Tthe fast PWM mode. W If.1the0 OCR2 isMset
O the.1output will OM be
W O Y. C W Y .C W
WWa narrow .C
00Yspike forMeach .TWMAX+1 timer WW clock cycle.
. 100 Setting M .TW
the OCR2 equalW to MAX .will 100result in M.T
a
W .1 highOor low output (depending W O W
W COM21:0 .C O
constantly
WW on the .C of the
polarity output set byWthe Ybits.) .TW
WW .100Y.C M.TW . 1 00Y M .TW W . 100 OM
W O 50% duty cycle) waveform O
W outputY.inCfast PWMWmode can beW .C
W
AWfrequency
0 0 Y .C
(with
.T W W W
1 0 0 M .T W achieved
. 1 0 0 Y
by set-
M.TW
ting OC2 1
. to toggle M .
Wcompare match O (COM2[1:0] = 1).W W .C O
W WW 0will 0 .CO its logical
Yhave .T
level on each
W frequency WWof f .10=0fY.C /2 when .TW W
The waveform
. 1 00Yfea- M.TW
generated
W.1 to OM
a maximum clk_I/O O M OCR2 is set to zero. W This O
WW except 0Y.C M.T
oc2
WWis similar
ture 0 Y .Cthe OC2 .T W
toggle in CTC W mode, 0 0 Y.C the double .T Wbuffer feature WWof the.1output 0
.10 is enabled OMin the fast PWM mode. .1 M WW 00Y.CO
compare W Wunit Y .C W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1
W W.1 Y.COM W W 0 W WW
W 00 .T W 0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 ModeOM .1 M
17.7.4 Phase Correct
W WPWM Y .C W W WW 00Y.CO .TW
W 0 .T
The
W .10phase
.C OM PWM mode (WGM2[1:0]
correct
W W.1 = 1)Y.provides CO
M a high resolution phase correct PWM
W
W Y W W 0
M .TW W waveform
W . 100 generation O M .T option. The phase W .10 PWMOmode
correct M.T is based on a dual-slope operation.
.CO .TW Y.Ccounts repeatedly W .C TW from MAX to BOTTOM. In non-
00Y WWThe counter . 1 00Compare M .TW from WBOTTOM . 0to0YMAX and
1Compare M .then
. 1 M W O
inverting Output mode, the
W
Output
W
1 0 0 Y.C (OC2)
.T
isWcleared on the compare match
0 0 between .1 TCNT2 O and MOCR2 while upcounting, W. and set OM
on the compare match while downcount-
W.1 Y.COM W WW
ing. In inverting0 Y .COutput.Compare W mode, W Wthe operation0 0 Y.Cis inverted. .TWThe dual-slope operation has
00 .T W . 1 0 M T . 1 M
. 1 M W O W .C O
lower maximum operation frequency than WW single slope
. 1 00Y operation. M .TW However, due to the symmet-
W. 1 OM ric feature of the dual-slope PWM modes, W these modes O are preferred for motor control
W Y .C W W W W
0 Y .CO .TW W W 0 0 Y.C .T W
W .1 00 M .T applications.
W . 10 O M W .1 O M
W O W .C W Y.C W
WW .100Y.C M.TW TheW PWM resolution . 1 00Y for the M
W correctW
.Tphase PWM W mode. 100is fixedOto M .Tbits.
8 In phase correct PWM
W C O W W .C O W Y . C W
WW .100Y . W mode Wthe counter Y W until theWcounter.1value 0 0 .TMAX. When the counter
.1it00changes
is incremented .T matches
W O M.T W C O M W WTCNT2Yvalue . C OMwill be equal to MAX for one
WW .100Y.C M.TW timer clock
reaches
W
MAX,
W
1 0Y
0The
. the
M
count direction.
.TW for the phase W The
. 100PWM O M .TW
cycle. . timing diagram W
correct mode is shown on Figure 17-7.
W .C O WvalueW Y .CO .TW W W 0 Y.C W
W W
.1 00 Y
M .T W The TCNT2 W
W . 1 0
is 0 in the
O
timing
M diagram shown as
Wa . 1 0
histogram O forMT .
illustrating the dual-slope
W C O W .C W Y .C W
WW .100Y. W operation.WThe diagram .100 slopes TW
Yincludes .non-inverted andW inverted .10PWM0 outputs. .T The small horizontal
W O M.T line marks onW the W TCNT2 C O Mrepresent compare W W
matches .
between C OMOCR2 and TCNT2.
W
WW .100Y.C M.TW Y. .TW W .100
Y
M.T
W
W . 100 O M W C O
W O .C WW .100Y . .TW
WW .100Y.C M.TW Figure 17-7.WW Phase Correct 1 00Y PWM .TW Timing Diagram
Mode, M
W . O M W O
W
WW .100Y.C M.TW
O
W .C O WW 00Y.CO .TW W WW 00Y.CO OCn Interrupt Flag Set
W
W W
. 1 00 Y
M .T W W
W . 1 O M W .1 O M.T
W
WW .100Y.C M.TW
O
W W .C O WW 00Y.CO .TW W WW 00Y.OCRn COUpdate TW
Y W W .
W
W .100 O M.T W .1
.C OM W W.1 Y.COM W
C W W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 TOVn Interrupt .T
OMFlag Set
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M
O
W W .C O TCNTn
W 00 Y .T W .1 M
W W 00 .T W .1 = 2) OM
W
W .100 OCn
O M.T W.1 Y.COM W W W(COMn1:0
.C W
WW .100Y OCnM.TW .C W W
. 100 M .T W .1 00Y M.T
W O W C O
O WW .100Y.
(COMn1:0 = 3)
W
W O W O
W
WW .100YPeriod .CO .TW 1WW
0 02Y.C M.TW3 WW .100Y.C M.TW
. 1 W O
W OM W O
WW .100Y.C M.TW
O time the counter reaches WBOTTOM.OThe
The
W Timer/Counter .CO .T Overflow Flag (TOV2 WW) is set Y.C
each
W WW .100Y.C M.TW
WWInterrupt 0 Y W
0 Flag can be used to generate anWinterrupt W .1 0 0 eachM .T
time the counter reaches the BOTTOM
W value. 00 .T W 0 0 .1 M
W W 0 .T W
WIn phase
W
0
correct
.10Setting
PWM.Tmode, the compare
O MCOM21:0 bits to 2 will
unit0allows
W.1 aYnon-inverted .C
generation
OM
of PWM waveforms
W W.1 onYthe .C OM
W
OC2 pin. .C the W produce W PWM. An inverted
W PWM 0 out-
WW .100Y M
W
.Tsetting W
W .1030 (see Table O M .T W .10actual O M.T
WW .100Y.C M.T
put can be generated by the COM21:0 to 17-5 on page 134). The
W
WWvalue.1will .CO .TW W .C
00Ydirection W
OC2 00Y only be M visible on the portWpin if the.1data M .T
for the port pin is set W as output. O
The W
PWM
W waveform Y .C O
is W
generated by W
clearingWW(or setting) 0 Y .COthe OC2 .T W Register W
at
W compare
the 00Y
.C
W 0 0 .T . 1 0 M . 1
match W W.1 OCR2
between
Y
M
.COand TCNT2 W when theW W increments,
counter
0 Y.C
O and Wsetting (orWclearing) WW the
W 0 0 .T W .1 0 .T
OC2 Register W.1at compare C OM match between OCR2 and
WW TCNT2 OM the counter decrements. The
.Cwhen
W W
1 0 0 Y .
M .T W W .1 0 0 Y
M .TW
W . O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
WPWM.10 frequency
C OM for the output when WusingW.1 phase .CO
M
correct PWM can be calculated by the follow-
W W 00 Y
ing.1equation:
. .T W W . 1 0 0 Y
M . TW
M WW 00Y.CO
W W WW 00Y.CO .TW W f clk_I/O.TW
.T . 1 M .1 M
.C O M W W Y .C O
W W
f
W W
OCnPCPWM
0 Y
= . NO⋅ 510- .TW
C -----------------
Y W W 0 .T 0
00
W.1 Y.COM W
.T 0
WN.1variable .C OM W W.1 Y.COM W
W
The Y represents W the prescale W factor 1008, 32, 64, .T 256, or 1024).
. 1 00 M .T W
W . 100 O M .T W .(1, O M128,
W .CO .TW W extreme .C for.Tthe W OCR2 Register WW represent Y . C W when generating a PWM
. 1 00Y M
WThe . 1 00YvaluesM W . 100 special O M .Tcases
W O Y.COCR2 is.Tset
WW 00Y.CO .TW waveform
WW .1output 0 0Y.Cin theMphase .TW correct PWM WWmode. . 1 0If0the M
W equal to BOTTOM, the out-
W. 1 OM put will be continuously low and if set equal to WMAX the output O will be continuously high for non-
W Y.C W W WW 00Y.CO .TW W W 0 0 Y.C .T W
W .1 00 M .T inverted PWM
W . 1 mode. O For M inverted PWM the output W .1will have O the Mopposite logic values.
W O
WW .C WW has Y.C .TWhigh to low even though
WW .100Y.C M.TW At the very start . 1 00Y of period M
W
2.Tin Figure 17-7 OCn W . 10a0transition O M from
W O isW
W .CO .The WW .C
00isYto guarantee W
WW .100Y.C M.TW thereW no Compare
. 1 00Y Match. M TWpoint of this transition
W . 1 O M.T symmetry around BOT-
O W O Y. C
W
WW .100Y.C M.TW
TOM. THere
WW are.1two 00Y
.C that.Tgive
cases W a transition WW without Compare
. 100 .TW
Match.
M
W itsYvalue O M W O
W
WW .100Y.C M.TW
O • OCR2A WWchages 0 0 .C from .TMAX,
W like in Figure WW 17-7. . 1 0Y.C theM
0When .TW value is MAX the
OCR2A
OCn pin valueW . 1is the same O M as the result of a down-countingW C O
Compare Match.
W O
WWaround Y.C W 0Y. W To ensure
WW .100Y.C M.TW symmetry 1 0 0
BOTTOM the .T W value atW
OCn MAX must . 1 0correspond M .Tthe
to result of an up-
W C O W W. .C OM W W Y .CO .TW
W . W Y W W 0 0
Y .100
counting W Compare Match. .T
W
W .100 O M.T W .C OMa value higher than W W.1 Y.COM W
C W .TW
WW .100Y. M .TW
• The timer W starts
. 1 00Y
counting from
M
W the one
W .1in00OCR2A,M
O
.T for that reason
and
O misses the Compare WW 0Match O
and hence the OCn change Y.C have happened
W
WW .100Y.C M.TWway up. W 0Y.C M.TW WW that .
would
100 M .TW
on the
W . 1 O W O
W
WW .100Y.C M.TW
O
W O
17.8 W .CO Timing WW 00Y.CO .TW WW .100Y.C M.TW
WWTimer/Counter0 Y .T W Diagrams W
0
W.1 Y.COM W.1the Timer/Counter M
.CO .TWin Synchronous WW O
Y.Cthe timer
W The following
W figuresW
W show
0 Y W mode, 0and
0
.1 clk should M.beTW clock (clkT2)
W . 1 00 M
is .T
therefore shown as a clock
W . 10enable signal. O M In Asynchronous W
mode, C O replaced by
W O
WW .1clock. .C WW .on Y.
I/O
TWFlags are
WW .100Y.C theMTimer/Counter .TW Oscillator 00Y The figures .T Winclude information 1 0 0when M .
Interrupt
W O Figure 17-8 contains WW OM
.Cfor W W .COfigure.Tshows
YThe W the
WW .100Y.Cset.M . T W W timing0data
. 1 0 Y basic
M .T WTimer/Counter W operation.
W .1 0 0
O M
O sequence close to W W O C
Y. PWM mode.
W
WW .100Y.C M.TW
count
W
the MAX value
00Y
.Cin all modes.TW
other than WW phase correct
. 100 M .TW
W . 1 O M W O
W
WW .100YFigure .CO 17-8. . T W Timer/Counter WW Timing 0 Y.C
0Diagram, no. W
TPrescaling WW .100Y.C M.TW
.1 M
W W . C OM
Y W
W 00
W.1 Y.CO M.T W.1 Y.COM W W W.1 Y.COM W
W
W W
. 1 00
clk I/O .TW
M
W
W . 100 O M .T W
W .100 O M.T
W O W . C
Y
M.T
W
W O W CO
W
WW .100Y(clk CO
.clk Tn
/1) M.T
W O W O
W O WW .100Y.C M.TW
I/O

O W O
W O WW MAX Y.C WBOTTOM WW BOTTOM 0Y.+C1 M.TW
WW .10TCNTn 0Y.C M.TW MAX - 1 W 1 0 0 . T .1 0
W. OM W O
W
WW .100Y.C M.TW
O
W W TOVnY.CO W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W W 00 .T W
W
W .C W W 00 .T
WFigureW 17-9
Y
.100shows O the Msame.TW timing data, W
but W with.10the 0
prescaler O M.Tenabled. W.1 Y.COM
. C W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
W WFigure Y . C W W WW Diagram, with
0 Y .COPrescaler .
(f
TW clk_I/O
/8)
W .1 0 0 M .T . 1 0 M
W
O M.T W .1 clk
.C OM W W.1 Y.COM W
.C W W
Y W .100 .T
I/O
00Y .TW W .100 M.T OM
00 .T WW clk . 10Tn0 M .TW W .100 M.T
. 1 M W O W .C O
W .CO .TW WW (clkI/O.1/8) 00Y
.C .TW WW .100Y .TW
. 1 00Y M W O M W O M
W. 1 OM W O
W Y .C W W
TCNTn
W W
0 Y .CO MAX .T
-1
W W WMAX
0 0 Y.C BOTTOM .TW
BOTTOM + 1
W 00 .T . 1 0 M .1 O M
W.1 OM W O W
WW .100Y.C M.TW
W W .C O
W
TOVnWW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W W 0 0 .T W .1
W
W .100 O M.T Figure 17-10 W shows
W .100the setting .T
OMof OCF2 in all modes W
.1 CTC mode.
except
W M
.CO .TW
W Y .C W W W 0 Y .C T W W 0 0 Y
W 00 .T
W.1 Y.COM WFigure 17-10.WTimer/Counter
0
W.1 Y.COTiming M. Wof
1
W.OCF2, M
.COPrescaler
W W 00 .T W 10 0 M .T Diagram,
W Setting
W . 10 0 Ywith
M .TW (fclk_I/O/8)
W. 1 OM W . O W O
W O
WW .100Y.C M.TW clkI/O W .1 M
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM WclkTn W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T (clkI/O/8) W.1 Y.COM W W W.1 Y.COM W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW OCRn + 100Y.
C
WW .100Y.C M.TCNTn TW WWOCRn.1- 010Y.C MOCRn .TW . 1 M .TW
OCRn +2
W O W C O W W .C O
WW .100Y. Y W
W .100 OM.T
W O OCRn W O W Y. C
WW .100Y.C M .TW WW .100Y.C M.TWOCRn Value W .100 M .TW
W O W O
W
WW .100Y.C M.TW
O
W W .C OOCFn
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y TW
M.shows
W
W .100and theOclearing
M.T of TCNT2 in CTC
W .100
Wmode. OM
.T
W Figure C 17-11
O the setting of OCF2 C W .C
WW .100Y. .TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
M W . O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 17-11.
WFigure C OMTimer/Counter Timing W.1 YClear
WDiagram, .CO Timer
M on Compare Match Mode, with Pres-
W W 0 0 Y . .T
caler
W(f /8) W . 1 0 0 M .TW
.1 M WW 00Y.CO .TW
WW 00Y.CO .TW
clk_I/O
W W W
O M.T W .1
.C OM W W.1 Y.COM W
.C W W
00Y .TW W .10clk0YI/O M.T
W .100 OM
.T
00 .T WW .100Y. M .TW W .100
Y
M.T
. 1 M W O W .C O
W .CO .TW WW (clk clkTn0Y.C
.TW WW .100Y .TW
. 1 00Y M W . 1 0/8)
O M W O M
I/O
W. 1 OM W O
.C W
WTCNTn Y .CO TOP W W W 0 Y.C BOTTOM W
W W
.1 00 Y
M .T W W (CTC)
W . 10 0
O M .T - 1 TOP
W .1 0
O M.T BOTTOM + 1
W O .C W Y .C W
W W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW
W Y.C .TW W .100
Y
M.T
W
WOCRn
W . 100 O M W
TOP
C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
OCFn WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
17.9
W W Asynchronous
.C O
WOperation W ofW the Timer/Counter
Y .CO .TW W WW 00Y.CO .TW
Y W 0
W 00
W.1 Y.COM When
.T Timer/Counter2
0
W.1operates . C
M
Oasynchronously, some W W.1 Y.CO
considerations
M taken.
must be W
W Y W W 0
W W
. 1 00 M .TW W
W . 100 between O M .T W .10 O M.T of
W O • Warning: When switching
Y.C asynchronous and synchronous
WW .100Y .C clocking
TW
WW .100Y.C M.TW Timer/Counter2, WWthe Timer . 100 Registers M
W
.TTCNT2, OCR2, and W TCCR2 might M.corrupted.
be A safe
W O W C O W .C O
W .C W W Y . W W 0 0 Y .T W
W .100
Y
M.T
procedure forW switching1clock 00 source .T
is:
W.1 Y.COM W
W C O W W. .C OM W
WW .100Y . 1. TW
. Disable the Timer/Counter2 Y W W 00 M.T
M
W
W . 100 interrupts O M .Tby clearing OCIE2 and W .1TOIE2.
C O
W
WW .100Y.C M.TW
O 2. Select clock source
WW by .setting 00Y
.CAS2 as .appropriate.
TW WW .100Y. M .TW
to W
1 M
O and TCCR2. W O
W
WW .100Y.C 4.MTo
O3. Write new values W
.TW W
TCNT2, OCR2,
. 1 CO
W W .C O switch to asynchronous
W WW operation: Y .CO Wait for TCN2UB, OCR2UB,
W W WW 0and 0 Y .TCR2UB. .TW
W 00 Y 5. M .T the Timer/Counter2
Clear W . 1 0 0
Interrupt Flags.M .T .1 M
. 1 O W O
WW .100Y.C6. Enable . T Winterrupts, W if needed. .1 M .TW
W W . C OMOscillator is optimized WforW Y .CaO32.768 W W WWApplying 0 Y .CO .TW
Y• The W W use 0with
M. T kHz watch crystal. 0 an external
W
W .100 clock O M .T W .10
.C O W W.1 TheY.CPU M
CO mainTW
W .C to the TOSC1 pin may W result in incorrect
Y Timer/Counter2
W Woperation. 0
W . 1 00Yclock frequency
M .TW must beWmoreW than. 0
10four timesO M the
.TOscillator frequency. W .10 O M.
W O W .C
WW .10•0Y .C .TW WW .10TCNT2, 0Y.C OCR2, M .TW W 0Y
10transferred
.is Mto.Ta
W
When writing M to one of the registers W O or TCCR2, the value W C O
W
WW .100temporary Y.C
O
.TW and latched
register, WW after.1two .C
00YpositiveMedges .TW on TOSC1. WW The user. 0Y. notM.TW
10should
M O W O
W W write Y .C aO new value W before theW WW of00the
contents Y .Ctemporary
.T W register have W W transferred
been
1 0 0 Y.C to its .TW
W 00 .T .1 M their individual W W. .CO .TW
M
W W.1destination.
Y . C OMEach of the three mentioned
W WW 0registers 0 Y .CO have W W
temporary
0 0 register,
Y
W .T
W 100 means
which
W.To OM
.Texample that writingWto.1TCNT2 does
for
.C OM not disturb an OCR2 W W.1 in progress.
write
Y
M
.CO .TW
W .C
Y that a transfer
detect W to the destination W W 00 Y W W
.T place, the Asynchronous 0
0 Status
W
W .100 – ASSR O M.Thas been implemented. W .1register has taken
OM W W.1 Y.COM W
Register C W .C
WW .100Y. M .TW W .100 mode
Y .TW
Mafter
W
W .100 OM
.T
• W
When entering O Power-save or Extended W Standby C O having written W
to TCNT2, .C
WWOCR2, 0 0 .C
YTCCR2, .T W WWuntil the 1 0 Y .
0written M .TWhas been updated W . 1 00Y M .TW
W. 1 or OM the user must wait . Oregister W if O
Y.C is used WW 0Otherwise, 0Y.C Mthe TW WW 00Y
.C W
WWTimer/Counter2
. 1 0 0 M . T Wto wake upW the device.
W .1 O
. MCU will enter sleep .mode
W 1 O M.T
WW the00changes O
Y.C are.Teffective. WisWparticularly .C .TifW
W Y.C
Wbefore . 1 M
W This
. 1 00Yimportant M
the Output W Compare2
W . 100 O M.T
interrupt
W is usedCto O wake up the device, since W the output O
compare function is disabled
W during .C
W W
writing to.1OCR2
.
00Y or TCNT2. .TWIf the writeW
W
cycle is .
not 0Y.C and
10finished, M
W
.Tthe W
MCU enters sleep 100
.mode
Y
M W O W
W
WW the.1OCR2UB .CObit returns .TW to zero, W theW
.C
00Ynever receive .TWa compareWmatch
W
before 00Y M
device1will
. M
Wand the MCU O will not wake up. WW .CO .TW
WW .100Y.C M.TW
interrupt, W . 1 00Y M
W W Y . C O
W W WW 00Y.CO
W 00 .T W.1
W W.1 Y.COM W W
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1• If Timer/Counter2 OM .1 M
upOfrom Power-save
W Y .C W
is used to wake
W WW the device.C
0 0 Y .T W or Extended Standby
W 0 0 .T . 1 M
W W.1 Y.COM W
mode, precautions must be taken
W
if the
W user
0 Y
wants
. CO to re-enter
W
one of these modes: The
W W .to10be reset.OIfMthe T
. time between wake-up and re-
W .100 .T one TOSC1 cycle
interrupt logic needs
O M.T W C OMmode is less than one W W .C
00Y
.C
.TW W W entering
1
. sleep
00Ywill fail M TW
.wake W TOSC1
. 00
1doubt
Ycycle, the
M .TW will not occur, and the
interrupt
. 1 M .
device to up. If the user is W in whetherO the time before re-entering Power-
W .CO .TW WW 00Y.CO .TW W W 0 Y.C W
. 1 0 0 Y
M
W save
W . 1 or Extended
O M Standby mode is sufficient,
W .1 0 the following
O M.Talgorithm can be used to ensure
W .CO .TW Y.C cycle WW .100Y .C
00Y WWthat one 1 00TOSC1 M .TW has elapsed:
M .TW
. 1 M .
W a value O W O
WW 00Y.CO .TW W1.W Write 0Y.C to M TCCR2,
TW TCNT2, W or W OCR2. 00Y.C .TW
1 . 1 0 . W . 1 O M
W. OM W until the corresponding O W Flag0in .C returns
WW .100Y.C M.TW
2. Wait UpdateWBusy 0YASSR
WW .100Y.C M.TW .1 M .TWto zero.
O or Extended StandbyW W O
W O 3. Enter
WW Power-save Y.C
mode.
0Y.C M.TW
WW .100Y.C M.TW W 0 0
.1asynchronous .T W W . 1 0
W O • When the
WW running, OM operation is selected,
.Cexcept WWthe 32.768 .CkHz O Oscillator for Timer/Counter2
W W 00 Y.C
.T W is W always 10 0 Y
M .T
in W
Power-down W and Standby .1 0 0 Y
modes. M .TW
After a Power-up Reset or
W .1 O M W . O W W .C O
W .C Y .TW of the fact that this
WW .100Y.C M.TW
wake-up from Power-down or Standby mode, the user should be aware
W . 1 00Y M .TW W
W . 100 O M
W O Oscillator WW might take.C asOlong as one second toW stabilize. The .Cuser is.advised to wait for at
WW .100Y.C M.TW leastW
Y
00before W
.TTimer/Counter2 W after power-up . 1 00Y or wake-up M TW from Power-down
one second
W . 1 O M
using W O
W O
WW .100Y.C M.TW or Standby WW mode. 0 0 Y.Ccontents.TofWall Timer/Counter2
The WW Registers . 1 0 0Y.C must M .TW
be considered lost after
W . 1 O M W C O
W O C W . .TWupon start-up, no
WW .100Y.C M.TW matter whether
a wake-up
WW .100Y.from Power-down
M
or Standby
.TW mode Wdue to unstable
. 1 00Y clock signal
M
Wthe Oscillator O is in use or a clock signal O
Wis applied to the TOSC1 pin.
W O
WW .100Y.C M.TW• Description WW 0 0 Y.C . T W WW .100Y.C M.TW
of wake 1
W. up from M
Power-save or Extended Standby W modeCOwhenTthe timer is
W O
WW .100YWhen .CO the.Tinterrupt WWis met, 0Y.wake W is started
WW .100Y.C M.TWclocked asynchronously: W condition . 1 0 the up
M . process
W C O Wcycle W of the .C OM WW CO
Y.advanced W at least one
W Y. on the following
W W 0 Y timer clock,
.T W that is, theW timer is always 0 0
.1 the MCU
by
Mis.Thalted for four
W . 1 00 M .T before the processor W . 10 read the O M W O
WW .100Y.C M.TW
W O can .C counter value. After wake-up,
WW .100Y.C M.Tcycles, W it executes WW the .interrupt 1 00Y routine, M .Tand W
resumes execution from the instruction following
W W .C O
Y SLEEP. W
W 00
W.1 Y.COM
.T .1
CO after
M W.1 Y.COM W
WWRegister .shortly W W
W W
.100
• Reading
.T
Mresult.
W of the TCNT2
W
W
0
.10 on the
Y
O M .T wake-up W
from Power-save
W .100 mayOgive M.Tan incorrect
W O Since TCNT2 is clocked C asynchronous TOSC Wclock, reading.C TCNT2
WW .100Y.C done .T W WW synchronized 1 0 0Y. toM . W
Tinternal W .1
Y
00Synchronization M .Tmust
W be
OM through a register . the I/O clock
WW 00Y.C
domain. O takes
W W Y .C W W W W
0 Y . CO T W W .T W
W 00 M.Tfor every rising TOSC1
place 0
1edge. WhenMwaking . up from Power-save
W.1 mode, and Mthe I/O
W.1 Y.CO W W.active, Y . C O will read as the previous
W W 0 Y .CO entering W
W clock (clkW ) again becomes TCNT2 W value
.10
(before
M.T
W . 1 00 M .Tuntil I/O W
W .100edge.O M .T W C O
W O
sleep) the next rising TOSC1 The phase of the TOSC
WW .100Yclock after .
waking up from
WW .100Y.CPower-save . T Wmode is essentially WW .1unpredictable, 0 0Y.C M.T as
W
it depends on the wake-up time. M
The
.TW
W CO
M WW .CO is thus W WW 00Y.CO .TW
WW .100Y.recommended M. T W procedure W for reading 0 0 Y
TCNT2 .T as follows: W
W.1 Y.COM W
WW .101. 0Y WriteM any
.TW value to either Wof the registers .100
OCR2.T or TCCR2. W 00 .T
W O W . C O M W W.1 Y.COM W
W
WW .100Y.C M.TW
2. Wait for the corresponding Update Busy Flag to be W cleared.
W
W .100
Y
O M.T
W
W .100 OM
.T
W 3. Read O TCNT2. C W . C W
WW .•10During 0Y.C asynchronous .TW operation, WW .100Y. M .TW W 00Y
.1the M.T
M theW synchronization O of the Interrupt Flags W for C O
W .CO .timer WW Y.C plus.T W WW timer Y. .TW
WW .asynchronous
1 00Y M TW takes three processor . 1 00cycles M one timer cycle. The W .100is thereforeO M
W O
Y.C by at least
W
Wprocessor 0Y.can COread T Wtimer valueWcausing W Y.C of .TW
00setting
WW advanced 0 0 .T Wone beforeWthe . 1 0 M . the .the
1 M
Wthe 1
. InterruptOFlag.
. C
M The output compare WWpin is00changed Y .CO on.Tthe W timer clock W WW
and is not 0Y.CO W
W
W synchronized
. 1 00 Y
toM the
W
.T processor clock. W.1 W
O M W .1 0
O M.T
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
10
W.Prescaler OM .1 M
17.10 Timer/Counter W Y .C W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
M .TW W Figure
W . 10017-12.O Prescaler
M .T for Timer/Counter2 W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
WW .100Y.C10-BITM
clk
W O
WW .100Y.C M.TW W
I/O clkT2S
0 0 Y.C .T W T/C.T PRESCALER
. 1 M W O Clear W
.C O
TOSC1
WW .100Y .TW
00Y
clkT2S/8
clkT2S/32
clkT2S/64
clkT2S/128
clkT2S/256
clkT2S/1024
. 1 M W O W O M
WW 00Y.CO .TW WW .1AS2 0 0Y.C M.TW WW .100Y.C M.TW
W W. 1
.C OM
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
.C W PSR2 Y .C W W 0 .100 .T
WW .100Y M .TW W . 100 M .T W OM
W O W C O W .C
WW .100Y.C M.TW W W
1 00Y
.
M .TW W . 100
Y
M .TW
. W O
W O
WW
WW .100Y.C M.TW CS20
. 1 00Y M W O
CS21W O
W
WW .100Y.C M.TW
O
WCS22W 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 SOURCE M
W.1 Y.COM W W W.1 Y.COM W TIMER/COUNTER2 WclkW
CLOCK
0 Y.CO .TW
W W 00 .T W 0
T2
WW .100Y .TWclock source
MThe
W
W .100 O M .T W
W .100 O M.T to the main
W O for Timer/Counter2 C is named clkT2S. clkT2S W is by default .C connected
WW .100Y.C M .TW I/O clockWclkIOW
system
W
. By 10setting
.
0Y theMAS2 .TWbit in ASSR, W Timer/Counter2
.100
Y
M
is .TW
asynchronously
. O W O
W O W pin. Y.C enables WW .100as Y.Ca Real .Time W
WW .100Y.C clocked M .T W from the W TOSC1
. 1 0 0This M .TWuse of Timer/Counter2
W O M T Counter
W O C
W
WW .100Y.C then
O(RTC). When AS2 is set,
.T W WW pins TOSC1 .C and TOSC2
00YTOSC1Mand .TW WW .10from
are disconnected 0Y. Port C. M
W
.ATcrystal can
M be connected between W .1 the O TOSC2 pins to W
serve as an O
independent clock
W O WW .C
WW .100Y.Csource .T WTimer/Counter2.
for WW The . 1 0 0Y.C M
Oscillator .TW
is optimized for use withW 1 00Y kHz M
a .32.768 .TW Apply-
crystal.
M W O C O
W
WW .100Y.C
O an external clock source
ing
.TW WW to TOSC1 .C
00Y is notMrecommended. .TW WW .100Y. M .TW
M W . 1 O W O
W .COTimer/Counter2, WW Y.C TW Wclk W /8, 0clk Y.C
T2S .1 0 T2S /32,M
W/64,
.TT2S
WW .100YFor M .T W the possible00prescaled
.1 M
selections
. are:
W O
clk
O W O .C
W
WW .100Setting
clk.C
Y T2S/128,.T clkT2S/256, and clk
W WWT2S/1024. 00the
.C
YAdditionally, .TW
clkT2S as well WW as 0 (stop)
. .TW
Ymay be selected.
1to00operateOwith M
M
the PSR2 bit in SFIOR resets. 1 M
prescaler.
O This allows the W
user a pre-
W O WW 00Y.C W Y.C TW
WW .10dictable0Y.C prescaler. .T W W . 1 M .T W W
W .1 0 0
O M .
W OM W O
WW .100Y.C M.TW
W O
17.11 Register W W
Description Y .CO .TW W WW 00Y.CO .TW WW .100Y.C M.TW
W .10 0 .1 M
WW 00Y.CO
M
W
17.11.1 TCCR2 W – Timer/Counter
W .1 Control
O M.T Register
W .1
C W .TW 2
WW Bit.100Y. M7.T
W 6 W5 .1040
Y
3M
W
W .100 OM
.T
W O W C O 1
W 0
.C
WW .100Y.C FOC2 .TWWGM20 COM21 WW COM20 Y. .TW W CS20.100YTCCR2 M.TW
M W . 100 WGM21 O M CS22 CS21
W O
W W
Read/Write
Y . C OW
W R/W R/W W
W
R/W
0 Y .CR/W .TR/W W R/W
W WR/W 0 0 Y.C .TW
W Initial Value
. 1 00 0M.T 0 0 .
0 1 0 0 OM 0 0 0W.
1 O M
W
W
WW .100Y.C M.TW
O
• W BitW 7 – FOC2: .C O
Force Output
W CompareWW Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
The FOC2 W.1 bit isY.only C OM active when the WGM W W.1specify
bits
Y .CaO M
non-PWM
W mode. However, WWfor ensur- 0 Y .CO .T
W W W 00 W 0
W compatibility
ing
W .100 withOfuture M.T devices, this bitWmust W.1be set toOzeroM.Twhen TCCR2 is W W.1 when
written
.C OM
.C Y .C W W compare 0 Y
WW in.1PWM
operating 00Y mode. M.T
When W writing aWlogical one .100to the O M.T bit, an immediate
FOC2 0
W.1to its
match W is W forced on .the O W W .C W
0Y C Note
waveform W generation unit. The OC2
Y output isWchanged according
W
W bits.10setting.
COM21:0 W O M.T that the FOC2 bit is W
W .100
implemented O M.aTstrobe. Therefore it is the
as
.C WW the.1effect .C
valueW W in 0the
present 1 0YCOM21:0 M
W that determines
.Tbits 00Y of theMforced .TW compare.
W . O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WA.1FOC2 OM will not generate W .1
Winterrupt, OMwill it clear the timer in CTC mode using
W Y .Cstrobe
W W
any
0 Y .Cnor .TW
W OCR2
. 100 as TOP.M.T . 1 0 M
W O W O
.T W WW The.1FOC2 0 0Y.Cbit is M .TW read as zero. WW .100Y.C M.TW
always W O
OM W O
WW .100Y.C M.TW
0 0 Y.C .T W WW .100Y.C M.TW
W.1 Y.COM W WW 00Mode O
W • Bit
W 0 .CO .TWWaveformW
W 6, 3 –YWGM2[1:0]: Generation Y.C .TW
. 1 0 0 M .T . 0
1bits control M W 1
. the counter, O Mthe
O These W O the counting sequence of .C source for the maximum (TOP)
W
0 Y.C .TW W
Wcounter 0 0 C
Y.and . T W of waveform WWgeneration . 1 0 0Y to be M .TWModes of operation supported
.1 0 M W. 1
value,
OMwhat type W O used.
WW 00Y.CO .TW WW
by 0
the Timer/Counter Y.C unit.Tare: W Normal mode, WW Clear 0 Y.C on Compare
0Timer .TW match (CTC) mode, and
1 . 10 M W . 1 O M
W. OM W O Modulation (PWM)Wmodes. See .C
WW .100Y.C M.TW
two types
WW of.10Pulse 0Y.CWidth M .TW W .1 00Y Table M.T
17-2Wand “Modes of Operation”
on page 124.
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W.1 Y.COM W Table 17-2. W W.1Waveform Y .C
M
OGeneration
W Mode Bit WW 00(1)Y.CO .TW
Description
W W 0 0 .T W .1
W 00 .T W.1 Y OM Timer/Counter Mode M
.CO Update
W W.1 Y.COM W W
WGM21 .C
WGM20 W W WW of 0 Y
0 TOP MOCR2 .TW of TOV2 Flag
W 0 0 .T W (CTC2).100 (PWM2)M.T . 1
W W.1 Y.COM W Mode
WW 00Y.CO .TW
Operation
W WW 00Y.CO .TW Set on
W 00 .T W .1 0xFF M
W.1 Y.COM W
0
W
0
W.1 Y0.COMNormal W WW 00Y.CO .TW
Immediate MAX
W W 0 .T W 0 0 .T W 1
. 0xFF M
0
W.1 Y.COM W
1 0 .1 1 M
PWM, Phase Correct
WW 00Y.CO .TW
TOP BOTTOM
W W WW 00Y.CO .TW W 1
W 00 .T 2 1
W.1 0 Y.COCTC M .OCR2 M
Immediate MAX
W W.1 Y.COM W W W W WW 00Y.CO .TW
W .100 M.T 3
W 010 .T .1 OM
W.1 Y.COM W
1 Fast PWM
W O W W0xFF Y .
BOTTOM
C W
MAX
.C W W 00
WW .100Y .TW 1. TheW
MNote: CTC2 and.1PWM2
W
00 bit definition
O M.T names are now obsolete. W.1 UseYthe M.T definitions.
OWGM21:0
W O C W .C
WW .100Y.C M.TW However,WWthe functionality
1
.
00Y andM .TW of these bits
location W are compatible.100 withOprevious
M .TWversions of
W . O W
O WW .100Y.C M.TW
W the timer.
W CO Output W O
W
WW .100Y.C • M
O Bit 5:4 – COM2[1:0]:
.TW WWCompare 0 0 Y.Match .T W Mode WW .100Y.C M.TW
.1 M Wor bothY.ofCO
W O
These bits control the Output WW Compare .COpin (OC2) behavior.W IfW one the COM21:0
.TW bits
WW .100Y.Care M T W
. the OC2 output overridesW . 10 0 Y
M .T W .1 00 pin it is M
O
W W .C O set,
W W W the
Y .
normal
CO port
W
functionality
W WW 00Y.C
of the I/O connected
.T W
to.
Y W 0 T
0 Register. (DDR) bit corresponding
W 00 However,
W.1 Yin
.T note that the Data Direction
OM to enable the output W.1 Y.COM W W W.1 to OC2 Y
pinM
.CO .TW
must be set
W .C order W W driver. W 0 0
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C
Y. OC2.TisWconnected W W .C
Yfunction of.Tthe W COM21:0W 00 on the WGM21:0
WW .100When M Table 17-3 shows W
to the pin, the
W .100 O M
bits depends
W.1 Ybits M.T
Oare
W bit O
setting. the COM21:0 C bit functionality when theW WGM21:0 .C setTto
WW .10normal 0Y.C orM .TW W 100Y
.
M .TW W .100 M . Wa
CTC mode (non-PWM). . W O
W .CO W
WWMode,.1non-PWM .CO .TW WW .100Y.C M.TW
WW .1Table 00Y 17-3.M.TCompare W Output 00Y M
Mode W O
W Y.C
O WW 00Y.CO .TW WW .100Y.C M.TW
WW .100COM21 . T WCOM20 WDescription .1 M
W W .C OM
Y W
W
W .100 0 OM.T 0 Normal port
W .1 operation,
.C OM OC2 disconnected.
W W.1 Y.COM W
C W .TW
WW .1000Y. M.T 1
W W OC2.1on
Toggle
Y
00compare Mmatch
W
W .100 OM
.T
W O W C O W .C W
WW .1010Y.C M.TW 0 WW
Clear OC2 on . 0Y. match
10compare M .TW W .100
Y
M.T
O W O W .C O
W
WW .1100Y.C M.T1W Set W
W
OC2 on compare
.C
00Y matchM.TW WW .100Y M .TW
W . 1 O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 17-4 O M the COM2[1:0] bit .1 M
W WTable Y .C shows
W W WW functionality
0 Y .CO when theWWGM21:0 bits are set to fast PWM
.T
W .100 M.T .1 0
mode.
W C O W W .C OM
.TW WW .100Y. M .TW W 00Y
.1PWM M .TW
M W
Table 17-4. OCompare Output Mode, W
Fast Mode
C O (1)
. 1 00Y M WCOM21 O COM20 Description W O M
W
0 Y.C
O
1 0 O
W. .C OM
W WW 00Y.CO .TW
0 0 Normal
WW 00OC2
port operation,
W Y.C
disconnected.
.TW
00 Y .T W . 1 M . 1 M
. 1 M W 0 O 1 Reserved W O
WW 00Y.CO .TW WW 1 .100Y.C 0M.TW Clear OC2W
W
. 1 0Y.C M.TW
0match,
W. 1 OM on W
compare O OC2 at BOTTOM,
set
.C WW 00Y.CO .TW(non-inverting W W 0 Y.C W
W W
.1 00 Y
M .T W W
W . 1 O M mode)
W .1 0
O M.T
W O
WW .C WW match, Y.C W
WW .100Y.C M.TW 1
. 100Y 1 M.TW Set OC2 on compare
W . 100 clear OC2 O M .TBOTTOM,
at
W O W O (inverting mode) W .C
W
W O W C O
W O
W1.WAmatch .C occurs.Twhen WWTOP .and Y. .TW
WW .100Y.C M.TW
Note: special Y case W OCR2 equals COM21 is set. In this case, the compare
. 1 0is0ignored, but M the set or clear is done Wat 100 See “Fast
TOP. O M PWM Mode” on page 125 for
W W Y .C O
W W W W
more details.0 Y .CO .TW W W 0 0 Y.C .T W
W 0 0 .T .1 0 M . 1 OM
W W.1 Y.COM W Table 17-5 shows WW the 0 Y .CO .T
COM2[1:0] bitW functionality W WWthe0WGM21:0
when 0 Y.C .TW
bits are set to phase cor-
W 00 .T rect PWM modeW.10 W M . 1 M
. 1 M O W O
W
WW .100Y.C M.TW
O
W W .C O
W
.

W 00 Y .T W 1 (1) OM
W.1 Y.COM Table 17-5. Compare W.1 Output C O M Phase Correct PWM
Mode, W W.Mode .C
W W 00 .T W W W
1 0 0 Y .
M .T W W . 1 00Y M .TW
W. 1 OM COM21 COM20 .
Description W O
WW .100Y.C M.TW0 W
0 . 1 M
Normal port operation, OC2 disconnected.W O
WW .100Y.C M.TW W .1 M WW 00Y.CO .TW
0 1 Reserved
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T1 0 Clear.1OC2 on compare M match when up-counting. .1Set OC2 on M compare match
W W.1 Y.COM W W W
when downcounting. Y .CO .TW W WW 00Y.CO .TW
W 00 .T W .10 0 .1 M
W.1 Y.COM 1 W 1 W W .C OMmatch when up-counting. WW Y COcompare
.on W
W Set OC2 on Y
compare W W Clear
.10 0
OC2
M.T
match
W . 1 00 M .T W
when W . 100
downcounting. O M .T W C O
W
WW .100Y.C
O
TWA special case WW .C
00YOCR2 equals .TW WW .100Y. M .TW
Note: M.1. occursW . 1
when O M TOP and COM21 is W
set. In this O
case, the compare
W O
WW C is done
Y.clear WW Correct Y.C Mode”.TonWpage
WW .100Y.C M.Tmatch W is ignored, but the set
.1 0 0 or
M .T Wat TOP. See “Phase . 1 0 0PWM M
W W .C O 127 for more details.
Y W
W 00
W.1 • YBit O M.T W.1 Y.COM W W W.1 Y.COM W
.C W
W W
. 1 00 2:0 –
M .TW
CS2[2:0]: Clock W Select
W . 100 O M .T W
W .100 O M.T
W TheYthree O C
.source W .C
Y see Table W
WW .117-6. 00
.C Clock .TW
Select bits select
WW the.1clock 00Y M
to be
.TW
used by the W Timer/Counter,
.100 M.T
M W O W C O
W
WW .Table .CO .TW WW .100Y.C M.TW WW .100Y. .TW
1 00Y17-6. MClock Select Bit Description W O M
W O W
WW Description .CO .TW WW .100Y.C M.TW
WW .10CS22 0Y.C MCS21 .TW CS20 . 1 00Y M W O
WW .1000Y.C M0.TW 0 W No clock . 1 M WW 00Y.CO .TW
source (Timer/Counter stopped).
W O WW 00Y.CO .TW
WW .1000Y.C M 0. T W W clkT2S/(No .1 prescaling)
W
W.1 Y.COM W
W C O
1
W W .C OM W
WW 0.100Y. 1 .TW
Y W W 00 .T
M 0 WclkT2S/8.(From
W 100 prescaler) O M.T W.1 Y.COM W
W O W .C W
WW 0 .100Y.C 1 M.TW 1 WclkT2S/32 .(From Y
100 prescaler) M .TW W
W .100 OM.T
O W O .C
W
WW 1 .100Y.C0 M.TW 0
W/64 (From Y.C .TW WW .100Y M.T
W
WT2S
clk
W .100prescaler) O M W O
W
WW1 .100Y.C 0
O
.TW1 clkW W
T2S/128 (From
Y.C
00prescaler) .TW WW .100Y.C M.T
. 1 M
W W .C O M
W W W Y .CO .TW W WW 00Y.CO
W 1 00 Y 1 .T 0 clk W /256 (From 0 0
prescaler) .1
W.1 Y.COM W
T2S
W W.1 1Y.COM 1W clk /1024 W 0 W WW

W 1
00 .T T2S W (From prescaler)
0 .T
W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.CRegister OM .1 M
17.11.2 TCNT2 – Timer/Counter
W W W WW 00Y.CO .TW
W 00 .T W.1 4 Y.CO3M W2
W WBit.1 Y.COM 7 W 6 5W
0 1 0
.T W W 0 0 .T W . 1 0TCNT2[7:0] M .T
. 1 M
.C OM
W WW Y .CO R/W .TW R/W W WW 00Y.CO .TW TCNT2
00 Y .T W 10
Read/Write 0 R/W .1
0 .T W Initial
0 0 Y .T W 0 0
W .1 M
0 0
1 0 . 1 M W O
W. OM WW O
Y.C Register WW access, 0Yboth.C for read .TWand write operations, to the
0 0 Y.C .T W WThe Timer/Counter
. 1 0 0 M .T W gives direct . 1 0 M
. 1 M O W O
WW 00Y.CO .TW W WW 00Y.C
Timer/Counter unit 8-bit counter.
.T W
Writing
W
to
W the TCNT2
1 0 0 Y.C Register
. T
blocks
W (removes) the compare
match on .the 1 following OMtimer clock. Modifying .
the counter (TCNT2) M while the counter is running,
W W.1 Y.COM W WW a 0risk Y .Cmissing W W WW 0 .CO and
YTCNT2 .T W
W
introduces 0 of .T a compare match between 0 the OCR2 Register.
W
W .100 O M.T W .1
. C O M W W.1 Y.COM W
WW .17.11.3 Y.C OCR2 W WW Register .100
Y
M.T
W W .100 M.T
W 100 O M.T– Output Compare W O W W .C O
Y
M.T
W
W O W O W W .C O
WW .100Y.C M.TW .TW
Bit 7 6 5 4 3 2 1 0
WW .100Y.C M.TW W . 1 00Y M
W .CO R/W
OCR2[7:0] OCR2
W CO W W . C O W Y W
W . W Y W W .10 0 .T
Y W .10 00 M.T 0
W
W .100 O M.T W C 0O W W 0 .C
OM 0
WW .100Y. C
.T W
Initial Value
W W 0 0 Y . . T W 0
W 0
. 1 0 0 Y
M .TW 0
1
W. Register OMcontains an 8-bit value W O
W OM WW that.10is0continuously Y.C
WW .100Y.C M.TW
The Output Compare compared with the
WW .100Y.C M.TWcounter value M .TW
(TCNT2). A match can be used to WW 00Y.C
generate an output O compare interrupt, or to
W W Y.C O
W W W W
0 Y .CO .TW W .T W
W 00 .T generate a waveform 0
output
W.1 Y.COM W
on the OC2 pin. .1 M
W 100 – AsynchronousM.T
W 00 .T W.1 Y.COM W
17.11.4 W.‘ASSR
.C O Status RegisterW W.1 Y.COM W W
WW .100Y W W .100 M.T
W 00 .T
W O M.T W C O W W.1 Y . C OM 0
WW .100Y.C M.TW
Bit
WW .100Y
7 6 . 5
M .T– W AS2 WTCN2UBW.10OCR2UB
4 3 2 0 1
M .TW
O
WWR 00YR.CO R.TW R/W Y.C
– – – TCR2UB ASSR
W W . CO W W 0 .T W
Y W W 0
W 00 .T W.1 0 Y.COM
Read/Write R
W.1 Y.COM .1 OM0
R R R
W Initial Value
W 0
W WW 0
0 0 Y0 .C
.T W 0 W 0W
100
0
.TW
W . 1 00 M .T W .1 O M W . O M
W
WW .100Y.C• Bit
O
3T–W
. AS2: Asynchronous WW .10Timer/Counter2 0Y.C M.TW WW .100Y.C M.TW
W .C OM AS2 is written to zero, WWTimer/Counter Y .CO 2 .isTclocked W W
W
WI/O 0 .CO. When
Yclk W
W W 00 Y When
.T W W 10 0 from the clock,
. 1 0 I/O M.T AS2 is
. 1 M . O M
Wis clocked from a Crystal OscillatorW W .C O
W
WW .100Ylator .CO to.T
written one, Timer/Counter2
W WW .100Y.C M.TW W connected . 1 00Yto the Timer M .TW Oscil-
OM
1 (TOSC1) pin. When the value of AS2 is changed, the WW 00Y.C
contents of TCNT2, O OCR2, and
W W Y .C W W W W
0 Y .CO .TW W .T W
W 00TCCR2 might .T be corrupted. W.10 OM .1 M
W .10•0 Bit 2O– M .T W 00 .T W.1 Y.COM W
W .C TCN2UB: Timer/Counter2 W W.1Update Y . C OM
Busy
W W 0
WW .1When W W .10bit .T
W
00Y Timer/Counter2
O M.T
W
W .100
operates asynchronously O Mand.T TCNT2 is written,
W Wthis OM set.
becomes
.C
.C W .C Y .TW
WW .When 1 00Y TCNT2 M .TWbeen updated
has W from the .1
Y
00temporary M .TW register,Wthis bitWis.1cleared
storage 00 by M
O hard-
W O
Wware. A logical
WW .100Y.C M.TW
O zero in this bit indicates
WW that Y.C is ready
00TCNT2 .TWto be updated WWwith .a10new 0Y.C value. .TW
M
. 1 M
W W .C O W W Y .C O
W W W W
0 Y .CO .TW
Y W W 0 .T 0
W • Bit
W .1001 – OCR2UB: O M.T Output Compare W .10
Register2
.C
Update
OM Busy W W.1 Y.COM W
.C W W
W
W When .1 0Y
0Timer/Counter2 M .TWoperates W asynchronously
W .
Y
100 andOM OCR2 W
.T is written, this bitWbecomes .100 set.M.T
O
W W OCR2
When .C O been updated from the
has W temporary Y .Cstorage.Tregister, W this bit W W
is cleared 0by .C
Y hard- .TW
Y W W 0 0
W ware. .A10logical
W
0 .T
OMin this bit indicates W
zero that WOCR2.10 is ready
.C OMto be updated with W a newW.1value. Y
M
.CO .TW
W .C Y W W 0
W .100
Y .TW W .100 OM Busy
.T 0
W.1 Y.COM W
BitW .C OM W WRegister2 .C W W
• W 0 – TCR2UB: Y Timer/Counter
TW Control
W 0Y Update
M.T
W 00 .T
W
When W .100
Timer/Counter2 O M.operates asynchronously W .10and
.C
TCCR2 O is written, this bit W W.1 set.
becomes Y. C OM
Y.C W Y W W 0
WW TCCR2
When .100has been .TW from the
Mupdated
Wtemporary
W .100storageOregister, M.T this bit is cleared W .10hard-
by OM.T
W O Y.C to be.T W Y .C
WWA logical
ware. 00zeroY.Cin this .bit TW indicates that WW TCCR2.1is 00ready M
W
updated with aWnew value. .100
.1 M W O W
WW .CO .TofWthe three Timer/Counter2 WW .100YRegisters .C W its update WW
If a W write is performed
. 1 00Y to any M W O M .Twhile busy flag is
set, the W W value
updated .C O get corrupted andW
might cause an Y . C
unintentional W
interrupt to occur.
Y W W .100 .T
W
WW .100Y. C W Y
W O M.T
W
W .100
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 mechanisms OM for reading TCNT2, .1 M
W WThe Y .C W W WWOCR2, 0 Y .COTCCR2
and are different. When reading TCNT2,
.TW the value in the temporary stor-
W 00 timerMvalue
the.1actual .T is read. When reading . 1 0 OCR2 orM TCCR2,
W WW Y .CO W W WW 00Y.CO .TW
W age 0
register is read. .T
O M.T W .1 0
.C OM W W.1 Y.COM W
.C W W Y .TW RegisterW W.100 .T
00Y
W.1 Y17.11.5 O
W
M.T TIMSK – Timer/Counter W .100Interrupt O MMask W . C OM
.C WW .100Y. C Y W
1 00 M .TW M .TW W
W .100 3 OM.T2
. O W O .C
W
WW .100Y.COCIE2 M.TTOIE2 WWOCIE1A.100OCIE1B .TW OCIE0
Bit 7 6 5 4 1 0
Y.C W W Y
00 .T M
.1 W .CO R/W.TW R/W
TICIE1 TOIE1 TOIE0 TIMSK
M W O
WW 00Y.CO .TW W W
Read/Write
00 Y .C
R/W .TR/WW R/W W WR/W
.10 0 Y
R/W
M R/W
W .1 O M W.1 Y.0COM 0 W W 0W 0 .CO 0
Y .TW
Initial Value 0 0 0
.C W W 00
WW .100Y .T W W . 1 0 0 M .T .1 O M
W OM W .CO .TW OutputWCompare WW 0Match 0Y.C Interrupt .TWEnable
WW .100Y.C M.TW • Bit WW 7 – OCIE2:
. 1 0 0 YTimer/Counter2
M . 1 M
W O
W O WW .CisO written W Y.CStatus.T W
WW .100Y.C M.TW
When Wthe OCIE20Y bit
. 1 0 M .TWto one andWthe I-bit W . 1
in
00the
O M
Register is set (one), the
W O Timer/Counter2 W Compare .C O Match interrupt is enabled.
W The C
corresponding
. W interrupt is executed if
WW .100Y.C M.TW a compare WWmatch 0 0 YTimer/Counter2 .T W W . 1 0 0Y M .Tset
.1 in OM occurs, i.e., when the
WW 00Y.CO .TW
OCF2 bit is in the Timer/Counter
W W Y. CO
W Interrupt W WW
Flag Register 0 Y .–CTIFR. .T W W
W
W .10 0
O M.T W .1 0
.C OM W W.1 Y.COM W
C W W
WW .100Y. W
M.T • Bit 6 – TOIE2:
W .100
Y
Timer/Counter2 M.TOverflow Interrupt
W
W .100
Enable OM
.T
W O W C O W .C W
WW .100Y.C M.TWWhen the W
W Y. W
one and the W 0Y Register
.10Status M.T is set (one), the
TOIE2 bit
W . 10is0 written O Mto.T I-bit inW the
C O
W O .C W .
Y interrupt .TW
WW .100Y.C M.TW Timer/Counter2 WWOverflow . 1 00Yinterrupt M .isTW enabled. The Wcorresponding .100 M is executed if an
W O overflow in Timer/Counter2 W C O
occurs, i.e., when the TOV2 W W
bit is set in .C
the O Timer/Counter Interrupt
WW .100Y.C M.TFlag W W W
1 00Y
.
M .TW W . 100
Y
M .TW
Register – TIFR. W . O W O
W
WW .100Y.C M.TW
O
O W O
17.11.6WW TIFR – Y .CO .TW InterruptWFlag
Timer/Counter WWRegister 0 0 Y.C .T W WW .100Y.C M.TW
W 0
0
W.1 Y.COMBit W W.1 Y.COM W WW Y1.C
O
W
7WW 3 W 0
W W
. 1 00 M .T W
6 00
. 1 5
O M .T 4 2
W .1 0
O M0.T
W O OCF2 W TOV2 .C W 0Y. C TOV0 W TIFR
WW .100Y.C Read/Write
ICF1 OCF1A OCF1B TOV1 OCF0
M .TW R/W
W R/W.100YR/W M .TW R/W W R/W W.10R/W
R/W O M.T
R/W
W O W C O W .C W
WW .100Y.C InitialMValue .TW 0 WW 0 Y. W 0 W0 .1000
Y
M.T
W . 100 0 OM0.T W C O
0
W
WW .100Y.C
O
W
.–TOCF2: WW 00FlagY.C .TW WW .100Y. M .TW
• Bit M 7 Output Compare
W . 1 2 O M W O
W .COOCF2 WWthe Timer/Counter2 .C
WW .100YThe .T W is set (one)
bit WW when a
. 1 0 0Y.C match
compare M .TW occurs between . 1 00Y W
M.Tand the
W O M W O W W .C O
Y.C in OCR2 WW Register2. .C OCF2 .TW 0Y executing .TWthe
WW .100data M .TW– Output Compare . 1 00Y M
is cleared byWhardware
W . 10when O M
W CO
corresponding interrupt handling Wvector. Y .C O
Alternatively, OCF2 is cleared W by writing .C
a logic one
WW .10the 0Y.flag. .T W WW OCIE2 1 0 0(Timer/Counter2 M .TW CompareWmatch Interrupt . 1 00Y Enable), M .TWto
OM When the I-bit in SREG, . W O and
W W Y .C W W WW 00Compare Y .CO match .T W W W 0 0 Y.C .T W
W .1 00
OCF2 are set
M .T(one), the Timer/Counter2
W . 1 O M Interrupt is executed.
W .1 O M
W O WW .100Y. C
WW .•10Bit 0Y.C M.TW WW .100Y.C M.TW M .TW
O W O
W 6 – TOV2:
O
Y.C bit is set
Timer/Counter2 Overflow
WW 00Flag Y.C TW WW .100Y.C M.TW
WW The 0 0
TOV2 .T W (one) when W an overflow . 1 occurs in M .
Timer/Counter2. TOV2 W is cleared by
W W.1 Y.COM W WW interrupt Y
O
.Chandling W W W 0 Y .COhard-.TW
ware when executing the correspondingW .10 0 M. T vector. Alternatively, TOV2
.1 0 is cleared
W
W . 100 O M .T W C O W W OM
.CInter-
by writingYa.Clogic one W to the flag. When W the SREG Y . I-bit, TOIE2 W (Timer/Counter2 W Overflow
0 Y W
W
1 00
W rupt .Enable), M .T are set (one), W
W . 00
1Timer/Counter2 O M .T W
0
.1executed. O M.T
W and
.CO is.Tset
TOV2 the
Y.C counting
Overflow interrupt W is .C In
WW PWM .mode, 00Y this bit W when Timer/Counter2 WW .100changes M .TW directionWat $00. . 100
Y
M.TW
1 M W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
. C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1Function MRegister .1 M
17.11.7 SFIOR – Special
W Y .C OIO
W W WW 00Y.CO .TW
W 00 .T W.1 4 Y.COM3 W 2
.T W W . 10 0 M .T ADTS1 W . 1 0–0 M .T
.C OM
W WW Y .COR/W .TWR/W
ADTS2 ADTS0
W WW 00Y.CO .TW ACME PUD PSR2 PSR10 SFIOR
00 Y .T W 10
Read/Write 0 M R/W .1R R/W M R/W R/W R/W
W.1 Y.COM W W.Value C O WW 0 00Y.CO0
00 .T W WInitial
10 0 Y . 0
M .T W 0 0
W .1 M .TW 0 0 0
W. 1 OM W . O W O
0 Y.C .T W W• W Bit 1 – 0 0 Y.C Prescaler
PSR2: .T WW .100Y.C M.TW
WReset Timer/Counter2
.1 0 M W. 1 M W O
WW 00Y.CO .TW WW this.1bit
When CO toTone,
0isY.written WW .10prescaler
W the Timer/Counter2 0Y.C will .TbeWreset. The bit will be cleared
1 0 M . W O M
W. OM WW 0after
by hardware Y.C theOoperation is performed.
WWWriting a
0Y .C to this.Tbit
zero Wwill have no effect. This bit
WW .100Y.C M.TW W
will always . 1 0 M . TW
as zero if Timer/Counter2 isWclocked by .1 0
O M
W O W be read .CO .TisWoperating in W 0Y.C
the internal CPU clock. If this bit is
WW .100Y.C M.TW WWwhen.1Timer/Counter2
written 00Y M
Wasynchronous . 1 0 mode, M .TW
the bit will remain one until the
W O W C O W W .C O
.C W Y . W W 0 Y W
M.T
prescaler has been reset.
WW .100Y M .TW W . 100 M .T W .10 O
W O C
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
18. M .TW – Serial
SPI W Peripheral
W . 100 .T
Interface
O M
W
W .100 O M.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Features
1 0 O
W. .C OM
W •W W
Full-duplex, Y .CO .TSynchronous
Three-wire W W WW
Data Transfer
0 0 Y.C .TW
00 Y .T W . 1 0
0 Slave Operation M . 1 M
. 1 M • Master or O W O
WW 00Y.CO .TW WW 0or0Y
•WLSB First
.C .TWTransfer W
W
1 00Y
.C .TW
1 . 1 MSB First M Data
W . O M
W. OM WWProgrammable .CO Bit.Rates WW .100Y.C M.TW
WW .100Y.C M.TW •W Seven
. 1 00Y M TW
W O
of W O
W
WW .100Y.C M.TW
O • EndW
W
Transmission
0 0 Y.C Interrupt .T WFlag WW .100Y.C M.TW
• Write Collision .1 Flag Protection M WW 00Y.CO .TW
W W Y.C O
W W WW 0 Y .CO .TW W
W 00 .T • Wake-up from 0
Idle
W.1 (CK/2)
Mode
OM SPI Mode .1 M
W W.1 Y.COM W • DoubleW Speed Y .CMaster W W WW 00Y.CO .TW
W 00 .T W 0 0 .T .1 M
W W
W 18.2.100Overview
W O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W . C
WW .100Y. W W
M.T The Serial Peripheral
Y
.100Interface M .TWallows high-speed
(SPI)
W
W .100
synchronous OM
.T
data transfer between the
W O W C O W .C W
WW .100Y.C M.TWATmega32A WW Y. .TorWbetween several W 0Y
.10devices. M.T
and peripheral
W . 100 devices O M AVR
W C O
W O WW .100Y .
WW .100Y.C M.TW WW .100Y.C (1) M .TW M .TW
Figure 18-1. SPI Block
W Diagram O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM.T
W O WW .100Y. C
WW .100Y.C M.TW DIVIDER WW .100Y.C M.TW M .TW
/2/4/8/16/32/64/128 W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. W W .100
Y
M.T
W 00 .T
SPI2X

W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
SPI2X
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
W O W
Note:
W 1.WRefer to Figure
.CO .TW 1-1 on page 2, and
WW .100Y.C M.TW
Table 12-6 on page 59 for SPI pin
WW
placement.
TheW interconnection. 1 00Y between M Master and Slave CPUs with SPI is shown in Figure 18-2. The sys-
W W Y .C O
W W WW 0 Y .CO .TW
W
tem consists of
.10two0 Shift
M.T
Registers, and a Master clock
.1 0 generator. The SPI Master initiates the
W C O W W .C OM
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 OM cycle when pulling W .1 Slave Select M
W Wcommunication Y .C W W
low Wthe
0 Y .CO SS .TW
pin of the desired Slave. Master and
W 0 0 .T . 1 0 M
W W.1 Y.COM W
Slave prepare the data to be sent in
W
their
W respective
0 Y .CO Shift Registers,
W
and the Master generates
W W .10interchange .T
M.T
W the .required
W 100 Othe M.T
clock pulses on the SCK line to
WMOSI, C OandMdata. Data is always shifted from Mas-
C O W ter to Slave .C
on Master Out – Slave W In, Y .
line, from W
.T Slave to Master on the Master In
1 00Y
.
M .TW W . 1 0Y
0Out, M .TWAfter eachW W . 100the Master O M
. – Slave
WW 00Y.CO .TW
MISO, line. data packet, will synchronize the Slave by pulling
W
0 Y .CO .TW W high the Slave Select, SS, line. WW .100Y.C M.TW
0
W.1 Y.COM W .1 M WW 00Y.CO .TW
W WW 00Y.CO .TW W
.100 M.T W.1 Y.Cas
When configured
OM a Master, the SPI interface W.1 hasYno .CO
M
automatic control of the SS line. This
WW 00Y.CO .TW W
must W be
100
handled by user .T W
software before W W
communication.10 0 can M .T
start. W When this is done, writing a
W . 1 O M W . O M W
Wclock generator, . C O
byteW
W to the .SPI .C Register
Data
TWstarts the W SPI Y andTthe W hardware shifts the eight
WW .100Y.C M.TW bits into the
0Y
10Slave. AfterM .shifting one byte, the W .100clock generator
SPI O M. stops, setting the end of
O W O .C
W
WW .100Y.C M.TW WW .1Flag
Transmission
.C
00Y (SPIF). .
IfT W SPI Interrupt
the WWEnable . 1 0 0Y(SPIE)
bit Min .TWSPCR Register is set, an
the
W C O WisWrequested. .CTheOM WW Y.C
O
W
W Y. W interruptW 0 0 Y Master
.T W may W
continue to shift
.1 0 0
the next
M.Tby writing it into SPDR, or
byte
W .1 00 M .T W . 1 O M W C O
W O signal theWend of packet
0Y.C for
by pulling high the Slave
WWSelect, SS Y.line. The.Tlast W incoming byte will be
WW .100Y.C M.TW kept inWthe Buffer . 10Register M .TWuse.
later W . 100 O M
W O
W O
WW .100Y.C M.TW When configured WW .100Y.C M.TW WW .100Y.C M.TW
as a Slave, the SPI interface will W W sleeping
remain Owith MISO tri-stated as long
W O WW 00Y.CO .TW 0Y.C the M .TW of the SPI Data
WW .100Y.C M.TW as the SSWpin is driven . 1 high. InM this state, softwareW may.1update
W
0
O contents
W O
WW but.1the
W .CO .not outW .C
00Y clockMpulses .TW on the SCK pin
WW .100Y.C M.TWRegister, SPDR, 00Ydata will M TWbe shifted W by incoming
W . 1 O
O W O . C
W
WW .100Y.C M.TW
until the SS
W
pin W is driven
0 0 Y.C
low. As one
.T
byte
W has been
WW .100Y
completely shifted, the
M
end
.TWof Transmission
Flag, SPIF is set. IfW the 1
. SPI Interrupt OM Enable bit, SPIE, W in Wthe SPCR .Register O is set, an interrupt
W
WW .100Y.C M.TisW
O
requested. W
W
The Slave 0 0
may Y.C continue .T Wplace newW
to data to be
. 1 0 0Y Cinto SPDR
sent M .TWbefore reading
W .C O the incoming data.WThe W.1last incomingY
M
.CO byte W will be kept W in W
W
the Buffer 0
O
Y.C for.Tlater
Register W use.
W W 00 Y .T W W 10 0 .T .1 0 M
. 1 M W . O M W O
W
WW .100Y.C M
O
.TW 18-2. SPI WW .C
00Y Interconnection .TW WW .100Y.C M.TW
Figure Master-slave
. 1 M
W W .C O
Y W 0
W
W .100 O M.T MSB MASTER
W .10 LSB
C OMMISO MISO
MSB
W W.1SLAVE .C OM LSB
WW .100Y. C
.TW 8 BITW W
SHIFT REGISTER
1 00Y
.
M .TW W8 BIT SHIFT .
Y
100REGISTER M .TW
M W . O W O
W
WW .100Y.C M.TW
O
WW .100Y.C MOSI .TWMOSI WW .100Y.C M.TW
M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00 .T W.1 Y.COM W .1 M
W
W .100 O M.T
W
W .100 OM SCK
.T
W W.1 SHIFT M
.CO .TW
W Y .C W SPI
W W 0 Y .C SCK
T W W 0 0 Y
ENABLE
W 00 .T 0 . .1 M
W.1 Y.COM W
CLOCK GENERATOR
W W.1 YSS . C OM SS
W WW 00Y.CO .TW
W W 00 .T W
W
. C W W 00 .T
WW .100Y M.T
W O W W .C O W
WW .The .C is single
system W bufferedW in the transmit Y direction.Tand W double buffered W .100receiveOdirec-
in the
M.T
W
Y
100 This means O M.T that bytes to be W W .100 cannot O Mbe written to the SPI W W .C
tion. transmitted .C Data Register
Y before
.TW
WW the .1 0Y.CshiftMcycle
0entire .TWis completed. W When.1receiving 00Y data, M
W
.Thowever, W
a receivedW .100 must
character O Mbe
O W O C
Y. Oth-.TW
WW read
W
0Y.Cthe SPI .T W RegisterW W 0Y.C
0next .TW WW .shifted 100 in. O
. 1 0from M
Data before the
W . 1 character
O M has been completely
W .C
M
W
erwise, the .C O byte is lost.
first W Y . C W W W 0 Y W
W W
.1 00Y M .TW W
W . 100 O M .T W .10 O M.T
InW O the control logic will Y.Cincoming .C
W pin. 0To0Yensure .TW
WW SPI Slave
0 0Y.Cmode, .TW WW sample . 1 00the M .TW signal of theW SCK
.1 M
correct
W
. 1
W sampling .C
M
Oof the clock signal, theW W
minimum O
low.Cand high periods
Y W should W
W be:W
0 Y .CO .TW
W Y
.100 longer M .TW W 00
W.1 Y.COM W
.T 0
W.1 Y.COM W
Low W
periods: .C O than 2 CPU clock cycles.
W W
WW .100Y W W .100 M.T
W 00 .T
W O M.T2 CPU clock cycles. W .C O W W.1 Y.COM
WW .100Y.C M.TW
High periods: longer than WW .100Y M.T
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 the SPI
WWhen .C OMis enabled, the data W W.1 ofYthe
direction .CO
M
MOSI, MISO, W SCK, and SS pins is overridden
W W 0 0 Y .T W W 1 0 0 .Tport
W.1 Y.COM W
according to Table 18-1. For more .
details on automatic M overrides, refer to “Alternate Port
W W W W
0 Y .CO T W
W 0 .
.100
W Functions” on page.T55.
.C W .TW
00Y .TW W Table.118-1.00Y SPIMPin Overrides W .100 OM
.T
W.1 Y.COM W W C O W W .C W Slave SPI
00 .T WWPin .100Y. Direction, M .TWMaster SPI W W.100Y ODirection, M.T
. 1 M W O .C
W .CO .TW W .C Defined
00Y User M .TW WW .100Y Input .TW
. 1 00Y M
WMOSI . 1 O W O M
WW 00Y.CO .TW W WW 00YInput
MISO .C .TW WW .100Y.C UserMDefined .TW
1 . 1 M W O
W. OM W .CODefined WW .100Y.CInput M.TW
SCK User
M .TW
W O SSWWW
O
Y.CDefined.TW
W
WW .100YInput .CO .TW
WW .100Y.C M.TW
User
0
0 OM
W O W.1 Y.COM W W W .C
WW .100Y .C
.TW
W
Note:W See “Alternate
10of0 the user .T of Port B” onWpage 59
Functions
M
0 Y
10 a detailed
.for M .TW of how to define the
description
M W . O W C O
O WW .100Y.
W direction defined SPI pins.
WW .100Y.C M.TW The following WW code Y.C
00examples TW how to initialize
.show M .TW
. 1 M W the SPI as O
a master and how to perform a
W W Y .C O
W W WW 00Y .CO .inTW W W 0 0 Y.C by the .T W
W .100 M.T
simple transmission. .1 DDR_SPI M the examples must
W.be 1 replaced
OM actual Data Direction
W O W C Opins. W .C
WW .100Y. C Register
.TW actual data W W
controlling
1
the
00Y
.
SPI
M .TW
DD_MOSI, DD_MISO
W and
. 100
Y
DD_SCK
M .TWbe replaced by the
must
M . W O
W O WW 0bits
direction COtheseTpins.
for
0Y.DDR_SPI W For example WW .100Y.C M.TW
if MOSI is placed on pin PB5, replace
WW .100Y.C M.TWDD_MOSI W with DDB5 . 1 and M . with DDRB.
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100
WAssembly
.T
OM Example(1) W W.1 Y.COM W
W .C Code W
M .TW W
W . 00 Y
1SPI_MasterInit:O M .T W
W .100 O M.T
00Y WW .10;0Y M .T W M .TW
. 1 M W Set O
MOSI and SCK output, allW others O
input
W
0 Y.C
O
.T W WW .1ldi 0 0Y.C .TW WW .100Y.C M.TW
0 M
r17,(1<<DD_MOSI)|(1<<DD_SCK)
W. 1
.C OM
W WW out00YDDR_SPI,r17 .CO .TW W WW 00Y.CO .TW
Y W .1
.100 M.T W;.1Enable O M WWrate00fck/16
M
.CO .TW
WW 00Y.CO .TW W Y .C SPI, Master,W set W clock Y
W .1 O M
W
W .100r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
OM
.T
W W.1 Y.COM W
.C W ldi
0Y .C W W 00 .T
WW .100Y M.T
W W out.10SPCR,r17 M.T W.1 Y.COM W
W O W .C O W
WW .100Y.C M.TW WWret .100Y M.T
W W .100 M.T
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
SPI_MasterTransmit: WW .100Y. M .TW
W O
W O ; Start W transmission
WW SPDR,r16 .CO .TofWdata (r16) WW .100Y.C M.TW
WW .100Y.C M.TW out . 1 00Y M W O
W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
Wait_Transmit: WW .100Y.C M.TW
W O
W O W
WW for.1transmission .CO .Tcomplete WW .100Y.C M.TW
WW .100Y.C M.TW ; Wait
00Y M
W
W W .C O
W WW 00Y.CO .TW
sbis SPSR,SPIF
W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM W rjmp Wait_Transmit W W.1 Y.COM W WW 00Y.CO .TW
W ret W 00 .T W
W
.C W W 00 .T
WW .100Y W
M.TC Code Example WW.10
W (1) 0 M.T W.1 Y.COM W
W O .C O W
WW .100Y.C M.TWvoid SPI_MasterInit(void) W .100
Y
M.T
W W
W .100 O M.T
W O W O W .C
WW .100Y.C M.T{W WW .100Y.C M.TW W .100
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O /* Set MOSI W
W and SCK 00Y
.C all
output,
.TW others input WW*/ .100Y. M .TW
.1 M W O
W O W
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
WWMaster, .CO .TW WW .100Y.C M.TW
WW .100Y.C M.T/*WEnable SPI, . 100Yset clock M
W W .C O W W Y.CO .TW
rate fck/16
W
*/ W
W 0 Y .CO .TW
Y W W 0 0
W 00
W.1 Y.COM
.T = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
SPCR 0
W
W W
. 1 00
}
M .TW W
W .100 O M .T W
W .100 O M.T
W O WW .100Y .C
WW .100Y.C void W WW .100Y.C M.TW
.TSPI_MasterTransmit(char M .TW
M W O W O
O WW .100Y.C M.TW
W cData)
WW .100Y.C{ M.TW WW .100Y.C M.TW
W W .C O
W 00 Y /* .T
Start transmissionW */ 0 0 .1 M
W.1 Y.CSPDR OM = cData; W W.1 Y.COM W WW 00Y.CO .TW
W W W
W 00
W.1 Y/* M.Tfor transmission
OWait
W .100
Wcomplete OM
.T
W W.1 Y.COM W
.C W .C */ W
W W
.1 00 while(!(SPSR M .TW & (1<<SPIF))) W
W . 100
Y
O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.;C M.TW WW .100Y.C M.TW M .TW
W O W O
W
WW .1}00Y.C M.TW
O
W W .C O
Y W
W Note: .101.0 See “About
W OM
.TCode Examples” on page W.16. Y.COM W W W.1 Y.COM W
.C W
W W
.1 00Y M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y .C
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 following
WThe .C OMcode examples show Whow W.1 to initialize
Y
M
.CO the.TSPI W as a Slave and how to perform a
W W 0 0 Y .T W W 1 0 0
.1
simple reception. M . M
W WW 00Y.CO .TW (1) W WW 00Y.CO .TW
W
O M.T W .1
Assembly
. OMExample
Code
C W W.1 Y.COM W
.C W W
00Y .TW W 100
Y
.SPI_SlaveInit: M.T
W .100 OM
.T
W.1 Y.COM W W C O
Y. MISO output, W W Y .C W
00 .T WW .1;00Set M .TW all others W .100
input M.T
. 1 M W O W .C O
W .CO .TW WW ldi .C
00Yr17,(1<<DD_MISO) .TW WW .100Y .TW
. 1 00Y M W . 1 O M W O M
WW 00Y.CO .TW WW out 0 Y.C
0DDR_SPI,r17 .TW WW .100Y.C M.TW
. 1 M
W W. 1
.COM
W WW ; Enable C
Y . SPI O
W W WW 00Y.CO .TW
W 00 Y .T W 0
ldi.10r17,(1<<SPE) .T .1 M
W.1 Y.COM W W W .C OM WW 00Y.CO .TW
W W out .1SPCR,r17 00 Y .T W W
W
.C W W
WW .100Y .TW Y W .100 .T
ret
M
W
W . 100 O M .T W C OM
W O W .C W Y . .TW
WW .100Y.C M.TW W . 1 00Y M .TW W
W . 100 O M
W O SPI_SlaveReceive:
WW .100Y.C M.TW WWait
; .
for1 reception M complete W O
W O
W
WW .100Y.C M.TW
O
WWSPSR,SPIF
sbis 0 0 Y.C .T W WW .100Y.C M.TW
W. 1 OM W O
W
WW .100Y.C M.TW
O rjmp WW SPI_SlaveReceive
0 0 Y.C .T W WW .100Y.C M.TW
W .C O ; ReadW W.1 Ydata
received M
.CO and.Treturn W WW 00Y.CO .TW
W Y W W 0 0 W .1
W W.1 Y.COM W in r16,SPDR W W WW 00Y.CO .TW
W .100 M.T ret W 00 .T W.1 Y.COM W
W .CO W W.1 Y.COM W W
WW .100Y W W .100 M.T
W 00 .T
WW .100Y.C MC.TCode W Example WW .100Y
(1)
M.T
W W .100 M.T
W O W O W W .CO
WW .100Y.C M.Tvoid W SPI_SlaveInit(void) WW .100Y.C M.TW W .100
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O {
W O W O
O WW .100Y.C M.TW
W /* Set MISO output, all others input */
WW .100Y.C M.TDDR_SPI W WW .100Y.C M.TW
WW 00Y.CO .TW
= (1<<DD_MISO);
W W Y.C O
W W WW 00Y.CO .TW W
W 00 .T
/* Enable SPI */ 1 .1 M
W W.1 Y.COMSPCRW= (1<<SPE);WW. 0Y.COM W W WW 00Y.CO .TW
W .T
W
W .100 O M.T W .10
.C OM W W.1 Y.COM W
C } W W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.CcharMSPI_SlaveReceive(void)
.TW WW .100Y M .TW W .100 M.T
W O W O W W .C O
WW .100Y.C { .TW WW .100Y.C M.TW W .100
Y
M.T
W
M W O W C O
W
WW .100Y.C M.TW
/* O Wait for receptionWcompleteY.*/
W 00
C
.TW WW .100Y. M .TW
W .1 O M W O
W
WW .100Y.C; M.TW
O
while(!(SPSR
WW .100Y.C M.TW
& (1<<SPIF)))
WW .100Y.C M.TW
W O W O
W
WW .100Y .CO
/* Return.Tdata W register WW*/ .100Y.C M.TW WW .100Y.C M.TW
W OM WW 00Y.CO .TW WW 00Y.CO .TW
WW .10return 0Y.C SPDR; M. T W W .1
W
W.1 Y.COM W
W C O W W .C OM W
WW .100Y.
}
W Y W W 00 .T
W O M.T
W
.C onW .C
W
WNote: 1 0 Y “About
1. 0See
M .TW Examples”W
Code page 6. 00Y
. 1 M .TW W
W .100 OM.T
. O W O .C
W
W
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
18.3 .TSS
M
W Pin Functionality
W
W . 100 O M .T W
W .100 O M.T
.CO WW .100Y. C
00Y 18.3.1M.TW WW .100Y.C M.TW M .TW
. 1 Slave Mode W O W O
W
0 Y.C
O
.T W WW 0 0SPIY.C .TW as a Slave, WW .100Y.C M.TW
0 When . 1
the is M
configured theWSlave Select
W. 1
.C OM WW Y .COis activated, W W Wbecomes 0 Y .CO (SS).Tpin W
is always input. When SS is
Y W W held low,
.10 the0 SPI
M. T and MISO .1 0 an output if configured so by the user. All
W .100 O M.T W . C O W Wall .C O M
W
W 00 Y.C .T W WW .100Y
other pins are inputs. When
M .TW SS is driven W high,
. 1 00Y
pins are inputs
M
except
.T MISO which can be user
W. 1 OM configured W as an O and the SPI is passive,
output, W which .means O that it will not receive incoming
WWNote .that Y.CSPI logic WW .1SS YC W
WW .100Y.C M.TW data. 1 00the M .TW will be reset once the W
00pin is M
driven
O
.Thigh.
W O
W
WW .100Y.C M.TW
O W 0Y.Cfor packet/byte .TW WW .100Y.C M.TW
TheW SS pin is . 1 0useful
O M synchronization W to keep the
O slave bit counter synchronous
W .C O W
Wmaster Y .Cgenerator. W W 0 Y.C W Slave will immediately
W Y W with W
the 0
clock .T When the W
SS pin is 0
driven
.1 high, the.TSPI
W .1 00 M .T W . 10 O M W C O M
W O reset theW
W send and .C logic,
receive and drop any W
Wpartially Y. data .in
received TW the Shift Register.
WW .100Y.C M.TW . 1 00Y M .TW W . 100 O M
W O
WW18.3.2
W
0 .CO Mode
YMaster .T W WW .100Y.C M.TW WW .100Y.C M.TW
0 .COthe user
W.1 OM WW 00Y.COas a.TMaster WSPCR W
0Yset), .TWcan determine the
WW .100Y.C M.TW When theWSPI is configured . 1 M
W (MSTR Win
W . 1 0is
O M
W pin. O
W
WW .100Y.C M.TW
O direction of the
WW .100Y.C M.TW
SS WW .100Y.C M.TW
W .C O If SS is configured WWas an Y .CO the.Tpin
output, W is a general W W W
output pin 0 .CO does
Ywhich W
not affect the SPI
W W
. 1 00 Y
M
W
.T system. Typically, the W . 1 0
0 will be driving M W .1Slave. OM.T
0
W pin O the SS pin of the SPI
W
WW .100Y.C M.TW
O
W W .C O If SS is configuredWasWan input, Y
O be held high to ensure
.itCmust W W WWMaster 0 .COoperation.
YSPI W If the SS pin
.Twith
W 00 Y .
isT W
driven low by W peripheral . 1 0 0 circuitry M .
whenT the SPI is configured . 1 0 as a M
Master the SS pin
W W.1 Y.COMdefined W W Y .C O
W W WW master 0 Y .CO .TW
W as an W
input, the
.100
SPI system
M.T
interprets this as another .10 selecting the SPI as a
W
W .100 O M .T W O
C To avoid W W .C O M
W following
WW .100Y.C actions:
slave W and starting to W
W send data Y.it.
to
.TW
bus contention, W the SPI .100
Y
system takes
M.T
the
M .T W . 100 O M W C O
W
WW .100Y.C M.TW
O
W O
W O1. The MSTR bit in SPCR
WW
W is cleared .COand the SPI system becomes
WW .100Y.C M.TW
a slave. As a result of
WW .100Y.C Mthe .TW SPI becoming a slave, . 1 0YMOSI
0the and
M .TSCKW pins become inputs.
W W .C O
W WWis set, Y .CO W W WW 00Y.CO .TW
Y 2. The SPIF Flag in W SPSR .10 0 and if theM. T
SPI interrupt is enabled, .and
1 the I-bit in SREG
W
W .100 O M .T W C O W W .C OM
W
WW .100Y.C M.TW
is set, the interrupt
WW .100Y.
routine will be executed.
M .TW W .100
Y
M.T
Thus, O when interrupt-driven SPIW transmission O is used in master mode, W and there .C O
exists a
W
WW .100bility Y.C that SS .T W Wthe W 0 0 Y.C .T W WW .100Y M . Tpossi-
W
M is driven low, W .
interrupt1 should O Malways check that the MSTR
W bit is still
O set. If the
W W .C O W Y . C W W W 0 Y .C .T W
0Y bitM
MSTR has W clearedWby a slave
.Tbeen 0
0select, it must .Tbe set by the user to 0
re-enable SPI master
W
W .10mode. O W.1 Y.COM W W W.1 Y.COM W
.C W W 00 .T
WW .100Y M.T
W O W W .C O W
W Control Y.C W W .100
Y
M.T
W W .100 .T
18.3.3 SPCR W – SPI
W .100 Register O M.T W C O W W .C OM
W
WW Bit 00Y
.C .T7 W WW5 .1004Y. M .TW 2 W .1000
Y
M.T
.1 M 6 W O 3 1 W C O
W O W .C WW SPR0 Y. .TW
WW .100Y.C M .TW SPE W
SPIE DORD
. 00Y CPOL
MSTR
1 M .TWCPHA SPR1
W . 100 SPCR O M
W Read/Write .CO R/W
W R/W R/W WW R/W00Y.CO R/W
TW R/W R/W W R/W
W 00Y
.C W
WW Initial.1Value 00Y M .T W
W . 1 O M . W . 1 O M.T
W O 0 0 0 0 0 0 0
WW .100Y
0
. C
W O W O
W 7 – SPIE: O
WW .100Y.C M.TW
• Bit SPI Interrupt Enable WW .100Y.C M.TW WW .100Y.C M.TW
Oin the SPSR RegisterW is W O
This W bit causes C
. the OSPI interrupt to be executed WW if 0SPIF Y .Cbit W W set and the
0 Y.Cif W
W W
the global .1 00 Y
interrupt enable
M
W
.T bit in SREG is set.W.1 W 0
O M .T
W .1 0
O M.T
W
WW .100Y.C M.TW
O
• BitW 6W – SPE: SPI . C O
Enable W WW 00Y.CO .TW W WW 00Y.CO
Y W .1
W
When theW .100bit is written
SPE
.T
OM to one, the SPI isWenabled. W.1 Y This.C ObitMmust be set to enable WW any SPI
W Y . C W W 0 0 .T W W
W
operations. 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W•.1Bit 5Y–.CDORD: OM Data Order .1 M
W W W WW 00Y.CO .TW
W When
W .100the DORD .T
OM bit is written to one,Wthe W.LSB 1 of theOdata
.C
M word is transmitted first.
W Y .C W W 0 Y W
M .TW W When
W . 10the0 DORDMbit.Tis written to zero, the MSB
O W .10 of theOdata M.Tword is transmitted first.
.CO .TW WW .100Y. C
. 1 M W 4 – MSTR: O W O
W
0 Y.C
O
.T W WW • Bit
0 0Y.C Master/Slave .TW Select WW .100Y.C M.TW
1 0 . 1 M W to one, O Slave SPI mode when written logic
W. .C OM WW
This bit selects.CMaster
Y
O SPI mode when W
W W
written
0 Y .Cand .TWis set, MSTR will be cleared,
00 Y .TW W zero. W If SS. 0
10is configured M T
. as an input and is driven 0
.1 low while MMSTR
. 1 M O W .C O
WW 00Y.CO .TW WWSPIF.1in0SPSR
and 0Y.C willMbecome .TW set. TheWuser will.1then
W 00Yhave toMset .TW MSTR to re-enable SPI Mas-
.C ter W
mode. . W Y W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W
WW .100Y.C M.TW
O
• BitWW 3 – CPOL: 00Y
.C
Clock Polarity .TW WW .100Y.C M.TW
. 1 M O
W W .C O
W When WW
this bit is Y
written .CO W W WW 0 0 Y.CCPOL is.Twritten W to zero, SCK is low
W 00 Y .T W . 10 0 to one,
M .T SCK is high when idle. .1When M
.1 M W O W C O
W O when idle.
WW .100Y.C M.TW
Refer to Figure 18-3 and Figure 18-4 WW for an example. Y. The CPOL .TW functionality is sum-
WW .100Y.C M.TW marized below: W . 100 O M
W O
W
WW .100Y.C M.TW
O
Table 18-2. WW O W O
W
WW .100Y.C M.TW
O
W 0 0 Y.C
CPOL Functionality
. 1 OM W O
W O CPOL WW W Edge WW .100Y.C Trailing
WW .100Y.C M.TW W 0 0 Y.C Leading .T M .TWEdge
W . 1 O M W O
W
WW .100Y.C M.TW
O 0
WW .100Y.C M.TW
Rising
WW .100Y.C MFalling .TW
W O W O
WW .100Y.C M.TW
W O 1 Falling Rising
W W .C O • Bit 2 – CPHA: W
W Clock
W
Phase Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1
W.1 Y.COMThe W W.1Phase C
M
bitO(CPHA)W WW OM
.Con
W settings of the W
W Clock
0 Y
0Refer
. determine ifW
.T 18-3 and Figure W
data is sampled0 Y TW (first) or
the .leading
10for an example.
W . 1 00 M .T (last) edge . 1 M . O M
W W Y .C O trailing
W W
of
WW 00Y.CO .TW
SCK. to Figure
W W 18-4
0 0 Y.C .T WThe CPHA
W 00 .T
functionality is summarized.1 below: M .1 M
W
W 00
W.1 Y.CO M.T18-3. CPHA Functionality
Table W.1 Y.COM W W W.1 Y.COM W
W W 0
W W
. 1 00 M
W
.TCPHA W
W . 0
10Leading O M
Edge
.T W .10Trailing O
Edge M.T
W O .C WW .100Y. C
WW .100Y.C M.T0W WW .100Y M .TW M .TW
W Sample O W Setup O
W
WW .100Y.C M.T
O
1W WW .100Setup Y.C .TW WW .10Sample 0Y.C M.TW
M WW 00Y.CO .TW
W W Y .C O
W W WW 00Y.CO .TW W
W 00
W.1 • YBits
.T
O1,M0 – SPR1, SPR0: SPI W .1
Clock Rate .C OM 1 and 0
Select W W.1 Y.COM W
.C W W
W W
. 1 0
0These two M .TW
bits control the
W
SCK rateW . 10the
of
0 Y
device O M .T
configured as a
W
Master. W .100 and SPR0
SPR1 O M.Thave
W O W .C
WW .1no 00Y
.C
effect on .TW
the Slave. The W
W
relationship . 0Y.C SCK
10between M .TW W
and the Oscillator Clock
Y
.100frequency .TW
Mfosc is
W shown M
Othe following table: W W C O W W .C O
W .C W Y . W W 00 Y .T W
W . 1 00Y in
M .T W .1 00 M .T W . 1 O M
W .CO Relationship WW SCK
W
0Y.theCO TW Frequency WW .100Y.C M.TW
WW Table 0 0 Y18-4. .T W Between . 1 0and .
Oscillator
M O
W
WW .100Y.C M.TW
WW .100SPI2X .T SPR1 W . 1 SPR0 M SCK Frequency
W CO
M WW 000Y.CO f .T/W WW 00Y.CO .TW
WW .100Y 0. W W W
W O M. T 0
W .1
.C OMosc
4
W W.1 Y.COM W
C W /16W
WW .1000 Y. M.T
W 0 W .1100
Y fosc.T
M
W 00
W.1 Y.COM W
.T
W O W .C O W
WW .1000Y.C M.TW 1 WW .0100Y .TW
fosc/64
M
W .100 M.T
O W O W . C O
W
WW .0100Y.C M.TW1 WW 1 .100Y.C foscM /128.TW WW .100Y M.T
W
W O W O
W1
WW .100Y.C M.TW
O 0
WW 0 .100Y.Cfosc/2M.TW WW .100Y.C M.T
W W1 . C O 0
W W1W 00Y.fC O
osc/8 W W WW 00Y.CO
W 0 Y .T W 1 .T .1
1 .10
W OM 1 0 W. fosc
.C 32M
/O WW
W Y .C W W W 0 Y
0 f /64 M.T W W
W 1 .100 .T 1 W.1
W OM1 osc O
W W 0 0 Y .C
.T W W W
.1 0 0Y.C M.TW
W.1 OM W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W . 1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Register OM .1 M
18.3.4 SPSR – SPI Status
W 00 .T W.1 4 Y.CO3M W2
W WBit.1 Y.COM 7 W 6 5W 1 0
.T W W . 10 0 M .T WCOL W . 1 0– 0 M .T
.C OM
W WW Y .CO R .TW R
SPIF
W
–
WW 00Y.CO .TW – – – SPI2X SPSR
00 Y .T W 10
Read/Write 0 R .1
R R M R R R/W
0 .T W Initial
0 0 Y .T W 0 0
W .1 M
0 0
1 0 . 1 M W O
W. OM W O
Y.CSPI Interrupt W Flag WW .100Y.C M.TW
00 Y.C .T W W• W Bit 7 –1 0 0
SPIF: M .T
.1 M W. .CO is.Tcomplete, WWFlag00isY.set. COAn interrupt
WW 00Y.CO .TW WW a serial
When
1 0 0 Ytransfer W theWSPIF . 1 M .TW is generated if SPIE in
W. 1 OM . M W O
SPCR Wis Wset andYglobal .CO interrupts W are enabled. WW If SS is0anY.Cinput and .TisWdriven low when the SPI is
WW .100Y.C M.TW W . 1 0 0 M .T .1 0 M
W O in MasterW mode, this will O also set the SPIF Flag.
WW .10the
W
SPIF is cleared CO by hardware
0Y.SPIF
when executing the
WW .100Y.C M.TW WW .10interrupt
corresponding 0Y.C handling .T W vector. Alternatively, bit
M . TW
is cleared by first reading the
W C O W WRegisterY.with C OM W W Y .C O
W
WW .100Y . W SPI Status SPIF W
set, then W
accessing the SPI
0 0 Data .T
Register (SPDR).
W O M.T
W
W . C
WW .100Y.C M.TW • Bit W 6 – WCOL: 0Y COLlision
.10Write M.T Flag
W W
W .100 OM
.T
W O W . C O W Y .C W
WW .100Y.C M.TW The WCOL WWbit is.1set 00Yif the SPI M
W RegisterW(SPDR).1is00written
.TData M.T a data transfer. The
during
W O W C O
W O W the SPIF C are cleared
.bit) WW the Y.Status Register.TW with WCOL set,
WW .100Y.C M.TW and then W
WCOL bit (and
. 100YSPI Data M .TW by first reading W .
SPI
100 O M
W O
WW .100Y.C M.TW
W O accessing the Register.
W W .C O •
W Bit 5:1 – Res: WW Reserved Y .C O
Bits W W WW 00Y.CO .TW
Y W 0 .T
W 00
W.1 Y.COM These
.T
bits are reserved
0
W.1 bitsYin.Cthe OM ATmega32A and W willW W.1 read
always Y .C OM
as zero. TW
W W W 0
W . 1 00 M .TW W
W . 100 O M .T W .10 O M.
W O .C WW .100Y .C W
WW .100Y.C M•.TBit W 0 – SPI2X: WW Double . 00YSpeedM
1SPI .TW
Bit M.T
O When this bit is written W O W O
.Cdoubled
W
WW .100Y.C M .TW WW logic 0Y.Cthe SPI
0one .T W (SCK Frequency)
speed WW .10will 0Ybe M .TW when the SPI
W . 1 O M W C O
W O is in Master mode (see Table
Y.C
18-4). This means that the W
minimum SCK
0Y .period will
.TW
be two CPU
WW .100Y.C clock .T W WW . 10 0configured M .T W W . 1 0guaranteed M
W W . COM periods.
W
When the
W WSPI is
Y. CO as Slave,
W
the SPI
W WW 00Y.CO .TW at fosc/4
is only to work
W 00 Y or lower..T W 0 0 .T .1 M
W W
W
W .100 The SPI
O M.T interface on theW
W ATmega32A
W .100 is also
OM
.Tused for program memory
W W.1 and .C OM
EEPROM down-
C .C WProgramming Y W
WW .100Y. loading M.T
orW uploading. See W page.279 100
Yfor SPI Serial
M.T W .100
W and Verification.
OM
.T
W O W C O W .C W
18.3.5 WW – SPI
SPDR 0Y.CRegister
0Data .TW WW .100Y. M .TW W .100
Y
M.T
. 1 O M W O W .C O
W
WW .100YBit.C M.TW 7 WW .100Y.C M.TW WW .100Y M .TW
W O W O
W O 6 5
WW .100Y.C M.TW
4 3 2
WW .100LSB
1
Y.C
0
.TW
WW .100Y.C M.TWMSB W O MSPDR
W Y.C
O R/W W R/W
W
0YR/W.CO R/W TW R/W W R/W .10R/W
W 0Y.C M.TW
WW .10Read/Write0 .T WR/W
W . 1 0 M .
X W O
W Initial ValueOM X W O X
WW .100Y.C M.TW
WW .100Y.C M.TW
X X X X X Undefined
WW .100Y.C M.TW O
WThe SPI .C O Register is a read/write
Data WWregister Y CO for T
.used data transfer between
W W WW the00Register
Y.C File W
W W
and
.1 0the Y
0 SPI Shift M
W
.TRegister. Writing to W W 0 0
the.1register initiates O M . data transmission.W .1
Reading the O M.T
regis-
W .CO .TRegister .Cread. .TW WW .100Y. C
WW ter.causes 00Y the Shift W WW buffer
Receive 1 0to0Y be
M M .TW
1 M W . O W O
W
WW .100Y.C M.TW
O
18.4 Data Modes WW .C O
Y W
W There.1are
W
00 four combinations
OM
.T of SCK phase W.and 1 polarity
C OM with respect to serialWdata, W.1 which OM
are
.C
W
Wdetermined 0 0 Y
by
. C
control .T
bitsWCPHA andW W
CPOL. The
. 1 0 Y .
0SPI dataM .T formats are shown.10in FigureOM.TW
W
transfer W 0 Y
.1 OM Data bits are shifted W
18-3W Wand Figure Y .C 18-4. W W Wout W
and 0 Y .CO in on
latched .T W
opposite W
edges Wof the SCK
.C
00Ysig- M.TW
W 0 0 .T .1 0 M . 1 O
W.1 OM W O W
WW .100Y.C M.T
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W . C
WW .100Y. M.T
W W .100
Y
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 ensuring OM .1 OM This is clearly seen by summarizing
W Wnal, Y .C sufficient time for data
W W WW signals to.C
0 0 Y stabilize.
.TW
W Table
. 10018-2 andMTable .T 18-3, as done below: W . 1 O M
W O
OM W 18-5. O
Table CPOL and CPHA Functionality W O
0 O Trailing Edge
W.1 Y.COM W WW 00Y.CO .TW Leading
W WW Edge
0 0 Y.C .T W SPI Mode
0 0 .T W .1 = 0, CPHAM= 0 .1 M
CPOL
W WW 00Y.CO Setup
Sample (Rising)
.T W (Falling) 0
W .1
.100 M.T W.1 = 0,Y
CPOL CPHA OM =1 Setup (Rising)
WW 00Y.CO .TW
M
Sample (Falling) 1
WW 00Y.CO .TW W
W CPOL.1=01,0 CPHA =M .C
.T W W
W .1 O M W .C O0 Sample (Falling)
W W.1 Y.COSetup M (Rising)
W
2
W Y.C W W W 0 Y
0 CPHA = 1M .T W W
Setup (Falling) .1 0 0 .T
W 00 .T CPOL =.11, Sample M (Rising) 3
W W.1 Y.COM W W W Y .C O
W W WW 00Y.CO .TW
W .100 M.T
W 00 .T .1 OM
W . C O Figure W W.1 SPI Y
18-3. .C OM Format with CPHAW
Transfer
W =W 0
0 Y . C W
WW .100Y .TW W .10 M.T
M
W
W . 100 O M .T W C O
W
WW .100Y.C M.TW
O
WWmode 0.100Y.C M.TW
SCK (CPOL = 0)
WW .100Y. M .TW
W O W O
W
WW .100Y.C M.TW
O
WW SCK (CPOL 0
0 =Y1).C
.TW WW .100Y.C M.TW
modeW . 1 O M W O
WW .100Y.C M.TW
2
W O
WI O W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
SAMPLE
MOSI/MISO WW .100Y.C M.TW
W W .C O
W 00 Y .T W
CHANGE 0 .10 0 .1 M
W.1 Y.COM W MOSI PINW W .C OM WW 00Y.CO .TW
W W 00 Y .T W W
W
W .100 O M.T CHANGE 0 W.1
.C OM W W.1 Y.COM W
.C W Y W W 00 .T
WW .100Y M.T
W MISOW PIN
.100 M.T W.1 Y.COM W
W O W W . C O W
WW .100Y.C M.TW SS W .100
Y
M.T
W W
W .100 O M.T
W O W O W .C
Y
M.T
W
W O W O W
W Bit 2 00BitY1. LSB .TWC O
WW= 0) MSB .C6
WW .100Y.C M.TW MSB first (DORD
.1 00YBit M .TW Bit
Bit 5 4 BitW3
5 .1 Bit 6 M
W W .C O LSB first (DORD = 1) LSB
W W Bit 1
Y .C O Bit 2
W
Bit 3 Bit 4
W W W
Bit
0 Y.COMSB .TW
Y W W .100 M.T 0
W
W .100 O M.T18-4. SPI Transfer W .C O W W.1 Y.COM W
C
Figure W Format with CPHA = W1
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TSCK W (CPOL = 0)WW .100Y. M .TW W .100
Y
M.T
O W O W .C O
W .C WW .100Y
mode 1 W
W
WW .100Y.C MSCK .TW(CPOL = 1) W W.100Y OM.TW W O M.T
W
WW .100Y.C M.TW
O mode 3
W W .C O SAMPLE I
W 00 Y W .1
W.1 Y.COMOSI/MISO M.T W W.1 Y.COM W WW 00Y.CO .TW
M
W W W 00 .T W
W 00
W.1 Y.CO M.T 0
CHANGE W.1 Y.COM W W W.1 Y.COM W
W
W W
.1 00 MOSI PIN
M .TW W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.CMISO M
CHANGE
PIN.T
0
W WW .100Y.C M.TW M .TW
W O W O
W
WW .100Y.C M.TW
O
W W SSCO
. W WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W W
W
W .100 MSB O M.T= 0)
first (DORD MSB
WBit 6
Bit 1WWBit 2
.1500 Bit
Bit 4 MBit.T3
3 O Bit 4
Bit.C
Bit 2 Bit 1
Bit 6 WMSB
LSB .1
W .C OM
.C
LSB first (DORD = 1) LSB
W Bit 5 Y W
WW .100Y M .TW W
W .100
Y
O M .T W
W .100 O M.T
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1
W W 0 0 .T W
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
W
W .100 O M.T
W
W .100 OM
.T
C W .C
WW .100Y. M.T
W W .100
Y
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 Y.COM W W
19. M .TW
USART W
W . 100 O M .T W
W .100 OM.T
.CO .TW WW .100Y. C
. 1 M W O W O
W
0 .CO Features
1 0 O
W. .C OM
W •W WDuplexYOperation
Full .CO .T (Independent
W WW
Serial
W Receive0and
0 Y.CTransmit .TWRegisters)
00 Y .T W . 1 0 0 M . 1 M
. 1 M • Asynchronous or O Synchronous Operation W O
WW 00Y.CO .TW WW 0Slave
•WMaster or 0Y.CClocked . W
TSynchronous W W
Operation.100
Y.C .TW
1 . 1 M W O M
W. OM WW .CO Rate Generator WW
.C W
WW .100Y.C M.TW •W High Resolution
. 1 00Y Baud M .TW .1 00Y M.T
W O W O
W O • Supports
WW .10Parity 0Y.CGeneration
Serial Frames with 5, 6, 7, 8, or 9 Data W Bits and Y1.C or 2 Stop Bits
.TW
WW .100Y.C M.TW • Odd or Even M .TWand Parity W Check W . 100 byOHardware
Supported M
WW 0Detection O
W
WW .100Y.C M.TW
O
• DataWOverRun 0Y.C M.TW WW .100Y.C M.TW
. 1 W O
W O W
WWError.1Detection .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW • Framing 00Y
W C O WW Includes
• Noise Filtering OM Start Bit DetectionW
.CFalse and WDigital Y .CO
Low Pass Filter
W
W W 0 Y . .T W W 0 0 Y .T W W . 1 00 M.TRX Complete
.1 0 M • Three Separate
W . 1
Interrupts OonMTX Complete, TX Data Register
W Empty,
C O and
W O
WW .100Y.C M.TW • Multi-processor WW Communication 00Y
.C TW
.Mode WW .100Y. M .TW
. 1 M W O
W O W
WW Asynchronous .CO Communication WW .100Y.C M.TW
WW .100Y.C M.TW
• Double Speed Mode
. 100Y M .TW
W W .C O
Y W
W .100
19.2 WOverview OM
.C W
W W
. 1 00Y M
W UniversalWSynchronous
.TThe W . 100 andOAsynchronous
M .T W
serial Receiver W .100and Transmitter
O M.T (USART) is a
W O Y.C device. W diagram .C
WW .100Y.C Mhighly .TW flexible serial WWcommunication 100 M .TWA simplified Wblock Y
.100 of the .TW transmitter
MUSART
W . O W O
W O is shown in Figure 19-1.
WW .100Y.C M.TW
CPU accessible I/O Registers and WWI/O pins Y.C
are shown inTbold.
. W
WW .100Y.C M.TW W .100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O W .C O W
W O W O W W .C O
Y
M.T
W
W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-1. (1).1 M
W WFigure .C OMUSART Block Diagram WW 00Y.CO .TW
W 00 Y .T W W
W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C M.TW M .TW Clock Generator
. 1 M W O W O
W
0 Y.C
O
.T W WW .100Y.C M.TW WW .100Y.C OSCM.TW
UBRR[H:L]
0
W. 1
.C OM
Y W .1
.100 M.T W.1 Y.COM W BAUD RATE GENERATOR WW 00Y.CO .TW
M
W .1 O M W.1 Y.COM W W W.1 SYNC Y .C OM
W PIN
.C W
WW .100Y .TW W .100 M.T CONTROL
LOGIC
M
W
W . 100 O M .T W C O
XCK
W O .C W Y . W
W W .100 M.T Transmitter
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TWUDR (Transmit) W .100
Y WTX
M.TCONTROL
W O W C O
W O
WW .100Y.C M.TW WW GENERATOR Y. .TW
WW .100Y.C M.TW W . 100
PARITY
O M
W O W O TRANSMIT SHIFT REGISTER W .C
DATABUS
WW .100Y.C M.TW WW .100Y.C M .TW W . 1 00Y M

PINW
.T
CONTROL
TxD
W O W C O
W
WW .100Y.C M.TW
O
O W O W O
.C RX .TW
Receiver
W
WW .100Y.C M.TW WW .100Y.C M.TW WWRECOVERYCLOCK 00Y
. 1 M
CONTROL
W W .C O W
Y W W
W 00
W.1 Y.COM W
.T W.1 Y.C OM W W.1 Y.COPINM W RxD
W W DATA
W W .100 CONTROL M.T
RECEIVE SHIFT REGISTER
W 00 .T W 100 .T RECOVERY
W . 1 O M W . O M W W .C O
WW .100Y.C M.TW WW .100Y.C UDR M .TW W .100
Y
M.T
W
W O PARITY
W O
WW .100Y.C M.TW
(Receive)
W O
WW .100Y.C M.TW
CHECKER
WW .100Y.C M.TW
W W .C O
W 00 Y .T W .1 M
W.1 Y.COM W W.1 Y.COM W
WUCSRA WW 00Y.CO .TW
W W 0 0 .T W .1 UCSRC M
W 00 .T W.1 Y.COM W
UCSRB

W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C M.TW WW .100Y. M .TW W .100
Y
M.T
W O W O W W .C O
WW .100Note: Y.C 1. .T W to Figure W
Refer
W
1-1 on page Y.C 12-14.on
02,0Table TW page 66, andW Table 12-8 . 1on
Y 61 for .USART
00page M TW
M W . 1 O M W O
W
WW .100Y.C M.TW
O pin placement.
of W O
W W TheYdashed .C O boxes in the blockW
W W
W separate
diagram
0 Y .CO the.T three main parts W
W W
the USART
0 0 Y.C(listed .from TW
W .1 00 top): Clock
the M .TGenerator, Transmitter . 10and Receiver. M Control Registers are W 1
.shared byOallMunits.
W O C
Y. by syn-
WW .The
W .COgeneration.TW logic consists WW of synchronization
00Y
.C W for external WW 100 used O .TW
1 00Y clock
M .1 M .T
logic clock input
W . M
Wchronous O
Y.Cslave .operation,
W
WWbaud.1rate
and the .CO .TW
0Ygenerator. The XCK (Transfer WW Clock) .C
00Ypin is only W
WW used .1 0 0 by M
Synchronous
T W
Transfer mode. W The
0 TransmitterO M consists of a single W
write.1 buffer, a O M.T
serial
W O .C WWframe 0Y. C
WW Shift 0Y.C parity
0Register, .TW generator and WW control 1 00Y for handling
logic M .TWdifferent serial .10formats. M
The .TW
. 1 M . O W O
W .CO .TaW WW of00data Y.C without TW any delay W W .C
00Y TheM.TW
WWwrite.1buffer00Y allows continuousWtransfer
. 1 M . between . frames.
1
W W
Receiver is .the
C
M complex part ofWthe
Omost WUSART Y .C O
module dueW to its clock W WWdata0recovery
and 0 Y .CO .TW
W units. .The 00 Y .T W W 0 0 .T .1 recovery M
W 1 recovery .C OMunits are used for asynchronous W W.1 Y.C OMreception. In addition
data
W W Wthe
to
0 Y .CO .TW
W Y .TW a parityWchecker, 00 W
.Ta Shift Register andWa.1two 0 level M
Wunits, the
W .100receiver O
includes
M W W .1control
.C
logic,
OMformats as the transmitter, W .CO .TW
Ycan
W
receive buffer Y .C
(UDR). The Wreceiver supports
W the same0 Y frame .T W W and
0 0
W .100error, O T
M.overrun 0
W.1 Y.COM W .1 M
detectW
W frame
.C data
W
and parityW errors.
W WW 00Y.CO .T
W .100
Y
M.T
W 00 .T W.1 Y.COM
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1AVR UART OM .1 M
19.2.1 AVR USART vs.
W Y . C – Compatibility
W W WW 00Y.CO .TW
W The 0
.10USART is M .T compatible with theW
fully .1 UART O
AVR M
W W Y . C O
W W W 0 Y .C regarding: W
M .TW W
W .
• Bit
0
10locations O M .T all USART Registers
inside W .10 O M.T
.CO .TW Y.C Generation WW .100Y. C
00Y WW • Baud 1 00Rate M .TW M .TW
. 1 M W . O W O
W
0 Y.C
O
.T W WW• Transmitter 0 0Y.COperation .TW WW .100Y.C M.TW
0 . 1 M
W. 1
.C OM
W W W Y .COFunctionality W W WW 00Y.CO .TW
Y W • Transmit 0 0 Buffer .T .1
M
WW 00Y.CO .TW W • WReceiver 00 Operation .T W
W .1 O M W.1the receive . C OM W W.1 Y.COM W
.C W W
WW .100Y M .TW
However,
W
W . 1 00Y
O
buffering
M .T has two W
improvements
W .100 that will O
.T the compatibility in some
Maffect
W
WW .100Y.C M.TW
O special cases:
Wtwo Buffer O
W W Y.C O
W • A second
W WW Buffer 0 Y .CO .has
Register
T W been added. W W
The
0 0 Y.CRegisters .TWoperate as a circular
W 00 .T . 1 0 M . 1 M
O incoming data! More
W.1 OM FIFO buffer. W Therefore Othe UDR must only beWread
Y.Cthat the.TError
W onceYfor .Ceach W
WW .100Y.C M.TW WW is .the
important 1 0 0fact M
W Flags (FE W and DOR) . 1 0 0and the M9th.Tdata bit (RXB8) are
O W O W O
.C bits.must
W
WW .100Y.C M.TW buffered WWwith the Y.Cin the receive
00data .TW buffer. Therefore WW .1the 00Ystatus W
M T always be read
W . 1 O M W C O
W O
WW .100Y.C M.TW is lost.W
before theW UDR Register
0 0 Y.C is read.
.T W Otherwise
WW .100Y.
the error status will be lost
M .Tsince
W the buffer state
W. 1 M
W O .CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW • The receiver WW Shift.1Register 00Y W
W O W .C Ocan M now act as a third buffer W W.1level.YThis isMdone by allowing the
.CO if the W Registers
W Y.C W received Wdata W to remain0 0 Y in the serial
.T W Shift Register W (see 0
Figure
1 0 19-1) .TBuffer
W . 1 00 M .T W . 1 O M W . O M
.C resistant
W O WW
WW .100Y.C M.TWOverRun (DOR)
are full, until W
Wa new .start 1 0Ybit.Cis detected.
0conditions. M .TW
The USART is therefore
. 100
Ymore
M .TW to Data
error W O
W O W
WW bits.1have .CO .TW WW .100Y.C M.TW
WW .100Y.C MThe .TWfollowing control 00Y changed M
W W .C O W W Y .C O name,
W
but have
W
same
WWfunctionality0 Y .COand register
.T W
location:
Y W W to UCSZ2 00 .T 0
W
W .100 O M•.TCHR9 is changedW W.1 Y.COM W W W.1 Y.COM W
.C
WW .100Y M TWis changedW
• .OR to DOR W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
W O W O
19.3 Clock W
WW Generation 0 Y.C
O
0 .COReceiver.
W W.1 Y.C OMclock generation logic
The
W WW generates
0 Y .CtheO base clock for the Transmitter
W W WW 00Yand .TW The
W 00 USART .T W . 10 M T
. Normal Asynchronous, . 1 DoubleOSpeed M
. 1 M supports four modes W of clock O
operation: W Asyn-
W
WW .100Ychronous, .CO .TMaster W WW .1and
Synchronous 0
.C
0YSlave .T W
Synchronous WW The.1UMSEL
mode. 0 0Y.C bitM in.T W
USART
OMand Status RegisterW M WW and00synchronous .CO .Toper-
W W . C
Control
Y W W C
W
(UCSRC) 0 Y CO between
.selects T W W
asynchronous Y W
W 1 00 M .T . 1 0 M . W . 1 O M
W . ation. O
Double Speed (Asynchronous W mode O
.Conly) is.Tcontrolled by WtheWU2X found Y.inC the UCSRA
WW .10Register. 0Y.C M .TWusing Synchronous WW .mode 1 00Y(UMSEL M
W .100 M .TW
When
CO = 1), the Data Direction W Register O
for the XCK
W .C O WW Y .source W W W 0 Y.C (Slave W
W W
.1 00
pin Y (DDR_XCK)
M .T Wcontrols W
whether the
W . 10 0
clock
O M .
isT internal (Master mode)
W .1 0
or external
O M.T
W O XCK pin is only active W .C
WW .mode). 00Y
.CThe .TW WWwhen .1 0Y.CSynchronous
0using M .TW mode. W W.100Y OM.TW
1 M W O
WW Figure
W
0 .COshows
Y19-2 .T Wa block diagram WWof the.1clock 0 0Y.Cgeneration .TWlogic. WW .100Y.C M.TW
0 M O
W.1 OM W O W
WW .100Y.C M.TW
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W . C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y . C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-2. OMClock Generation Logic, .1 Diagram M
W WFigure Y .C W W WWBlock 0 Y .CO .TW
W 00 .T 0
W.1 Y.COM WUBRR W W.1 Y.COM W
W W .100 M.T
U2X
M .TW W
W . 100 O M .T fosc
W C O
.CO .TW WW .100Y.C M.TDown-Counter W W
WUBRR+1 Y. W /2
10/ 20 / 4 .T
Prescaling
. 1 00Y M W O W .
.C O M 0
W .CO W Y .C W W W 0 Y T W
. 1 00Y M .TW W
W . 100 O M .T W .10 O M. 1
W O WW .100Y .C
WW .100Y.C OSC
0
0 Y.C .T W .T W M .TW txclk
. 1 0 M W O M W O 1

DDR_XCK
WW .100Y.C M.TW
W W. 1
.C OM
W WW 0xcki Y .CO RegisterSync
W
Edge
W WW 00Y.CO .TW
Y W 0 .T Detector
W .100 M.T W.1 Y.COM W 1
0
W O W
XCK .1 xcko O M W
UMSEL
W .C W W Y .C W W 0 0 .T
W .100
Y
M.T
W Pin
00 .T W.1 Y.COM W
WW .100Y M .TW W
W . 100 O M .T W
W .100 OM
.T
W O DDR_XCK
W .C UCPOL
W Y .C TW
1
WW .100Y.C M.TW Y W W 0 . rxclk

W . 10 0 M .T . 1 0 M 0
W O W O
W
WW .100Y.C M.TW
O
W O W O
W O
WW .100Y.C M.TW Signal description: WW .100Y.C M.TW WW .100Y.C M.TW
CO W O
W O WW 00Y.clock W Signal). WW .100Y.C M.TW
WW .100Y.C M.TW txclkW Transmitter .1 M .T
(Internal
W W .C O
W 00 Y .T W
rxclk Receiver base clock (Internal Signal). .1 M
W xcki W 00 W
W
W .100 O M.T Input from
W.1 XCKYpin M.T Signal). UsedW
O(Internal forW .1
synchronous
. C
M operation.
Oslave
.C W . C W W 0 Y W
WW .100Y M .TW xcko Clock W output
W . 100to XCKOpin M .T
(Internal Signal). UsedW .10synchronous
for O M.T master
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
operation. WW .100Y.C M.TW
W W .C O
W 00 Y .T fosc XTAL W pin .10
frequency 0 (System M Clock). .1 M
W
19.3.1
W
Internal 00
W.1 Clock OM
.T
Generation – The BaudWRate W.1 Generator .C OM W W.1 Y.COM W
.C W
W W
. 1 00Y Internal M
W generation
.Tclock W is used
W .
Y
100for theOasynchronous
M .T W
and the synchronous
W .100 O M.Tmodes of
master
W O .C WW .100Y. C
WW .100Y.C operation. .TW The description WWin this.1section 00Y refers M .TtoW Figure 19-2. M .TW
M O W O
W .COUSART WW (UBRR) 0Y.C and TWdown-counter WWconnected .C
00Yto it function W
WW .100YThe M .T WBaud RateWRegister
W .1 0
O M .
the
W . 1 O M.T as a
W O orW .C WW running Y . C W
Y.C
WW .100programmable .TW
prescalerW baud rate
. 1 00Ygenerator. M .TTheW down-counter, . 100 at system M .Tclock
M W O W O
W
WW .10the
(fosc),COis loaded
0Y.UBRRL .T W
with the UBRR
WW A clock
value each
0 Y.Ctime the.Tcounter
0is W WW down
has counted
.1 0Yto.Czero M
0reaches
or whenW
.TThis
M Register is written. W . 1 generated
O M each time the counter
W O
zero.
W .CO .TWrate generator W .C
WW .1clock 00Y is theMbaud WW clock . 1 0Y.C (= fosc/(UBRR+1)).
0output M .TW WThe Transmitter
. 1 00Y divides M.Tthe
W
W O W C O
W baudYrate .COgenerator clock output WW by 2, 8 or016 .Cdepending
.TW on mode. The WW baud rate Y.
generator .TW
out-
WW .put 1 00is used directlyM .TWby the receiver’s .1 0 Y M W . 100 O M
Wclock and .data O recovery units. However, the recovery .C units
WW use
W
0 .CO .TW
Ystate W2,W8 or .16 0 Y C depending
0states .TW on mode WW 1 00Y .TW
.1 0 a machine
M that uses 1 O M set by
W . the state ofM
O the
W C
W
WW UMSEL, .CO .T W WW .100Y.C M.TW WW .100Y. .TW
. 1 00YU2X and M
DDR_XCK bits.
W O M
W Y.C
O WW 0the 0Ybaud .CO rate.T(in Wbits per second) WW and.10for0Ycalculat- .C W
WWTable .1 019-1
0 M
W
contains.Tequations for W
calculating
W . 1 O M W O M.T
Wthe UBRR value O for each mode of W .C an internally WW .C
WW .100Y.C M.TW
ing W operation 1 00Y
using
M .TW generated clock source.
. 100
Y
M.TW
W . O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W
WW .100Y M .TW W
W . 100 O M .T W
W .100
W O WW
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W . 1 0
O M.T
WW .100Y . C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-1.OMEquations for Calculating .1 M
W WTable Y .C W W WW Baud 0 Y .CORegister
Rate
.TW
Setting
W . 1 00 M .T . 1 0 M
W O W O
.C for Calculating
.T W WW Operating 0 0Y.CModeM.TW WW .Equation 1 00YBaud Rate M .T(1)W
Equation for Calculating
. 1 UBRR Value
.C OM
00 Y .T W .1 M
W.1= 0) Y.COM W
Asynchronous Normal Mode
W.1 Y.COM W W (U2X W WW BAUD 0= Y CO f OSCTW - UBRR = -----------------------
.-------------------------------------- f OSC
-–1
0 0 .T W 1 0 0 M .T .1 0 16 ( UBRR M . + 1 ) 16BAUD
. 1 M W . O W . C O
W .CO .TW W .C
00Y DoubleM .TWMode (U2XW W.100Y fO
W .TW
. 1 00Y M
WAsynchronous . 1 O
Speed M f OSC
1) W .C OSC
WW 00Y.CO .TW =W Y .C W W W Y
BAUD = 0---------------------------------- . T -W UBRR = -------------------- – 1
W.1 8 (Y
W 00 .T 0 UBRRM+ 1 ) 8BAUD
W .1
.C O M W W.1 Y.COM W W . C O
W
WW .100Y W W
Synchronous 0
.10Master Mode .T W 00 fOSC M.T
W O M.T W .C O M BAUDW W.=1 ----------------------------------
Y .CO - .TW UBRR = -------------------
f OSC
-–1
W . C W W 00 Y W W 10 (0 )
W .1 00Y M .T W . 1 M .T W . 2 UBRR
O
+ M1 2BAUD
W O Note:WW
W .CO defined WW rate.1in0bit 0Yper .C second.T(bps). W
WW .100Y.C M.TW 1. The baud
. 1 00Y rate is M .TWto be the transfer W O M
O W O Y. C
W
WW .100Y.C M.TW
BAUD
W W 00Y
.CBaud rate
.TW (in bits per second, WW bps) . 100 M .TW
. 1 M W O
W O W
WW .100YSystem .CO Oscillator W 00Y
.C W
WW .100Y.C M.TW fOSC
M .TW clock W frequency
W . 1 O M.T
W O C
W
WW .100Y.C M.TW
O UBRR WW .100Contents Y.C of.TtheWUBRRH and WW UBRRL
. 0Y.
10Registers, M(0.T W
- 4095)
M W O
W O
WW of .UBRR
W .CO .for WW 00Y
.C are.Tfound W in Table 19-9
WW .100Y.C M.TWSome examples 1 00Y values M TW some system clock .frequencies
W 1 O M
O W O .C
W
WW .100Y.C M.TW
(see page 172).
W O W O
W
WW .Double .CO .TOperation W WW .100Y.C M.TW WW .100Y.C M.TW
19.3.2
1 00Y Speed (U2X)
W O
W .C OM The transfer rate can WWbe doubled Y .CO W W W 0 Y.C this .bit W
W W
. 1 00 Y
M .T W W
W . 10 0 by
O
setting
M .T the U2X bit in UCSRA.
W .1 0 Setting
O M T only has effect
W O for the asynchronous
WW .100Y.C M.TW
operation. Set this bit to zero when using
WW synchronous Y.C operation. .TW
WW .100Y.C M.TW W . 100 O M
O Setting this bit will reduce W O to.C
W
WW .100Y.C the .T W WW the 0 Y.C of the
0divisor .TW baud rate divider WW from.116 00Y 8, effectively W doubling
M.T will in this
M transfer rate for asynchronous
W . 1 M
communication.
O Note however W that theC Oreceiver
W O W .C W Y. .TW
WW .100Y.C case M .T
onlyW use half W the number .1 0of0Ysamples M TW
.(reduced fromW 16 to 8) W . 100data sampling
for O M and clock
W C O W W .C O W Y .Care required W when
W . recovery,
.TW and therefore a more Y
accurate baud W
rate setting W
and system
.10 0
clock
M. T
W . 1 00Y thisM W
W . 100 O M .T W C O
W O mode is used. For theWTransmitter, .Cthere are no downsides. W Y. .TW
WW .100Y.C M.TW W . 1 00Y M .TW W
W . 100 O M
W O
19.3.3 WW Clock
External
W
0 Y.C
O
1 0 .CO .TinWthis
W W. .C
External OMclocking is used byWthe
W
Wsynchronous Y .CO slave W modes of operation.
W WW The 0 0 Y
description
Y W 0 .T
W 00
W.1 section M.T to Figure 19-2 for
Orefers W .10
details. . C OM W W.1 Y.COM W
. C W W
W W
. 1 0Y
0External M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W O clock input from the XCK pin is
Y.C
sampled by a synchronization W register to .C
minimize
WW .1chance .C
00Y of meta-stability. .T W W W
1 0 0 M . T W W .1 0 0Y M .Tthe
W
M The output W .
from the synchronization
O register must W then pass C O through
W O
Y.Cdetector W Y.C .TWand receiver. WW Y. .TW
WW .an 1 00edge M .TW before it canW be used.by 1 00the Transmitter
M 100 introduces
This process
W . O M
W O .C lim-
W
WW a.1two 0Y CPU .COclock.Tperiod W delay and WWtherefore 0 Y.Cmaximum
0the .TWexternal XCK WW 00Y is M
clock frequency
.1 .TW
0 M W . 1 O M W C O
WW .100Y.
W ited by the following
O equation:
WW .100Y.C M.TW WW .100Y.C f OSC M.T
W M .TW
W O
W O
WW f XCK
W .CO
< ----------- WW .100Y.C M.TW
WW .100Y.C M.TW . 1 00Y 4 M.TW
W W .C O
Y W
W Note that
W .100fosc depends OtoM.Ton the stability ofW W.1 Yclock
the system
C OM source. It is therefore recommended
W W.1 Y.Cto OM
W W
add some
0 0 Y .
margin C avoid
.T W possible loss
W of data
1 due
0 0 .
to frequency
M . T W variations. W . 1 0 0 M.TW
. 1 M . W O
W .1 M O
19.3.4 Synchronous Clock Operation
W.1 Y.COM W W=W1), the Y.C pin will
O
W WW clock
W
0Y.C M.T
WW Synchronous
When
.10 0 mode .T is used (UMSEL W .1 0 0 XCK M . T be used as either . 1 0input O
(Slave) W Wor clock Y .C
output OM (Master). W The dependency WW between Y .COthe clock W edges andW WW
data sampling0 0 Y.C
W 00 W 0 0 .T .1
or data change W.1 isYthe M.T The basic principle
Osame. W Wis.1that Y data.C OinputM (on RxD) is sampled WW at the
W .C W W 0 0 .T W W
W XCK.1clock
opposite 00 edge M .T W.1(TxD)Y.isCchanged. OM
W C O of the edge the data output W
W W
1 00Y
.
M .TW W .100 M .TW
W . O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-3. 1
W.Timing. M
W WFigure .C OMSynchronous Mode W XCK
Y .CO .TW
W 00 Y .T W W 0 0
W.1 YUCPOL . C OM= 1 XCK W W.1 Y.COM W
W W
M .TW W
W . 100 O M .T W
W .100 O M.T
.CO .TW WW .100Y. C
00Y WW .100Y.C M.T W M .TW
. 1 M W O RxD / TxD W O
W
0 Y.C
O
0
W. 1
.C OM
W WW 00Y.CO .TW W WW 00Y.CO .TSample W
00 Y .T W . 1 M . 1 M
. 1 M W UCPOL = 0 XCK O W O
W W. 1
.C OM
W 00 Y .T W .1 M
W.1 Y.COM W W W.1 Y.CRxD OM/ TxD
W WW 00Y.CO .TW
W W 00 .T W
W
W .100 O M.T W.1 Y.COM W W W.1 Y.COSample M
W
.C W W 0
WW .100Y M .TW W
W . 100 O M .T W .10 O M.T
W O WW edge C
. for data
WW .100Y.C M.TW
The UCPOL bit UCRSC selects which XCK clock is Yused
WW .100Y.C M.TW used for . 100 is zero M .TWsampling and which is
data change. As Figure 19-3 shows, when W
UCPOL O the data will be changed at
W W Y .C O
W W
W
Wedge 0 Y .CO .TW W W 0 0 .C
Yis .T W
W .1 00 M .T rising XCK .and
1 0 sampled M at falling XCK edge. If .
UCPOL
W 1 set,
O M data will be changed at
the
W O C
W O
WW .100Y.C M.TW falling XCK WW 0 Y
edge and 0sampled .C at .rising TW XCK edge. WW .100Y. M .TW
W . 1 O M W O
WW 00Y.CO .TW
W19.4 WW .100Y.C M.TW WW .100Y.C M.TW
W
1
W. Frame .C OM
Formats
Y W
W 00
W.1 Y.COM bits),
.T A serial frame is defined W.1 to be C OM
one character of data bits with
W W.1synchronization
.CO .T
M bits (start and stop
W W 00 .T W and optionally W W a parity
1 0 Y .
0 bit for M .
error W
T checking. The USART W . 1 0 Y
0accepts all M 30 Wcombinations of
W . 1 O M the following as valid .
Wframe formats: O W W .C O
.C W .C W Y W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100 O M.T
W
WW .100Y.C M•.T1W
O start bit WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O • 5, 6, 7, 8, or 9 data
W
W
Wbits Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T W .10 0 M .1 M
W W.1 Y.COM • no, even or odd parity
W WW bit
W 00 .T stop bits W 0 0 .1 M
W.1 Y.CO•M1 or 2W W W.1 Y.COM W WW 00Y.CO .TW
W W 00 .T W .1 Then the
W
W .100 AO M.Tstarts with the start
frame
W Wbit.1followed
. C OM
by the least significant data W Wbit. Y
M
.CO next.Tdata W bits,
W W 0 Y . C T W W 0 0 Y . T W W 1 0 0
0 up to a .
total of nine, are succeeding, . 1 ending
OM
with the most significant .
bit. If enabled, Mthe parity bit
W W.1 Yis.Cinserted OM after the data bits, W W before Y
the .C stop bits. W
When a W
complete W W
frame 0
isY .CO .TW
transmitted, it can
W W .100or the communication .T .10
W
W .100 be directly O M.Tfollowed by a newWframe, W C OM line can Wbe W set to an
M
CO(high)Tstate.
.idle
W W Y .C
00Figure 19-4 W W
.Tillustrates the possible 1 0 0 Y .
M T W
.of the frame formats.W W . 0 0 Y
1 inside bracketsM . W
. 1 M W . combinations O Bits O are
W
WW .10optional. 0Y.C M.TW
O
W W .C O
W 00 Y .T W 1 .1 M
W.1Figure C OM Frame Formats WW.
19-4. .C OM WW 00Y.CO .TW
W . W 00 Y W W
W 00Y .T W
W.1 FRAME OM
.T .1 M
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C W .C
WW .100Y. .TW W 00Y .TW W 100
W.(St OM
.T
W (IDLE)OMSt 0 1 2 3 W.41 [5] .C[6] O M[7] [8] [P] Sp1 [Sp2] W .C
/ IDLE)
Y W
W O W .C O
WW .St
W .CO .TW WW 00Y
.C .TW WW .100Y .TW
1 00Y M Start bit, always low. W . 1 O M W O M
WW (n)
W
0 Y.C
O
0
W W. 1
.C OM Data bits (0 to 8). WW
W 00 Y .T W .10 0 .1 M
W.1 Y.COMParityWbit. Can be odd
P W Weven.
or .C OM WW 00Y.CO .T
W W 0 Y .T W W
W
Sp W .100 O M.T bit, always high.WW.10
Stop .C OM W W.1 Y.COM
.C W
WW .100Y M .TW W
W . 100
Y
O M .T W
W .100
WW 00Y.CO
IDLE No transfers on the communication
.TW WW .100Y.C M.TW
line (RxD or TxD). An IDLE WWline must
be W W . 1 O M W O
WW .100Y.Chigh.M.TW WW .100Y.C M.TW
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 frame Oformat M used by the USART .1 M
byOthe UCSZ2:0,
W WThe Y . C W W WW is0set 0 Y .C .Tthe W UPM1:0, and USBS bits in
W 0 0 .T . 1 M
W W.1 Y.COM W
UCSRB and UCSRC. The Receiver
W
andW Transmitter
0 Y .CO use
W
same setting. Note that changing
W W all0ongoing communication . T
M.T
W the .setting
W 100 of any OM
.Tthese bits will corrupt
of
W.1 Y.COM W
for both the Receiver and
.C O W Transmitter. .C W W
00Y .TW W .100
Y
M.T
W .100 OM
.T
W.1 Y.COM W W C O
.Character W W .C
0Y the number .TWof data bits in the frame. The
00 .T WW The USART
. 00Y mode
1Parity M .TW SiZe (UCSZ2:0) W bits .select 10set Mof
. 1 O M USART W O (UPM1:0) bits enable Wand the.C O
type parity bit. The selection between
W
0 Y.C .T W Wone W 0 0 Y.Cbits is done .T W by the USART WW Stop.10Bit0YSelect (USBS) M .TW bit. The receiver ignores the
.1 0 or
W. 1
two stop
OM O
WW 00Y.CO .TW
M
Y.C WW 0only 0Y.Cbe detected .TW in the cases where the first
WW stop
second
. 1 0 0
bit. An FE (Frame
M .T W Error) will Wtherefore . 1 M
W. 1 OM W O
stopW W
W bit is zero. .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW . 1 00Y M W O
W .COParity WW 00Y.CO .TW WW .100Y.C M.TW
WW .19.4.1 00 Y .T W
Bit Calculation W .1 M O
W W 1 Y.COM W The parityWW bit is Y .CO by.Tdoing
calculated W an W
exclusive-or WW of 0all0Y the .Cdata .TWIf odd parity is used, the
W .1 00 M .T W
W . 1 0 0
O M W .1 O Mbits.
W O result of W the exclusive .Cor is inverted. WW between
The relation C
Y. the parity
WW .100Y.C M.TW follows:: W 1 00Y M .TW . 100 M .TWbit and data bits is as
W . O W O
W
WW .100Y.C M.TW
O
WW .100Y.CP evenM=.TdW WW ⊕.1d010⊕Y.dC0 ⊕ 0M.TW
n – 1 ⊕ … ⊕ d 3 ⊕ d 2W
O W O =d d 0.C
O
– 1 ⊕ … ⊕ dW 3 ⊕ d 2 ⊕ d1 10⊕ ⊕1
W W
WW .100Y.C M.TW WW .100Y.CP odd M .TnW . 0Y M .TW
W O W O W W .C O
WW .100Y.C M.TW PevenWW
. 1 0Y.C bit using
0Parity M .TW even parity W . 1 00Y M.T
W
O W O W .C O
W
WW .100Y.C M.TW Podd W
W .C
00Y bit using
Parity W parity WW .100Y
.Todd M .TW
W . 1 O M W O
W
WW .100Y.C M.TW dn
O
WW Data .C
00Ybit n of M W
the.Tcharacter WW .100Y.C M.TW
. 1
W W .C O
W 00 Y W
If.Tused, the parity bit is located .1stop bit of aMserial frame.
W.1 Y.COM W W W.1 Ybetween .C OM the last data bit and
W
first
WW 00Y.CO .TW
W W 00 .T W
W 00
W.1 InitializationOM
19.5 W USART .C W
W . 1 00Y M .TW W
W . 100
O M .T W
W .100 O M.T
W OThe USART has to beW Y.C any .communication
initialized before canWtake place. C
. The initialization pro-
WW .100Y.C cess W
.Tnormally W of .setting 100 the M TWrate, setting W . 00Y andMenabling
1format .TW
M consists W baud frameW O the
W O W depending .CO W Y .C W the
WW .100Y.CTransmitter .T W or the W
Receiver .1 0 0 Y on the
M .T W
usage. For W
interrupt 1
driven
. 0 0 USART .T
operation,
M
W W .C OM Interrupt Flag should
Global WW be0cleared Y .CO (and W
interrupts WWdisabled)
globally
W 0 Y .COwhen .doing TW the
W Y
00 initialization. .T W W . 1 0 M .T .1 0 M
. 1 M W O W O
W
WW .100Y.C M.TW
O
W W Before
.C O doing a re-initialization W changed
Wwith Y .CObaud.rate W or frame format,
W WWbe sure 0 .COthere.Tare
Ythat Wno
W 00 Y .T W W . 1 0 0 M T . 1 0 M
W.1 ongoing Mtransmissions during the Wperiod the O registers are changed. The
WWTXC00Flag O be used
.Ccan
WW .10to 0Ycheck.CO that .T W
the Transmitter W Whas 0 0 Y
completed
.C all transfers,
.T W and W
the RXC 1
Flag
.
Ycan beM .TWto
used
. 1 M W O
W OMthere are no unread W O
Y.Creceive.Tbuffer. W the TXC .C W
WW .1check 0 0Y.CthatM .TW WW data.1in 00the M
W Note W that
.1 00YFlag must M.T
be
cleared before each transmission W
(before UDR O
is written) if it is used for W
this purpose. C O
W
WW .100Y.C M.TW
O
O simple USART initialization W code O W O
.C C func-
WW tion
WThe following
0 Y.C .T W WW 0 0Y.C assume
examples
.TW
show one assembly
WW .and 1
Yone
00using M.T
W
.1 0that are equal
M in functionality. The W . 1
examples O M asynchronous W
operation C O
polling
W .COenabled) W format. .C W is given W W Y. .TW
WW (no.1interrupts
00Y M .TW and a fixed Wframe . 1 00Y The baud M .Trate as a function
W .100parameter. O M
O code, the baud rate W O .C
W
WWFor the 0 Y.C
assembly
.T W WWparameter 0 0Y.C is assumed
.TWto be stored WW 00Y regis-M.TW
in the r17:r16
. 1
0 . 1 M
W
ters. 1
W. WhenYthe . C
M
Ofunction writes to the UCSRC WW Register, Y .COthe URSEL W bit (MSB) W
W
W be setYdue
must
0 .COto .TW
W the sharing 00 of I/O location W
.T by UBRRH and W W .10 0 .T .1 0 M
W.1 Y.COM W W
UCSRC.
.C OM WW 00Y.CO .TW
W W 00 Y .T W W
W
.C W W 00 .T
WW .100Y M.T
W O W . C O W
W W .100 M.T
W O W O W W .C O
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1Assembly M .1 M
W Y .C OCode
W
Example (1)
W WW 00Y.CO .TW
W 00 .T W.1 Y.COM W
W W.1 USART_Init: .C OM
W W
M .TW W
W .
Y
100; Set Obaud M .T W
W .100 O M.T
.CO .TW WW .100Y. C
0Y.C M.TW .TW
rate
00Y WW .10out M
. 1 M W O
UBRRH, r17 W O
W
0 Y.C
O
.T W WW .1out 0 0Y.C .TW WW .100Y.C M.TW
0 UBRRL, M r16
W. 1
.C OM
W WW ; Enable Y .COreceiver W W WW 00Y.CO .TW
Y W .10 0 M. T and transmitter .1
.100 M.T Wldi O(1<<RXEN)|(1<<TXEN) WW 00Y.CO .TW
M
WW 00Y.CO .TW W Y
r16, .C W W
W .1 O M
W
W .100UCSRB,r16 OM
.T
W W.1 Y.COM W
.C W out .C W
WW .100Y M.T
W W ; Set
W
Y
.100frame Oformat: M.T 8data, 2stop
W
W
bit .100 OM
.T
W O C W .C
WW .100Y.C M.TW WWldi .1r16, . .TW
00Y (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)
M
W . 100
Y
M .TW
W O
W O
WW
WW .100Y.C M.TW out UCSRC,r16
. 1 00Y M W O
WW .100Y.C M.TW Wret .1 M
W W .C O
W C Code Example WW (1) Y .CO .TW W WW 00Y.CO .TW
Y W 0
W
W .10 0
O M.T W .1 0
.C OM W W.1 Y.COM W
C void W
USART_Init( unsigned W int baud )
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O { W C O W . C W
WW .100Y.C M.TW /* W
W
. 10rate0Y. */ M.TW W .100
Y
M.T
O
Set baud
W O W .C O
W
WW .100Y.C M.TW UBRRH WW = (unsigned
.C
00Y char)(baud>>8); .TW WW .100Y M .TW
. 1 O M W O
W O WW 00Y.char)baud; C WW .100Y.C M.TW
WW .100Y.C M.TW UBRRLW= (unsigned . 1 M .TW
W W .C O
W
/* EnableWreceiver W Y CO transmitter
.and W */
W WW 00Y.CO .TW
W 00 Y .T W 0 0 .T .1 M
W.1 Y.COM W UCSRB = (1<<RXEN)|(1<<TXEN); W W.1 Y.COM W WW 00Y.CO .TW
W W 00 8data, .T2stop bit */ W
W
W .100 O M.T /* Set frame W.1 Y.COM W
format:
W W.1 Y.COM W
.C W
WW .100Y M .TWUCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);
W
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C M.TW
}
W O
W O WW 00Y.ConOpage.6. WW .100Y.C M.TW
WW .100Y.CNote:M.T1.W See “AboutWCode Examples” . 1 M TW
W W .C O advanced initialization
More WW routinesYcan .CObe made W that include W WW format
frame 0 Y .CO
as parameters,
.TW dis-
W Y
00 able M .T W W . 1 0
0 manyMapplications .T . 0
1setting ofOthe M
. 1 interrupts and so on. However,
W O use a W
fixed Baud and
W .CO Registers, Wthese Y .C W W W 0 Y.Ccan be.Tplaced W
WW .100YControl M .T W and W for .1 0 0
types of .T
applications
M the initialization
W . 1 0 code O M
W O W .C O W other 0I/O .C
WW .100directly Y.C in the .TW
main routine, Wor Wbe combined
1 .TW
00Y withMinitialization code Wfor .
Y
1 0 modules. M .TW
M W . O W O
19.6 DataW W. 1
Transmission – OM The USART Transmitter WW 00Y.CO .TW
W Y .C W W WW 00Y.CO .TW W
W 00 USART
The
W.1Register. OM
.T
Transmitter is enabled Wby .1 setting O
C
the MTransmit Enable (TXEN) Wthe W.1bit inYthe .COUCSRB
M
W W 00Y
.C When .T W
the Transmitter W W
is enabled,1 00 Y .
the normal
M .T W
port operation W of TxD
. 1 00 pin is .TW
overrid-
M
. 1 M W . O W .C O
Wden byYthe
WW of.1operation .COUSART Wand given the function
WW .1as 0 Y.Ctransmitter’s
0the .TW serial output. WWThe .baud 1 00Yrate, mode M.T
W
00 M
and .Tframe format must beW set up once O M
before doing any W
transmissions. If O
synchro-
C
W
WW nous 0Y.C M
O
TW the clockWon the .XCK
is .used,
W .C
00Ypin will M be.T
W WW .10transmission 0Y. M .TW
. 1 0operation W 1 O overridden and usedWas O
W
WWclock. 0 Y.C
O
0
W W. 1
.C OM
Y W
19.6.1 Sending Frames W with.1500to 8 DataMBit
W O
.C W
W
WA data transmission
.1 00Y M TW by loading
is .initiated W the transmit
W . 100 buffer O M with W
.T the data to be transmitted. W .100 TheOM.T
WW O Y.C I/O location. WW data .C
WCPU can loadY.the
0 0 C transmit
.T Wbuffer by writing WW to .the 1 0 0UDR M .TW The buffered . 1 00inYthe M.TW
.1 M COShift Register to W O
transmit
WWbuffer Y . O moved
willCbe
W
to the Shift Register
W WW when 0 0 Y.the .T W is ready WW send a new
1 00Y.C M.T
W 0 .T .
frame. The.1Shift
W
0 Register
.C OM is loaded with newW dataW.if1 it is Y in idle
CO
M
state (no ongoing transmission)
.transmitted. W WW 00or Y .CO
W
immediately after Y the last stop W bit of the W
previous frame 0 is .T When the W
Shift Register is
W
W.new 100 O M.T 10
W.frame .C OM W.1
WRegister,
loadedW with data,
Y . C it will transfer
W one complete
W W 0 0 Yat the rate given
.TW by the Baud
W
W
by.1 00 depending .T W.1 Y.COM W
U2X bit or W
W
XCK
.C OM on mode of operation. W
Y W W .100 .T
W
WW .100Y. C W Y
W O M.T
W
W .100
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 following OMcode examples show .1 M
W WThe Y .C W W WaWsimple 0 Y .CO transmit
USART
.
function based on polling of the
TWless than eight bits, the most signif-
W .1
Data 0 0
Register Empty
M .T (UDRE) Flag. When . 1 0
using frames M with
WW Y .CO to.Tthe W W WW The 0 Y .CO has W
M .T W W icant
W . 1 0 0
bits written
O M
UDR are ignored.
W . 1 0 USART
O M.T to be initialized before the function
.CO .TW .CFor the.Tassembly WWthe data C
Y.be sent .isTW
00Y WWcan be . 1
used.
00Y M
W code,
. 100
to
M
assumed to be stored in Register
. 1 M R16 W O W O
W
0 Y.C
O
.T W WW .100Y.C M.TW(1) WW .100Y.C M.TW
0
W. 1
.C OM
W WW 00Code
Assembly
Y.COExample W W WW 00Y.CO .TW
Y W .T .1
M
WW 00Y.CO .TW
USART_Transmit:
W W
.1 M
W
W 100 for Oempty
; .Wait M.T transmit buffer W.1 Y.COM W
W .C O W . C W W
WW .100Y W W sbis 0Y M.T
W 00 .T
W O M.T W .10UCSRA,UDRE
.C O W W.1 Y.COM W
WW .100Y.C M.TW WWrjmp.1USART_Transmit
00Y M.T
W W .100 M.T
W O W O W W .C O
WW .100Y.C M.TW WW .100Y.C M.TW Y W
; Put data (r16) into buffer, sends the data
W O
W
W .100 O M.T
W O out UDR,r16
.C WW .100Y. C
WW .100Y.C M.TW Wret W
1 00Y M .TW M .TW
. W O
W O WW (1) .CO .TW WW .100Y.C M.TW
WW .100Y.C M.TW C Code WExample . 100Y M
W O WW 00Y.CO .TW WW 00Y.CO .TW
WW .100Y.C M.TW WUSART_Transmit( 1
W )W.1 M
W C O
void
W W. .C OM unsigned char data
W Y .CO .TW
W . W Y W W 0 0
W
W .100
Y
O M.T
{ W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. Y W 00 .T
W /* Wait for empty transmit buffer */
W O M.T
W
W .100 & (1<<UDRE)) O M.T W W.1 Y.COM W
while ( W !( UCSRA .C )
WW .100Y.C M.TW W . 100
Y
M .TW W
W .100 O M.T
W O ; W O W .C
WW .100Y.C M.TW /* PutW
W Y.C .TW the dataW*/ W.100Y OM.TW
data into
W . 100buffer, O M sends
W O
WW .100Y.C M.TW UDR = data; WW .100Y.C M.TW WW .100Y.C M.TW
W W .C O }
W 00 Y W .1
W.1 Y.CONote: M.T W W.1 Y.COM W WW 00Y.CO .TW
M
W W 1. See “About W Code Examples”0 on page .T 6. W
W 00
W.1 Y.CO M.T 0
W.1the transmit .C OM W W.1 Y.COM W
W The function simply waitsW for Y buffer Wto be empty Wby checking 0the UDRE Flag,
.T before
W . 1 00 M
loading
.TitWwith new data W
to W
be . 00
1transmitted. O M If
.T
the Data Register W .10Interrupt
Empty C OMis utilized, the
W
WW .100Y.C
O
.T W writesW W 0 0 Y.C .T W WW .100Y. M .TW
interrupt routine the dataW. 1
into the OM
buffer. W O
W OM WW .100Y.C M.TW
19.6.2 Sending
W WFrames .with
C O 9 Data Bit
W Y
00 9-bit characters .T W .1 TXB8 bitOinMUCSRB
W.1 If Y OM are used (UCSZ W.1= 7), Y the C OM bit must be writtenWtoWthe
ninth
0Y.C Mshow
W W 00 .C
before the .T
low W byte of the W W
character 1 0is
.
0written to M .
UDR.
W
T The following code W .1 0examples .TWa
W. 1 M W . O W O
.C sent
WW .1transmit .CO .TWthat handles WW 0Y.C For Wassembly W W the data 00Y to be M .TW
00Y function M
9-bit characters.
W . 1 0
O M .Tthe code,
W .1
.C O
is
W assumed O to be stored in Registers W R17:R16. .C W Y .TW
WW .100Y.C M.TW W .1 00Y M .TW W
W . 100 O M
W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100
WAssembly
.T
W . C Code W
M .TW W
W . 00 Y
1USART_Transmit: O M .T W
W .100 O M.T
00Y WW .10;0Y M .T W M .TW
. 1 M W Wait O for empty transmit W
buffer O
W
0 Y.C
O
.T W WW .1sbis 0 0Y.C .TW WW .100Y.C M.TW
0 UCSRA,UDRE M
W. 1
.C OM
Y W 0 0 USART_Transmit .1
.100 M.T W;.1CopyY.9th OM WW 00Y.CO .TW
M
WW 00Y.CO .TW W C bit from W r17 toW TXB8
W .1 O M
W
W .100UCSRB,TXB8 OM
.T
W W.1 Y.COM W
.C W cbi
0Y .C W W 00 .T
WW .100Y M.T
W W sbrc .10r17,0 M.T W.1 Y.COM W
W O W .C O W
WW .100Y.C M.TW WWsbi .1UCSRB,TXB8 00Y M.T
W W .100 M.T
W O W O W W .C O
WW .C (r16) Y W
WW .100Y.C M.TW ; Put LSB
. 100
Ydata
M .TWinto buffer, W sends
W .100the data O M.T
W O C
W
WW .100Y.C M.TW
O
Wout W UDR,r16 0 0Y.C M.TW WW .100Y. M .TW
ret W . 1 O W O
W O
WW .100Y.C M.TW C Code WW .1(1) 0 0Y.C M.TW WW .100Y.C M.TW
Example W O W O
W
WW .100Y.C M.TW
O
)W O
W O WW 00Y.CO unsigned
void USART_Transmit( int data W
Y.C W
WW .100Y.C M.TW { W . 1 M .T W W
W . 1 0 0
O M.T
W O W .C O W .C
WW .100Y.C M.TW /* Wait WWfor .1empty 00Y transmit M .TWbuffer */W W.100Y OM.TW
WW 00Y&.C(1<<UDRE))) O
W O
WW .100Y.C M.TW whileW( !( UCSRA .TW ) WW .100Y.C M.TW
. 1 M
W W .C O
W
; WW
W 00 Y .T W 0
.10to TXB8OM .1 M
W W.1 Y.COM W /* Copy 9th W Wbit
Y .C */
W W WW 00Y.CO .TW
W .100 M.T UCSRB &= ~(1<<TXB8);
W 00 .T W.1 Y.COM W
WW .100Y M .TWif ( dataW& 0x0100 W . 100) O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C M.TW
UCSRB |= (1<<TXB8);
Wbuffer, sends O W O
W O
W = data;WW .100Y.C M.TW WW .100Y.C M.TW
/* Put data into the data */
WW .100Y.C M.TUDR
W W . C O
W 00 Y } .T W 0 0 .1 M
W W 00written toM .T W .1 be optimized
W
W .100 Note:OM1..TThese transmit functions W W .1are
.C O be general functions. They W Wcan Y
M
.CO if .the W
con-
W Y .C W
tents of the UCSRB W is static. 0 Y
(i.e., only the .T
TXB8W bit of the W
UCSRB 0
Register0 is used T
after
W 00
W.1 Y.COM initialization).
.T 0
W W 100
W W
. 1 0 ninthM
0The bit
W
.Tcan be used
W
for indicating
W . 100an address O M T
.frame when using W
multi .processor O M.T
communi-
W O Y.C W Y .C W
WW .1cation .C
00Y mode .Tfor
or W other protocol WWhandling . 100 as forOexample M .TW synchronization. W .100 M.T
M W W C O
W
WW .100Y.C M.TW
O
W O
19.6.3 Transmitter Flags
W and O
Interrupts
Y.C transmitter
W
WWflags .1that .CO .TW
0Yindicate WW .100Y.C M.TW
WW The 0 0 .T W 0 M O
W W.1 Y.COM WUSART has two
W W
0 Y .CO its state:
W
USART
W WWRegister
Data
0 0 Y .CEmpty .TW
W (UDRE) 0 0 and Transmit .T W
Complete (TXC). Both . 1 0 flags can Mbe .Tused for generating 1
interrupts.
. M
. 1 M W O
W .CO Empty WW 00Y.CO .TW WWis ready .C
00toYreceiveM.TW
WWThe .Data 00YRegister .T W (UDRE)W Flag indicates . 1 whether M the transmit buffer . 1
1
W data. Y ObitMis set when the transmit WWbuffer CO and W W CO
.buffer
W Wnew
0 0 .
ThisC
.T W W 1 0 0 Yis .empty,
M .T W cleared W
when the transmit
. 1 0 0 Y
M .TW
. 1 to O M .
Wyet been O W .C O
WW data
contains
Wibility 0
be transmitted that hasW
Y.C devices, .T W
not
Wthis bit to 0 0Y.C
moved intoW
.T the UCSRA WW For
the Shift Register.
. 1
compat-
00Y M .TW
with
.1 0 future M always write W . 1 zero whenO M writing W
Register. O
When W the .1 Data Register M empty Interrupt W Enable
W (UDRIE) Obit in UCSRB is written Wto one, the O
.CO Empty Y.Cas long.TasWUDRE is set WW Y.C
0that
WW Data
USART
.10 0 Y
Register
M .T W Interrupt W
will be
W
0
executed
.1 0
O M (provided
W . 1 0
O M.T
W O Y.C UDR. W .C
WWinterrupts
global
0 0Yare .C enabled). .TW UDRE isW
W by00writing
cleared
. 1 M
W interrupt-driven
.TWhen W 00Y
.1data
.1 O M W O W
transmission W is used,
WinWorder.1to0clear 0Y.CUDRE
the Data Register Empty
.T W WW .100Yempty .C
Interrupt routine must
WW data to
either write new
.TW otherwise
UDR M or disable the Data Register M
Interrupt, a new inter-
W W Y .C O
W W WW 00Y.CO .TW
rupt willW occur once0 0 the interrupt .T routine terminates. .1 M
W 00 .T W
W.1 Y.COM W W W.1
WW .100Y. C W 8155B–AVR–07/09
W O M.T
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 Transmit OMComplete (TXC) Flag .1 M
W WThe Y . C W W WW bit is set one
0 Y .COwhen.Tthe W entire frame in the transmit Shift
W 0 0 .T . 1 0 M
W W.1 Y.COM W
Register has been shifted out and there
W W are no
0
new
Y .CO data currently
W
present in the transmit buffer.
W W The.1TXC 00 Flag bitMis.Tautomatically cleared W 10 a transmit
.when T
M. complete interrupt is executed, or it
O M.T W W
can be cleared.C O by writing a one toW its Wbit location.
Y .C OThe TXCW Flag is useful in half-duplex
.C 00Y interfaces .TW (like the RS485 W 100 where .T
. 1 00Y M .TW W . 1
communication M W .
standard), O M a transmitting application must enter
W Y .CO .TW W WW 00Y.CO .TW WW bus.1immediately 0 0Y.C Mafter .TWcompleting the transmission.
00 receive .1mode and free
M the communication
W .1
.100 M.T When the
W.1 Transmit OCompete
M Interrupt EnableW(TXCIE) bit O inM
.Cbecomes
UCSRB is set, the USART Transmit
WW 00Y.CO .TW W W
Complete 0 Y
Interrupt
1 0
.C will be. T W
executed when W W
the TXC . 1 0 0
FlagY
M
W (provided that global inter-
.Tset
W. 1 OM W . O M W .C O
WW .100Y.C M.TW
ruptsW
W are enabled). 0 0Y.CWhen .
the
TWtransmit complete WW interrupt .1 00Y is used, M
W interrupt handling routine
.Tthe
does not W .
have 1 to clear O M
the TXC Flag, this is done W automatically O when the interrupt is executed.
W
WW .100Y.C M.TW
O
W W19.6.4Y.CO Parity Generator
W 00 .T W .1 M
W.1 Y.COM W The parityWgenerator W.1 Ycalculates C OM the parity bit for W theW serial frame .COdata. .When
W W 0 0 . W
.T logic inserts theW W 0 0 Y
1 bit between TW parity bit is enabled
W .1 00 M .T (UPM1 = 1), W the.1transmitter O Mcontrol .
parity O M the last data bit and the
W W Y .C O
W W Wof the frame 0 Y .Cthat .T W W W 0 0 Y.C .T W
W .1 0 0 M .T first stop bit . 1 0 is
M sent.
W . 1 O M
W O C
WW
W .CO .TW WW .100Y.C M.TW WW .100Y. .TW
. 1 00Y M W O M
19.6.5
W Disabling
O the Transmitter
WW
WW .100Y.C M.TWThe disabling of the . 1 00Y
transmitter M
(setting the TXEN to zero) Wwill notYbecome
W W .C O WW 00Y.C O
W W Wthe 0 .CO effective .T W
until ongoing
Y W
and pending W transmissions are T
completed,
M. i.e., when 0
transmit
1 Shift Register and transmit
W
W .100 O M.T Buffer Register do W .1
. C O W W.disabled, Y .C OMtransmitter will no lon-
W
WW .100Y.C M.Tger W WW .100Y not contain data
M
to be
.TW transmitted. W When
.100
the
M.T
O override the TxD W pin. O W .C O
W
W
W O W O
W
WWData.1Reception .CO .–TW WW 00Y
19.7 00Y The USART Receiver . 1 M O
W .C
M
O The USART ReceiverWisWenabledYby .CO W W WW(RXEN) 0 Ybit.Cin W Regis-
W W
. 1 00 Y
M .T W W
W . 10 0 writing
O M . the
T Receive Enable
W .1 0
O M.T
the UCSRB
W Oter to one. When the receiver .C
is enabled, the normal WW .of10the
pin operation C
0Y.RxD pin
WW .100Y.C byM W
.TUSART WW .function 1 00Y as the M .T W M .isTWoverridden
the and given the receiver’s serial input. W The baud O
rate, mode of oper-
W O W
Wmust .CO W Y.C can .be W
WW .100Y.Cation M. T
and W frame W
format .1 0
be 0 Y set up Monce .T W before any W serial
W. 1 0 0
reception
OM
T done. If
W C O W W .C Oon W Y . C W
WW .100Y. synchronous W operation is used, the Y
clock the W
XCK pin will be
W used
.100
as transfer clock. .T
W O M.T
W
.C WW .100Y. C Y W
19.7.1 WW .1Frames
Receiving 00Y with M .5TtoW8 Data Bits M .TW W
W .100 O M.T
W O W .C O W bit 0that .C
WW .100The Y.C receiver .TW starts data reception WW .when 1 00Yit detects M .TaW valid start bit. WEach .
Y
1 0 follows M .TW
the start
bit C
will be sampled at the
WW .100Y
baud rate or XCK . clock, and
TW shifted into the receive 00Y
Shift Register W
.Tuntil
WW .10the 0Y.first .T W
M bit of a frame is received. M . W
W .1 O M
W .CO bit
stop
WW 0A0Y .CO stop
second bit will be ignored
TWis present W
W by the .C
receiver.
00YShift Register,
When
.TW
WW .1the 00Yfirst stop M . T W
is received, W
i.e., a 1
complete
. serial M .
frame in the .1
receive
W O M
O of the Shift Register W O Y. C
W
WW .the Y.C .TW WWwill be 0Y.C into .TW WWThe receive 100 buffer .TW
1 00contents M .1 0moved M
the receive buffer.
W . O M can
Wthen be read O by reading the UDR W I/OW location.Y.CO WW .100Y.C M.TW
WW .100Y.C M.TW W . 1 00 M .TW O
W O W .CO receive WWon polling 0Y.C of the .TW
The following
WW Receive 0 0 Y.C code . T
example shows
W WWa simple . 1 0 0 USART
Y
M .T W functionW based
.1 0 M
. 1 Complete M (RXC) Flag. When W
using frames O
with less than eight bits W O
WW .100Y.C M.TW
W O the most significant
W W . C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 of the O
Wbits C dataM read from the UDR WwillW.1be masked M
.CO to .zero. The USART has to be initialized
W W 0 0 Y . .T W W . 1 0 0 Y
M TW
.1
before the function
M can be used.
WW 00Y.CO .TW
W W WW 00Y.CO .TW (1) W
O M.T W .1
Assembly
.
Code
C OMExample W W.1 Y.COM W
.C W W
00Y .TW W 100
Y
.USART_Receive: M.T
W .100 OM
.T
W.1 Y.COM W W C O
Y. for data W W Y .C W
00 .T WW .1;00Wait M .TW to be received W .100 M.T
. 1 M W O W .C O
W .CO .TW WW sbis .C
00YUCSRA,MRXC .TW WW .100Y .TW
. 1 00Y M W . 1 O W O M
WW 00Y.CO .TW WW rjmp 0 Y.C
0USART_Receive .TW WW .100Y.C M.TW
1 . 1 M W buffer O
W. .C OM WW ; Get andCreturn
Y . O .Treceived W
dataWfrom
W 0 Y.C W
W W
.1 00 Y
M .TW W
W
0
in .10r16, UDR O M W .1 0
O M.T
W
WW .100Y.C M.TW
O
WWret .100Y.C M.TW WW .100Y.C M.TW
W W .C O
W
W
WExample Y .CO .TW W WW 00Y.CO .TW
W 00 Y .T C W
Code 0 0 (1)
.1 M
W W 0 0 .T W .1
W 00 .T unsigned char
W.1 Y.COM W
USART_Receive( void ) M
W W.1 Y.COM W { WW W WW 00Y.CO .TW
W .100 M.T 100 data OtoM.be
.for T .1 M
W W .C O /* Wait W W Y . C received */ WW
W W 0 Y .CO .TW
W 00 Y .T W W .10 0 M. T .1 0 M
W W.1 Y.COM W while (W
W
!(UCSRA
Y .C&O (1<<RXC))
W
)
W WW 00Y.CO .TW
W
W .100 O M.T
W;
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W /* Get W and return .100
Y received
M.T data from buffer
W */00
W.1 Y.COM W
.T
W O W .C O W
WW .100Y.C M.TW
return
WW .100Y
UDR;
M .TW W .100 M.T
O W O W .C O
W
} W
W O
W
WW .100Y.C M.TW
O Note: 1. See “About
WW Code 00Y
.C on page
Examples”
.TW6. WW .100Y.C M.TW
. 1 M
W W .C O The function simply waits WW for 0data Y toO
.C be present W in the receive
W WW .CO .the
buffer byYchecking
0 TWRXC Flag,
W 00 Y .T W W . 1 0 M .T . 1 0 M
W.1 OMbefore reading the buffer W and returning O the value. W O
O with 9 Databits WW O W O
19.7.2 W
WW .100Y.C M.TW
Receiving Frames W 0 0 Y.C .T W WW .100Y.C M.TW
.1 OM W the Y .CO bit in
W W Y.CIf O
9 bit characters are used
W W WW (UCSZ=7)
0 0 Y.Cthe ninth bit must be read
.T W W Wfrom
1 0 0
RXB8
.TW
UCSRB
W 0 0 .T 1 . M
W.1 Yas
before
C OM
reading the low bits
W W.
from the UDR.
.C OM
This rule applies to the FE,
W W DOR and
Y
PE
.CO .TW Status Flags
W . .TW status from Y W W 0 0
W
W .100 change
well. Read
O Mthe
W UCSRA,
W .100then data Oand
T UDR. Reading the.1UDR
M.from W W FE, DOR
I/O location
.C OandM will
Y. C state of the receive W buffer FIFO
0Y .C consequently
W the
W TXB8,
00 Y PE
.T W
bits,
WW .100which allM .TW W .10change. M.T W.1 Y.COM W
W O are stored in the FIFO,W will
. C O W
WW .100Y.C M.TW WW .100Y M .TW W 0
.10handles M.T9-bit
W The following
O code example showsW a simple O
USART receive function W Wthat .C Oboth
WW .1characters00Y
.C
and W status bits.
.Tthe WW .100Y.C M.TW W .100
Y
M.T
W
M W O W C O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W O W O
W
WW .100Y.C M.TW
O
W W .C O
W 00 Y .T W .1 M
W W 00 .T W
W
.C W W 00 .T
WW .100Y M.T
W O W .C O W
W W .100 M.T
W O W O W W .CO
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Y.COM W .1 M
W W WW 00Y.CO .TW
W .100
WAssembly
.T
W .C Code W
M .TW W
W . 00 Y
1USART_Receive: O M .T W
W .100 O M.T
00Y WW .10;0Y M .T W M .TW
. 1 M W Wait Ofor data to be received W O
W
0 Y.C
O
.T W WW .1sbis 0 0Y.C .TW WW .100Y.C M.TW
0 UCSRA, M RXC
W. 1
.C OM
Y W 0 0 USART_Receive .1
.100 M.T W;.1Get Ystatus OM and 9th bit, then WW .CO
M
WW 00Y.CO .TW W W
1 0 0 .C
.T W W data from
. 1 0 0 Y buffer
M .TW
W. 1 OM W . O M W O
0Y.CUCSRB WW .100Y.C M.TW
in r18, UCSRA
WW .100Y.C M.TW WW in .10r17, M .TW W O
W O W
WWin .1r16, .CO WW .100Y.C M.TW
WW .100Y.C M.TW 00Y UDR M.TW
W W .C O
W W W Y
O
.Creturn W W WW 00Y.CO .TW
W 00 Y .T W ; If error,
.10 0 .T-1
.1 M
W.1 Y.COM W W
andi . C OM
Wr18,(1<<FE)|(1<<DOR)|(1<<PE) WW 00Y.CO .TW
W W 0 Y .T W W .1
W 00
W.1 Y.COM W
.T breq W .10
USART_ReceiveNoError OM WW 00Y.CO .TW
M
W W
W r17, 0 Y .C W W
.10HIGH(-1) .T W.1 Y.COM W
W
W .100 O M.T ldi
W W . C OM W
WW .100Y. C W
M.T
W W r16,.1LOW(-1)
ldi
W
00Y
O M.T
W
W .100 OM
.T
W O C W .C W
USART_ReceiveNoError:
M .TW W .100
Y
M.T
O W O W .C O
W
WW .100Y.C M.TW
;
WW .100Y.C M.TW
Filter the 9th bit, then return
WW .100Y M .TW
O W O
WW 00Y.C WW .100Y.C M.TW
W O lsr r17
WW .100Y.C M.TW andi W r17, 0x01 . 1 M .TW
W W .C O
W 00 Y .T ret W .1 M
W.1 Y.COM C Code W W.1 Y.COM W WW 00Y.CO .TW
W W Example W (1)
00 .T W
W
.C W
WW .100Y M
W
.Tunsigned intW USART_Receive(
W . 100 O
void
M .T ) W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C M.TW
{
W O
W O unsigned charW W
status, .CO resl;
resh,
WW .100Y.C M.TW
WW .100Y.C M.T/*WWait forWdata to.1be 00Yreceived M
W
.T*/
W W .C O
W W W Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W 0 0 .1 M
W.1 Y.COM W
while ( !(UCSRA & (1<<RXC)) )
W W.1 Y.COM W; W W WW 00Y.CO .TW
W
W .100 O M .T W
W .100 .T
OMdata */ W W.1 Y.COM W
C /* Get status and W 9th bit, .C
then W
WW .100Y. TW buffer W
M.from .100
Y
M.T
W 00
W.1 Y.COM W
.T
W O /* */
W W .C O W
WW .100Y.C status M .TW= UCSRA; W W.100Y OM.TW W
W .100 O M.T
W O W .C
WW .100Y.C resh .=TW UCSRB; WW .100Y.C M.TW W .100
Y
M.T
W
M W O W C O
W
WW .100Y.CreslM=.TUDR;
O
W O W O
W
WW .100Yif .COIf error,
/*
.T W
return -1W*/
W 0 0Y.C M.TW WW .100Y.C M.TW
M W . 1 O ) W O
WW .100Y.C M.TW
( status & (1<<FE)|(1<<DOR)|(1<<PE)
W
WW .100Y.return CO T W WW .100Y.C M.TW
.
-1;
W CO
M WWreturn .C O
W WW 00Y.CO .TW
WW .10/* 0Y.Filter T
theW 9th
M. >> 1) & 0x01;WW.1
bit, W then 0 0 Y */ .T W
W.1 Y.COM W
W C O .C OM W
WW .100Y.
resh = (resh W Y W W 00 .T
W O M.T << 8) | resl);
W
returnC((resh
WW .100Y .C
WW } .100Y. M .TW M .TW W
W .100 OM.T
O W O .C
W
W
W O W O
Note: W1. See “About
WW 0Y.C example
O Code Examples” on page
.TW reads all W
W 6. 00Y.C W
.TRegister WW .100Y.C M.T
1 0function .1 M any com-.CO
The receive
W W .
. C O M
W
the
WW 00Y.CO .TW
I/O Registers into the File WW
before
W 0Y
W is done.
putation
.1
Y
00 This gives M
W
.Tan optimal receive buffer W . 1 utilization O since the buffer locationW
M .10will
read
W
WWto accept
be free new .CO data asTearly
. W as possible. WW .100Y.C M.TW WW
. 1 00Y M W O
W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
0
W.1 Flag OM .1 M
19.7.3 Receive Compete
W Y .and
C Interrupt
W W WW 00Y.CO .TW
W The 0
.10USART M.T has one flag that
Receiver .1
indicates M
W W Y .C O
W W W W
0 Y .the
COreceiver
.T W
state.
.T W W 0 0 .T 1 0
OM W.1Receive
The OM
CComplete (RXC) Flag indicates
WW if0there
.
.CareOMunread data present in the receive buf-
Y .C W W Wfer. 0 Y . T W
.when unread data exist W 0 Y W and zero when the receive
.Tbuffer,
. 1 00 M .T This
. 1 0 flag is one M W . 1 in the receive O M
W O W is empty O W unread .C If the
00 Y.C .T W WW buffer
. 1 0 0Y.C (i.e.,Mdoes .TWnot contain Wany .1 00Y data).
M.bit TW receiver is disabled (RXEN = 0),
. 1 O M the W
receive buffer O will be flushed and consequentlyW the .C O
RXC will become zero.
W
0 Y.C .T W WW .100Y.C M.TW WW .100Y M .TW
.1 0 O
WW 00Y.CO .TW
M WhenWW the Receive O
Y.C Complete W Interrupt W WW (RXCIE)
Enable
0 0Y.Cin UCSRB .TWis set, the USART Receive
W . 1 0 0 M .T . 1 M
W. 1 OM Complete Interrupt will be executed as long asW the RXC O
Flag is set (provided that global inter-
W Y .C W W Ware W
0 Y .CO .T W W W 0 0 Y.Cis used,.Tthe W receive complete routine
W .1 00 M .T rupts
W . 10
enabled). When
O M interrupt-driven data
W .1
reception
O M
W O W the 0received 0Y.C data WW to clear Y.C .TWotherwise a new interrupt
WW .100Y.C M.TW must Wread . 1 M
W UDR in order
.Tfrom W . 100the RXC O M
Flag,
W O will occur W
once the interrupt O routine terminates.W .C
W
W O W C O
WW 19.7.4
W .CO .TW Error FlagsWW 00Y
.C .TW WW .100Y. .TW
.1 00Y ReceiverM . 1 M W O M
W O
WWReceiver
W .COthree.Error WW Error.10(FE), 0Y.CData M .TW (DOR) and Parity
WW .100Y.C M.TW Error (PE).
The USART
. 1 0 0Yhas M TW Flags: Frame OverRun
O All W
can be accessed O by reading UCSRA. W
Common for. C O
the Error Flags is that they are
W
WW .100Y.C M.TW located inWthe receive
W 0 0 Y.C together .T Wwith the frame WWfor which . 1 0 0Y M .TW
W. 1 buffer
OM they indicate the error status. Due
W W .C O W Y . C W W W W
0 Y .CO the .receive T W buffer (UDR),
W . 1 00Y M .TW to the buffering
W of
W
the
. 100 Error Flags,
O M .Tthe UCSRA must be
W
read.10 before
C O M
W O C WW read.10location. . .TW equality for the
WW .100Y.C M.TW
since reading W
W
the UDR I/O
. 1 0Y.location
0can M
changes the buffer
.TW by software 0Y Another
M
Error Flags is that they not Obe altered W
doing a write O
to the flag location. How-
W O WW 00toY.zero C W Y.C TW
WW .100Y.C M.Tever, W all flagsW must be .set 1 when
M .T Wthe UCSRA W is written
W . 1 0
for 0upward
O M .
compatibility of future
W C O W W None .C Othe Error Flags can generate W Y .C W
WW .100Y . USART
W implementations. Y of W W 00
interrupts. .T
W O M.T
W
W Flag0indicates .C
WW .100Y.C M .TW
The Frame ErrorW(FE)
.1 The 0Y the stateW of the W
M.Tis zero when the W
first stop .bit
W 100of the next O
T
M.readable frame
W O W O . C
WW .100Y.C M.TW .TW
stored in the receive buffer. FE Flag stop bit was correctly read (as one),
WW .100Y.C and .T W W . 1 00Y M
OM the FE Flag will be one when the W This O can be used for
W WW 00Y .COstop.TbitWwas incorrect W(zero). .Cflag
0Yhandling. W
WW .100Y.C detecting M .T W out-of-sync Wconditions, .1 detecting M break conditions Wand .
protocol
W 1 0
O M .T
The FE Flag
W O affected by the setting
WW of.1the
W .CO bit in W receiver .C
00YignoresM W for
WW .100Y.Cis not M .T W 0 0Y USBS
M . W
TUCSRC since Wthe
W .1 O
.Texcept
all,
W O C
W
WW .100Y.C
O
the first,
.T
stop
W
bits. For compatibility
W W 0 0
with
Y.C future devices,
.T W always
WW .100Y.
set this bit to zero when
M .Twriting
W to
UCSRA. M W. 1 OM W O
W
WW .100YThe .CO .TW WW .100Y.C M.TW WW .100Y.C M.TW
W W .C ODataM OverRun (DOR) Flag W Windicates Y .CdataO loss due to a receiverWbuffer
W W
W fullYcondition.
0 .CO .ATW Data
W Y
00OverRunMoccurs W
.T when the receive.1buffer W 0
0 is fullM (twoT
. characters), it is a W new 0
.1 character Mwaiting in
W W.1 the . C O Shift Register, andWaW
receive new start Y .C
bit
O
is detected. W If the DOR W W
Flag is set 0 Y .COwas one
there .TWor
W 00 Y . T W W . 1 0 0 M .T .1 0 M
1
W. more OM frame lost between W frameY.last COread Tfrom W O
.C read from
WW .1UDR. .Cserial W Wthe 0 always W UDR, and WW the next frame
00Y to UCSRA. M.T
W
00Y For compatibility
M .T with
W
future . 1
devices,
W
0
O M .
write this bit to zero whenW .1 writing C O
W
WW .The .COFlag .isTW W frame0received 0Y.C was W WW from 0Y.Shift Regis-
10the .TW
1 00Y DOR
M
cleared when Wthe
W .1 O M .Tsuccessfully moved
W . O M
Wter to the receive
WW .100Y.C M.TW
O buffer. WW .100Y.C M.TW WW .100Y.C M.TW
W O WWhad 0a0parity O
W O
WWthat .the Y.Cframe .in Y.C error.TW
WW The.1Parity 0 0Y.CErrorM(PE) .TW
Flag indicates
1 00next T Wthe receive W buffer
.1 M
W received.
when C O If parity check is not enabled W W theYPE .C bitM
O will always be read zero. W WFor compatibil-
Y .CO .TW
W Y . W W bit to.1zero 00 when M .T W W 0 0
W ity with
W .100future devices, O M.T always set thisW W C O writing to UCSRA. ForWmore W.1 details OM
.Csee
W W“Parity Bit
00 Y . C
Calculation” .T W
on page 153 W and “Parity 1 0 0 Y .
Checker” Mon .T W
page 160. W . 1 0 0 Y
M .TW
. 1 M W . O W O
19.7.5 Parity Checker
W W. 1
.C OM
Y W
WThe Parity
W
0
.10Checker .T when the high USART
is active
OM (odd or even) is selected W.1 Parity .C
mode
O M (UPM1) bit is set.W W.1of parity
Type
Y
M
.CO .T
W .C W W Y W W 0 0
check
W to
W
be
.100
Y
performed
O M .T W .100by
Wincoming
the UPM0 .T bit.
OM and compares the
When enabled,
W
the parity
W.1 with .COM
checker calculates .C the parity of the data bits W in Y .C frames W W result 0 Y
WW bit.1from 00Ythe serial W
M.Tframe. The result W
W 00 is stored
.1check M.Tin the receive buffer W .10
the parityW O of the
W .C O W together
Wreceived Y.C .TWbits. The Parity W Error.1(PE) 00Y Flag can W
M.Tthen be read by software to
W
withW the
W .100data and O Mstop W C O
checkW if Wthe frame0had
0 Y
.Ca parity.Terror. W WW .100Y. M .TW
W . 1 O M W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 PE bit O is M
.1 OM from the receive buffer had a parity error
W WThe Y .C set if the next character
W W WW that can be
0 Y .Cread TW
W when. 1 00receivedM and.T the parity checkingWwas . 0
1 enabled O Mat .that point (UPM1 = 1). This bit is valid
W
W
WW until.1the 0Y .CO buffer
receive .TW(UDR) is read. WW .100Y.C M.TW
.T 0 M W O
OM WW 00Y.CO .TW WW .100Y.C M.TW
0 0 Y.C .T W W . 1 M
W.1 Y19.7.6 M Disabling the Receiver W O
.CO .TW WW 00Y.CO .TW WWof the 0 Y.C W
. 1 0 0 M
W In contrast
W . 1 to the
O
Transmitter,
M disabling W .1 0Receiver O M.T
will be immediate. Data from ongoing
W .CO .TW C W .C
00Y
W
Wreceptions 1 0Y.therefore
0will M .TbeWlost. WhenWdisabled . 00Y the RXEN
1(i.e., M .TW is set to zero) the Receiver will
W . 1 O M W . O W W .C O
W Y.C W
no longer
WW when
override
Y
0the .C the normal function
TisWdisabled. Remaining
W of the RxD port
00Yin the M
pin. The
.TW receiver buffer FIFO will be
1 0 0 .T flushed . 1 0 M
receiver . W . 1data O buffer will be lost
W W. .C OM WW 00Y.CO .TW W W 0 Y.C .T W
W 00 Y W W .1 0
W.119.7.7 M.T
OFlushing W W.1 Y.COM W WW 00Y.CO .TW
M
W Y . C W the Receive W Buffer
00 .T W 1
W
W .100 O M.T The receiver W W.1bufferY.FIFO C OMwill be flushed whenWthe W.Receiver Y .C O M
is disabled, W i.e., the buffer will be
WW .100Y . C T W W of its.1contents. 0 0 . W
T data will beWlost. If the 1 0
0 buffer has .Tbe
. emptied M
Unread . M
W W .C OM W W Y .C O
W W W W
0 Y .CO .TWflushed during normal
to
Y W operation, W due to
.10 0
for instance
M.Tan error condition, read the
.1 0 UDR I/O M location until the RXC Flag is
W
W .100 O M.T W C O W W .C O
WW .100Y.C M.TW
cleared. The
WW following 100
.
Ycode example
M .TW shows how W to flush.1the 00YreceiveM .TW
buffer.
W . O W C O
W
WW .100Y.C M.TW Assembly
O
WW Code Example 00Y
.C(1) .TW WW .100Y. M .TW
W . 1 O M W O
W
WW .100Y.C M.TW
O
WW .100Y.C M.TW
USART_Flush: WW .100Y.C M.TW
W W .C O
W
sbis UCSRA,
WW RXC00Y.CO .TW W WW 00Y.CO .TW
Y W
W 00
W.1 Y.COM W in r16,
.T ret
W
W W
. 1 00 M .T W UDR .100
W O M .T W
W .100 O M.T
W O WW .100Y .C
rjmp USART_Flush
M.T
W
W O W O
W O C Code Example W WW .100Y.C M.TW
(1)
.C
WW .100Y.C M.TW W . 100Y M .TW
W W .C O void USART_Flush(
W WWvoid00) Y.CO .TW W WW 00Y.CO .TW
W 00 Y .T W .1 M
W.1 Y.COM { W W W.1 Y.COM W WW 00Y.CO .TW
W W 0 .T W
W 00
W.1 Y.COM while
.T unsigned char dummy; 0
W.1 )Y.dummy C OM= UDR; W W.1 Y.COM W
W W
W W
. 1 00 M .TW
( UCSRA W & (1<<RXC)
W . 100 O M .T W
W .100 O M.T
W O WW .100Y. C
WW .100Y.C M.TW .TW
}
WW .100Y.C M.TW W O M
W O
W
WW .100Y.C M.TW
Note: O 1. See “About CodeWExamples”
W 00Y on.Cpage 6. TW
. WW .100Y.C M.TW
.1 M
W W .C O
Y W
19.8 Asynchronous W 00
W.1 Data OM
.T
Reception W.1 Y.COM W W W.1 Y.COM W
.C W W 00
W W
. 1 0Y USART
0The M .T W
includes a clock W recovery
W . 10and0 a data
O M .T
recovery unit for handling W .1asynchronous O M.Tdata
W O W is used .C W .C
Y baud.T W
WW .1reception. 0 0Y.C The M .Tclock
W recovery Wlogic . 1 00Yfor synchronizing
M .TW the internally W
W .100
generated
O M rate
W O C
WW .ples
W clockYto .Cthe O incoming asynchronous
.TW WW .1bit, Y.C at the
serial frames
00thereby
RxD pin. The data
.TW the noise WW recovery 0Y. logic M
10of
sam-W
.T
1 00 and lowM pass filters each incoming W O M
improving immunity
W . the
.C O
receiver.
W O C W W
WW The Y.C
00asynchronous .TW WW .10range
reception operational 0Y. depends M .TW on the accuracy W of the 0Y
.10internal M.T
baud
.1 M W O W C O
W
WW rate.1clock, .Cthe O rate of the incoming W
.TW W frames,.1and .C
00Ythe frame W in numberWofWbits. .100Y.
.Tsize .TW
00Y M W O M W O M
WW Clock
W
0 Y.C
O
19.8.1 Asynchronous 1 0 Recovery
.CO .TW
W W.clock Y .C OM
W
W
Winternal Y .Cto O
W W WW Figure 0 0 Y
The recovery logic synchronizes W 0
clock the
M. T
incoming serial frames. 19-5 M
W
W .100the sampling O M.T process of the start W .10
.C O W W.1is 16Ytimes .CO .TW
illustrates
W Y .C W W W bit of
0
an
0 Y incoming frame.
.T W The sample
W rate
1 0 0
Wthe baud
0
.10rate for Normal T
M. mode, and 8 times the .1baud rateOfor M Double Speed mode. W .
The horizon- OM
W .C O W W .C W W Y .C W
W W
tal arrows . 1 0Y
0illustrate the
M TW
.synchronization Wvariation
W . 10due0Y to theMsampling
O
.T W
process. Note W .100larger OM.T
the
W O
Y.C using.T WWmode.1(U2X .C .TW Samples WWdenoted Y.C
WWvariation
time
. 1 00when M
theWdouble speed 00Y = 1) ofMoperation. W . 100zero OM.T
are samples W done when O the RxD line is idle W Wno communication
(i.e., .CO .TW activity). WW .100Y.C
WW .100Y.C M.TW W . 1 00Y M W
O W O
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-5. 1 M
W WFigure .C OMStart Bit Sampling WW. Y .CO .TW
W 00 Y .T W W 0 0
W.1 RxDY.COM W W.1 Y.COM W
W W
.TW 100
W .100 M.T
IDLE START BIT 0
W . M .T
M W O W C O
. 1 00Y M W O W O M
W O Sample W6 7 080Y9.C 10 11 .T12W 13 14 15 16 1 2 3
Y.C W WW (U2X.1=00)0Y.C0 0M.1TW2 3 4 W 5
W. 1 0 0
O M .T
W .C O W W.1 Y.COM W
Y.C W W
W (U2X Sample 0Y W W 4 .100 5 .T 7
W .100 O M.T W .=11)0 0 OM1 .T 2 3
W W .C O6M 8 1 2
W .C W W Y .C W W 0 0 Y .T W
.100
Y
M.T
W 00 .T W.1 Y.COM W
WW .100Y W W the clock .100 recovery .T detects aW 00 .T
W O M.T When
W C O Mlogic high (idle)
W W.1 to low . C OM transition on the RxD line, the
(start)
WW .100Y.C M.TW start Wbit Wdetection
1
.
00Ysequence M .TisWinitiated. Let Wsample.110denote 0 Y the first
M .TWzero-sample as shown in
O the figure. W .
The clock.C O
recovery logic then uses W W 8, 9,.C O
W
WW .100Y.C M.TW WW .160for 0YDoubleMSpeed .TW mode (indicated W samples . 1 00Y
and 10 forW
M .T
Normal mode, and sam-
W W . CO
W
ples 4, 5, and
W W Y .C O
W W WW 00Y.CO .TW inside boxes on the
with sample numbers
W 00 Y .T figure),Wto decide 0
0if a valid start .T
bit is received. If two or.more 1 of these Mthree samples have logical
W.1 Y.COM W high levelsW(the W.1majority Y .C OM the start bit is rejected
wins), W WW as0a0Y .COspike.Tand
noise W the receiver starts
W W 0 .T W .1 start bitOisMdetected, the clock recov-
W .1 00 M .T looking for the Wnext. 10high to O M
low-transition. If however, aW valid C
W O W .C WW Y. .TW
WW .100Y.C M.TW ery logicW is synchronized . 1 00Y andM .TW
the data recovery can W . 100 The O
begin. M
synchronization process is
W . Wrepeated for Y W W 0 0 . T
W
W .100
Y
O M.T
Weach start
W .100bit. OM.T W W.1 Y.COM W
W .C W W 0Y .C W W 00 .T
W 00Y
19.8.2 .1Asynchronous M.T Data RecoveryWW.10
W
O M.T W.1 Y.COM W
W O . C W
WW .100Y.C M.TWhen W the receiver W clock .
Y
10is0 synchronized M .TWto the startW bit, theWdata .100recovery O Mcan.T begin. The data
O W O .C
W
WW .100Y.C Mrecovery WWa state Y.C that.Thas W 16 statesW forWeach 1 Y .TW and 8 states
.TW unit uses W . 100
machine
O M W . bit00in normal O Mmode
W O for each bit in Double W Speed00mode. Y.C Figure 19-6 shows the WW sampling0ofYthe .C data .bits TWand the par-
WW .100Y.C M ity
W
.Tbit. Each of the
Wsamples . 1 is given a M .TW that is equal
number to W
the . 0 of the M
1state O recovery unit.
W W Y .C O
W W WW 00Y.CO .TW W W 00 Y.C .T W
W 00 M.T 19-6. Sampling .1 OM Bit .1 M
W W.1 Y.COFigure W WW of Data0and Y .CParity W W WW 00Y.CO .TW
W 00 .T W 0 .T .1 M
W W
W
W .100 O M.RxD T W
W .100 OM
.T BIT n
W W.1 Y.COM W
C W .C W
WW .100Y. M.T
W W .100
Y
M.T
W
W .100 OM
.T
W O W C O W .C W
WW .100Y.C (U2X Sample .0)TW WW .100Y. M .TW W Y
.11500 16 1 OM.T
O M 3W4 6 O W .C
W
WW .100Y.C M.TW WW .100Y .TW
= 1 2 5 7 8 9 10 11 12 13 14
WW .100Y.C Sample M .TW W O M
W O W 3 Y.C4 O W 8 00Y.1C
WW .100Y.C(U2X = 1)M.TW 1 WW 2
1 00 M
5 W
.T 6 W 7
.1 M .TW
W . O W O
W
WW .100Y.C M.TW
O
W .CO of.Tthe W W O
Y.Cbit is taken Wby doing aW WW 00Y.CO .TW
WW .The 0 Y
decision W logic level W of the 0
received 0 .T majority 1
W.voting of theM logic
10
Wvalue . C
M
Othree W W.1of theYreceived .C OM bit. The center samples
W W 0 Y .CO .TW
W to the samples
.TW the sample
in the center 0 W are
.10
emphasized
W 00Yfigure by
.1the Mhaving
W
W .10inside .T
OM The majority voting W is.C OMas
W Won
. C O number
W Y .C boxes.
W W W process Y
0 done
.TW
W follows: Y W
00 If two orMall.Tthree samples haveW W .
high 0
10 levels, O .T
theMreceived bit is registered .to 0
1 be a logic M1.
.
W or Y1 O W W .C O
all.Cthree samples WW .C
0Yreceived TW Wto 00Y 0. ThisM.TW
WWIf two 1 0 0 M .T W have low levels,1the
. 0 M .
bit is registered be a.1logic
W O
W W. voting
majority Y .C Oprocess
W acts as a low W filterYfor
Wpass 0 .CO the incoming W signal W onW the RxD00pin. Y .CThe .TW
W recovery 00process isMthen W
.T repeated until a complete . 1 0 frameM .T . 1 stop bit. M
. 1 W O W O
WW .100Y.C M.TW
is received. Including the first
WWthat0the
WNote 0 CO
Y.receiver T Wuses the first WW 0 0Y .C .TW
.
only stop bit
. 1 of a frame. M
W W. 1
. C OM
Y W .1start bit OM
W
Figure 19-7
W .100shows O the .T
Msampling of the stop bitWand
W
.1 the earliest
.C OM possible beginningW ofW the
Y.C
.C Y W W 100
of W
Wthe next.1frame. 00Y M .T W W
W .1 00
O M .T W . O M.T
W O W .C
Y
O W O W
W
W O W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-7. OMStop Bit Sampling and .1 M
BitOSampling
W WFigure Y .C W W WW Next Start.C
0 0 Y .TW
W . 100 M .T W . 1 O M
W O C
.T W WW .10RxD 0Y.C M.TW WW .100Y.STOP 1M (A)
.TW (B)
O M W O W W . C O (C)
Y .C W W W 0 Y .C .T W W 0 0 Y . T W
00 .T 10
W.Sample OM .1 M
W.1 Y.COM W W Y .C W W WW 00Y.CO .TW
00
W.1 Y.COM W
.T W
W .1=00)0
(U2X .T
OM 1 2 3 4 5 W 6
W7 .1 8 Y 9 10 M
.CO .TW
0/1 0/1 0/1
W W 0 Y . C T W W 0 0
0 . .1
.100 M.T W.=11) Y.COM1 W 2
Sample
WW 5 Y.C
O6M 0/1
WW 00Y.CO .TW W W (U2X
10 0 .T
3
W 4
. 1 0 0 M .TW
W. 1 OM W . O M W O
W O WWmajority CO is done
Y.voting WW 0Y CO
for. the other W in the frame. If the stop
WW .100Y.C M.TW TheW same
. 1 0 0 M .T W to the stop Wbit as done
W . 1 0
O M .Tbits
O W to haveOa logic 0 value, the Frame .CFlag will
W
WW .100Y.C M.TW
bit is registered
WW .100Y.C M.TW WW Error . 1 00Y
(FE)
M .TW
be set.
W O W O indicating the start bit
WWof a .new
W .CO can .come
WW .100Y.C M.TW TW right after the last of
A new high to low transition frame
WW .100Y.C M.TW the bits 1 00Y M
used for majority voting. For Normal Speed W mode, the O
first low level sample can be at
W W Y .C O
W W WW 0 Y .CO .TW W W 0 0 Y.C .T W
W .1 00 M.T point marked (A) . in
1 0Figure 19-7.
M For Double Speed mode
W . 1 the first OlowM level must be delayed to
W CO W W . C O W Y .C W
WW .100Y. W (B). (C) marks W a stop Y of full length.
bit W The early Wstart bit.1detection 00 .T
influences the operational
W O M.T range of the receiver. W .100 O M.T W W .C OM
WW .100Y. C Y W
W .100 O M.T
W O .C
WW Asynchronous .CO .TW W 00Y
.C .TW WW .100Y .TW
W19.8.3
. 1 00Y M
Operational WRange . 1
W of the O M W O M
W O
WW .C onW Y.C between .TW
WW .100Y.C M.TW .TisW
The operational range
. 1 00Y receiver M
dependent W the mismatch
W . 100 O M
the received bit
O rate and the internally W generated O
baud rate. If the Transmitter is sending .C frames at too fast or too
W
WW .100Y.C Mslow .TWbit rates, or Wthe W .C
00Y generated .TW WW .100Y M .TWa similar (see
W . 1
internally O M baud rate of the receiver
W does not
O have
W
WW .100Y.C M
O Table 19-2) base frequency,
.TW WW .100the Y.Creceiver.Twill W not be able WW to synchronize .1 0 0Y.Cthe M .TW to the start
frames
W O M W O
W
WW .100Y.C M.TW
O bit.
W OThe following equations W O
Y.Cto calculate of W
W CO rateTand
0Y.data
WW .100Y.C M.TW WWcan .be 1 0 used
0 M . T W the ratio W the incoming
. 1 0 M . W internal
W O W O
WW .100Y.C M.TW
W receiver baud rate.
O
W W .C O
W 00 Y .T W ( D + 1 )S .1 M
W.1 Y.COM W W W.1 R slow Y .C =OM -------------------------------------------
W ⋅ WW 00Y.CO .TW
W S – 1 + D S + S W
W
W .100 O M.T
W
W .100 OM
.T F
W W.1 Y.COM W
C W .C
WW .100Y. W W Y
.10R0fast = O ( D.T+W 2 )S W 00 .T
W O M.T W C
M
----------------------------------- W W.1 Y.COM W
WW .100Y.C M.TW WW .100Y ( D +M1.)S . TW + SM W .100 M.T
W O W O W W .C O
WW .1D00Y.C M.T W WW .100Y.C M.TW W .100
Y
M.T
W
Sum of character sizeW and parity O
size (D = 5 to 10 bit) W C O
W
WW .100Y.C M.TW
O
W O
WS O Samples per bit. S =W16 Wfor Normal .CO Speed mode and S = 8W for
00Y
.C W
WW .100Y.C M .TW Speed mode.
Double W . 1 00Y M .TW W
W .1 O M.T
W O C
W
WW SF .100Y.C First
O
W
.Tsample WW for 0Y.C voting.
0majority .TW WW .100Y. M.TW
M number used . 1 M S = 8 for Normal WSpeed and O
W O
WW mode.
W .CO .TW F
WW .100Y.C M.TW
WW .100Y.C SFM = .4TforW Double Speed . 1 00Y M
W W .C O
Y W 0
W SM .100 Middle
W
.Tsample number used for
O=M5 for Double Speed W W.1 Y.COM W
0majority voting. SM = 9 for Normal Speed
W W.1 and Y
M
.CO .TW
W Y M.CS W W mode.
00 .T W 0 0
W
W
Rslow .C
Yis the ratio.TofWthe slowestW W
incoming data rate that .can be accepted Win relation 100to the OM.T
W
W .100 receiver O Mbaud rate. R is the W .10of0the fastest O MT W W.can beY.C
Y.C WW .100Y
ratio . C incoming data rate that
WW .100accepted M in
W
.Trelation to
fast
the receiver baud rate. M .TW W
W . 100 OM.T
W O W O W .C
Y
O W O W
W
W O W O
W O W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 19-2 O
WTable C andM Table 19-3 list the W W.1 receiver
maximum .CO baud
M rate error that can be tolerated. Note
W W 0 0 Y . .T W W . 1 0 0 Y
M .TW
W W.1 Y.COM W
that Normal Speed mode has higher
W
toleration
W
0
of
Y
baud
.CO .TW
rate variations.
W W 0 W .10
O M.T Table
W .1019-2. O M.T
Recommended Maximum W W Receiver CO Rate
.Baud
M Error for Normal Speed Mode
Y .C W W W 0 Y .C T W W 0 0 Y .TW
0 0 .T . 1 0 (U2X M . = 0) . 1 M
W.1 Y.COM W WW 00DY.CO .TW W WW 00Y.CO .TW
W
0 0
W.1 Y.COM W
.T
#W
.1
.C OM Rslow (%) RfastW W.1 MaxYTotal .C
M
OError
W
Recommended Max Receiver
W W (Data+Parity
00Y
Bit)
.TW W (%)
100
(%) .T Error (%)
. 1 00 M .T W . 1 O M W . O M
WW 00Y.CO .TW WW .1500Y.C M.T93.20 W WW .10+6.67/-6.8
106.67 0Y.C M.TW ± 3.0
W. 1 OM W 6 O 105.79W W .C O
WW .100Y.C M.TW .TW
94.12 +5.79/-5.88 ± 2.5
WW .100Y.C M.TW W .1 00Y M
W O W7 O 94.81 105.11 WW +5.11/-5.19 .CO .TW
WW .100Y.C M.TW
± 2.0
WW .100Y.C M.TW W . 1 00Y M
W O W 8 O 95.36 104.58 W +4.58/-4.54 W .C O ± 2.0
WW .100Y.C M.TW WW .100Y.C M.TW W . 1 00Y M .TW
9W O 95.81 W O
O WW .100Y.C M.TW
W 104.14 +4.14/-4.19 ± 1.5
W O
W W Y .C O
W W
10 W
W 0 Y .CO96.17 .TW 103.78 WW +3.78/-3.83
0 0 Y.C .TW
± 1.5
W 00 .T . 1 0 M . 1 O M
W.1 OM W O W
WW .100Y.C M.TW
W O WWRate00Error O
W O Table 19-3.WWRecommended Y.C Maximum Y.Cfor Double WSpeed Mode
WW .100Y.C M.TW . 0
1= 1)0 M .T W ReceiverWBaud
W . 1 O M.T
O (U2X W O .C
W
D W O Max Total W
Error O
Recommended Max Receiver
W O
WW .100Y.C M.TW# (Data+Parity WW Bit) 0
R 0 Y.(%)C R.T W (%) W(%) W
. 1 0 0Y.C MError .TW(%)
.1 slow M fast
WW 00Y.CO ±.T2.5
W W Y.C O
W 5 W WW 094.12 0 Y .CO 105.66 .T W W
+5.66/-5.88 W
W . 1 00 M .T W . 1 O M W .1 O M
W
WW .100Y.C M.TW 6
O
WW .94.92 00Y
.C 104.92 .TW WW .100Y.C M
+4.92/-5.08 .TW
± 2.0
1 M W O
W O
WW 95.52
W .CO .TW +4.35/-4.48 WW .100Y.C ±M .TW
WW .100Y.C M.TW 7 . 1 00Y 104.35 M W O
1.5
W O C
W
WW .100Y.C M.TW 8
O
WW 96.00 .C
00Y 103.90 .TW +3.90/-4.00 WW .100Y. ± 1.5 M .TW
W .1 O M W O
W O 103.53 TW+3.53/-3.61WW .C
WW .100Y.C M.TW9 WW 96.39.100Y.C M . .1 00Y ± 1.5M.TW
W O
W W Y.C O 10
W W
W
W96.70 0 Y .CO .TW
103.23 +3.23/-3.30 WW 0 0 Y.C ± 1.0 .TW
W . 1 00 M .T . 1 0 M W .1 O M
WW 00Y.C O .C
W
WW .100YThe .COrecommendations
.T W Wthe . W
Tbaud WW . 1 00Y TW
M.assump-
M of
W .1
maximum receiver
O M rate error was Wmade under
C O the
W O W error. .
WW .100tion Y.Cthat the.Treceiver W and W W
transmitter
. 1 0Y.C divides
0equally M .TW the maximum Wtotal . 100
Y
M .TW
M W O W O
W O
WW for.1the Y.C W Y.C W
WW .10There 0Y.C areMtwo .TW possible sources 00receivers M .TW rate error.WThe receiver’s
baud
W .100 system O M .T
clock
W instability O C tempera-
W (XTAL)
WW .1ture .CO will always W have some WW minor 0Y.C over .the
TWsupply voltage WWrange 0Y.the
0and TW
M.for
00Yrange.M .
When
T using a crystal toW . 1 0
generate the O M
system clock, this is rarely W .
a
1
problem, C O
but a
W .COthe system W Y .C W W
Wresonators Y.
0tolerance. TW
WW .resonator 0 Y . T W W 0 0 .T . 1 0 M .
10
Wsecond .C
clock
OM for the error is more
may differ
W.1 Y.COM W
more
Wcontrollable.
than 2% depending of the
Wcan W
0
O
Y.C do an
The
W
W Y source W W 0 0 The T
baud
. rate generatorW not
1 0 always M.T
W .1 00 M .T W . 1 O M W .
C O
W exact division .CO of the system frequency
WW to get the.C baud rate W wanted. In this WW case an UBRR Y. value.TW
WW that.1gives 00Y an acceptable .TW low error . 1 00Yif possible. M .T . 100 M
W W . C O M can
W
be
W used
Y .C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
Y. C W Y W W 00 .T
19.9 Multi-processor WW Communication
.100 M.T
WMode W .100 M.T W.1 Y.COM W
W O W . C O W
W
WSetting the Y .C
Multi-processor
0of0 incoming .TW
CommunicationWW .mode 00Y (MPCM)
1USART M .TbitWin UCSRAWenables 0
.1a0filtering M.T
function .1 O M frames received by W
the O
Receiver. Frames that do W not .
contain C O
W WW 00Y.C .TbeWignored and Wnot W .C
00Ythe receive W
.Tbuffer. WW .100Y .TW
1
address .information will
M put
W .1into O M This effectively W reducesCOM
W .CO .frames Wbe handled .C TW in a system WWwith multiple Y.
WW
the number 0of0Y
. 1 incoming
M TW that has Wto .1 00Y by the M .CPU, W . 100 O M.T
W O W .C O W Y .C
MCUs
WW .has
that communicate
00Y
.C via W the same serial
.Tdifferently when WWbus. .The YTransmitter
100 of a system M .TW is unaffectedWby the MPCM
.100
setting, but 1 to be used
O M it is W a part O utilizing the W
Multi-processor
W
WW .100mode.
Communication Y.C .TW WW .100Y.C M.TW WW
W O M W O
W O W O
W O W
WW .100Y.C M.TW 8155B–AVR–07/09
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T ATmega32A
M WW 00Y.CO .TW
0 Y .CO .TW W
0
WIf.1the receiver OMis set up to receive frames .1 M 8 data bits, then the first stop bit indi-
W Y .C W W WW that 0 Y .CO 5 to
contain
.T W
W cates
. 1 00if the frame M .Tcontains data or address . 0
1 information. M If the receiver is set up for frames with
W CO thenTthe W .C O
.T W WW nine.1data 0 0Y.bits, . W ninth bit (RXB8) WW is.1used 00Yfor identifying W
M.T address and data frames. When
M W O M W C O
. the frame
.CO .TW WWthe frame .C bit (the
type
00Ybit is zero
first
W stop or the WW ninth bit) is
100
Yone, .TW contains an address. When the
. 1 00Y M frameW . 1type O M .Tthe frame is a data W
frame.. O M
W
0 Y.C
O
1 0 .CO slave
W. .C OM
W
The W
W Multi-processor Y .CO Communication W
mode
W WW enables several
0 0 Y .
MCUs to receive data from a
TtoWfind out which MCU has been
00 Y .T Wmaster 1
MCU.0 0 This is .
done T by first decoding an . 1
address frame M
.1 M W. OM WW addressed, O
WW 00Y.CO .TW WW .10If0Y
addressed. a.Cparticular .T W
Slave MCU W has been . 1 0 0Y.C Mit.Twill W receive the following data
W. 1 OM W M
O the other slave MCUs W O
frames
WW as .normal, 0Y.Cwhile WW will Y.C the .received
00ignore W frames until another
WW .100Y.C M.TW address frame 1 0 is received. M .TW
W .1 O MT
W O
W
WW .100Y.C M.TW
O
W W19.9.1Y.CO Using MPCM
W 00 .T W .1 M
W.1 Y.COM W For an MCU Wto.1act as C
a OM MCU, it can useW
master aW 9-bit character .CO frame format (UCSZ = 7). The
W W 00 .T W W
1 0 Y .
0 be setMwhen W
.T an address frame W . 1 0 0 Y
M .TW
.1 M ninth bit (TXB8) . must W (TXB8 = 1)O or cleared when a data frame
W W Y . CO
W W W W
0 Y .CO The .T W W W 0 0 Y .C .T Wuse a 9-bit character
W 0 0 .T (TXB = 0) is being .1 0
transmitted. M slave MCUs must in . 1
this case be Mset to
W W.1 Y.COM W frame format. WW 00Y.CO .TW W WW 00Y.CO .TW
W 00 .T W .1 M
W.1 Y.COM WThe followingWprocedure W.1 Yshould . C OM
W WW 0 Y .CO .TW Communication
W be used to exchange W data in
0 Multi-processor
W
W .100 O M.T mode:
W
W .100 OM
.T
W W.1 Y.COM W
C W .C W
WW .100Y. W
M.T 1. All slave MCUs
W .100
Y
M.T
W 100
W.mode
.T
OMin UCSRA is set).
W O W C O W .C
WW .100Y.C M.TW WW .100Y are in .
Multi-processor
M .TW
Communication W . 100
(MPCM
Y
M .TW
W O
W O 2. The Master W MCU W sendsYan .CO address frame, and all slaves
WW as.1normal.
receive
00Y
.Cand read .TW
this frame.
WW .100Y.C M.TW In the Slave W MCUs,.1the 00 RXC Flag M .T W
in UCSRA will be setW O M
WWreads O
W
WW .100Y.C M3.
O
.TWEach SlaveWMCU W 0 0 Y.CUDR Register
the .T W and determines WW if.1it0has 0Y.C been .TW If so,
selected.
M
. 1 O M W O
W O Y.C otherwise forWthe next 0address .C byte W
WW .100Y.C M.TW
it clears the MPCM
WW bit.1in00UCSRA, M .TW it waitsW . 1 0 Y M.T
and
keeps the MPCM setting.
W O W C O
W O W 0Y.C allM
W Y. TW
WW .100Y.C 4. M .TTheW addressed WMCU .
will1 0receive data.TW frames until
W a new W . 100 frame
address O M
is .received.
W O WW which .CO .the WWwill ignore .C
00Ythe dataMframes. .TW
WW .100Y.C MThe .TWother slaveW MCUs,
. 1 00Ystill have M TWMPCM bit set,
W .1 O
W O C
W
WW .100Y.C M
O5. When Wthe last data
.TMPCM WW frame is received
0a0newY.C by the Waddressed MCU,
.Tframe WW the .addressed 0Y.
10process
MCU
M
W
.Tsets
the bit and waits W .
for 1 O
address M from Master. WThe O then
W
WW .100Y.C repeats
O
.T Wfrom 2. WW .100Y.C M.TW WW .100Y.C M.TW
W W .C Oany M WW 0frame Y
O
.Cformats W W W W
0 Y .COthe receiver
.TW
W 00 Y
Using of
.T W
the 5- to 8-bit W character
. 1 0 M .T is possible, but impractical . 1 0 since M
. 1 M W O W O
W must O
change between using n
WWand n+1 Y.C
0character frame
TW formats. W This Y.C
Wmakes00full-duplex .TW
opera-
WW .10tion 0Y.C .T W . 1 0 M . W .1 O M
W .C OM
difficult since the transmitter and receiver
WW 00Y.CO .TW
uses the same character
W W size setting.
0 Y.C If 5- to 8-bit
W
W W
.1 00 Y
character frames
M
W
.T are used, the transmitter W
W . 1 mustObeMset to use two stop bitW (USBS 0
.1 = 1) O M Tthe
since .
W .CO .C WW .100Y. C
WW .first 00Y
stop bit is used
.TWfor indicating WWthe frame 1 00Y type.
M .TW M .TW
1 M . W O
W notY.use CORead-Modify-Write WW 00Y .COand .CBI) TW to set or W
W .C The
00Y bit. M .TW
WW Do .1 0 0 M .T W Winstructions . 1 (SBI
M
clear the.1MPCM
W O
WMPCM bit.Cshares O the same I/O location W O
.C Flag.T W C
Y. cleared.TW
WW when 0Y SBIMor.TCBI
0using W WW as.1the 00Y
TXC
M
andW this mightWaccidentally .100
be
M
W W . 1
.C O instructions.
W W Y . C O
W W W W
0 Y .CO .TW
Y W W .100 .T 0
W
W .100 O M.T W . C OM W W.1 Y.COM W
. C W Y W W 00 .T
19.10 Accessing UBRRH/ WW .1UCSRC 00Y Registers
M.T
W O W .C O W
WTheW UBRRH 00Y
C
.Register shares the same
.TW WWI/O location .
Y as the UCSRC
100 thisOI/O M .TW Register. W Therefore .100 someOM.T
.1 M W W
special W
WW .100Y.C M.TW
consideration O must be taken when accessing
WW .100Y.C M.TW
location.
WW .100Y.C M.TW
W O
19.10.1 Write Access WW
W Y .CO .TW W WW 00Y.CO .TW WW .100Y.C M.T
0 0 .1 M O
WhenWdoing W.1 a write Y . C OM of this I/O location,
access W WW the high 0 Ybit.CofOthe value W written, the W WW Reg-
USART 0 0 Y.C
W .T
W
ister Select 100
W.(URSEL)
.T
OMcontrols which one ofWthe
bit,
0
W.1two registers .C OMthat will be written. IfWURSEL W.1 is
W Y .C W W will.1be 0 Y W
0 updated.MIf.TURSEL is one, the UCSRC W
zeroW during a.1write 00 operation, M.Tthe UBRRH value W O
W O
setting W
Wwill be updated. 0 0 Y .C
.T W W W
.1 0 0Y.C M.TW
W.1 OM W O
W O W
W C O
8155B–AVR–07/09
WW .100Y. M.T
W
W O
WW .100Y.C
O
0 Y.C W
W .1 0
O M.T
WW .100Y .C W
W O M.T
.TW WW .100Y.C M.TW
M WW 00Y.CO .TW
0 Y .CO .TW W
.10 following
WThe C OM code examples showW howW.1to access M registers.
.COthe two
W W
100 Y .
M .T W W . 1 0 0 Y
M .TW
.
WAssembly Code O Example W O
WW .100Y.C M.TW
(1)
OM W :. .CO W O
0 Y.C .T W WW .10;0Y .T W WW .100Y.C M.TW
0 M to 2
Set UBRRH
W WW 00Y.CO .TW
W
0 0
W.1 Y.COM W
.T
W.1 Y.COM W
ldi r16,0x02
W W.1 Y.COM W
W
.100 M.T
W
W .100
out UBRRH,r16 .T
O M
W
W .100 OM
.T
W O C W .C
W 00 Y.C .T W WW :..100Y .
M .TW W . 1 00Y M .TW
W. 1 OM W O and the UCSZ1 bit W O
Y.C WW .100Y.C M.TW
; Set the USBS to one, and
WW .100Y.C M.TW WW ; the . 1 00remaining M .T W
W O bits to zero. W O
W
WW .100Y.C M.TW
O
0 0 Y.C
WWldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)
W . C O W W.1 Y.COM W WW 00Y.CO .TW
W Y W W out UCSRC,r16
0 0 .T W .1
W W.1 Y.COM W W
:. W WW 00Y.CO .TW
W 00 .T W 0 0 .T .1 M
W.1 Y.COM W C Code Example W W.1 (1) Y.COM W WW 00Y.CO .TW
W W
W
W .100 O M.T
W
W .100 OM
.T
W W.1 Y.COM W
C :. W . C W
WW .100Y. M.T
W W
/* Set W
Y
.100 to 2 O*/M.T
W
W .100 OM
.T
W O UBRRH
Y. C W Y .C W
WW .100Y.C M.TW WW= 0x02; . 100 M .TW W .100 M.T
O
UBRRH
W O W .C O
W
WW .100Y.C M.TW :. WW 00Y
. 1 O M W O
W O WWUSBS00and Y.C the UCSZ1 W and 0*/0Y.C .TW
WW .100Y.C M.TW /* Set Wthe . 1 M .TW bit to W one,
W . 1 O M
WW 00bits O
W O /* the remaining
WW .100Y.C M.TW UCSRC =W(1<<URSEL)|(1<<USBS)|(1<<UCSZ1); Y.C to zero. .TW
*/
WW .100Y.C M.TW
W . 1 O M W O
W
WW .100Y.C M.TW :.
O
W W .C O
W 00 Y W .1
W.1 Y.CONote: M.T 1. See “About W Code 1
W.Examples” .CO onM page 6. WW 00Y.CO .TW
M
W W W 0 Y .T W W
W 00
W.1 Y.CO
AsM .T code examples illustrate,
the
W.1 write
0
.C OM
accesses of the two registers
W W.1are relatively
Y .CO .TW
M unaffected of
W W of I/O location. W Y W W 0 0
W
W .100
the sharing
O M.T
W
W .100 OM
.T
W W.1 Y.COM W
Y.C W .C W
19.10.2 W
W
.100
Read Access M.T
W W
W .100
Y
O M.T
W
W .100 OM
.T
W O
.C a read W Y. C W Y .C W
WW .100YDoing M .TWaccess to W the UBRRH .100or the UCSRC M .TW

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O

WW .100Y.C M.TW REGISTERS

WW 00Y.CO .TW WW 00Y.CO .TW

W .C O WW 00Y.CO .TW W WW 00Y.CO

Y .C W W W 0 Y .C I .TWT H W N.TW Z C SREG

W Y.C W WW .100Y .CSP7

W O Initial Value W.1 O M0.T 0 0

W O Y.C4 WW 1 .100Y0.C M.TW

W W.1 Y.COM W W W WW 00Y.CO RESET

W.1 Y.COM W WW 00Y.CO .TW

WW .100Y.C M.TW L CLR Q CLR Q

WW .100Y.C M.TW M .TW

W O MInitial W.01 Y.C0 OM 0W W W 0.CO

W .CO .TW WW .100Y .

0 0 Y.C .T W M .TW (To Clock

W.1 Y.COM W W C O W W .C O Select Logic)

W W.1 Y.COM W InitialWValue 0 .CO 0 W 0

W W.1 Y.COM Initial Value

W.1 Y.COM W TCNTn W . C OM WW 00Y.CO .TW

M.T O W.1 OCnY.COM W

WW .100Y.C M.TW M .TW Unit O

WW .100Y.C M.TW WWasynchronous

W WW 00TCNTn Y .CO .TWclear ControlW Logic

.100 M.T W.1 Y.COM direction .1 M

WW .100Y.C M.TW WW .100Y.C M.TW

WW 00Y.CO .TW W WW 00Y.CO .TW

W W.1 1Y.COM 1W clk /1024 W 0 W WW

W O M.T W .C O W W.1 Y.COM W

WW .100Y.C M.TW WW .100Y.C M .TW W . 1 00Y M

W W.1 Y.COM W W W WW 00Y.CO .TW

WW 00Y.CO .TW WW .100Y.C M.TW

WW .100Y.C M.TW Y W W 0 . rxclk

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