FORMATTEDbha

Institute of Science & Technology, Klawad, 2010-2011
CHAPTER-1
EMBEDDED SYSTEM
1.1 INTRODUCTION
Electronic devices that incorporate a computer (usually microprocessor) within their

implementation. A computer is used in such devices primarily as a means to simplify the
system design and to provide flexibility. Often the user of the device is not even aware that a
computer is present. Theoretically, an embedded controller is a combination of a piece of
microprocessor based hardware and the suitable software to undertake a specific task.
These days designers have many choices in microprocessors/microcontrollers. Especially, in 8

bit and 32 bit, the available variety really may overwhelm even an experienced designer.
Selecting a right microprocessor may turn out as a most difficult first step and it is getting
complicated as new devices continue to pop-up very often.
In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance
of this particular family has driven many semiconductor manufacturers to develop something
new based on this particular architecture. Even after 25 years of existence, semiconductor
manufacturers still come out with some kind of device using this 8031 core.
1.2 DEFINiTION
In Embedded system only one specific application software is loaded into ROM that controls
the whole hardware system.
1.3 CLASSIFICATION OF EMBEDDED SYSTEM
• Microprocessor Based
• Micro controller Based
1.4 APPLICATIONS
• Automotive electronics
• Aircraft electronics
• Trains
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• Telecommunication
1.5 STRUCTURE
• Distributed and Non distributed

• Reactive and Transformational
• Control dominated and Data dominated
Fig. 1.1
1.6 CLASSIFICATION
• Distributed and Non distributed

• Reactive and Transformational
• Control dominated and Data dominated
1.7 DISTRIBUTED CHARACTERISTICS

• Components may be physically distributed
• Communicating processes on multiple processors
• Dedicated hw connected through communicating channels
• Often economical
• 4 x 8 Bit controllers may be cheaper than a 32 bit microcontroller
• Multiple processors can perform multiple time critical tasks.
• Better logistics – devices being controlled may be physically distributed.
1.8 MEMORY
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Memory is an important part of embedded systems. The cost and performance of an embedded
system heavily depends on the kind of memory devices it utilizes. In this section we will
discuss about “Memory Classification”, “Memory Technologies” and “Memory Management”.
1.8.1 MEMORY CLASSIFICATION
Memory Devices can be classified based on following characteristics
(a) Accessibility
(b) Persitance of Storage
(c) Storage Density & Cost
(d) Storage Media
(f) Power Consumption
1.8.2 ACCESSIBILITY
Memory devices can provide Random Access, Serial Access or Block Access. In a Random
Access memory, each word in memory can be directly accessed by specifying the address of
this memory word. RAM, SDRAMs, and NOR Flash are examples of Random Access
Memories. In a Serial Access Memory, all the previous words (previous to the word being
accessed) need to be accessed, before accessing a desired word. I2C PROM and SPI PROM are
examples of Serial Access Memories. In Block Access Memories, entire memory is sub-
divided in to small blocks (generally of the order of a KByte) of memory. Each block can be
randomly accessed, and each word in a given block can be serially accessed. Hard Disks and
NAND flash employ a similar mechanism. Word access time for a “RAM” (Random Access
Memory) is independent of the word location. This is desirable of high speed application
making frequent access to the memory.
1.8.3 PERSISTENCE OF STORAGE
Memory devices can provide Volatile storage or a non-Volatile stroage. In a non-Volatile
storage, the memory contents are preserved even after power shut down. Whereas a Volatile
memory looses its contents, after power shut down. Non-Volatile storage is needed for storing
application code, and re-usable data. However volatile memory can be used for all temporary
storages. RAM, SDRAM are examples of volatile memory. Hard Disks, Flash (NOR &
NAND) Memories, SD-MMC, and ROM are example of non-Volatile storages.
1.8.4 STORAGE CELLS
Memory Device may employ electronic (in terms of transistors or electron states) storage,
magnetic storage or optical storage. RAM, SDRAM are examples of electronic storage. Hard
Disks are example of magnetic storage. CDs (Compact Discs) are example of optical storage.
Old Computers also employed magnetic storage (magnetic storages are still common in some
consumer electronics products).
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1.8.5 STORAGE DENSITY & COST

Storage Density (number of bits which can be stored per unit area) is generally a good meausre
of cost. Dense memories (like SDRAM) are much cheaper than their counterparts (like
SRAM).
1.8.6 POWER CONSUMPTION
Low Power Consumption is highly desirable in Battery Powered Embedded Systems. Such
systems generally employ memory devices which can operate at low (and ultra low) Voltage
levels. Mobile SDRAMs are example of low power memories.
1.9 MEMORY TECHNOLOGIES

1.9.1 RAM
RAM stands for Random Access Memory. RAMs are simplest and most common form of data
storage. RAMs are volatile. The figure below shows typical Data, Address and Control Signals
on a RAM. The number of words which can be stored in a RAM are proportional (exponential
of two) to the number of address buses available. This severely restricts the storage capacity of
RAMs (A 32 GB RAM will require 36 Address lines) because designing circuit boards with
more signal lines directly adds to the complexity and cost.
1.9.2 DPRAM (Dual Port RAM)
DPRAM are static RAMs with two I/O ports. These two ports access the same memory
locations - hence DPRAMs are generally used to implement Shared Memories in Dual
Processor Systems. The operations performed on a single port are identical to any RAM. There
are some common problems associated with usage of DPRAM:
(a) Possible of data corruption when both ports are trying to access the same memory location -
Most DPRAM devices provide interlocked memory accesses to avoid this problem.
(b) Data Coherency when Cache scheme is being used by the processor accessing DPRAM -
This happens because any data modifications (in the DPRAM) by one processor are unknown
to the Cache controller of other processor. In order to avoid such issues, Shared memories are
not mapped to the Cacheable space. In case processor's cache configuration is not flexible
enough (to define the shared memory space as non-cacheable), the cache needs to be flushed
before performing any reads from this memory space.
1.9.3 Dynamic RAM
Dynamic RAMs use a different storage technique for data storage. A Static RAM has four
transistors per memory cell, whereas Dynamic RAMs have only one transistor per memory
cell. The DRAMs use capactive storage. Since the capacitor can loose charge, these memories
need to be refreshed periodically. This makes DRAMs more complex (because we need to have
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extra control) and power consuming. However, DRAMs have a very high storage density (as
compared to static RAMs) and are much cheaper in cost. DRAMs are generally accessed in
terms of rows, columns and pages which significantly reduces the number of address buses
(another advantage over RAM). Generally you need a SDRAM controller (which manages
different SDRAM commands and Address translation) to access a SDRAM. Most of the
modern processors come with an on-chip SDRAM controller.
1.9.4 EPROMs
EPROMs (Electrically Programmable writable Read Only Memory) are non-volatile memories.
Contents of ROM can be randomly accessed - but generally the word RAM is used to refer to
only the volatile random access memories. The operating voltage for writing in to the EPROMs
is much higher than the operating voltage. Hence you can write in to a PROM in-circuit (which
signifies ROM). You need special programming stations (which have write mechanism) to
write in to the EPROMs.
1.9.5 OTP-EPROMs
OTP-EPROMs are One Time Programmable. Contents of these memories can not be changed,
once written. UV-EPROM are UV erasable EPROMs. Exposure of memory cells, to UV light
erases the exisiting contents of these memories and these can be re-programmed after that.
EEPROM are Eletricaly Erasable EPROMs. These can be erased electrically (generally on the
same programming station where you write in to them). The write cycles (number of times you
can erase and re-write) for UV-EPROM and EEPROM is fairly limited. Erasable PROMs use
either FLOTOX (Floating gate Tunnel Oxide) or FAMOS (Floating gate Avalanche MOS)
technology.
1.9.6 FLASH (NOR)
Flash (or NOR-Flash to be more accurate) are quite similar to EEPROM in usage and can be
considered in the class of EEPROM (since it is electically erasable). However there are a few
differences. Firstly, the flash devices are in-circuit programmable. Secondly, these are much
cheaper as compared to the conventional EEPROMs. These days (NOR) Flash are widely used
for storing the boot code.
1.9.7 NAND FLASH
These memories are denser and cheaper than NOR Flash. However these memories are block
accessible, and can not be used for code execution. These devices are mostly used for Data
Storage (since it is cheaper than NOR flash). However some systems use them for storing the
boot codes (these can be used with external hardware or with built-in NAND boot logic in the
processor).
1.9.8 SD-MMC
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SD-MMC cards provide a cheaper mean of mass storage. These memory cards can provide
storage capacity of the order of GBytes. These cards are very compact and can be used with
portable systems. Most modern hand-held devices requiring mass storage (e.g. still and video
cameras) use Memory cards for storage.
1.9.9 HARD DISC

Hard Discs are Optical Memory devices. These devices are bulky and they require another
bulky hardware (disk reader) for reading these memories. These memories are generally used
for Mass storage. Hence they memories do not exist in smaller and portable systems. However
these memories are being used in embedded systems which require bulk storage without any
size constraint.
1.10 ADVANTAGES
Embedded Systems have the following advantages:
- They are highly reliable
- They are very economical
- They are small in size
1.11 DISADVANTAGES
Embedded Systems have the following disadvantages:
- They have very few resources at their disposal
- They are very expensive to repair
- They do not have any user interface (more often than not)
1.12. SOFTWARE ARCHITECTURES USED IN EMBEDDED SYSTEM

• Simple Control Loop
• Interrupt Controlled System
• Cooperative Multitasking
• Preemptive Multitasking
• Microkernels and Exokernels
• Monolithic Kernels
• Exotic Custom Operating Systems
• Additional Software Component
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EXAMPLES
Fig.1.2
Hunter Programmable Digital Thermostat
Fig.1.3
Vendo VMAX 720 vending machine
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Fig.1.4
Garmin StreetPilot GPS
Fig. 1.5
Robot
1.13 COMPONENTS OF EMBEDDED SYSTEM
• CPU (Central Processing Unit)-Microprocessors are general purpose CPUs meant for
general-purpose computer applications .Microcontroller consists of CPU, Memory and
set of I/O controllers within a single chip.
• MEMORY-RAM, ROM, Flash Memory, EPROM, EEPROM
• I/O CONTROLLERS-It Provide interface to external devices such as
Keyboard,display, printer, Digital Input, Digital Output, Analog Input, Analog Output
etc.
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CHAPTER-2
8051 MICROCONTLLORER
2.1 MICROCONTROLLER
A microcontroller is a computer-on-a-chip optimized to control devices. It is a type of
microprocessor emphasizing self-sufficiency and cost-effectiveness, in contrast to a general-
purpose microprocessor, the kind used in a PC. A typical microcontroller contains all the
memory and I/O interfaces needed, whereas a general purpose microprocessor requires
additional chips to provide these necessary functions.
Microcontrollers are a component in many kinds of electronic equipment (see embedded

system). They are the vast majority of all processor chips sold. Over 50% are "simple"
controllers, and another 20% are more specialized digital signal processors (DSPs). A typical
home in the Western world is likely to have only one or two general-purpose microprocessors
but somewhere between one and two dozen microcontrollers. They can be found in almost any
electrical device, washing machines, microwave ovens, telephones etc.
2.1.1 DESCRIPTION
Most microcontrollers today are based on the von Neumann architecture, which clearly defined
the four basic components required for an embedded system. These include a CPU core,
memory for the program (ROM or Flash memory), memory for data (RAM), one or more
timers (customisable ones and watchdog timers), as well as I/O lines to communicate with
external peripherals and complementary resources — all this in a single integrated circuit. A
microcontroller differs from a general-purpose CPU chip because the former generally is quite
easy to make into a working computer, with a minimum of external support chips. The idea is
that the microcontroller will be placed in the device to control, hooked up to power and any
information it needs, and that's that.
A traditional microprocessor won't allow you to do this. It requires all of these tasks to be
handled by other chips. For example, some number of RAM memory chips must be added. The
amount of memory provided is more flexible in the traditional approach, but at least a few
external memory chips must be provided, and additionally requires that many connections must
be made to pass the data back and forth to them.
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For instance, a typical microcontroller will have a built in clock generator and a small amount
of RAM and ROM (or EPROM or EEPROM), meaning that to make it work, all that is needed
is some control software and a timing crystal. Microcontrollers will also usually have a variety
of input/output devices, such as analog-to-digital converters, timers, UARTs or specialised
serial communications interfaces like I²C, Serial Peripheral Interface and Controller Area
Network. Often these integrated devices can be controlled by specialised processor instructions.
Some modern microcontrollers include a built-in high-level programming language; BASIC is

quite common for this.
Microcontrollers trade away speed and flexibility to gain ease of equipment design and low
cost. There's only so much room on the chip to include functionality, so for every I/O device or
memory increase the microcontroller includes, some other circuitry has to be removed. Finally,
it must be mentioned that some microcontroller architectures are available from many different
vendors in so many varieties that they could rightly belong to a category of their own. Chief
among these are the 8051 and Z80 derivatives.
ATMEL
• Atmel AT91 series (ARM THUMB architecture)
• AT90 series – AVR (Atmel Norway design)
• Atmel AT89 series (Intel 8051/MCS51 architecture)
• MARC4
CYPRESS MICROSYSTEMS
• CY8C2xxxx (PSoC)
HOLTEK
• HT8
INTEL
• 8-bit
• 8XC42
• MCS48
• MCS51
• 8xC251
16-BIT
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• MCS96
• MXS296
• 32-bit
• i960
MICROCHIP
• 12-bit instruction PIC
• PIC16F84
MOTOROLA
• 8-bit
• 68HC05 (CPU05)
• 68HC08 (CPU08)
• 68HC11 (CPU11)
• 16-bit
• 68HC12 (CPU12)
• 68HC16 (CPU16)
• Motorola DSP56800 (DSPcontroller)
• 32-bit
• Motorola 683XX (CPU32)
• MPC500
• MPC 860 (PowerQUICC)
• MPC 8240/8250 (PowerQUICC II)
• MPC 8540/8555/8560 (PowerQUICC III)
NATIONAL SEMICONDUCTORS
• COP8
• CR16
NEC
• 78K
PARALLAX, INC.
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• BASIC Stamp
PHILIPS SEMICONDUCTORS
• LPC2000
• LPC900
• LPC700
RENESAS TECH. CORP.
(Renesas is a joint venture of Hitachi and Mitsubishi.)
• H8
STMICROELECTRONICS
• ST 62
• ST 7
TEXAS INSTRUMENTS
• TMS370
• MSP430
WESTERN DESIGN CENTER
• 8-bit
• W65C02-based µCs
• 16-bit
• W65816-based µCs
UBICOM
• SX-28
• Ubicom's SX-28 is an 8 bit, 28 pin microcontroller which has unusually high speed,
large memory resources, and a high degree of flexibility. Some users have referred to it
as the PIC in steroids. While Ubison has a limited variety of microcontrollers to choose
from, the high speed and additional resources allow the programmer to create 'virtual
devices' as required. Refer to Parallax's Web site for information as they are the main
distributor
ZILOG
• Z8
• Z86E02
2.1.2 BLOCK DIAGRAM
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Fig. 2.1.
Block Diagram of 8051
2.2 MEMORY TYPES
The 8051 has three very general types of memory. To effectively program the 8051 it is
necessary to have a basic understanding of these memory types.
The memory types are illustrated in the following graphic. They are: On-Chip Memory,
External Code Memory, and External RAM.
On-Chip Memory refers to any memory (Code, RAM, or other) that physically exists on the
microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly.
External Code Memory is code (or program) memory that resides off-chip. This is often in the
form of an external EPROM.
External RAM is RAM memory that resides off-chip. This is often in the form of standard
static RAM or flash RAM.
2.2 CODE MEMORY
Code memory is the memory that holds the actual 8051 program that is to be run. This memory
is limited to 64K and comes in many shapes and sizes: Code memory may be found on-chip,
either burned into the microcontroller as ROM or EPROM. Code may also be stored
completely off-chip in an external ROM or, more commonly, an external EPROM. Flash RAM
is also another popular method of storing a program. Various combinations of these memory
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types may also be used--that is to say, it is possible to have 4K of code memory on-chip and
64k of code memory off-chip in an EPROM.
When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or 16k. This
varies depending on the version of the chip that is being used. Each version offers specific
capabilities and one of the distinguishing factors from chip to chip is how much ROM/EPROM
space the chip has.
2.3 EXTERNAL RAM
As an obvious opposite of Internal RAM, the 8051 also supports what is called External RAM.
As the name suggests, External RAM is any random access memory which is found off-chip.
Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For
example, to increment an Internal RAM location by 1 requires only 1 instruction and 1
instruction cycle. To increment a 1-byte value stored in External RAM requires 4 instructions
and 7 instruction cOn-Chip Memory
2.3.1 On-Chip Memory
The 8051 includes a certain amount of on-chip memory. On-chip memory is really one of two
types: Internal RAM and Special Function Register (SFR) memory. The layout of the 80
51internal memory is presented in the following memory map:
r! HYUIUIKP;
Fig. 2.2
Memory Map
As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal
RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most
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flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so
when the 8051 is reset this memory is cleared.
The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes
(00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use
register banks 1, 2, or 3. These alternative register banks are located in internal RAM in
addresses 08h through 1Fh. We'll discuss "register banks" more in a later chapter. For now it is
sufficient to know that they "live" and are part of internal RAM.
Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very
shortly, but for now just keep in mind that bit memory actually resides in internal RAM, from
addresses 20h through 2Fh.
The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by
user variables that need to be accessed frequently or at high-speed. This area is also utilized by
the microcontroller as a storage area for the operating stack. This fact severely limits the 8051s
stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes--
and usually it is less since this 80 bytes has to be shared between the stack and user variables.
2.4 REGISTERS BANK

The 8051 uses 8 "R" registers which are used in many of its instructions. These "R" registers
are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are
generally used to assist in manipulating values and moving data from one memory location to
another. For example, to add the value of R4 to the Accumulator, we would execute the
following instruction:
ADD A,R4
Thus if the Accumulator (A) contained the value 6 and R4 contained the value 3, the
Accumulator would contain the value 9 after this instruction was executed.
However, as the memory map shows, the "R" Register R4 is really part of Internal RAM.
Specifically, R4 is address 04h. This can be see in the bright green section of the memory map.
Thus the above instruction accomplishes the same thing as the following operation:
ADD A,04h
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This instruction adds the value found in Internal RAM address 04h to the value of the
Accumulator, leaving the result in the Accumulator. Since R4 is really Internal RAM 04h, the
above instruction effectively accomplished the same thing.
But watch out! As the memory map shows, the 8051 has four distinct register banks. When the
8051 is first booted up, register bank 0 (addresses 00h through 07h) is used by default.
However, your program may instruct the 8051 to use one of the alternate register banks; i.e.,
register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address
04h. For example, if your program instructs the 8051 to use register bank 3, "R" register R4
will now be synonomous with Internal RAM address 1Ch.
The concept of register banks adds a great level of flexibility to the 8051, especially when
dealing with interrupts (we'll talk about interrupts later). However, always remember that the
register banks really reside in the first 32 bytes of Internal RAM.
2.5 BIT MEMORY

The 8051, being a communications- oriented microcontroller, gives the user the ability to
access a number of bit variables. These variables may be either 1 or 0.
There are 128 bit variables available to the user, numberd 00h through 7Fh. The user may make
use of these variables with commands such as SETB and CLR. For example, to set bit number
24 (hex) to 1 you would execute the instruction:
SETB 24h
It is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit
variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you write the
value FFh to Internal RAM address 20h youve effectively set bits 00h through 07h. That is to
say that:
MOV 20h,#0FFh
is equivalent to:
SETB 00h
SETB 01h
SETB 02h
SETB 03h
SETB 04h
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SETB 05h
SETB 06h
SETB 07h
As illustrated above, bit memory isnt really a new type of memory. Its really just a subset of
Internal RAM. But since the 8051 provides special instructions to access these 16 bytes of
memory on a bit by bit basis it is useful to think of it as a separate type of memory. However,
always keep in mind that it is just a subset of Internal RAM--and that operations performed on
Internal RAM can change the values of the bit variables.
Bit variables 00h through 7Fh are for user-defined functions in their programs. However, bit
variables 80h and above are actually used to access certain SFRs on a bit-by-bit basis. For
example, if output lines P0.0 through P0.7 are all clear (0) and you want to turn on the P0.0
output line you may either execute:
MOV P0,#01h
or you may execute:
SETB 80h
Both these instructions accomplish the same thing. However, using the SETB command will
turn on the P0.0 line without effecting the status of any of the other P0 output lines. The MOV
command effectively turns off all the other output lines which, in some cases, may not be
acceptable.
2.6 SPECIAL FUNCTION REGISTERS (SFR) MEMORY

Special Function Registers (SFRs) are areas of memory that control specific functionality of the
8051 processor. For example, four SFRs permit access to the 8051s 32 input/output lines.
Another SFR allows a program to read or write to the 8051s serial port. Other SFRs allow the
user to set the serial baud rate, control and access timers, and configure the 8051s interrupt
system.
When programming, SFRs have the illusion of being Internal Memory. For example, if you
want to write the value “1” to Internal RAM location 50 hex you would execute the instruction:
MOV 50h,#01h
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Similarly, if you want to write the value "1" to the 8051s serial port you would write this value
to the SBUF SFR, which has an SFR address of 99 Hex. Thus, to write the value "1" to the
serial port you would execute the instruction:
MOV 99h,#01h
As you can see, it appears that the SFR is part of Internal Memory. This is not the case. When
using this method of memory access (its called direct address), any instruction that has an
address of 00h through 7Fh refers to an Internal RAM memory address; any instruction with an
address of 80h through FFh refers to an SFR control register.
2.7 BASIC REGISTERS

• ACCUMALATOR
The Accumulator, as its name suggests, is used as a general register to accumulate the results of
a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile
register the 8051 has due to the shear number of instructions that make use of the accumulator.
More than half of the 8051s 255 instructions manipulate or use the accumulator in some way.
For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the
Accumulator. Once you have a value in the Accumulator you may continue processing the
value or you may store it in another register or in memory.
• THE “R” REGISTERS
The "R" registers are a set of eight registers that are named R0, R1, etc. up to and including R7.
These registers are used as auxillary registers in many operations. To continue with the above
example, perhaps you are adding 10 and 20. The original number 10 may be stored in the
Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition
you would execute the command:
ADD A,R4
After executing this instruction the Accumulator will contain the value 30.
You may think of the "R" registers as very important auxillary, or "helper", registers. The
Accumulator alone would not be very useful if it were not for these "R" registers.
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The “R” registers are also used to temporarily store values. For example, lets say you want to
add the values in R1 and R2 together and then subtract the values of R3 and R4. One way to do
this would be:
MOV A,R3 ;Move the value of R3 into the accumulator
ADD A,R4 ;Add the value of R4
MOV R5,A ;Store the resulting value temporarily in R5
MOV A,R1 ;Move the value of R1 into the accumulator
ADD A,R2 ;Add the value of R2
SUBB A,R5 ;Subtract the value of R5 (which now contains R3 + R4)
As you can see, we used R5 to temporarily hold the sum of R3 and R4. Of course, this isnt the
most efficient way to calculate (R1+R2) - (R3 +R4) but it does illustrate the use of the "R"
registers as a way to store values temporarily.
• “B” REGISTERS
The “B” register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-
byte) value.
The “B” register is only used by two 8051 instructions: MUL AB and DIV AB. Thus, if you
want to quickly and easily multiply or divide A by another number, you may store the other
number in “B” and make use of these two instructions.
Aside from the MUL and DIV instructions, the “B” register is often used as yet another
temporary storage register much like a ninth "R" register.
• DATA POINTER(DPTR)
The Data Pointer (DPTR) is the 8051s only user-accessable 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all 1-byte values.
DPTR, as the name suggests, is used to point to data. It is used by a number of commands
which allow the 8051 to access external memory. When the 8051 accesses external memory it
will access external memory at the address indicated by DPTR.
While DPTR is most often used to point to data in external memory, many programmers often
take advantge of the fact that its the only true 16-bit register available. It is often used to store
2-byte values which have nothing to do with memory locations.
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• PROGRAM COUNTER (PC)
The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction
to execute is found in memory. When the 8051 is initialized PC always starts at 0000h and is
incremented each time an instruction is executed. It is important to note that PC isnt always
incremented by one. Since some instructions require 2 or 3 bytes the PC will be incremented by
2 or 3 in these cases.
The Program Counter is special in that there is no way to directly modify its value. That is to
say, you cant do something like PC=2430h. On the other hand, if you execute LJMP 2430h
youve effectively accomplished the same thing.
• STACK POINTER
The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value.
The Stack Pointer is used to indicate where the next value to be removed from the stack should
be taken from.
When you push a value onto the stack, the 8051 first increments the value of SP and then stores
the value at the resulting memory location.
When you pop a value off the stack, the 8051 returns the value from the memory location
indicated by SP, and then decrements the value of SP.
This order of operation is important. When the 8051 is initialized SP will be initialized to 07h.
If you immediately push a value onto the stack, the value will be stored in Internal RAM
address 08h. This makes sense taking into account what was mentioned two paragraphs above:
First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed
value at that memory address (08h).
SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET,
and RETI. It is also used intrinsically whenever an interrupt is triggered (more on interrupts
later. Dont worry about them for now!).
2.8 SPECIAL FUNCTION REGISTERS

SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal
RAM is from address 00h through 7Fh whereas SFR registers exist in the address range of 80h
through FFh.
20
Each SFR has an address (80h through FFh) and a name. The following chart provides a
graphical presentation of the 8051's SFRs, their names, and their address
Fig.2.3
Special Function Register
2.8.1 SFR Types

As mentioned in the chart itself, the SFRs that have a blue background are SFRs related to the
I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines. Whether a given I/O
line is high or low and the value read from the line are controlled by the SFRs in green.
The SFRs with yellow backgrouns are SFRs which in some way control the operation or the
configuration of some aspect of the 8051. For example, TCON controls the timers, SCON
controls the serial port.
The remaining SFRs, with green backgrounds, are "other SFRs." These SFRs can be thought of
as auxillary SFRs in the sense that they don't directly configure the 8051 but obviously the
8051 cannot operate without them. For example, once the serial port has been configured using
SCON, the program may read or write to the serial port using the SBUF register
21
2.8.2 PIN DISCRIPTION
Fig. 2.4
Pin Description of 8051
• VCC
Pin 40.Provides supply voltage to the pin,+ 5V.
• GND:
Pin 20.
• XTAL1 and XTAL2:
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can
be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven as shown in Figure below.
22
Note: C1, C2 = 30 pF  1 0 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators

GND
• Port 0:
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order address/data bus during accesses
to external program and data memory. In this mode P0 has internal pull-ups. Port 0 also
receives the code bytes during Flash programming, and outputs the code bytes during program
verification. External pull-ups are required during program verification.
• Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pullups.Port 3 also receives some
control signals for Flash programming and verification.
• Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to external
data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong
internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit
addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2
also receives the high-order address bits and some control signals during Flash programming
and verification.
• Port 3:
23
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of
various special features of the AT89C51 as listed below:
Table 1
AT89C51
ALE:
Address Latch Enable output pulse for latching the low byte of the address during accesses to
external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may
be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped
during each access to external Data Memory. If desired, ALE operation can be disabled by
setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or
MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has
no effect if the microcontroller is in external execution mode.
• PSEN:
Program Store Enable is the read strobe to external program memory. When the AT89C51 is
executing code from external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
• EA/VPP:
External Access Enable must be strapped to GND in order to enable the device to fetch code
from external program memory locations starting at 0000H up to FFFFH. Note, however, that
if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to
VCC for internal program execution.
24
• SFR Registers:
Special Function Registers can be seen as a sort of control panel for managing and monitoring
the microcontroller. Every register and each of the belonging bits has its name, specified
address in RAM and strictly defined role (e.g. controlling the timer, interrupt, serial connection,
etc). Although there are 128 available memory slots for allocating SFR registers, the basic core
shared by 8051 MCUs has but 22 registers. The rest has been left open intentionally to allow
future upgrades while retaining the compatibility with earlier models. This fact makes possible
to use programs developed for obsolete models long ago.
Table No.2
Special Function Registers
• COUNTERS AND TIMERS
MCU clock employs quartz crystal. As this frequency is highly stable and accurate, it is ideal
for time measuring (similar oscillators can be found in watches). To determine the amount of
time past between two occurrences, all you need to do is count the generated impulses. This is
where the timer takes part; properly programmed, value of timer register will increase or
decrease with every MCU clock impulse. Since one instruction takes 12 oscillator cycles to
complete, the math is easy. For example, if quartz oscillator works at 12 MHz, timer register
will increase/decrease every microsecond (million times per second). 8051 has two 16-bit
timers/counters marked as T0, T1.
• TMOD - Timer Mode:
25
This register sets mode for timers T0 and T1. As shown in the image below, lower 4 bits (bit 0 -
bit 3) are associated with T0, while the higher 4 bits (bit4 - bit7) are associated with T1.
Fig. 2.5
Timer Mode:
Table 3
Timer Mode
Bit Bit Name Purpose Timer
7 GATE1 1 Timer works only if INT1 (P3.3) is set T1

0 Timer works regardless of INT1 (P3.3)
6 C/T1 1 Timer counts impulses on T1 (P3.5) T1

0 Timer counts impulses of internal oscillator
5 T1M1 Timer mode T1
3 GATE0 1 Timer works only if INT0 (P3.2) is set T0

0 Timer works regardless of INT0 (P3.2)
2 C/T0 1 Timer counts impulses on T0 (P3.4) T0

0 Timer counts impulses of internal oscillator
Four bits from the previous table determine the operating mode of timers T0 and T1. There are
4 of these modes, and each will be covered in details.
26
Table 4
Timer Mode
T0M1 T0M0 Mode Description
0 0 0 13-bit Timer
0 1 1 16-bit Timer
1 0 2 8-bit auto-reload
1 1 3 Split mode
2.9 Interrupt Priorities

It cannot be predicted with absolute certainty when will interrupt request take place. If multiple
interrupts are enabled, it's quite possible to have interrupt requests during execution of another
interrupt routine. In such cases, controller needs to resolve whether to proceed with the current
interrupt routine, or to enter a new one, based on a priority check. Our microcontroller can
differentiate between three priority levels:
1. Reset. If there is a request for reset, all processes are halted and the controller behaves
as if the power had just been turned on.
2. Priority 1 interrupts. Can be interrupted only by reset.
3. Priority 2 interrupts. Can be interrupted by any of above.
2.9.1 IP (INTERRUPT PRIORITY)
Fig. 2.6
Interrupt Priority
SFR register IP determines the priority of existing interrupt sources (Same rule applies to all
bits : logical state of 1 assigns higher priority to the appropriate interrupt):
Table 4
27
Bit Purpose
PT2 Timer T2 interrupt priority
PS Serial port interrupt priority
PX1 External interrupt INT1 priority
PX0 External interrupt INT0 priority
If two interrupt requests collide, the one with higher priority has precedence in execution. If
both interrupts are of same priority, the one with the later request has to hold one and let the
controller handle the first one.
2.9.2 EXECUTION OF INTERRUPT
Upon receiving an interrupt request, following scenario takes place:
1. Current instruction is executed first.

2. Address of the instruction that would be executed next if there was no interrupt request
is put away to stack.
3. Depending on the interrupt in question, program counter will take value of one of
possible 6 vectors (addresses) according to the table below.
Table 5
Interrupt source Vector (address in hex)
IE0 3h
TF0 Bh
IE1 13h
TF1 1Bh
RI, TI, SPIF 23h
TF2, EXF2 2Bh
28
Table
These addresses should hold the appropriate subroutines for handling the interrupts. In
practice, instead of actual routines, they only point to the location of appropriate routines in
the code.
4. Upon accomplishing the interrupt routine, address of the next instruction to be executed
is retrieved from the stack, and the program proceeds from the location where it was
interrupted.
2.10 ADDRESSING MODES
There are four addressing modes in 8051:
MOV destination, source: The data stored in Source is COPIED to the Destination and the
original data of destination gets lost.
2.10.1 IMMEDIATE ADDRESSING MODE

Instructions using #
• MOV A,#n
• MOV Rr,#n
2.10.2 REGISTER ADDRESSING MODE
Registers A and R0 to R7
• MOV A,Rr
• MOV Rr,A
2.10.3 DIRECT ADDRESSING MODE
All 128 bytes (00h to 7Fh) of RAM and SFRs(80 to FFh) may be accessed directly.
• MOV A,ADD
• MOV ADD,A
• MOV Rr,ADD
• MOV ADD,#n
• MOV ADD1,ADD2
2.10.4 INDIRECT ADDRESSING MODE
Registers R0 or R1 used as data pointers (00h to 7Fh)
29
@ symbol is used
• MOV @Rp,#n
• MOV @Rp,ADD
• MOV @Rp,A
• MOV ADD,@Rp
• MOV A,@Rp
2.10.5 EXTERNAL DATA MOVES
• R0,R1,DPTR can be used to hold the address of the data byte in external RAM
• R0,R1 can access memory from 00h to 0FFh
• DPTR can access memory from 0000h to 0FFFFh
• MOVX command is used
• All external data moves must involve the register A
• MOVX A,@Rp
• MOVX A,@DPTR
• MOVX @Rp,A
• MOVX @DPTR,A
2.10.6 CODE MEMORY
• Read only data moves
• Data which is permanent and of repeated use
• Indirect addressing
• Register A in conjunction with either PC or DPTR is used
• MOVC A,@A+PC
• MOVC A,@A+DPTR
2.10.7 PUSH AND POP:
Push and Pop commands are used to store are retrieve the data from SP.
• PUSH add
Increment SP;copy the data in add to the internal Ram address contained in SP
• POP add
Copy the data from the internal RAM address contained in SP to add;decrement the SP
2.10.8 DATA EXCHANGE

In this the data of Source gets copied to destination and the data of destination gets copied to
the Source.
30
• XCH A,Rr
• XCH A,add
• XCH A,@Rp
• XCHD A,@Rp
2.10.9 LOGICAL OPERATIONS
AND logic of both the operands takes place and the result is stored in the left side (A or ADD)
operand.
• ANL A,#n
• ANL A,ADD
• ANL A,Rr
• ANL A,@Rp
• ANL ADD,A
• ANL ADD,#n
OR logic of both the operands takes place and the result is stored in the left side (A or ADD)
operand.
• ORL A,#n
• ORL A,ADD
• ORL A,Rr
• ORL A,@Rp
• ORL ADD,A
• ORL ADD,#n
XOR logic of both the operands takes place and the result is stored in the left side (A or ADD)
operand.
• XRL A,#n
• XRL A,ADD
• XRL A,Rr
• XRL A,@Rp
• XRL ADD,A
• XRL ADD,#n
ROTATE INSTRUCTIONS:
• RL A
Shifts the contents of register A one place to the left. MSB becomes LSB.
• RLC A
31
Shifts the contents of register A one place to the left along with Carry.
MSB becomes Carry and Carry becomes LSB.
• RR A
Shifts the contents of register A one place to the right. LSB becomes MSB.
• RRC A
Shifts the contents of register A one place to the right along with Carry. LSB becomes
Carry and Carry becomes MSB.
• SWAP A
This instruction swaps the data of lower nibbles of register A with the higher nibbles of A.
BIT LEVEL OPERATIONS:

• ANL C,b
• ANL C,/b
• ORL C,b
• ORL C,/b
• CPL C
• CPL b
• MOV C,b
• MOV b,C
• SETB C
• SETB b
Here, C=Carry, b=Addressed bit
ARITHMETIC OPERATION
Increments or Decrements the contents of operand.
• INC A
• INC Rr
• INC add
• INC DPTR
• INC @Rp
• DEC A
• DEC Rr
• DEC add
32
• DEC @Rp
ADDITION
All addition is done with the A register as the destination of the result.
• ADD A,#n
• ADD A,Rr
• ADD A,add
• ADD A,@Rp
Flags which gets affected after Addition:C,AC, OV
ADD WITH CARRY
• ADDC A,#n
• ADDC A,Rr
• ADDC A,add
• ADDC A,@Rp
SUBSTRACTION
Always with Borrow
• SUBB A,#n
• SUBB A,Rr
• SUBB A,add
• SUBB A,@Rp
Flags which gets affected :C, AC set if Borrow required otherwise
2.11 MULTIPLICATION and DIVISION:

MUL A B:Put the lower order byte of product in A,put the high order byte in B
DIV A B:Divide A by B;put the integer part of quotient in register A and the integer part of the
remainder in B
JUMP AND CALL INSTRUCTIONS

• Jump and Call are the decision codes that alter the flow of the program by examining
the results of the action codes and changing the contents of PC.
• Jump permanently changes the contents of the PC if certain program condition exists.
• A call temporarily changes the PC to allow another part of the program to execute.
BIT JUMPS
• JC radd
33
Jump to the label if carry flag is set i.e. 1.
• JNC radd
Jump to the label if carry flag is not set i.e. 0.
• JB b,radd
Jump to the label if the addressable bit b is set i.e. 1.
• JNB b,radd
Jump to the label if carry flag is not set i.e. 0.
Where radd=Any user defined label.
BYTE JUMPS
CJNE:Compare jump not equal
Compares the contents of left hand side operand with contents of right hand sie operand and
they are not equal then jumps to the user defined label (radd). The carry flag sets to 1 if the
contents of left hand side operand are smaller then the contents of right hand side operand.
• CJNE A,add,radd
• CJNE A,#n,radd
• CJNE Rn,#n,radd
• CJNE @Rp,#n,radd
DJNZ: Decrement jump not equal
Decrements the contents of operand and jumps to the label if it is not zero.
• JNZ Rn,radd
• DJNZ add,radd
JZ:Jump if zero
• JZ radd
If the contents of register A are zero then jump to the label.
• JNZ radd
If the contents of register A are not zero then jump to the label.
Unconditional Jumps:
Do not test any bit or byte and jump is always taken.
34
• JMP @A+DPTR
• AJMP sadd
• LJMP ladd
• SJMP radd
• NOP
• RET
35
36
CHAPTER 3
OR CAD
3.1 INTRODUCTION
Or CAD is a proprietary software tool suite used primarily for electronic design automation.
The software is used mainly to create electronic prints for manufacturing of printed circuit
boards, by electronic design engineers and electronic technicians to manufacture electronic
schematics and diagrams, and for their simulation. The Or CAD product line is fully owned by
Cadence Design Systems. The latest iteration has the ability to maintain a database of available
integrated circuits. This database may be updated by the user by downloading packages from
component manufacturers, such as Analog Devices or Texas Instruments.
It is also called as CAD\CAM 2
3.2 PRODUCTS OF OR CAD
 Capture CIS
 P Spice
 Or CAD Capture CIS is a software tool used for circuit schematic capture. It is part of the Or
CAD circuit design suite.
Capture CIS is nearly identical to the similar Or CAD tool, Capture. The difference between
the two tools comes in the addition of the component information system, or CIS. The CIS
links component information, such as printed circuit board package footprint data or simulation
behavior data, with the circuit symbol in the schematic. When exported to other tools in the Or
CAD design suite, the data stored in the CIS is also transferred to the other tool. Thus, when a
design engineer exports a schematic to the circuit board layout utility, the majority of the circuit
elements have footprints linked to them. This saves time for the design engineer
 P Spice is a SPICE analog circuit and digital logic simulation software that runs on
personal computers, hence the first letter "P" in its name. It was developed by
Microseisms and is used in electronic design automation. Microseism was bought by Or
CAD which was subsequently purchased by Cadence Design Systems. The name is an
37
acronym for Personal Simulation Program with Integrated Circuit Emphasis. Today it
has evolved into an analog mixed signal simulator.
P Spice was the first version of UC Berkeley SPICE available on a PC, having been released in
January 1984 to run on the original IBM PC. This initial version ran from two 360KB floppy
disks and later included a waveform viewer and analyzer program called Probe. Subsequent
versions improved in performance and moved to DEC/VAX minicomputers, Sun workstations,
the Apple Macintosh, and the Microsoft Windows platform.
38
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Institute of Science & Technology, Klawad, 2010-2011

Electronic devices that incorporate a computer (usually microprocessor) within their

These days designers have many choices in microprocessors/microcontrollers. Especially, in 8

1.3 CLASSIFICATION OF EMBEDDED SYSTEM

• Distributed and Non distributed

• Distributed and Non distributed

1.7 DISTRIBUTED CHARACTERISTICS

1.8.5 STORAGE DENSITY & COST

1.9 MEMORY TECHNOLOGIES

1.9.9 HARD DISC

1.12. SOFTWARE ARCHITECTURES USED IN EMBEDDED SYSTEM

Microcontrollers are a component in many kinds of electronic equipment (see embedded

Some modern microcontrollers include a built-in high-level programming language; BASIC is

2.1.2 BLOCK DIAGRAM

2.4 REGISTERS BANK

2.5 BIT MEMORY

or you may execute:

2.6 SPECIAL FUNCTION REGISTERS (SFR) MEMORY

2.7 BASIC REGISTERS

• THE “R” REGISTERS

MOV A,R3 ;Move the value of R3 into the accumulator

ADD A,R4 ;Add the value of R4

MOV R5,A ;Store the resulting value temporarily in R5

MOV A,R1 ;Move the value of R1 into the accumulator

ADD A,R2 ;Add the value of R2

SUBB A,R5 ;Subtract the value of R5 (which now contains R3 + R4)

• PROGRAM COUNTER (PC)

2.8 SPECIAL FUNCTION REGISTERS

2.8.1 SFR Types

2.8.2 PIN DISCRIPTION

Pin 40.Provides supply voltage to the pin,+ 5V.

• XTAL1 and XTAL2:

Note: C1, C2 = 30 pF  1 0 pF for Crystals

= 40 pF 10 pF for Ceramic Resonators

Special Function Registers

• COUNTERS AND TIMERS

• TMOD - Timer Mode:

Bit Bit Name Purpose Timer

7 GATE1 1 Timer works only if INT1 (P3.3) is set T1

6 C/T1 1 Timer counts impulses on T1 (P3.5) T1

5 T1M1 Timer mode T1

4 T1M0 Timer mode T1

3 GATE0 1 Timer works only if INT0 (P3.2) is set T0

2 C/T0 1 Timer counts impulses on T0 (P3.4) T0

1 T0M1 Timer mode T0

0 T0M0 Timer mode T0

T0M1 T0M0 Mode Description

2.9 Interrupt Priorities

2.9.1 IP (INTERRUPT PRIORITY)

PT2 Timer T2 interrupt priority

PS Serial port interrupt priority

PT1 Timer T1 interrupt priority

PX1 External interrupt INT1 priority

PT0 Timer T0 interrupt priority

PX0 External interrupt INT0 priority

2.9.2 EXECUTION OF INTERRUPT

Upon receiving an interrupt request, following scenario takes place:

1. Current instruction is executed first.

Interrupt source Vector (address in hex)

RI, TI, SPIF 23h

TF2, EXF2 2Bh

2.10 ADDRESSING MODES

There are four addressing modes in 8051:

2.10.1 IMMEDIATE ADDRESSING MODE