Problem 1.

2-28
Figure P1.2-28 illustrates a power conversion electronic chip.

Ws = 1.5 cm
Wc = 1 cm

Wc = 1 cm

Ws = 1.5 cm

2
ha = 37.2 W/m -K
Ta = 30°C
lead ribbon
ε = 0.9
metal vias & underfill
g = 5 W thv = 1.2 mm, Dv = 0.5 mm, vd = 100 vias/cm2
chip
thc = 3.2 mm, kc = 121 W/m-K kv = 25.3 W/m-K, kuf = 2.1 W/m-K
Rc′′ = 8.2x10 − m -K/W
5 2
dielectric
spreader thd = 0.35 mm, kd = 0.85 W/m-K
hw = 458 W/m -K
2
ths = 7.5 mm, ks = 85 W/m-K
Tw = 20°C
Figure P1.2-28: Power conversion chip.

The chip is Wc = 1 cm x Wc = 1 cm in area and thc = 3.2 mm thick with conductivity kc = 121
W/m-K. Inefficiencies in the power conversion process result in the generation of thermal
energy at a rate g = 5 W. This generation is distributed throughout the chip but can be modeled
as occurring at the upper surface. The lower surface of the chip is attached to a dielectric
material with thickness thd = 0.35 mm and conductivity kd = 0.85 W/m-K. The dielectric
material is attached to a spreader block; this attachment is characterized by contact resistance Rc"
= 8.2x10-5 K-m2/W. The spreader is Ws = 1.5 cm x Ws = 1.5 cm in area and ths = 7.5 mm with
conductivity ks = 85 W/m-K. The bottom surface of the spreader is cooled by water. The water
temperature is Tw = 20°C and the heat transfer coefficient is hw = 458 W/m2-K. Above the chip
there are many metal vias used for signals that lead to traces on a ribbon lead. Each metal via is
a cylinder with diameter Dv = 0.5 mm and thickness thv = 1.2 mm. There are vd = 100 vias/cm2
and the conductivity of the via material is kv = 25.3 W/m-K. Between the vias is an underfill
material with conductivity kuf = 2.1 W/m-K. You may neglect the thermal resistance of the lead
ribbon. The top surface is cooled by convection with air, ha = 37.2 W/m2-K and Ta = 30°C. The
top surface also radiates to the air temperature. The emissivity of the surface is ε = 0.9.

This problem is clearly three-dimensional. However, it is possible to develop simple resistance

network models of the problem that can be used to obtain an upper and lower bound on the chip
temperature (i.e., the temperature at the interface between the vias and the chip where the
thermal energy generation occurs).
a.) Obtain a lower bound for the chip temperature using a resistance model. Your solution
should include a resistance network that is clearly labeled with the numerical value of each
resistance for the conditions shown in Figure P1.2-28.

The inputs are entered in EES:

$UnitSystem SI Mass Radian J K Pa

W_c=1 [cm]*convert(cm,m) "chip width"

th_c=3.2 [mm]*convert(mm,m) "chip thickness"
g_dot=5 [W] "rate of thermal energy generation"
k_c=121 [W/m-K] "thermal conductivity of chip"
W_s=1.5 [cm]*convert(cm,m) "spreader width"
th_s=7.5 [mm]*convert(mm,m) "spreader thickness"
k_s=85 [W/m-K] "spreader conductivity"
th_v=1.2 [mm]*convert(mm,m) "via thickness"
D_v=0.5 [mm]*convert(mm,m) "via diameter"
vd=100 [1/cm^2]*convert(1/cm^2,1/m^2) "via density"
k_v=25.3 [W/m-K] "via conductivity"
k_uf=2.1 [W/m-K] "underfill conductivity"
th_d=0.35 [mm]*convert(mm,m) "dielectric thickness"
k_d=0.85 [W/m-K] "dielectric conductivity"
R``_c=8.2e-5 [K-m^2/W] "dielectric to spreader contact resistance"
h_bar_a=37.2 [W/m^2-K] "air heat transfer coefficient"
e=0.9 [-] "emissivity"
h_bar_w=458 [W/m^2-K] "water heat transfer coefficient"
T_w=converttemp(C,K,20 [C]) "water temperature"
T_a=converttemp(C,K,30 [C]) "air temperature"

The isothermal model is used to obtain a lower value of each resistance and therefore a lower
value of the chip temperature. The isothermal resistance network is shown in Figure 2.

Ruf = 7.11 K/W Rconv,a,iso = 268.8 K/W

g = 5 W
Rs,iso = 0.39 K/W Rd = 4.12 K/W
qupper ,iso
Tw Tus Ta

Rconv,w,iso = 9.7 K/W Rc = 0.26 K/W

Rcontact = 0.82 K/W

Rv = 2.42 K/W Rrad,iso = 1303 K/W

Figure 2: Isothermal resistance network.

The resistance of the chip and dielectric material are computed according to:
 thc
Rc = (1)
Wc2 kc

thd
Rd = (2)
Wc2 kd

The contact resistance between the dielectric and the spreader is calculated according to:

Rc′′
Rcontact = (3)
Wc2

"Isothermal model"
R_c=th_c/(W_c^2*k_c) "chip resistance"
R_d=th_d/(W_c^2*k_d) "dielectric resistance"
R_contact=R``_c/W_c^2 "contact resistance"

The conduction resistance of the spreader and convection resistance to the water, estimated using
the isothermal model (in which the entire spreader area can be used for conduction and
convection), are:

ths
Rs ,iso = (4)
Ws2 ks

1
Rconv , w,iso = 2
(5)
W hw
s

R_s_iso=th_s/(W_s^2*k_s) "isothermal spreader resistance"

R_conv_w_iso=1/(h_bar_w*W_s^2) "isothermal water convection resistance"

The number of vias is estimated according to:

N v = Wc2 vd (6)

The area of each via is:

Dv2
Av = π (7)
4

The resistance to conduction through all of the vias is:

thv
Rv = (8)
kv N v Av

The resistance to conduction through the underfill surrounding the vias is:
 thv
Ruf = (9)
kuf (W − N v Av )
c
2

The resistance to convection from the air for the isothermal model is:

1
Rconv ,a ,iso = (10)
Wc2 ha

N_v=W_c^2*vd "number of vias"

A_v=pi*D_v^2/4 "area of each via"
R_v=th_v/(k_v*N_v*A_v) "via resistance"
R_uf=th_v/(k_uf*(W_c^2-N_v*A_v)) "resistance of underfill"
R_conv_a_iso=1/(h_bar_a*W_c^2) "isothermal air convection resistance"

The radiation resistance from the top surface depends on the temperature of the top surface, Tus,iso
in Figure 2. This temperature is guessed initially and used to compute the resistance to radiation:

1
Rrad ,iso = (11)
ε σ W (Tus ,iso + Ta ) (Tus2 ,iso + Ta2 )
c
2

T_us_iso=T_a "guess for upper surface temperature"

R_rad_iso=1/(e*sigma#*W_c^2*(T_us_iso+T_a)*(T_us_iso^2+T_a^2)) "radiation resistance"

The resistance from the chip to the water is:

Rlower ,iso = Rc + Rd + Rcontact + Rs ,iso + Rconv , w,iso (12)

The resistance from the chip to the air is:

−1 −1
⎛ 1 1 ⎞ ⎛ 1 1 ⎞
Rupper ,iso =⎜ + ⎟ +⎜ + ⎟⎟ (13)
⎜R R ⎟ ⎜R
⎝ v uf ⎠ ⎝ conv ,a ,iso Rrad ,iso ⎠

The chip temperature is computed according to:

g =
(T
c ,iso − Tw )
+
(Tc ,iso − Ta )
(14)
Rlower ,iso Rupper ,iso

R_lower_iso=R_c+R_d+R_contact+R_s_iso+R_conv_w_iso "resistance from generation to water"

R_upper_iso=(1/R_v+1/R_uf)^(-1)+(1/R_conv_a_iso+1/R_rad_iso)^(-1)"resistance from generation to air"
g_dot=(T_c_iso-T_w)/R_lower_iso+(T_c_iso-T_a)/R_upper_iso "chip temperature"
T_c_iso_C=converttemp(K,C,T_c_iso) "in C"
The problem is solved and the guess values updated (select Update Guess Values from the
Calculate menu). The guess for the upper surface temperature is commented out:

{T_us_iso=T_a} "guess for upper surface temperature"

The heat transfer rate to the air ( qupper ,iso in Figure 2) is:

qupper ,iso =
(T c ,iso − Ta )
(15)
Rupper ,iso

The upper surface temperature is computed according to:

−1
⎛ 1 1 ⎞
= Tc ,iso − qupper ,iso ⎜ +
⎜ R R ⎟⎟
Tus ,iso (16)
⎝ v uf ⎠

q_dot_upper_iso=(T_c_iso-T_a)/R_upper_iso "heat transfer to air"

T_us_iso=T_c_iso-q_dot_upper_iso*(1/R_v+1/R_uf)^(-1) "upper surface temperature"

which leads to Tus,iso = 365.4 K (92.25°C). The values of each resistance are labeled in Figure 2.

b.) Obtain an upper bound for the chip temperature using a resistance model. Your solution
should include a resistance network that is clearly labeled with the numerical value of each
resistance for the conditions shown in Figure P1.2-28.

The adiabatic model is used to obtain an upper bound on the chip temperature. The adiabatic
resistance network is shown in Figure 3.

Rrad,uf,ad = 1285 K/W

Tus,uf,ad
Ta
g = 5 W
Ruf = 7.11 K/W
Rs,ad = 0.88 K/W Rd = 4.12 K/W
Tw Tc,ad Rconv,a,uf,ad = 334.5 K/W
Ta
Rconv,w,ad = 21.8 K/W Rc = 0.26 K/W Rrad,v,ad = 5196 K/W
Tus,v,ad
Rcontact = 0.82 K/W Ta

Rv = 2.42 K/W

Rconv,a,v,ad = 1369 K/W

Ta
Figure 3: Adiabatic resistance network.
The resistance of the chip and dielectric material and the contact resistance do not change. The
resistance of the spreader and convection to the water do change because heat is not allowed to
spread in order to take advantage of the entire area of the spreader in the isothermal model.

ths
Rs ,ad = (17)
Wc2 k s

1
Rconv , w,ad = 2
(18)
W hw
c

"Adiabatic model"
R_conv_w_ad=1/(h_bar_w*W_c^2) "adiabatic water convection resistance"
R_s_ad=th_s/(W_c^2*k_s) "adiabatic spreader resistance"

In the adiabatic model, the heat is not allowed to spread as it leaves the vias; therefore, the
convection resistance from the surface above the vias and the convection resistance from the
surface above the underfill must be computed separately:

1
Rconv ,a ,v , ad = (19)
ha N v Av

1
Rconv ,a ,uf ,ad = (20)
ha (W − N v Av )
c
2

The surface temperature above the vias and underfill (Tus,v,ad and Tus,uf,ad) are assumed in order to
calculate the radiation resistances:

1
Rrad ,v , ad = (21)
ε σ N v Av (Tus ,v ,ad + Ta ) (Tus2 ,v ,ad + Ta2 )

1
Rrad ,uf ,ad = (22)
ε σ (W − N v Av ) (Tus ,uf ,ad + Ta ) (Tus2 ,uf ,ad + Ta2 )
c
2

T_us_v_ad=T_a "guess for upper surface temperature over vias"

T_us_uf_ad=T_a "guess for upper surface temperature over underfill"
R_rad_v_ad=1/(e*sigma#*N_v*A_v*(T_us_v_ad+T_a)*(T_us_v_ad^2+T_a^2))
"radiation resistance over vias"
R_rad_uf_ad=1/(e*sigma#*(W_c^2-N_v*A_v)*(T_us_uf_ad+T_a)*(T_us_uf_ad^2+T_a^2))
"radiation resistance over underfill"

The resistance from the chip to the water is:

Rlower ,ad = Rc + Rd + Rcontact + Rs ,ad + Rconv , w,ad (23)

The resistance from the chip to the air is:

−1
⎛ 1 1 ⎞
Rupper , ad =⎜ + ⎟⎟ (24)
⎜R
⎝ upper ,v Rupper ,uf ⎠

where
−1
⎛ 1 1 ⎞
Rupper ,v = Rv + ⎜ + ⎟⎟ (25)
⎜R
⎝ conv ,a ,v , ad Rrad ,v ,ad ⎠

−1
⎛ 1 1 ⎞
Rupper ,uf = Ruf + ⎜ + ⎟⎟ (26)
⎜R
⎝ conv ,a ,uf , ad Rrad ,uf , ad ⎠

The chip temperature is computed according to:

g =
(T c , ad − Tw )
+
(T c , ad − Ta )
(27)
Rlower , ad Rupper ,ad

R_lower_ad=R_c+R_d+R_contact+R_s_ad+R_conv_w_ad "resistance from generation to water"

R_upper_v=R_v+(1/R_conv_a_v_ad+1/R_rad_v_ad)^(-1) "upper resistance through vias"
R_upper_uf=R_uf+(1/R_conv_a_uf_ad+1/R_rad_uf_ad)^(-1) "upper resistance through underfill"
R_upper_ad=(1/R_upper_v+1/R_upper_uf)^(-1) "resistance from generation to air"
g_dot=(T_c_ad-T_w)/R_lower_ad+(T_c_ad-T_a)/R_upper_ad "chip temperature"
T_c_ad_C=converttemp(K,C,T_c_ad) "in C"

The problem is solved and the guess values updated (select Update Guess Values from the
Calculate menu). The guess for the upper surface temperature is commented out:

{T_us_v_ad=T_a "guess for upper surface temperature over vias"

T_us_uf_ad=T_a "guess for upper surface temperature over underfill"}

The heat transfer rates to the air through the vias ( qupper ,v ,ad in Figure 3) and through the underfill
( qupper ,uf ,ad ) are calculated:

qupper ,v ,ad =
(T c , ad − Ta )
(28)
Rupper ,v

qupper ,uf ,ad =

(T c , ad − Ta )
(29)
Rupper ,uf
The upper surface temperatures over the via (Tus,v,ad) and over the underfill (Tus,v,uf) are computed
according to:

Tus ,v , ad = Tc ,ad − qupper ,v ,ad Rv (30)

Tus ,uf ,ad = Tc ,ad − qupper ,uf ,ad Ruf (31)

q_dot_upper_v_ad=(T_c_ad-T_a)/R_upper_v "heat transfer to air through vias"

q_dot_upper_uf_ad=(T_c_ad-T_a)/R_upper_uf "heat transfer to air through underfill"
T_us_v_ad=T_c_ad-q_dot_upper_v_ad*R_v "upper surface over vias"
T_us_uf_ad=T_c_ad-q_dot_upper_uf_ad*R_uf "upper surface over underfill"

which leads to Tus,ad = 418 K (144.9°C). The values of each resistance are labeled in Figure 3.

c.) You need to reduce the chip temperature (or increase the power level of the chip). Based on
your resistance network from (a), provide two areas of research which would provide the
most benefit and two areas that are not likely to provide much benefit. For example,
"improving convection from the air to the upper surface" would be an area of research.
Clearly justify your answers.

The majority of the heat travels from the chip surface to the water; this is evident because the left
side of the resistance network in Figure 2 is much smaller than the right side. The largest
resistances in the series on the left correspond to the convection with the water and conduction
across the dielectric. Therefore, the two areas of research that would provide the most benefit
are:
• improve the convection coefficient with the water
• improve the conductivity or reduce the thickness of the dielectric

Two resistances that are not very important according to Figure 2 are the resistance to radiation
and the resistance of the chip material. Therefore, two areas of research that would provide very
little benefit are:
• increase the emissivity of the surface
• increase the conductivity of the chip material

d.) You have decided to aggressively cool the top surface using impinging jets to increase the
value of ha and want to understand the potential benefit of this approach. Plot the upper and
lower bounds on the chip temperature as a function of ha for 1 W/m2-K < ha < 1x106 W/m2-
K. Use a logarithmically scaled x-axis so that you can clearly see the various regimes of
behavior (note that if you plot linearly spaced data on a log-scale your graph will not be
adequate). You should see three regimes in your plot (i.e., the behavior of Tc will be
different in different regions of your plot). Clearly explain why these three regimes occur.

The requested plot is shown in Figure 4.

 160

140

Chip temperature (°C)

120 adiabatic model

100

80

60 isothermal model

40

20
100 101 102 103 104 105 106
2
Air-side heat transfer coefficient (W/m -K)
Figure 4: Chip temperature predicted by the adiabatic and isothermal models as a function of the air-side
heat transfer coefficient.

At low values of ha , the chip temperature is high and insensitive to ha ; this is because very little
heat is transferred to the air. At some point, the value of ha is reduced sufficiently that heat is
transferred both to the water and the air; therefore, the value of Tc is quite sensitive to ha and
reduces as ha increases. Finally, at high values of ha the chip temperature is low but is again
insensitive to ha ; this is because most of the heat is transferred to the air but the heat transfer rate
is limited by other resistances along this path (e.g., the via conduction resistance).