PLC Instructions

 Latching instructions: They are retentive output instructions.

 PLC has two types of latching instructions. They are Output Latch(OTL) & Output
Unlatch(OTU).
 OTL & OTU are always used with the same bit address. They both modify the same
bit.
 OTL sets the addressed bit to logic 1 when the rung in which it is contained becomes
true.
 After that, it remains at logic 1 regardless of whether the rung is true or false, until it
is set to logic 0 by the corresponding OTU instruction.
 Timer Instruction
It is used to activate/deactivate a PLC output. It has 3 parameters. They are\
 i) Time Base: Duration of each time interval counted by the timer.
 ii) Accumulated value(ACC): Value since the timer was last reset to zero. When true, timer
updates ACC continuously.
 iii) Preset value(PRE): Final value that the ACC must reach.

PLC has 3 types of timer instruction:

a) TON(timer-on-delay)
b) TOF(timer-off-delay)
c) RTO(retentive TON)
TON: It starts counting when rung goes from false to true. As long rung is true, ACC increases
until PRE is reached. If rung false, ACC is reset to zero regardless of whether PRE is reached or
not.
TOF: Polar opposite of TON. Activates when rung goes from true to false. When rung false, ACC
increases, when rung true, ACC=0.
RTO: Same as TON but RTO can retain its ACC even when the rung is false.

Timer instructions are in the form of 3 word elements.

Word 0: Control Word.
Word 1: PRE
Word 2: ACC
Word 0 includes 3 status bits that gives important information on the timing process. They are:
i) Timer Enable(EN) bit (Bit no. 15 of Word 0): 1 when rung is true, 0 when rung is false.
ii) Timer Timing(TT) bit (Bit no. 14 of Word 0):
For TON: TT is 1 when rung is true & ACC<PRE.
TT is 0 when rung is false or ACC=PRE.
For TOF: TT is 1 when rung is false & ACC<PRE.
TT is 0 when rung is true or ACC=PRE.
For RTO: TT is 1 when rung is true & ACC<PRE.
TT is 0 when rung is false or ACC=PRE.

iii) Done(DN) bit (Bit no. 13 of Word 0):

For TON: DN is 1 when ACC=PRE.
DN is 0 when rung is false.
For TOF: DN is 1 when rung is true.
DN is 0 when ACC=PRE.
For RTO: DN is 1 when ACC=PRE.
DN is 0 when RES(reset bit/switch) is true.
 Addressing the status bit:
EN, TT and DN bit can control the XIC and XIO switches. For this, address of the XIC/XIO must
be entered by specifying the number or identifier of the bit.
Example:
T4:0/13 or T4:0/DN
T4:0/14 or T4:0/TT
T4:0/15 or T4:0/EN
 Counter Instruction
It counts the no. of times the rung makes transitions.
PLC counter has 2 parameters: ACC(no. of transitions made by rung since last reset) and
PRE(final value that ACC must reach).
Since counter instructions are retentive, they retain their ACC when rung becomes false.
PLC has two types of counter: The Count Up(CTU) instruction and the Count Down(CTD)
instruction.
CTU: ACC increases by 1 on each false-true transition. When ACC=PRE, DN =1 after which ACC
increases until RES=1 which makes ACC=0 and DN=0.
CTD: ACC decreases by 1 on each false-true transition. When ACC<PRE, DN =0 after which
ACC decreases until RES=1 which makes ACC=0 and DN=1.
Counter has the following status bits:
CU(Count up enable): CU=1, when rung with CTU is true.
CU=0, when rung is false or RES=1.
CD(Count down enable): CD=1, when rung with CTD is true.
CD=0, when rung is false or RES=1.
DN(Done): DN =1, when ACC>=PRE.
DN=0, when ACC<PRE.
OV(Overflow): It is related to CTU.
OV=1, when ACC>32767.
OV=0, when RES=1.
UN(Underflow): It is related to CTU.
UN=1, when ACC<-32768.
UN=0, when RES=1.
XIC & XIO can be controlled by the counter status bits.
Example:
C5:0/11 or C5:0/UN
C5:0/12 or C5:0/OV
C5:0/13 or C5:0/DN
C5:0/14 or C5:0/CD
C5:0/15 or C5:0/CU
Comparison instruction: To perform comparison functions.
Comparison instructions has the following parameters:
Source A: Only address can be given as input.
Source B: Constant/address can be given as input.

There are 6 comparison instructions:\

i) Equal(EQU)
ii) Not equal(NEQ)
iii) Less than(LES)
iv) Less than or equal(LEQ)
v) Greater than(GRT)
vi) Greater than or equal(GEQ)