Int. J. Electron. Commun.

(AEÜ) 128 (2021) 153501

Contents lists available at ScienceDirect

International Journal of Electronics and Communications

journal homepage: www.elsevier.com/locate/aeue

Regular paper

A scalable high-linearity two-step DTC-assisted voltage–to-time converter

with rail-to-rail input-range for time-based circuits
Amir Hossein Miremadi, Omid Hashemipour *
Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

A R T I C L E I N F O A B S T R A C T

Keywords: This paper presents a highly digital voltage-to-time converter (VTC), which is compatible with advances in CMOS
Delay element scaling and ability of operating under low supply voltages. The proposed design utilizes coarse-fine structure
Linearity which operates at rail-to-rail input range with high linearity, as well as making it possible to increase the gain
Voltage-to-time converter
conversion and output delay range of VTC up to a desired value. The inverter-based implementation of the
Digital-to-time converter
proposed VTC makes it suitable for time-based circuits which use digital-like circuits to perform time-mode
Threshold quantization
Digital to analog converter signal processing (TMSP). The presented VTC is designed and simulated in TSMC 90-nm CMOS technology at
supply voltage of 1 V, which shows a conversion gain of 5 ns/V, and the output delay range is as high as 5000 ps.
With a 33.3 MHz sampling frequency, the VTC exhibits a signal-to-noise-and distortion ratio (SNDR) of 56 dB,
while the power consumption is 210 μW.

1. Introduction
The advancement of CMOS technology with decreasing CMOS
technology nodes for scaled nanometer devices has resulted in CMOS
circuits with the nominal supply voltages of about 1 V or less. With
shrinkage of supply voltages and short-channel effects, it becomes
increasingly difficult to realize analog signal processing functions in
mixed-signal integrated circuits in order to achieve high linearity and
high accuracy in the voltage domain. Unlike the traditional voltage
based analog circuits, digital circuits benefits from scaling such as faster
devices with less parasitic capacitance, increased digital circuits density
through the minimum device length scaling, reduction the supply volt­
ages [1,2]. Also, Staszewski et al. [3] have noted that “In a deep-
submicron CMOS process, the time-domain resolution of a digital
signal edge transition is superior to the voltage resolution of an analog
signal”. Thus, if information with continuous nature can be encoded as
an analog quantity using a time-mode variable which is defined as the
time (or phase) difference between two digital signal edges, this idea
will enable the realization of analog signal processing in time domain
using digital circuits due to the digital shape of signals as well as
bringing with it, all the flexibility and programmability of digital
computer-aided design (CAD) tools using digital design methodologies.
Therefore, Time-Mode Signal Processing (TMSP) paradigm using time-
based circuits can help reducing gap between high accuracy analog
signal processing and digital design flow via maximizing the digital
circuits, while minimizing the analog circuitry [4].
In time-based circuits, adjustable delay elements play a key role in
the implementation of basic building blocks, which can be defined by a
time-difference variable as a time interval between a digital event
occurrence with respect to a reference time or event. This time delay
may be controlled by either analog voltage/current or digital code,
which are often known as voltage/current controlled delay unit (VCDU/
CCDU) [5,6] and digitally controlled delay element (DCDE) [7,8],
respectively.
Based on the idea behind TMSP to consider time as the variable
under processing instead of conventional analog variables such as
voltage or current by using the propagation delay of most basic element
available, that is, the delay element [9], this approach causes the po­
tential for innovation in time-based circuits and leads to many new ideas
which have been widely reported in various applications, such as all
digital frequency synthesizers [10], analog to digital converters [11],
TMSP filters [12], buck converters [13], class-D amplifiers [14], Digital
RF [15], etc.
The analog and mixed-signal circuits with traditional voltage based
approach, can be related to the TMSP methodology using the block di­
agram shown in Fig. 1. Since the output information of a sensor is
typically in the form of analog voltage, a front-end voltage-to-time
Converter (VTC) is employed to convert the input signal into a time-

* Corresponding author.
E-mail addresses: a_miremadi@sbu.ac.ir (A.H. Miremadi), hashemipour@sbu.ac.ir (O. Hashemipour).

https://doi.org/10.1016/j.aeue.2020.153501
Received 26 June 2020; Accepted 13 October 2020
Available online 17 October 2020
1434-8411/© 2020 Elsevier GmbH. All rights reserved.
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

Voltage to Time Time Mode Time to Digital 10110011…

Converter Signal Processing Converter
ANALOG VOLTAGE (VTC) TIME SIGNAL (TMSP) TIME SIGNAL (TDC) DIGITAL CODE

Fig. 1. Block diagram of the analog and mixed-signal circuits via time-mode signal processing.

Voltage
Tdelay
Vin[n] H

L
Фout
Фin Фout H
VCDU
L
Фin
Time
tin tout

Fig. 2. Symbol of VCDU with timing diagram [16].

Fig. 3. Principle of VCDU operation.

mode variable, the time-mode signal is then processed by various time- 2. Literature survey
based circuits in time domain. After processing, the resulted time-mode
output signal is converted into a digital representation using the post- The voltage-to-time conversion is generally performed using a
processing Time-to-Digital Converter (TDC) [9,16]. voltage-controlled delay unit (VCDU). The VCDU takes the sampled
VTCs are one of the key building blocks necessary to realize the time- input voltage Vin[n], and a rising (or falling) edge input time event Фin,
based circuits. Since they serve as the interfacing block between analog then Фin is converted to the delayed rising (or falling) edge output time
input voltage and digital-oriented time-based circuits, an all-digital event Фout at the output, as shown in Fig. 2. Ideally, the time interval
implementation of a VTC is the ideal case, which makes it fully Tdelay[n] between the edges of the input and output is linearly propor­
compatible with TMSP approach. On the other hand, the poor linearity tional to the amplitude of Vin[n]. We can express Tdelay[n] as
operation of a VTC limits the overall linearity performance of a time-
Tdelay [n] = tout − tin = G0 Vin [n] + toffset (1)
based circuit as well as a larger and flexible output range is desired to
match its output range and the input range of a subsequent time-based
where tout and tin are arrival times for the rising (or falling) edges of the
circuit such as a time based ADC that typically realized using two
output and input, respectively. and practically G0 and toffset are defined
cascaded blocks VTC and TDC as time quantizer [17]. In this paper, we
as gain and time offset of VCDU [16].
propose a DTC-assisted VTC with two-step structure which uses only
The VCDU structure can be explained with the aid of simplified di­
switches, capacitors, and digital circuitry, applicable in newer CMOS
agram shown in Fig. 3, which consists of the ramp generation action and
processes under low supply voltages. This structure enhances the input
subsequently the threshold crossing detection operation.
range up to the rail-to-rail operation with high linearity. In addition, this
In the ramp generation circuit, a digital signal can be defined as the
VTC also offer the advantage of a tunable output range with flexible
input time event Фin that has a rising (or falling) edge transition at time
conversion gain for applications where these are critical concerns, this
tin. The input time event Фin triggers a charging (or discharging) process
can be realized through adjusting the delay of its coarse and fine stages.
of the ramping capacitor Cr with the defined current Ir. It creates the
The reminder of this paper is organized as follows. In Section 2, the
slope (S = ΔVCr/Δt) with the rate of Ir/Cr (S = Ir/Cr) in the ramp gen­
most frequently implemented topologies for voltage-to-time conversion
eration circuit and then followed by the threshold crossing detector
and basic building blocks are described. Section 3 explains the proposed
(TCD) circuit. The TCD detects the time instant at which VCr reaches the
VTC. In Section 4, the circuit implementation and operation details are
defined threshold voltage Vth and produces a rising (or falling) edge
described. Simulation results and comparison with recent works are
transition of the output time event Фout at time tout. Therefore, after the
presented in Section 5. Finally, Section 6 provides the conclusion.
edge transition of Фin occurs at the time instant of tin, the output signal

2
A.H. Miremadi and O. Hashemipour
vDD
Vin Ir(Vin)
Фin=Фramp
VCr TCD
Фout
Фreset Cr
vth
(a)
Fig. 4. Structure of variable-slope VTC. (a) Current controlled. (b) Capacitance controlled.
vDD
Ir
Фin=Фramp
Фsampling TCD
VCr
Vin
Фout
Фreset Cr
Vth
(a)
Fig. 5. Structure of (a) Constant-slope VTC. (b) PWM based VTC.
Фout has an edge transition some time later at tout. As a result, a sampled
input voltage Vin[n] can be mapped to a time-difference output variable,
Tdelay, using a VCDU. With the aforementioned operation, there are
different VCDU circuits but generally implemented based on two
methods, variable-slope and constant-slope method [18,19], as illus­
trated in Fig. 3.
The variable-slope method has been presented in [5,16,17,20,21,22]
that is realizable by varying the slope of S in a charging or discharging
process that is controlled by tuning the current source Ir or the ramping
capacitor Cr through the sampled input voltage Vin, as illustrated in
Fig. 4(a) and (b), respectively. In the rising edge of the ramping phase
when ϕin = ϕramp = 1, we have the charging process with the defined rate
Ir/Cr. The TCD will change its output Фout when the capacitor voltage of
Cr surpasses its threshold voltage Vth. At the end of each ramping phase
and during the logic-high of the reset phase where ϕreset = 1, the residual
charge of the ramping capacitor is removed for correct operation in next
cycle. Hence, the amount of the time-difference variable Tdelay is
controlled by the value of Cr/Ir(Vin) for current controlled case and is
modified to Cr(Vin)/Ir in the capacitance controlled case. CMOS inverters
are most common building blocks used for voltage-to-current-to-time
and voltage-to-capacitance-to-time transformation that generally can
be implemented using current starved and shunt capacitor structures,
respectively.
The constant-slope method proposed in [23–26] is based on defining
constant controlled slope of S (i.e., the constant rate of Ir/Cr) by deter­
mining both the constant values for the capacitor Cr and the current Ir,
on the other hand, changing the start voltage (Vst in Fig. 3) at the onset
of the ramp operation. As shown in Fig. 5(a), first, in the sampling phase,
when ϕsampling = 1, The input voltage is sampled on capacitor Cr as a start
voltage Vst for ramp operation while the current source Ir is turned off
and then in the ramping phase (i.e., ϕin = ϕramp = 1), the current source Ir
3
AEUE - International Journal of Electronics and Communications 128 (2021) 153501
vDD
Ir
Фin=Фramp
VCr TCD
vin
Фout
Фreset Cr(Vin)
vth
(b)
vDD
Ir
Фin=Фramp
VCr TCD
Фsampling Фout
Фreset Cr
Vin
(b)
is turned on and the capacitor voltage VCr increases with the constant
slope. The TCD senses the difference between VCr and its threshold
voltage Vth, and in the time instant that VCr crosses Vth, TCD produces an
edge at the output node Фout. In the reset phase where ϕreset = 1, the
residual charge of Cr is removed for correct operation in next cycle. As a
result, the input voltage Vin controls the delay by varying the start-
voltage Vst of ramp signals with the same slope Ir/Cr, resulting in a
output time-difference variable known as Tdelay which is linearly related
to Vin. Note that we need to have Vcr < Vth at the start of ϕramp for correct
operation of the TCD circuit.
Another way for the constant slope method, relies on pulse width
modulation technique so that VTC acts as pulse-width modulator (PWM)
[27,28]. Fig. 5(b) illustrates the operation of the circuit. First, it simul­
taneously operates in the sampling and reset phase, when
ϕsampling = ϕreset = 1, the input voltage Vin is sampled onto the input
capacitor of the threshold detector, and during this time the capacitor Cr
of the ramp generation circuit is reset to zero. The ramping operation
begins when ϕin = ϕramp = 1, an asynchronous comparator as TCD,
continuously compare Vin with a ramp-shape waveform that comes from
the ramp generation circuit with the constant controlled slope Ir/Cr, at
the time instant at which crossing between Vin and VCr take places, the
threshold detector will change its output Фout, and therefore, a PWM
signal is realized, where the width of each pulse is linearly proportional
to the magnitude of Vin.
There are many trade-offs involved in implementing the VTCs such
as linearity, voltage to time conversion gain, output delay range, power
consumption, speed, process-voltage-temperature (PVT) variations, and
technology scalability. For example, from a better linearity point of view
that is one of the most indicators in data converters such as VTCs, the
constant slope VTCs have a much better linearity as compared with the
variable slope VTCs because of the direct voltage to time conversion but
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

Coarse VTC Fine VTC H

CLKdly-coarse CLKdly-buf CLKin L
Delay-Line-Based Delay Constant-Slope
CLKref Buffer CLKout H
DTC VTC
CLKref L
H
Threshold DAC-based Subtractor CLKdly-coarse L
Quantizer H
VDD CLKdly-buf L
Control
Vin logic DAC H
Ti Pk-Sk-Nk Vres
CLKout L
Coars e Conv., Fine
GND Sampling Quant. DAC SUB. Conv.
Time
CLKin t1 t2 t3 t4
TVTC=t4-t1

(a) (b)
Fig. 6. (a) Simplified circuit diagram. (b) Timing diagram.

this comes at the expense of analog design effort such as current sources 3. Proposed DTC-assisted voltage-to-time converter
with a constant current along with low voltage and accurate compara­
tors that do not scale well with technology, hence, it forces to use analog The operation of the proposed DTC-assisted VTC with two-step
blocks that are less attractive in time-based circuits. On the other hand, structure can be explained with the aid of the simplified circuit dia­
the variable slope VTCs benefits from simple construction based on gram along with its timing diagram shown in Fig. 6. It is composed of a
inverter-based circuits which are more compatible with advanced coarse VTC by using a combination of threshold quantizer with delay-
nanometer CMOS technology nodes and can achieve a high speed, low line-based DTC, a fine VTC, and a DAC-based subtractor. There is an
voltage and low power operation, whereas the indirect voltage to time external input clock CLKin and one extra reference signal CLKref, which is
(additional voltage to current or voltage to capacitance) suffer from a a delayed version of CLKin.
noticeable nonlinearity that increases with larger input range and can be The operational principle of the proposed voltage-to-time converter
a major problem in some applications. includes four main phases: sampling, quantization, coarse conversion,
As mentioned earlier, a notable reported advantage of using the and fine conversion. In the sampling phase when the input clock CLKin is
constant slope VTCs in comparison with their variable slope counter­ low, the sampling capacitors of threshold quantizer sample the input
parts is the better linearity performance of voltage to time conversion voltage Vin. During the quantization phase, the time interval from the
but suffer from a limited input range, when the output resistance of the rising edge of CLKin to the rising edge of CLKref, the threshold quantizer
ramping current source shown in Fig. 5(a) is not large enough, the detects threshold crossings and will change its output only when the
current Ir produced by the current source depends on the voltage across sampled input voltage Vin crosses the specific threshold levels and then
it, therefore, VCr does not vary linearly with time, resulting in nonline­ produces a thermometer digital code Ti at its output before the arrival of
arity. To achieve high output resistance in the ramping current source, a the rising edge transition of CLKref. At the arrival of the rising edge of the
cascoded current source can be used [23,24,26]. Moreover, the voltage reference signal, where CLKref = 1, the coarse conversion operation
across a current source can be held constant by utilizing the current begins and the DTC converts its input clock CLKref into a edge transition
source with feedback opamp [29], however, with the continuous at the delayed output CLKdly-coarse, which is dependent on the value of Ti.
decrease of supply voltage in nanometer-scale CMOS technologies, the Moreover, during the coarse conversion, the digital to analog converter
performance of these circuit designs scales poorly with technology and (DAC) together with the control logic acts as the DAC-based subtractor
therefore will become increasingly difficult to implement as technology- and determines the amount of residue voltage Vres for fine conversion
scalable solutions. where the control logic is used to control DAC switching. The fine VTC is
composed of a delay buffer and a constant-slope VTC. The delay buffer
that is placed in front of the constant-slope VTC is needed to provide two
distinct tasks, firstly, after the arrival of the rising edge of at CLKdly-coarse,

Q1 Q2 Q3 Q4
VDD VDD
VDD VDD VDD VDD
CLKin CLKin CLK MP CLKin CLKin CLK MP CLKin CLKin CLKin CLKin
in in
M1 M3 M5 M7
S1 V S2 S1 V S2 S1 S2 S1 V S2
S1 VB1 S2 VB2 VS3 VB3 S4 VB4
Vin
Buf1 T1 Buf2 T2 Buf3 T3 T4
CS1 CB1 M2 CS2 CB2 CS3 CB3 M6 CS4 CB4 Buf4
M4 M8
CLKin CLKin CLKin CLKin MN CLKin MN
CLKin CLKin CLKin CLKin CLKin
TIQ1 (VTH=0.5VDD) TIQ2 (VTH=0.5VDD) TIQ3 (VTH=0.5VDD) TIQ4 (VTH=0.5VDD)

Ti

Vin
VTL1 VTL2 VTL3 VTL4
T1 T2 T3 T4

Fig. 7. Circuit diagram of the proposed threshold quantizer with voltage transfer characteristics.

4
A.H. Miremadi and O. Hashemipour
a additional delay time is intended to let the DAC prepares the correct
Vres before the arrival of the falling edge transition of CLKdly-buf. Sec­
ondly, the input buffer is served in order to increase the driving force of
the input signal CLKdly-buf of the constant-slope VTC. The DAC-based
subtractor sends Vres to the fine VTC and depending on the value of
Vres, the fine voltage to time conversion is enabled at the falling edge of
CLKdly-buf. Finally, this resulted in a delayed clock of fine VTC, denoted
by CLKout, which is a total time shifting with respect to the rising edge of
CLKin. Therefore, the voltage to time conversion process can be realized
by combination of the coarse and fine conversion. After the voltage to
time conversion process is completed, again the aforementioned cycle
can be repeated for the new sample of the input voltage Vin when the
next falling edge of CLKin arrives at the input of the VTC.
4. Circuit implementation
4.1. Threshold quantizer
The threshold quantizer circuit is realized by four single-bit quan­
tizer stages Q1-Q4 with predefined threshold levels VTL1-VTL4, respec­
tively, whose schematic is shown in Fig. 7. Each quantizer stage
compares the sampled input voltage Vin with its threshold level whereby
when the input voltage Vin is higher than the threshold level, a logic low
state is produced, otherwise, a logic high is set at the outputs of T1-T4.
Hence, depending on where Vin lies, an equivalent 5-bit thermometer
code Ti (‘T5T4T3T2T1′ ) is created, where T5 = 1. Each quantizer stage
includes a signal conditioning at the input and then quantization oper­
ation. By using the signal conditioning circuit at the front-end of the
quantizer stages Q1-Q4, we provide four threshold levels VTL1-VTL4. The
signal conditioning circuit contains the transmission gate switches S1
and S2, the sampling capacitors CSi (i = 1, …, 4), and then followed by
the bias capacitors CBi (i = 1, …, 4) along with pull-up or pull-down
switches (MP or MN). In the sampling phase when the input clock
CLKin is low, all of the S1 switches are closed and the analog input
voltage Vin is sampled by sampling capacitors CSi (i = 1, …, 4), at the
same time, the bias capacitors CBi (i = 1, 2) is pre-charged to VDD
through the pull-up switches MP that cause the value of VBi (i = 1, 2) is
set to VDD for the quantizer stages Q1-Q2 and simultaneously, the value
of VBi (i = 3, 4) through the pull-down switches MN are reset to zero at
the quantizer stages Q3-Q4. In the quantization which is defined between
the rising edges of CLKin and CLKref shown in Fig. 6(b), a time interval
related to the propagation delay of the threshold quantizer, the bias
switches of S2 are closed while other switches are open, the signal
conditioning circuit acts as a capacitive voltage divider between two
capacitors of CSi and CBi based on the predefined voltages of VSi and VBi,
where i = 1, …, 4. As a result, during the quantization phase and using
the charge conservation principle, forcing the nodes of VSi and VBi to a
final voltage, denoted by Vdiv,i, can be expressed as
CSi CBi
Vdiv,i = VSi + VBi , i = 1, ⋯, 4 (2)
CSi + CBi CSi + CBi
from (2), in order to provide the threshold levels VTL1-VTL4 of the
quantizer stages Q1-Q4, the values of CSi and CBi for the quantizer stages
Q1-Q4, are individually selected in such a way that Vdiv,i are set at 500
mV (equal to VDD/2), while the threshold levels of 200, 400, 600 and
800 mV (i.e., VTL1-VTL4) are assigned to VSi (i = 1, …, 4), respectively,
and the voltages of VBi (i = 1, …, 4) have been biased at a DC offset of
VDD or GND as previously mentioned in the sampling phase. Based on
the above-mentioned explanation, the values of CSi (i = 1, … ,4) are
chosen at 200 fF, while CBi (i = 1, 4) and CBi (i = 2, 3) are 120 fF and 40
fF, respectively.
The built-in threshold voltage VTH of inverters M1-M8, are used as a
built-in reference voltage where each inverter acts as one-bit quantizer
and is known as threshold inverter quantizer (TIQ) in the literature [30].
According to Fig. 7, at the input nodes of the inverters M1-M8, the
5
AEUE - International Journal of Electronics and Communications 128 (2021) 153501
τ0 τ1 τ2 τ3 τN
td SW1 td SW2 td SW3 td SWN td CLKdly
CLKref Switch Controller
CLKref
CLKdly
N.td
CODEDTC
Fig. 8. Simplified structure of delay-line-based DTC.
voltages Vdiv,i provided by the signal conditioning circuit, are compared
with the VTH of inverters M1-M8, having the same value of half-VDD (500
mV) according to (3) [30].
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
/
KP (W/L)P KN (W/L)N (VDD− |VTHP | ) + VTHN
VTH = √̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (3)
/
1 + KP (W/L)P KN (W/L)N
where KP,N = μP,NCOX, VTHP and VTHN are the threshold voltage of PMOS
and NMOS transistors, respectively. In reality, the transition from high
to low logic at the threshold levels VTL1-VTL4 is not a specific point
because of the gain of the used inverters M1-M8 in the transition region is
not infinite. Therefore, to sharpen the edge of the transition region, we
boost the total gain of the quantizer stages Q1-Q4 by adding the buffers
Buf1-Buf4 to the output inverters M1-M8, where each buffer consists of
four cascaded inverters with the same structure.
4.2. Delay-line-based DTC
The delay-line-based DTC is implemented based on delay-line tech­
nique, as shown in Fig. 8, which whose topology was inspired by [31],
for pulse-width modulation in a digital power amplifier. It can be real­
ized using the same delay stages td of τ0-τN associated with their input
switches of sw1-swN and a switch controller. The switch controller takes
reference clock CKref and a thermometer-format value as the input
digital code CODEDTC and then selects whether the input of each delay
stage will be injected by CKref or it will be connected to the previous
stage. As a result, the position of output of the DTC, denoted by CKdly,
remains the same but that of the input is determined depending on the
CODEDTC. When the value of thermometer CODEDTC is N, then the input
of the DTC would be set to N delay stages before the output CLKdly for
input clock injection, therefore, the output CLKdly is delayed by an
amount that is equivalent to the sum of N delay stages td.
Based on the aforementioned structure, the proposed DTC circuit
comprises a chain of the four voltage buffers td that act as the delay
chain, as shown in Fig. 9(a). The input switches along with their switch
controller are implemented using PMOS transistors MP1-MP5 and NMOS
Transistors MN1-MN5 where serve as pull-up and pull-down switches,
respectively, and the AND gates at the input of MN1-MN5 are served to
control the gates of MN1-MN5, while the gates of MP1-MP5 are directly
connected to CLKref. For the voltage buffers, four cascaded inverters of
inv1-inv4 and the load capacitance of Cdly are utilized, as shown in Fig. 9
(a), the load capacitance of Cdly is added to adjust arbitrary delay value.
The inv1 and inv4 are inserted between the delay stages to sharpen the
transition edges of the delayed input clock in the forward path.
The operation of the DTC is described in two separate phases, reset
and propagation. In the reset phase when reference clock CKref is low,
regardless of the received 5-bit thermometer code of the DTC (is shown
in the table of Fig. 9(a)), which comes from the threshold quantizer and
denoted by Ti (‘T5T4T3T2T1′ ), all the pull-up switches MP1-MP5 are in the
on state, in order to force all the nodes are set to logic high level.
Therefore, the delay chain output is set to logic high state. When CLKref
= 1 arrives, the propagation phase of the DTC starts according to the
value of the received code Ti, which acts as CODEDTC and comes from the
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

CLKref MP1 CLKref MP2 CLKref MP3 CLKref MP4 CLKref MP5
H H H H H CLKref L
X1
td X2
td X3
td X4
td X5 CLKdly-coarse X1-X5 H
MN1 MN5 CLKdly-coarse H
MN2 MN3 MN4

T5 T4 T3 T2 T1 CODE DTC T5T4T3T2T1

CLKref (N)
VDD

1 11111
Buffer CLKref Ti
2 11110
in td out in out CLKref out out 3 11100
inv1 inv2 inv3 inv4 Ti
Cdly CLKref 4 11000
Ti 5 10000

(a)

X1 X2 X3 X4 X5
Floating Nodes X4-X5 td td td td CLKdly-coarse
CLKref
H
CLKref MP1 CLKref MP2 CLKref MP3 CLKref MP4 CLKref MP5 CLKref L
H L H L X1-X3 H
td td td td CLKdly-coarse L
X1 H X2 H X3 H X4 X5 X4 H
MN1 L MN2 L MN3 L MN4 MN5 L
X5 H
L
T5(1) T4(1) T3(1) T2(0) T1(0) td td
CLKref CLKdly-coarse H
tclk-to-start +2td L
(b)
Fig. 9. Operation of the proposed DTC. (a) Reset phase. (b) Propagation phase with two buffer delays.

threshold quantizer. If the applied CODEDTC is N, then the active input of

DTC would be set to N buffer stages before the output, and the signal VDD VDD
CKref propagates through the last N buffers, it will reach the output after
N buffer delays, thus creating N buffer delays at the delay chain’s output MPr MPt
Bufdly Ir VCr invout
CLKdly-coarse. For more details, Fig. 9(b) shows examples of how the DTC CLKdly-coarse CLKout
creates two buffer delays in the propagation phase. When CLKref = 1 CLKdly-buf
arrives, PMOS transistors MP1-MP5 are off, the DTC is set according to MNr Cr MNt
the thermometer code Ti (‘11100′ ) and the pull-down switches of MN1- Vres
MN3 (red color in Fig. 9(b)) are set to on state, hence, the input nodes of
Thereshold Cros sing
X1-X3 are then changed from the logic high of the reset phase to logic low Ramp Gene rator
Detector (TCD)
level.
At the same time, the pull-down switches of MN4 and MN5 are set to Fig. 10. Circuit schematic of the fine VTC.
off state, causing the inputs nodes of X4 and X5 to be in the floating state.
Therefore, the input node of X3 determines the output CLKdly-coarse, after linearity, whose schematic is shown in Fig. 10, the ramp generation is
the X3 transitions to low, the signal CKref propagates through the last two implemented using the load capacitor Cr and a PMOS transistor of MPr
buffers (red color in Fig. 9(b)) creating 2td delay at the falling edge of which operates as a current source. It is then followed by a TIQ, which
CLKdly-coarse. Thus, based on the described operation, in the case of the acts as a TCD. The calculated residue voltage Vres of the DAC-based
coarse VTC shown in Fig. 6, the rising edge of the input clock is even­ subtractor is fed to the fine VTC through the NMOS transistor of MNr
tually propagated to the falling edge of the output CLKdly-coarse after the as a switch. The front-end delay buffer Bufdly is needed to realize the
total delay Tdly-coarse, which can be digitally controlled by its input code. desired delay time tdly-buf, which has to be large enough to make sure the
The value of Tdly-coarse is expressed as Vres is ready before the ramp operation. The circuit of Bufdly is imple­
mented quite similar to the voltage buffers used to construct the DTC in
Tdly− = tclk− + N.td (4)
coarse to− start
the coarse conversion, as shown in Fig. 9(a).
When the delayed clock signal CLKdly-Buf at the output of Bufdly in
where td is the delay amount of one buffer, N is the number of buffer
Fig. 10, exhibits a high logic level, this will cause MNr is switched on,
stages, and a time offset tclk-to-start, which is the time that it takes for the
then the voltage across Cr, denoted by VCr, is precharged to the starting
input node of the delay chain goes from high to low logic, triggering of
voltage of Vres. After the high-to-low transition of CLKdly-Buf, MNr turns
propagation phase (X3 for the example shown in Fig. 9(b)).
off and MPr turns on in saturation mode, and thereby, the ramp opera­
tion starts with the starting voltage of Vres, the load capacitor Cr will be
4.3. Fine VTC charged by the controlled current Ir of MPr whose value is determined by
sizing of MPr, therefore, VCr rises linearly with time at the rate of Ir/Cr.
The fine VTC employs a constant-slope method to provide a better

6
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

S0
Vres

C C C C C
C5 C4 C3 C2 C1

DAC
N5 S P5 N4 S P4 N3 S P3 N2 S P2 N1 S P1 Switches
5 4 3 2 1

VIN
VDD

N5-S5-P5 N4-S4-P4 N3-S3-P2 N2-S2-P2 N1-S1-P1 S0

CLKref
Control Logic

VDD Ti GND

Fig. 11. Proposed DAC-based subtractor.

When VCr crosses the determined threshold voltage Vtd of TCD, the TCD
will change its output and then the following inverter invout will produce
a low-to-high transition at the output signal CLKout, as shown in Fig. 6
(b). The amount of Vtd can be adjusted through sizing of MPt and MNt in
order to ensure enough margin from the maximum value of Vres (200
mV), where Vtd is set to around half-VDD (500 mV). the value of resultant
delay Tdly-fine, which is defined between the falling edge of CLKdly-coarse
and the rising edge of CLKout, is given by
Cr
Tdlyfine = (Vtd − Vres ) + tdlybuf + tdlyTCD
Ir
where tdly-buf and tdly-TCD are the fixed delay times of Bufdly and TCD,
respectively. It should be noted that with the aid of the two-step con­
struction of the proposed VTC, it will be able to yield a small voltage
change over the simple ramping current source (i.e., PMOS transistor of
MPr), hence, mitigating the effect of finite output resistance of the
ramping current source and its negative impact on the linear ramp
operation.
4.4. DAC-based subtractor
The residue voltage signal Vres for fine conversion is produced by
means of the DAC-based subtractor that is composed of a switched-
capacitor DAC and a control logic, where the control logic determines
the on or off state of all the switches of DAC, as illustrated in Fig. 11.
There are two operational phases, sampling and subtraction. In the
sampling phase when CLKref is low, all of the S (5:0) switches are on and
all top plates of the capacitor array Ck (k = 1, 2, …, 5) are shorted to the
ground, while all bottom plates are connected to the input voltage Vin,
causing the entire capacitor array stores the voltage Vin. After the
quantization phase of the threshold quantizer and at the rising edge of
(5) CLKref, when CLKref is high as depicted in Fig. 6(b), the DAC enters the
subtraction phase, the S (5:0) switches are turned off and all bottom
plates of the capacitor array switch from Vin to ground or VDD,
depending on the values of the digital control signals of PK and NK (k = 1,
2, …, 5). During this phase, if Pk and NK, where k = 1, 2, …, 5 (the kth
digit of Pk and NK), are set to logic-0, the kth PMOS and NMOS switches
are on and off, respectively, the bottom plate of capacitor Ck (k = 1, 2,
…, 5) is connected to VDD. Otherwise, if the kth digit of P and N are set to
logic-1, the kth PMOS and NMOS switches are off and on, respectively,
and the bottom plate of capacitor Ck (k = 1, 2, …, 5) is connected to
ground. In the result, the value of Vres at the end of subtraction phase can
be obtained from

Control
Unit (UK)
DAC PK, NK, SK
VDD Switches
PK
T5
T4 Ti
VDD 0 PK VDD
T3 2:1
T2 MUX
T1 1 GND
NK

GND
GND 0 NK To DAC
2:1 CLKref SK
MUX Ck Caps
1
U5 VIN
U4
U3 SK SK
U2 CLKref
U1 S0

S0 GND

(a) (b)
Fig. 12. Control logic. (a) Simplified diagram. (a) Circuit schematic.

7
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

Fig. 13. (a) Simulated transfer characteristic curve and linear regression. (b) VTC output for various input voltages.

( )
CR shown in Fig. 12(a). Each control unit takes the ith digit of the received
Vres = VDD − Vin = Vth,i+1 − Vin (6)
CT code Ti (i = 1, 2, …, 5) from the threshold quantizer and then creates Kth
of the digital control signal PK, SK, and NK (k = 1, 2, …, 5), respectively,
where and it is implemented by two of 2:1 multiplexers that have pass tran­
sistor logic style is shown in Fig. 12(b). In the sampling phase of DAC
∑
N ∑
5
CR = Ci = NC, CT = Ci = 5C (7) operation, (i.e., CLKref is low), regardless of the value of Ti, the digital
i=1 i=1 control signals PK and NK (k = 1, 2, …, 5) at the outputs of two multi­
plexers, are set to logic-1 and logic-0, respectively, and therefore all of P
In Eqs. (6) and (7), CR is the sum of all capacitors that are connected
(5:1) and N (5:1) switches of DAC are turned off. At the same time, the
to VDD (N = 1, 2, …, 5) in the subtraction phase, CT is the sum of all
digital control signals of SK (k = 1, 2, …, 5) and S0, are set to logic-1,
capacitors of the capacitor array. The first term (CR /CT )VDD of Eq. (6)
hence, all of S (5:0) switches of DAC are turned on, and the sampling
represents the next threshold voltage level Vth,i+1 of the threshold
of Vin take places inside the capacitor array of the DAC. Subsequently,
quantizer when the input voltage Vin crosses the previous one Vth,i,
during the subtraction phase of DAC, when CLKref is high, the received
where DAC is designed to have the amounts of Vth,i+1 (i = 0, 1, …, 4)
signal Ti is routed to DAC via multiplexers by their selection commands,
equal to the threshold levels (VTL1-VTL4) of the threshold quantizer cir­
which are driven with CLKref, resulting in an on or off state for the P (5:1)
cuit and VDD, respectively. Therefore, the value of the residue voltage
and N (5:1) switches based on the value of the ith digit of signal Ti,
Vres can be realized by subtraction a predefined threshold level Vth,i+1
whereas all of S (5:0) switches are off, as described earlier in the sub­
from the input Vin. The size of the switches shown in Fig. 11 are carefully
traction operation of DAC, the residue voltage Vres is produced in DAC
chosen to minimize their on-resistance to have a proper settling time of
output. Therefore, according to the realized circuit in Fig. 12, the logic
Vres in order to apply in fine conversion process before the arrival of the
function of the digital control signals Pk, Sk, Nk (k = 1, 2, …, 5), and S0
falling edge of CLKdly-buf shown in Fig. 6(b).
can be expressed as

PK = CLKref + Ti
4.5. Control logic NK =CLKref .Ti (8)
Sk , S0 =CLKref

The control logic consists of k identical control units UK (k = 1, 2, …,

5) in order to achieve the correct operation of the DAC switching, as

Fig. 14. Timing diagram of proposed VTC.

8
A.H. Miremadi and O. Hashemipour
Fig. 15. Power spectral density of VTC output.
5. Simulation results
The proposed VTC was designed and simulated in TSMC-90 nm
CMOS process with a supply voltage VDD of 1 V, using Cadence Spectre
and the results were processed in MATLAB simulator to extract related
specifications. The devices sizes of VTC and the number of the delay
stages (four delay stages) of delay-line-based DTC of coarse VTC were
designed to produce 5 ns time-difference when input voltage Vin ranging
from GND to VDD (rail-to-rail input range). Fig. 13(a) depicts the transfer
characteristic curve of the proposed VTC, displaying its time-difference
versus Vin. As can be seen, the VTC achieves an output delay range of 5
ns within the full input range of the ground to the supply voltage VDD,
which has resulted in the curve slope of 5 ns/V, is referred as voltage to
time conversion gain. the output delay range and the corresponding gain
of the VTC can be modified by manipulating the delay value of each
delay stage of DTC in the coarse conversion and the rate of Ir/Cr at its
fine conversion, respectively. the output delay data was imported to
MATLAB and the linearity check of characteristic curve is performed
based on curve fitting method through a linear regression, it shows a
high linearity for whole range of input voltage Vin. Fig. 13(b) shows the
transient response of the CLKin (input)-CLKout (output) signals for
various input analog voltages Vin, the time-difference between the rising
edge of CLKin and CLKout is linearly proportional to the input voltage of
the analog signal Vin, when changing from 0 to 1 V.
Fig. 14 presents the detailed sequence of timing waveforms at the
whole circuit when the sampled input voltage Vin is 0.9 v, where the
overall VTC conversion cycle is 30 ns with a clock frequency of 33.3
MHz. As can be seen from this Figure, in the sampling phase (i.e., CLKin
is low), VS1-VS4 are set to 0.9 v and VB1-VB4 are initialized to VDD or GND.
The quantization phase starts by the rising edge of CLKin at time 15 ns,
the allocated time it takes to ensure the outputs of threshold quantizer
T1-T4 are fully settled to the final values is 3 ns. The coarse conversion
starts when CLKref is set to high at time 18 ns, and is done during 4 ns, a
time interval that is equivalent to the sum of four delay stages of DTC.
The coarse conversion is completed at time 22 ns by the assertion of the
falling edge of signal CLKdly-coarse, but the CLKdly-coarse at the output of
DTC is delayed by nearly 25 ns through delay buffer stage to complete
DAC subtraction operation and then the falling edge of CLKdly-Buf signal
will permit the linear increasing of VCr for fine conversion operation.
When VCr crosses around 0.5 v (i.e., half-VDD), the rising edge of delayed
clock signal CLKout will occur at time around 27.3 ns.
In order to evaluate of VTC circuit linearity, a full-scale sinusoidal
input signal with maximum sampling frequency is applied to the pro­
posed VTC and captured a record of sequential output delays of the VTC,
9
AEUE - International Journal of Electronics and Communications 128 (2021) 153501
Fig. 16. Power breakdown of VTC.
Table 1
VTC power budget.
Building Blocks Power (Percentage)
Thereshold Quantizer 13.8 µW (7%)
Delay-Line-Baesd DTC 64.4 µW (31%)
DAC-Based Subtractor 96.6 µW (46%)
Fine VTC (Delay Buffer + Constant–Slope VTC) 35.2 µW (16%)
Total 210 µW (100%)
the data were then exported to MATLAB and analyzed using a 256-point
FFT to calculate the signal-to-noise-and-distortion ratio (SNDR),
spurious-free-dynamic-range (SFDR) and effective-number-of-bits
(ENOB). Fig. 15 presents the power spectral density (PSD) of the VTC
circuit, this output spectra corresponds to fin = 1.17 MHz and fs = 33.3
MHz, the value of SNDR is 56.07 dB which is equivalent to 9.02-bit
ENOB, indicating a SFDR of 59.68 dB.
The simulated average of VTC power consumption under maximum
sampling frequency is 210 µw. Fig. 16 shows the power breakdown of
VTC. As can be seen from Table 1, the power consumption on DAC and
DTC are 46% and 31%, respectively (i.e., 77% of the total power
together), Due to the switched-capacitor structure of DAC, the sizes of
the switches and capacitors suffer from tradeoffs between the DAC
power consumption, realizing precise residue voltage Vres at the DAC
output, and settling time behavior. Moreover, regarding the power
consumption of DTC, the sizes of the capacitors of DTC should be large
enough so that the delay stages of DTC can provide the determined
delay, which will in turn give rise to an increase in power consumption
of DTC.
It is noteworthy that due to the two-step structure of the proposed
VTC, the sampling speed of VTC is lower as compared with that of their
conventional counterparts with single-step conversion. This is the price
paid for some attractive characteristics over the single-step approach
including linearity improvement, technology scalability, and the ease of
adjustments for gain conversion and output range regarding to any
desired requirement whenever the VTC is used in a time-based circuit.
Hence, it is targeted to achieve low to moderate sampling rates (tens of
MHz and below) and this design becomes less attractive for speed-
constrained applications. As can be seen from the transfer character­
istic curve of VTC in Fig. 13, we always need to have a constant time
interval equal to nearly 8 ns in order to complete conversion operation
for any sampled input voltage Vin. As mentioned earlier, this additional
delay time is the sum of the required time from input (CLKin) to output
(CLKout), ensuring proper operation in threshold quantizer, DAC-based
subtractor, and fine VTC, respectively. In the result, the minimum
time difference between the occurrence of the rising edges at CLKin and
CLKout signals are limited to 8 ns delay plus a desirable output range for
the VTC that would cause an ultimate sampling frequency in the tens of
MHz range and below. Fig. 14 shows the aforementioned timing con­
straints during the conversion time of VTC, in this case, the period of
CLKin signal is set to 30 ns (i.e. 33.3 MHz sampling frequency) while the
output range of interest is 5 ns. In general, for a given sampled input
voltage Vin, the larger the gain conversion of the VTC, the wider is the
resultant output range. This, however, is at the cost of the reduced
sampling frequency of the VTC.
To examine the effect of process, voltage, and temperature (PVT)
A.H. Miremadi and O. Hashemipour
Fig. 17. Performance of VTC in PVT variation. (a) VDD and temperature variation. (b) Process corners.
Fig. 18. Monte Carlo simulation of SNDR the VTC. (a) Process variation. (b) Process and mismatch.
variations on the linearity of the proposed VTC, Fig. 17(a) depicts the
simulation results of the SNDR variation versus ±10% supply voltage
drift with − 25 ◦ C to 75 ◦ C temperature variation in the TT corner, as well
as, on four process corners (FF, SS, FS, and SF) that lead to the worst case
SNDR (nearly 29 dB) on the FS and SF process corners, as shown in
Fig. 17(b).
By inspection of the circuit, it can be detected that the TIQ based
structure of the threshold quantizer is the main source of VTC sensitivity
to PVT variation, where the built-in threshold voltage VTH of inverters
M1-M8 in (3), corresponding to the Vdiv,i (i = 1, …, 4) of the quantizer
stages Q1-Q4 in (2) which are set at 500 mV, are vulnerable to the PVT
variation. This implies that if better linearity is required on the FS and SF
process corners, extra tuning/calibration circuitry may be required to
minimize sensitivity to PVT at the cost of increasing the complexity and
power of the VTC circuit, however, It can be inferred from these results
that the proposed design without using a tuning/calibration circuit, still
offers comparable linearity performance with other reported VTCs.
In order to better investigate the SNDR sensitivity of the proposed
VTC in the presence of process variation and transistor mismatches, a
50-point Monte-Carlo simulation has been performed. Fig. 18(a)
10
AEUE - International Journal of Electronics and Communications 128 (2021) 153501
presents the histogram of the SNDR for the process variation that results
in a mean (µ) value of 45.82 dB and a standard deviation (std) equal to
5.68 dB, respectively. For both process and mismatch case, as depicted
in Fig. 18(b), the values of the mean and std are 36.68 dB and 3.65 dB,
respectively.
It should be noted that all simulation results presented in this paper
are based on the pre-layout simulations which not include parasitic
capacitors and resistors. The parasitic gate and drain capacitors of
MOSFETs appear in parallel with all load capacitors Cdly of the buffer
stages of DTC in Fig. 9, as well as, the load capacitor Cr of fine VTC in
Fig. 10. Since these parasitic capacitances are voltage-dependent, it may
have a noticeable impact on the charging or discharging process of the
load capacitors and causes an unwanted delay variation. This leads to an
unexpected transition edges at the time-based signals within the forward
path from CLKref to CLKout in Fig. 6, thereby degrading the linearity
performance and resulting in a reduced SNDR of VTC. In order to ach­
ieve a nearly fixed capacitive loading, this design contains the delay
stages with load capacitors which are large enough in the order of
several hundreds of femtofarads, on the other hand, selecting the small-
size transistors with a few femtofarads parasitic capacitances. Hence, the
A.H. Miremadi and O. Hashemipour AEUE - International Journal of Electronics and Communications 128 (2021) 153501

Table 2
Performance summary and comparison.
Specification CSSP’2015 AEU’2017 JSSC’2019 TVLSI’2016 JSSC’2018 This work
[17] [20] [21] [22] [25]
Architecture Variable-Slope Variable- Variable-Slope Variable-Slope Constant-Slope Constant
(Differential) Slope (Differential) (Differential) (Differential) -Slope

Technology (nm) 65 130 65 65 65 90

Supply Voltage (V) 1.2 1.2 1 1 1.2 1
Input Range (V) ±0–0.1 (Diff.) 0–1.2 ±0–0.4 (Diff.) ±0–0.18 (Diff.) ±0–0.6 (Diff.) 0–1
Output Range (ps) 50 1596 100 100 480 5000
Sampling Rate (MHz) 5000 100 1000 5000 2000 33
Conversion Gain (ps/ 0.25 1.33 0.125 0.28 0.4 5
mV)
SNDR (dB) 28.25 30.4 45a 27a 40.7a 56
Power Consumption 4000 30 2300b 4300 1900 210
(µW)
a
The values is based on the SNDR of ADC.
b
The total power of ADC.

effect of the additional parasitic capacitances of transistors can be
considered negligible. Another consideration that needs to be taken into
account during physical layout is related to the parasitic capacitance and
resistance of the interconnections which connect the driving and driven
delay stages. If a careful place-and-route for the delay stages is not
employed, the interconnections between the delay stages may create a
large extra delay along the transmission line of the CLKref signal from
input to output. This delay can act as an unpredictable time offset, which
can in turn give rise to a decrease in the sampling frequency of VTC.
Table 2 summarizes the simulation results of the proposed VTC and
compares the performance of this work with the recent reported VTCs.
As can be seen, the input range is extended to rail-to-rail operation with
better linearity, while also provides higher conversion gain in wide
output range. Regarding to its inverter based structure, the proposed
design easily operates at lower supply voltage with newer CMOS
processes.
6. Conclusion
This paper presents a scalable, highly digital VTC that is fully
compatible with shrinking across future CMOS processes. The proposed
design is based on the constant-slope architecture which leverages two-
step voltage-to-time conversion. The coarse and fine structure along
with its inverter-based implementation of the proposed VTC can offer
better configurability for conversion gain and output range while
allowing the migrating of this design into other deep nanoscale CMOS
processes without additional design effort. The design creates a rail-to-
rail input range with high linearity, as well as achieves high conver­
sion gain with wide output range. The circuit simulated using TSMC 90-
nm CMOS technology under 1 V supply voltage, which provides a
voltage-to-time gain of 5 ns/V and 5000 ps output range. With a 33.3
MHz sampling frequency, the VTC achieves 56 dB SNDR while the
overall power consumption is 210 μW.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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