A B C D E

1 1

QFKAA
2

Yosemite 10F 2

LA-8392P REV 1.0 Schematic

3
Intel Processor(Ivy Bridge / Sandy Bridge) 3

PCH(Panther Point)
2012-02-06 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF B
Date: Thursday, February 16, 2012 Sheet 1 of 51
A B C D E
 A B C D E

Intel CPU
Ivy Bridge
Sandy Bridge
eDP Conn.
1

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

page 13
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s

CRT FDI X8 DMI X4

page 14
2.7GT/s 5GT/s

USB30 4x USB Right USB Left

5V 5GT/s USB20 port 2,3 USB20 port 0,1
USB30 port 3,4 USB30 port 1,2
USB20 4x page 25 page 30
LVDS Conn.
5V 480MHz
page 13

2
USB20 3x FingerPrinter Int. Camera 2

5V 480MHz USB port 8 USB port 11

EC SMBus page 29 page 13
HDMI-CEC HDMI Conn.
page 15

page 15 Intel PCH USB20 3x PCIeMini Card PCIeMini Card

5V 480MHz
Panther Point PCIe Gen1 1x
WiMax USB port 9 3G/TV#1
TV#2
USB port 12
USB port 10
page 27 page 27
1.5V 5GT/s
RJ45 RTL8105E-VD 10/100M PCIe Gen1 1x PCIeMini Card
SATA Gen3 port 1
page 40 RTL8111F-VB 1G 1.5V 5GT/s
5V 6GHz(600MB/s) WLAN PCIe port 2 mSATA
PCIe port 1 page 31 SATA port 1
FCBGA-989 page 27 page 27 B-CAS SIM
25mm*25mm page 26 page 27

Cardreader PCIe Gen1 1x SATA Gen3 port 0 5V 6GHz(600MB/s)

RTS5229 1.5V 5GT/s
PCIe port4 page 16,17,18,19,20,21,22,23,24
page 29 SATA port 2 SATA ODD SATA HDD
3 5V 3GHz(300MB/s) SATA port 2 SATA port 0 3
page 23 page 23
PCIe Gen2 2x
1.5V 5GT/s
LPC BUS HD Audio
3.3V 33 MHz 3.3V 24MHz
USB3.0 Right-side USB3.0 Left-side
HDA Codec UPD720202 UPD720202
PCIe port5 PCIe port6
ALC280 page 31 page 32
SPI ROM Debug Port ENE KB930/KB9012 page 33
page 36 page 35
(4MB
page 16
+ 2MB)
RTC CKT.
page 16
SPK Conn JPIO
page 34
(HP &page
MIC)34
DC/DC Interface CKT. Touch Pad Int.KBD EC ROM CIR G-Sensor
page 38 page 37 page 36 page 35 page 36
(128KB)
page 36
4 4

Power Circuit DC/DC EC SMBus

page 39,40,41,42,43,
44,45,46,47,48,49
Finger Printer/B
page 26 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

Power On/Off CKT. Power/B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
page 37 Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 37 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 2 of 51
A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A DESIGN CURRENT 11A +5VALW
SUSP#

DESIGN CURRENT 1.8A +1.8VS

SY8033BDBC
SUSP

D D
N-CHANNEL DESIGN CURRENT 6.5A +5VS
SI4800 BCPWON
DESIGN CURRENT 0.1A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
TPS51125 DESIGN CURRENT 0.4A +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 0.3A +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
SYSON

Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A +1.5V

SY8036 SUSP

N-CHANNEL DESIGN CURRENT 5A +1.5V_CPU

FDS6676AS
SUSP
C C
N-CHANNEL DESIGN CURRENT 1.5A +1.5VS
FDS6676AS

0.75VR_EN#

DESIGN CURRENT 1A +0.75VS

VCCPPWRGD
G2992

Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

SY8037

LNB EN

Imax=0.3A, Iocp min=0.8A DESIGN CURRENT 0.3A +16VS

APW7137

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 7.5A +3VALW

WOL_EN

P-CHANNEL DESIGN CURRENT 0.1A +3V_LAN

SUSP AO-3413

N-CHANNEL DESIGN CURRENT 6A +3VS

B B
SI4800 UMA_ENVDD

P-CHANNEL DESIGN CURRENT 2A +LCD_VDD

AO-3415

FELICA_PWR
DESIGN CURRENT 0.1A +FLICA_VCC
P-CHANNEL
AO-3413
VR_ON

DESIGN CURRENT 94A +CPU_CORE

NCP6132A DESIGN CURRENT 50A +GFX_CORE

SUSP#

Ipeak=14A, Imax=9.8A, Iocp min=16.92A DESIGN CURRENT 15A +1.05VS_VCCP

TPS51212

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 3 of 51
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW
+1.8VS
+VSB
power +1.5VS
1 plane +1.05VS
1

+0.75VS BTO Option Table

+CPU_CORE
+VGA_CORE Function HDMI Internal Display Port CPU KB Light
+GFX_CORE
description HDMI Internal Display Port Sandy Bridge Ivy Bridge KB Light
+VTT
State
+VRAM_1.5VS explain HDMI CEC LVDS EDP Sandy Bridge Ivy Bridge KB Light
+3VS_DGPU
BTO HDMI@ CEC@ LVDS@ IEDP@ SANDY@ IVY@ KBL@
+1.05VS_DGPU

Function MINI PCI-E SLOT LAN Fingerprint CIR

S0 description SLOT2 SLOT1 LAN Fingerprint CIR

O O O O O O
explain 3G TV Tuner BCAS mSATA WIMAX 10/100M Giga Fingerprint CIR
S1
O O O O O O
BTO 3G@ TV@ BCAS@ mSATA@ WIMAX@ 8105ELDO@ 8111FVB@ FP@ CIR@
2 2
S3
O O O O O X
Function SPI ROM Green CLK G-SENSOR Sleep&Charge USB 3.0 Camera & Mic
S5 S4/AC
O O O O X X
description SPI ROM Green CLK G-SENSOR Sleep&Charge USB 3.0 Camera & Mic
S5 S4/ Battery only
O O O X X X explain WIN8 Green CLK NOGCLK G-SENSOR 14600 14617 Internal External Camera & Mic

S5 S4/AC & Battery BTO WIN8@ 271@ NOGCLK@ GSENSOR@ 14600@ 14617@ IUSB30@ EUSB30@ CAM@
don't exist
O X X X X X
Function USB Repeater

description USB Repeater

PCH SM Bus Address
explain TIUR PRUR
Power Device HEX Address TIUR@ PRUR@
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3

+3VS New Card

+3VS WLAN/WIMAX
+3VS Clock Generator
+3VS 3G

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH

+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VS G-Sensor 40 H 0100 0000 b
S5 (Soft OFF) LOW LOW LOW
4
Power Device HEX Address 4

G3 LOW LOW LOW

+3VL Cap. Sensor Virtual I2C

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 4 of 51
A B C D E
 5 4 3 2 1

JCPUB

100 MHz
@ A28 CLK_CPU_DMI Stuff R41 and R42 if do not support eDP
BCLK CLK_CPU_DMI <17>
1000P_0402_50V7K 2 1 CC63 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#

MISC

CLOCKS
<21> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <17>
@ +1.05VS_VCCP
120 MHz
1000P_0402_50V7K 2 1 CC62 H_PWRGOOD_R T1 PAD TP_SKTOCC# AN34 SKTOCC# CLK_CPU_EDP
DPLL_REF_CLK A16 CLK_CPU_EDP <17>
A15 CLK_CPU_EDP# CLK_CPU_EDP# RC1571 LVDS@ 2 1K_0402_5%
DPLL_REF_CLK# CLK_CPU_EDP# <17>

D CLK_CPU_EDP RC1581 LVDS@ 2 1K_0402_5% D

T2 PAD H_CATERR# AL33 CATERR#

THERMAL
+1.05VS_VCCP H_PECI AN33 R8 H_DRAMRST#
<35> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>

DDR3
MISC
RC44 2 1 62_0402_5% H_PROCHOT# RC159
<35,40> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
SM_RCOMP[1] SM_RCOMP_2 RC61
SM_RCOMP[2] A4 2 1 200_0402_1% resistors near Processor
RC45 2 1 10K_0402_5% H_PWRGOOD
H_THERMTRIP# AN32
<21> H_THERMTRIP# THERMTRIP# @
H_DRAMRST# 1 2
CC34 180P_0402_50V8J

PRDY# AP29
PREQ# AP27 by ESD requestion and place near CPU
@
1000P_0402_50V7K 2 1 CC70 H_PECI AR26 T4
TCK T5
AR27

PWR MANAGEMENT
TMS

JTAG & BPM

@ <18> H_PM_SYNC H_PM_SYNC AM34 AP30 XDP_TRST#_R 2 1
1000P_0402_50V7K 2 H_PM_SYNC PM_SYNC TRST#
1 CC71 RC55 51_0402_5%
AR28 T6
@ RC187 TDI T7
TDO AP26
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# <21> H_PWRGOOD 1 2 H_PWRGOOD_R AP33
0_0402_5% UNCOREPWRGOOD
Layout request for test point
DBR# AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R
Please place near JCPU RC58 130_0402_5%
V8 SM_DRAMPWROK
C BPM#[0] AT28 C
BPM#[1] AR29
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30
RESET# BPM#[3]
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
+3VALW_PCH
+3VALW_PCH
2 1 DRAMPWROK +1.5V_CPU
RC11 200_0402_5%
2 1 TYCO_2013620-2_IVY BRIDGE
1

@
10K_0402_5% 0.1U_0402_10V7K
+3VS 2 RC13 1 CC33 RC14
UC1 200_0402_5%
5

74AHC1G09GW_TSSOP5
2

1 2 1
P

<18,35> PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
O
<18> DRAMPWROK 2 A
G

1
3

RC25
39_0402_5%
@
RC181
1 @ 2 0_0402_5%
1 2

D QC2
<9,27,38,43> SUSP SUSP 2 2N7002_SOT23
G @
S
3

B B

+5VS FAN Control Circuit

+3VS

1
0.5A R1 @
Buffered Reset to CPU 1 2 +FAN1 R2 JFAN
2 0_0603_5% 10K_0402_5% 6 G2
5 G1
C1 4

2
+3VS 10U_0805_10V6K FANPWM 4
<35> FANPWM 3 3
@ 1 2
<35> FAN_SPEED1 2
1 +FAN1 1
C2 1
1 0.1U_0402_10V7K 0.01U_0402_25V7K ACES_50278-00401-001
CC36 @
+1.05VS_VCCP 2
PLT_RST# <20,27,28,29,31,35,36>
2
1

UC2
PLT_RST# 1 RC38 FANPWM
OE# 75_0402_5%
VCC 5

2
C5

1
2 RC35 330P_0402_50V7K 1 1
2

IN 43_0402_1% @

1
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# D1 C3 C4
OUT
3 GND
1

BAS16_SOT23-3 2 2

2
A 74AHC1G125GW_SOT353-5 RC40 Add C5 for ESD request 02/01 10U_0603_6.3V6M 1000P_0402_50V7K A
0_0402_5%
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 5 of 51
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical

1
impedance = 43 m ohm (4 mils)
RC1
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)

2
D J22 PEG_COMP D
PEG_ICOMPI
PEG_ICOMPO J21
DMI_PTX_CRX_N0 B27 H22
<18> DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_PTX_CRX_N1 B25
<18> DMI_PTX_CRX_N1 DMI_RX#[1]
DMI_PTX_CRX_N2 A25
<18> DMI_PTX_CRX_N2 DMI_RX#[2]
DMI_PTX_CRX_N3 B24 K33
<18> DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
PEG_RX#[1] M35
DMI_PTX_CRX_P0 B28 L34
<18> DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2]
DMI_PTX_CRX_P1 B26 J35
<18> DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]
DMI_PTX_CRX_P2 A24 J32

DMI
<18> DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 B23 H34
<18> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
PEG_RX#[6] H31
DMI_CTX_PRX_N0 G21 G33
<18> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
DMI_CTX_PRX_N1 E22 G30
<18> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 F21 F35
<18> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
DMI_CTX_PRX_N3 D21 E34
<18> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
PEG_RX#[11] E32
DMI_CTX_PRX_P0 G22 D33
<18> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
DMI_CTX_PRX_P1 D22 D31
<18> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
DMI_CTX_PRX_P2 F20 B33

PCI EXPRESS* - GRAPHICS

<18> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
DMI_CTX_PRX_P3 C21 C32
<18> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]

PEG_RX[0] J33
PEG_RX[1] L35
PEG_RX[2] K34
FDI_CTX_PRX_N0 A21 H35
<18> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
FDI_CTX_PRX_N1 H19 H32
<18> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
FDI_CTX_PRX_N2 E19 G34
<18> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 F18 G31
<18> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
C FDI_CTX_PRX_N4 B21 F33 C
<18> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
FDI_CTX_PRX_N5 C20 F30
<18> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 D18 E35
<18> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 E17 E33
<18> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11] F32
PEG_RX[12] D34
FDI_CTX_PRX_P0 A22 E31
<18> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 G19 C33
<18> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
FDI_CTX_PRX_P2 E20 B32
<18> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3 G18
<18> FDI_CTX_PRX_P3 FDI0_TX[3]
FDI_CTX_PRX_P4 B20 M29
<18> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 C19 M32
<18> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI_CTX_PRX_P6 D19 M31
<18> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
FDI_CTX_PRX_P7 F17 L32
<18> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
PEG_TX#[4] L29
<18> FDI_FSYNC0 FDI_FSYNC0 J18 K31
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5]
<18> FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28
PEG_TX#[7] J30
<18> FDI_INT FDI_INT H20 J28
FDI_INT PEG_TX#[8]
PEG_TX#[9] H29
<18> FDI_LSYNC0 FDI_LSYNC0 J19 G27
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10]
<18> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29
PEG_TX#[12] F27
PEG_TX#[13] D28
PEG_TX#[14] F26
PEG_TX#[15] E25
+1.05VS_VCCP RC2 1 2 24.9_0402_1% EDP_COMP A18 eDP_COMPIO
A17 eDP_ICOMPO PEG_TX[0] M28
H_EDP_HPD# B16 M33
B eDP_HPD# PEG_TX[1] B
eDP_COMP signals should be PEG_TX[2] M30
L31
shorted near balls and <13> H_EDP_AUXP C15
PEG_TX[3]
L28
eDP_AUX PEG_TX[4]
routed with typical <13> H_EDP_AUXN D15 eDP_AUX# PEG_TX[5] K30
K27
eDP

impedance <25m ohm PEG_TX[6]

J29
PEG_TX[7]
<13> H_EDP_TXP0 C17 eDP_TX[0] PEG_TX[8] J27
<13> H_EDP_TXP1 F16 eDP_TX[1] PEG_TX[9] H28
C16 eDP_TX[2] PEG_TX[10] G28
G15 eDP_TX[3] PEG_TX[11] E28
PEG_TX[12] F28
<13> H_EDP_TXN0 C18 eDP_TX#[0] PEG_TX[13] D27
<13> H_EDP_TXN1 E16 eDP_TX#[1] PEG_TX[14] E26
D16 eDP_TX#[2] PEG_TX[15] D25
F15 eDP_TX#[3]

+1.05VS_VCCP TYCO_2013620-2_IVY BRIDGE

@
2

Reserve RC3 for HW Review demand

RC3
1K_0402_5%
1

H_EDP_HPD#

A A
1

D
2N7002_SOT23-3
<13> CPU_EDP_HPD 2
G QC1
S IEDP@
3
2

IEDP@
RC4
100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title
SCHEMATICS, MB A8392
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]

AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0 <11> SB_CLK[0] DDRB_CLK0 <12>
AA6 DDRA_CLK0# AD2 DDRB_CLK0#
SA_CLK#[0] DDRA_CLK0# <11> SB_CLK#[0] DDRB_CLK0# <12>
DDR_A_D0 C5 V9 DDRA_CKE0 DDR_B_D0 C9 R9 DDRB_CKE0
SA_DQ[0] SA_CKE[0] DDRA_CKE0 <11> SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDRA_CLK1 DDR_B_D4 SB_DQ[3] DDRB_CLK1
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 <11> A9 SB_DQ[4] SB_CLK[1] AE1 DDRB_CLK1 <12>
D DDR_A_D5 DDRA_CLK1# DDR_B_D5 DDRB_CLK1# D
C6 SA_DQ[5] SA_CLK#[1] AB5 DDRA_CLK1# <11> A8 SB_DQ[5] SB_CLK#[1] AD1 DDRB_CLK1# <12>
DDR_A_D6 C2 V10 DDRA_CKE1 DDR_B_D6 D9 R10 DDRB_CKE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 <11> SB_DQ[6] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDRA_SCS0# DDR_B_D22 SB_DQ[21] DDRB_SCS0#
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# <11> K8 SB_DQ[22] SB_CS#[0] AD3 DDRB_SCS0# <12>
DDR_A_D23 K2 AL3 DDRA_SCS1# DDR_B_D23 K7 AE3 DDRB_SCS1#
SA_DQ[23] SA_CS#[1] DDRA_SCS1# <11> SB_DQ[23] SB_CS#[1] DDRB_SCS1# <12>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDRA_ODT0 DDR_B_D29 SB_DQ[28] DDRB_ODT0
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 <11> N5 SB_DQ[29] SB_ODT[0] AE4 DDRB_ODT0 <12>
DDR_A_D30 N9 AG3 DDRA_ODT1 DDR_B_D30 M2 AD4 DDRB_ODT1

DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] DDRA_ODT1 <11> SB_DQ[30] SB_ODT[1] DDRB_ODT1 <12>

DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <11> AN3 SB_DQ[36] DDR_B_DQS#[0..7] <12>
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] SB_DQ[40] SB_DQS#[3]
AK8 SA_DQ[41] SA_DQS#[4] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[41] SB_DQS#[4] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] SB_DQ[42] SB_DQS#[5]
AK9 SA_DQ[43] SA_DQS#[6] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[43] SB_DQS#[6] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] <11> SB_DQ[48] DDR_B_DQS[0..7] <12>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
SA_DQ[59] DDR_A_MA[0..15] <11> SB_DQ[59]
DDR_A_D60 AL14 DDR_B_D60 AT12
SA_DQ[60] SB_DQ[60] DDR_B_MA[0..15] <12>
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 <12> DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_BS1 DDR_A_MA8 DDR_B_BS1 DDR_B_MA8 B
<11> DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 <12> DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] <12> DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
<11> DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 <12> DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_RAS# AB8 R5 DDR_B_MA14
<11> DDR_A_RAS# SA_RAS# SA_MA[14] <12> DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_WE# AF9 V7 DDR_A_MA15 DDR_B_WE# AB9 R4 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

@ @

+1.5V

RC75
1

0_0402_5%
1 2 RC76
@ 1K_0402_5%

RC77
2

QC3 1K_0402_5%
S

<5> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 SM_DRAMRST# <11,12>

2

BSS138_NL_SOT23-3
RC78
G
2

4.99K_0402_1%
A A
1

<11,17> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

RC73 0_0402_5%
1
CC37 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K 2011/12/14 2012/12/31 Title
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 7 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

JCPUF POWER +1.05VS_VCCP

D D
97A
AG35
8.5A
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12
PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
C C
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48
AA27 VCC49
AA26 VCC50
Y35
CORE SUPPLY

VCC51 +1.05VS_VCCP +1.05VS_VCCP

Y34 VCC52
Y33 VCC53
Y32 0.1U_0402_10V7K 0.1U_0402_10V7K
VCC54
Y31 VCC55 1 2 1 2
Y30 CC50 CC49
VCC56
1

Y29 @ @
VCC57 RC91 RC89
Y28 VCC58
Y27 130_0402_5% 75_0402_5%
VCC59
Y26 VCC60
V35
2

VCC61 H_CPU_SVIDALRT#
V34 AJ29 1 2
SVID

B VCC62 VIDALERT# VR_SVID_ALRT# <46> B

V33 AJ30 H_CPU_SVIDCLK RC90 1 2 43_0402_1%
VCC63 VIDSCLK VR_SVID_CLK <46>
V32 AJ28 H_CPU_SVIDDAT RC88 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <46>
V31 RC92 0_0402_5%
VCC65
V30 VCC66 Pull high resistor on VR side
V29 VCC67
V28 VCC68
V27 VCC69
V26 VCC70
U35 VCC71
U34 VCC72
U33 VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 +CPU_CORE
VCC79
U26 VCC80
R35 VCC81
R34 VCC82
2

R33 VCC83
R32 RC93 Close to CPU
VCC84 100_0402_1%
R31 VCC85
R30 VCC86
R29
1

VCC87
R28
SENSE LINES

VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R RC94 1 2 0_0402_5% VCCSENSE <46>
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R RC95 1 2 0_0402_5% VSSSENSE <46>
P35 VCC91
P34 VCC92
1

P33 VCC93
P32 B10 VCCIO_SENSE RC97
A VCC94 VCCIO_SENSE VCCIO_SENSE <44> A
P31 A10 100_0402_1%
VCC95 VSS_SENSE_VCCIO
P30 VCC96
1

P29
2

VCC97 RC96 RC98

P28 VCC98
P27 10_0402_1% 10_0402_1%
VCC99
P26 VCC100
2

+1.05VS_VCCP
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title
Close to CPU SCHEMATICS, MB A8392
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
@ TYCO_2013620-2_IVY BRIDGE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

+GFX_CORE

1
+GFX_CORE

JCPUG
POWER RC105
10_0402_1%
Close to CPU

33A

2
AT24 AK35 VCC_AXG_SENSE

SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE <46>
AT23 AK34 VSS_AXG_SENSE
D VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <46> D
AT21 VAXG3
AT20 VAXG4 1 RC106 2
AT18 10_0402_1%
VAXG5
AT17 VAXG6 +V_SM_VREF should
AR24 VAXG7
AR23 have 20 mil trace width +1.5V_CPU
VAXG8 RC120
AR21 VAXG9
AR20 VAXG10 1 1K_0402_0.5%
2
AR18 AL1 +V_SM_VREF
VAXG11 SM_VREF
AR17 VAXG12 1 1K_0402_0.5%
2
AP24 RC109

VREF
VAXG13 1
AP23 VAXG14
AP21 CC65
VAXG15 0.1U_0402_10V7K
AP20 VAXG16 SA_DIMM_VREFDQ B4 +VREF_DQA_M3 2
AP18 VAXG17 SB_DIMM_VREFDQ D1 +VREF_DQB_M3
AP17 VAXG18 +1.5V_CPU Decoupling:
AN24 VAXG19
AN23 VAXG20 1X 330U (6m ohm), 6X 10U
AN21 VAXG21
AN20 +1.5V_CPU
VAXG22
AN18
5A

DDR3 -1.5V RAILS

VAXG23
AN17 VAXG24
AM24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K

GRAPHICS
VAXG25 VDDQ1 ESR 6mohm
AM23 VAXG26 VDDQ2 AF4 1
AM21 VAXG27 VDDQ3 AF1 1 1 1 1 1 1
AM20 AC7 CC55 CC56 CC51 CC57 CC52 CC53 + CC54
VAXG28 VDDQ4 @
AM18 VAXG29 VDDQ5 AC4
AM17 AC1 330U_D2_2VM_R6M
VAXG30 VDDQ6 2 2 2 2 2 2 2
AL24 VAXG31 VDDQ7 Y7
AL23 VAXG32 VDDQ8 Y4
AL21 Y1 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VAXG33 VDDQ9
AL20 VAXG34 VDDQ10 U7
C C
AL18 VAXG35 VDDQ11 U4
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
AK23 VAXG38 VDDQ14 P4
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40 +VCCSA Decoupling:
AK18 VAXG41
AK17 VAXG42 1X 330U (6m ohm), 3X 10U
AJ24 VAXG43
AJ23 VAXG44 +VCCSA
AJ21 VAXG45 Bottom Socket Cavity Co-lay for Cost Down Plan
AJ20 VAXG46 6A
AJ18 VAXG47 +VCCSA
VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ17 M27 10U_0805_10V6K 10U_0805_10V6K
VAXG48 VCCSA1

SA RAIL
AH24 M26 ESR 17mohm
VAXG49 VCCSA2
AH23 VAXG50 VCCSA3 L26 1 2+VCCSA_SENSE 0 0 0.90 V For Sandy Bridge
AH21 VAXG51 VCCSA4 J26 1 1 1 1 1 RC189 0_0402_5% 1
AH20 J25 CC40 CC41 CC42 CC43
VAXG52 VCCSA5 + CC44 +
AH18 VAXG53 VCCSA6 J24 0 1 0.80 V
AH17 H26 @ @ @
VAXG54 VCCSA7 2 2 2 2 330U_D2_2VM_R6M
VCCSA8 H25
2 CC67 2 1 0 0.75 V
10U_0805_10V6K 10U_0805_10V6K 330U_2.5V_M_R17
VCCPLL Decoupling: Bottom Socket Edge 1 1 0.65 V
1X 330U (6m ohm), 1X 10U, 2x1U
1.8V RAIL

+1.8VS H23
VCCSA_SENSE +VCCSA_SENSE <45>
RC119 1.2A 1 RC111 2
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 0_0402_5% @
0_0805_5% VCCPLL1 H_VCCSA_VID0
A6 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <45>

1 A2 C24 H_VCCSA_VID1 Please kindly check whether
B VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <45> B
1 1 1 pull down by 10k in PWR-Side
+ CC58 CC59 CC60 CC61
@
1U_0402_6.3V6K A19
2 2 2 2 VCCIO_SEL

330U_B2_2.5VM_R15M 1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

@
+1.5V_CPU +1.5VS CC74
PJ1 @ 4.7U_0805_10V4Z
2 2 1 1 1 2
+1.5V_CPU +1.5V
JUMP_43X118 CC72
Vgs=10V,Id=14.5A,Rds=6mohm +1.5V 1 2
CC46 1 2 0.1U_0402_10V7K QC4
1 8 1U_0402_6.3V6K
CC47 1 S D
2 0.1U_0402_10V7K 2 S D 7 1 2

2
1 3 6 CC73
CC48 1 S D
2 0.1U_0402_10V7K RC192 CC68 4 G D 5 4.7U_0805_10V4Z
470_0805_5% 10U_0805_10V6K
CC45 1 2 0.1U_0402_10V7K FDS6676AS_SO8 RC193
2 RUN_ON_CPU1.5VS3 1 2 +VSB

3 1
220K_0402_5%

6
QC5B 1
CC69 RC194 QC5A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP <5,27,38,43>
2N7002DW-T/R7_SOT363-6

2
2N7002DW-T/R7_SOT363-6

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

JCPUH JCPUI JCPUE (CFG[17:0] internal pull high to VCCIO)
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 AJ16 T35 F22 AH27 PAD T3
VSS3 VSS83 VSS161 VSS234 VCC_DIE_SENSE
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19 AK28 CFG[0] VSS_DIE_SENSE AH26
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 AK29 CFG[1]
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27 AL26 CFG[2]
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24 AL27 CFG[3]
AT16 AJ3 T30 E21 CFG4 AK26 L7
VSS8 VSS88 VSS166 VSS239 CFG[4] RSVD28
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 AL29 CFG[5] RSVD29 AG7
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15 AL30 CFG[6] RSVD30 AE7
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AM31 CFG[7] RSVD31 AK2
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10 AM32 CFG[8]
D D
AT3 AH32 P9 E9 AM30 W8

CFG
VSS13 VSS93 VSS171 VSS244 CFG[9] RSVD32
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8 AM28 CFG[10]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM26 CFG[11]
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AN28 CFG[12] RSVD33 AT26 PEG Static Lane Reversal - CFG2 is for the 16x
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5 AN31 CFG[13] RSVD34 AM33
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4 AN26 CFG[14] RSVD35 AJ27
AR10 AH19 N35 E3 AM27 1: Normal Operation; Lane # definition matches
AR7
AR4
VSS19
VSS20
VSS21
VSS100
VSS101
VSS102
AH16
AH7
N34
N33
VSS177
VSS178
VSS179
VSS250
VSS251
VSS252
E2
E1
AK31
AN29
CFG[15]
CFG[16]
CFG[17] CFG2
* socket pin map definition
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32 0:Lane Reversed
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29 RSVD37 T8
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26 RSVD38 J16
AP25 AF6 N28 D20 AJ31 H16 CFG4
VSS26 VSS107 VSS184 VSS257 VAXG_VAL_SENSE RSVD39
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17 AH31 VSSAXG_VAL_SENSE RSVD40 G16

1
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34 AJ33 VCC_VAL_SENSE
AP16 AF2 M34 C31 AH33 RC82
VSS29 VSS110 VSS187 VSS260 VSS_VAL_SENSE 1K_0402_1%
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 AE34 L30 C27 IEDP@
VSS31 VSS112 VSS189 VSS262
AP7 AE33 L27 C25 AJ26 AR35

2
VSS32 VSS113 VSS190 VSS263 RSVD5 RSVD_NCTF1
AP4 AE32 L9 C23 AT34

RESERVED
VSS33 VSS114 VSS191 VSS264 RSVD_NCTF2
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10 RSVD_NCTF3 AT33
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1 RSVD_NCTF4 AP35
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22 RSVD_NCTF5 AR34
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15 F25 RSVD8 Embedded Display Port Presence Strap
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13 F24 RSVD9
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11 F23 RSVD10
AN10 AC9 K32 B9 D24 B34 1 : Disabled; No Physical Display Port
AN7
AN4
VSS42
VSS43
VSS44
VSS123
VSS124
VSS125
AC8
AC6
K29
K26
VSS200
VSS201
VSS202
VSS273
VSS274
VSS275
B8
B7
G25
G24
RSVD11
RSVD12
RSVD13
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
A33
A34
* attached to Embedded Display Port
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5 E23 RSVD14 RSVD_NCTF9 B35 CFG4
C AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3 D23 RSVD15 RSVD_NCTF10 C35 0 : Enabled; An external Display Port device is C
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2 C30 RSVD16 connected to the Embedded Display Port
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35 A31 RSVD17
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32 B30 RSVD18
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29 B29 RSVD19
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26 D30 RSVD20 RSVD51 AJ32
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23 B31 RSVD21 RSVD52 AK32
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20 A30 RSVD22
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3 C29 RSVD23
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214 BCLK_ITP AN35
AL34 VSS57 VSS138 AB26 H8 VSS215 J20 RSVD24 BCLK_ITP# AM35
AL31 VSS58 VSS139 Y9 H7 VSS216 B18 RSVD25
AL28 VSS59 VSS140 Y8 H6 VSS217
AL25 VSS60 VSS141 Y6 H5 VSS218
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220 J15 RSVD27 RSVD_NCTF11 AT2
AL16 VSS63 VSS144 Y2 H2 VSS221 RSVD_NCTF12 AT1
AL13 VSS64 VSS145 W35 H1 VSS222 RSVD_NCTF13 AR1
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 VSS67 VSS148 W32 G29 VSS225
AL2 W31 G26 B1 PAD T64
VSS68 VSS149 VSS226 KEY
AK33 VSS69 VSS150 W30 G23 VSS227 PCIE Port Bifurcation Straps
AK30 VSS70 VSS151 W29 G20 VSS228
AK27 VSS71 VSS152 W28 G17 VSS229
AK25 W27 G11 11: (Default) x16 - Device 1 functions 1 and 2 disabled
AK22
AK19
VSS72
VSS73
VSS74
VSS153
VSS154
VSS155
W26
U9
F34
F31
VSS230
VSS231
VSS232
TYCO_2013620-2_IVY BRIDGE *10: x8, x8 - Device 1 function 1 enabled ; function 2
AK16 U8 F29 @
VSS75 VSS156 VSS233 disabled
AK13 VSS76 VSS157 U6 CFG[6:5]
AK10 VSS77 VSS158 U5 01: Reserved - (Device 1 function 1 disabled ; function
AK7 VSS78 VSS159 U3 2 enabled)
AK4 VSS79 VSS160 U2
B AJ25 VSS80 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled B

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

@ @

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

de assertion
CFG7
0: PEG Wait for BIOS for training

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] <7>

DQ0 DQ5 DDR_A_DQS#[0..7] <7>

1 1 DDR_A_D1 7 8
CD1 CD2 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] <7>
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_10V7K

2.2U_0603_6.3V4Z
13 VSS VSS 14 DDR_A_MA[0..15] <7>
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 DDR_A_D7 +1.5V
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13
D DQ9 DQ13 RD1 D
25 VSS VSS 26
DDR_A_DQS#1 27 28 1K_0402_1%
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
Close to JDDRL.1 29 DQS1 RESET# 30 SM_DRAMRST# <7,12>
31 32
Intel DDR Vref M3

2
DDR_A_D10 VSS VSS DDR_A_D14
33 DQ10 DQ14 34 +VREF_DQA
DDR_A_D11 35 36 DDR_A_D15 2 @ 1
DQ11 DQ15

1
37 38 0_0402_5%
DDR_A_D16 VSS VSS DDR_A_D20 RC115 RD2
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21 1K_0402_1%
DQ17 DQ21 BSS138_NL_SOT23-3
43 VSS VSS 44
DDR_A_DQS#2 45 46 QC7

2
DQS2# DM2

D
DDR_A_DQS2 47 48 +VREF_DQA_M3 3 1 +VREF_DQA
DQS2 VSS DDR_A_D22
49 VSS DQ22 50
DDR_A_D18 51 52 DDR_A_D23 @
DDR_A_D19 DQ18 DQ23
1 RC117 2

G
53 54

2
DQ19 VSS DDR_A_D28 1K_0402_1%
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29 @
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60 DRAMRST_CNTRL_PCH <7,17>
DDR_A_DQS#3 +1.5V
61 VSS DQS3# 62
63 64 DDR_A_DQS3 @
DM3 DQS3

2
G
65 VSS VSS 66 1 RC118 2

1
DDR_A_D26 67 68 DDR_A_D30 1K_0402_1% @
DDR_A_D27 DQ26 DQ30 DDR_A_D31 RD10
69 DQ27 DQ31 70 +VREF_DQB_M3 3 1 +VREF_DQB
1K_0402_1%

D
71 VSS VSS 72
QC8
BSS138_NL_SOT23-3

2
DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 76 2 @ 1 +VREF_DQB
VDD VDD DDR_A_MA15 0_0402_5%
77 NC A15 78
C DDR_A_BS2 79 80 DDR_A_MA14 RC116 C
<7> DDR_A_BS2 BA2 A14

1
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11 RD11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7 1K_0402_1%
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6

2
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
+1.5V
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98 1 2
99 100 CD50 33P_0402_50V8K
DDRA_CLK0 VDD VDD DDRA_CLK1
<7> DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 <7>
DDRA_CLK0# 103 104 DDRA_CLK1# 1 2
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 106 CD51 33P_0402_50V8K
DDR_A_MA10 VDD VDD DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS# 1 2
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 112 CD52 33P_0402_50V8K
VDD VDD

1
DDR_A_WE# 113 114 DDRA_SCS0#
<7> DDR_A_WE# WE# S0# DDRA_SCS0# <7>
DDR_A_CAS# 115 116 DDRA_ODT0 RD6 1 2
<7> DDR_A_CAS# CAS# ODT0 DDRA_ODT0 <7>
117 118 1K_0402_1% CD53 33P_0402_50V8K
DDR_A_MA13 VDD VDD DDRA_ODT1
119 A13 ODT1 120 DDRA_ODT1 <7>
DDRA_SCS1# 121 122 1 2

2
<7> DDRA_SCS1# S1# NC CD54 33P_0402_50V8K
123 VDD VDD 124
125 126 +VREF_CAA +VREF_CAA_DIMMA
TEST VREF_CA
127 VSS VSS 128 1 2

1
DDR_A_D32 129 130 DDR_A_D36 CD55 33P_0402_50V8K
DDR_A_D33 DQ32 DQ36 DDR_A_D37 RD7
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_A_DQS#4 VSS VSS
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1

2
B DQS4 VSS DDR_A_D38 CD15 CD16 B
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DQ34 DQ39
2.2U_0603_6.3V4Z

0.1U_0402_10V7K

DDR_A_D35 143 144

DQ35 VSS DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
DDR_A_DQS#5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
151 VSS DQS5# 152
153 DM5 DQS5 154 DDR_A_DQS5 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 close to JDDRL.126 +1.5V
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 +1.5V +0.75VS
DDR_A_D49 DQ48 DQ52 DDR_A_D53 CD7 2 390U_2.5V_M_R10
+
165 DQ49 DQ53 166 1
167 VSS VSS 168
DDR_A_DQS#6 169 170 CD20 1 2 0.1U_0402_10V7K CD56 1 2 10U_0603_6.3V6M
DDR_A_DQS6 DQS6# DM6 CD8
171 DQS6 VSS 172 1 2 10U_0603_6.3V6M
173 174 DDR_A_D54 CD17 1 2 0.1U_0402_10V7K
DDR_A_D50 VSS DQ54 DDR_A_D55 CD9
175 DQ50 DQ55 176 1 2 10U_0603_6.3V6M CD24 2 1 1U_0402_6.3V6K
DDR_A_D51 177 178 CD18 1 2 0.1U_0402_10V7K
DQ51 VSS DDR_A_D60 CD10 1
179 VSS DQ60 180 2 10U_0603_6.3V6M CD21 2 1 1U_0402_6.3V6K
DDR_A_D56 181 182 DDR_A_D61 CD19 1 2 0.1U_0402_10V7K
DDR_A_D57 DQ56 DQ61 CD11 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M CD22 2 1 1U_0402_6.3V6K
185 186 DDR_A_DQS#7
VSS DQS7# DDR_A_DQS7 CD12 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M CD23 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62 CD13 1 2 10U_0603_6.3V6M
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
RD8 1 2 195 196
10K_0402_5% VSS VSS
A 197 SA0 EVENT# 198 A
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <12,17,27,37>
PM_SMBCLK
0.1U_0402_10V7K

201 202
2.2U_0603_6.3V4Z

SA1 SCL PM_SMBCLK <12,17,27,37>

1 1 +0.75VS 203 VTT VTT 204 +0.75VS
1

CD26
CD25 205 206
RD9 GND1 GND2
207 208
2 2 10K_0402_5% BOSS1 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title
2

LCN_DAN06-K4406-0103
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 11 of 51
5 4 3 2 1
 A B C D E

+1.5V +1.5V
JDDR3H
1 2
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
Reverse Type
DDR_B_D1 7
9
DQ0
DQ1
DQ5
VSS 8
10 DDR_B_DQS#0
DDR3 SO-DIMM B
VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12
1 1 13 VSS VSS 14
CD28 CD27 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0603_6.3V4Z

0.1U_0402_10V7K
19 VSS VSS 20 DDR_B_DQS[0..7] <7>
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_D[0..63] <7>
1 DQ9 DQ13 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_MA[0..15] <7>
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# <7,11>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
Close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
2
<7> DDR_B_BS2 79 BA2 A14 80 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 VDD VDD 112

1
DDR_B_WE# 113 114 DDRB_SCS0#
<7> DDR_B_WE# WE# S0# DDRB_SCS0# <7>
DDR_B_CAS# 115 116 DDRB_ODT0 RD12
<7> DDR_B_CAS# CAS# ODT0 DDRB_ODT0 <7>
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDRB_ODT1
119 A13 ODT1 120 DDRB_ODT1 <7>
DDRB_SCS1# 121 122

2
<7> DDRB_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAB +VREF_CAB_DIMMB
TEST VREF_CA
127 VSS VSS 128

1
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37 RD13
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_B_DQS#4 VSS VSS
135 DQS4# DM4 136 1 1
DDR_B_DQS4 137 138 CD46 CD47

2
3 DQS4 VSS DDR_B_D38 3
139 VSS DQ38 140
2.2U_0603_6.3V4Z

0.1U_0402_10V7K

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
DDR_B_DQS5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
153 DM5 DQS5 154
155 VSS VSS 156 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D42 157 158 DDR_B_D46 Close to JDDRH.126
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 162 +1.5V
DDR_B_D48 VSS VSS DDR_B_D52 @ +1.5V +0.75VS
163 DQ48 DQ52 164
DDR_B_D49 DDR_B_D53 CD31 1 2 330U_B2_2.5VM_R15M

+
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170 CD33 1 2 0.1U_0402_10V7K CD57 1 2 10U_0603_6.3V6M
DDR_B_DQS6 DQS6# DM6 CD41 1
171 DQS6 VSS 172 2 10U_0603_6.3V6M
173 174 DDR_B_D54 CD29 1 2 0.1U_0402_10V7K
DDR_B_D50 VSS DQ54 DDR_B_D55 CD36 1
175 DQ50 DQ55 176 2 10U_0603_6.3V6M CD45 2 1 1U_0402_6.3V6K
DDR_B_D51 177 178 CD30 1 2 0.1U_0402_10V7K
DQ51 VSS DDR_B_D60 CD37 1
179 VSS DQ60 180 2 10U_0603_6.3V6M CD42 2 1 1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61 CD32 1 2 0.1U_0402_10V7K
DDR_B_D57 DQ56 DQ61 CD38 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M CD43 2 1 1U_0402_6.3V6K
185 186 DDR_B_DQS#7
VSS DQS7# DDR_B_DQS7 CD39 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M CD44 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 CD40 1 2 10U_0603_6.3V6M
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
RD14 1 2 195 196
10K_0402_5% VSS VSS
4 197 SA0 EVENT# 198 4
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <11,17,27,37>
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <11,17,27,37>
2.2U_0603_6.3V4Z
1 1 1 RD15 2 +0.75VS 203 204 +0.75VS
@ 10K_0402_5% VTT VTT
205 GND1 BOSS1 206
CD48 CD49 207 208
2 2 GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_10V7K 2011/12/14 2012/12/31 Title
FOX_AS0A626-UASN-7F_204P
Issued Date Deciphered Date
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 12 of 51
A B C D E
 A B C D E F G H

OPT for 2D HD eDP Panel <19> LCD_TXOUT0+ 1 LVDS@ 2 LVDS_TXOUT0+

R262 0_0402_5%
+5VS
<19> LCD_TXOUT0- 1 LVDS@ 2 LVDS_TXOUT0-
IEDP@ R263 0_0402_5%
<6> H_EDP_AUXP C890 1 20.1U_0402_10V7K LVDS_EDID_CLK <19> LCD_TXOUT1+ 1 LVDS@ 2 LVDS_TXOUT1+
IEDP@ R265 0_0402_5%
C891 1 20.1U_0402_10V7K LVDS_EDID_DATA 1 LVDS@ 2 LVDS_TXOUT1-
<6> H_EDP_AUXN
C912
IEDP@
1 20.1U_0402_10V7K LVDS_TXOUT0+
<19> LCD_TXOUT1-
R264 0_0402_5%
LCD_TXOUT2+
LCD/PANEL BD. Conn. IEDP@ 2
C293
W=80mils
<6> H_EDP_TXP0 <19> LCD_TXOUT2+
IEDP@ only need for 3D with DCDC/B 0.1U_0402_10V7K

3
S
C913 1 20.1U_0402_10V7K LVDS_TXOUT0- <19> LCD_TXOUT2- LCD_TXOUT2- ,JLVDS Pin8 can connect to @ IEDP@
<6> H_EDP_TXN0
LCDPWR_GATE 1 2
G
IEDP@ 2 1 +3VS Q23
C914 +LCV_VDD directly for
1 <6> H_EDP_TXP1 1 20.1U_0402_10V7K LVDS_TXOUT1+ <19> LCD_TXCLK+ LCD_TXCLK+ R1441 0_0603_5% AO3413_SOT23 1
IEDP@ 3D w/o DCDC/B D

1
C915 1 20.1U_0402_10V7K LVDS_TXOUT1- <19> LCD_TXCLK- LCD_TXCLK-
<6> H_EDP_TXN1 +LCD_VDD
+PANEL_VDD 1LVDS@ 2 +LCD_VDD
<19> LCD_EDID_CLK 1 LVDS@ 2 LVDS_EDID_CLK R106 0_0805_5%
R300 0_0402_5%
For RF @ <19> LCD_EDID_DATA 1 LVDS@ 2 LVDS_EDID_DATA W=80mils
C256 47P_0402_50V8J R299 0_0402_5%
1 2

W=20mils CAM@ 2 1 IEDP@ +LCD_VDD reserve for 3D w/o DCDC/B

0.1U_0402_10V7K R392 0_0603_5%
+3VS 1 CAM@ 2 +3VS_LVDS_CAM 1 2 +LCD_VDD_R 2 1 @ +5VS
JLVDS4 R388 0_0603_5% C225 R390 0_0603_5% LVDS_ENVDD 2 3D@ 1
1 1 2 @ 40MILS R1442 0_0603_5%
+3VS
USB20_N11_R +LCD_VDD +3VS +5VS
41 G1 2 2 1 For LVDS 3D only
42 3 USB20_P11_R 3 1 @ 2 UMA_ENVDD
G2 3 D84 AZ5125-02S.R7G_SOT23-3 R361 0_0402_5%
43 G3 4 4

1
44 5 INT_MIC_CLK For RF @
G4 5 INT_MIC_CLK <33>

1
45 6 INT_MIC_DATA C258 47P_0402_50V8J R109 for 3D with DCDC/B
G5 6 INT_MIC_DATA <33>
46 7 +LCD_VDD +LCD_VDD 1 2 150_0603_5% R108 R120
G6 7 +PANEL_VDD 100K_0402_5% 100K_0402_5%
8 8
9 +LCD_VDD_R 1 1 2A LVDS@ IEDP@

2
9 +3VS_LVDSDDC +3VS
10

2
10 LVDS_EDID_CLK C226 C227
11 11

6
12 LVDS_EDID_DATA 0.1U_0402_10V7K 4.7U_0805_10V4Z
12 LVDS_TXOUT0- 2 2 LVDS@ 2
13 13
LVDS_TXOUT0+ Q1A C228
W=80mils
14 14
15 2N7002DW-T/R7_SOT363-6 2 0.1U_0402_10V7K
15

3
S
2 16 LVDS_TXOUT1- GND_R 1 2 LCD_ENVDD_R LVDS@ 2
16 LVDS_TXOUT1+ R62 0_0402_5% 1
R110 2LCDPWR_GATE
G
Q17
17 1 2
20MILS

1
17

2
18 LCD_TXOUT2- IEDP@ 47K_0402_5% 1 AO3413_SOT23
18

3
19 LCD_TXOUT2+ R389 D

1
19 LCD_TXCLK- C230 +LCD_VDD
20 20 0_0603_5%
21 LCD_TXCLK+ LVDS@ 0.01U_0402_25V7K W=80mils
21 LCD_ENVDD_R Q1B 2
22 <19> UMA_ENVDD 2 1 5

1
22 R260 2.2K_0402_5% 2N7002DW-T/R7_SOT363-6
23 23 LCD_TZOUT0- <19> 1 1 1

10U_0603_6.3V6M
0.1U_0402_10V7K
C233 C229 C393

4.7U_0603_6.3V6K
24 LCD_TZOUT0+ <19>

4
24

2
25 25 LCD_TZOUT1- <19> Prevent to use wrong interface panel. +3VS
26 LCD_TZOUT1+ <19> R112
26 100K_0402_5% 2 2 2
27 27 LCD_TZOUT2- <19>
28 28 LCD_TZOUT2+ <19> Reserve for EMI request
29 LCD_TZCLK- <19>

1
29

3
S
30 LCD_TZCLK+ <19> @
30 LCDPWR_GATE 2
G
Q20
31 31 1 2
32 USB20_N13_R R78 CAM@ 0_0402_5% AO3413_SOT23
32 USB20_P13_R WCM-2012-900T_0805
33 D

1
33 GND_R USB20_P11_R USB20_P11 <20>
34 34 4 4 3 3
35 LVDS_ENVDD +LCD_VDD
35 LED_PWM
36 36
USB20_N11 <20>
close to Q17
37 BKOFF#_R USB20_N11_R 1 2
37 1 2
38 38 1.5A L55 @
39 39 +LCD_INV
40 +3VS
40 C261
1 2 Reserve for eDP panel
1

E-T_0871K-F40N-00L R96 CAM@ 0_0402_5% 1 2

@ C257 IEDP@ 0.1U_0402_10V7K
47P_0402_50V8J IEDP@1 2 IEDP@
2

5
3 R103 0_0402_5% U17 3
@
1
USB for Glasses free 3D

P
IN1 UMA_ENBKL <19,35>
BKOFF#_R 1 2 4
D15 RB751V40_SC76-2 O
IN2 2 BKOFF# <35>

G
For RF LVDS@

1
1 2

3
1.5A R79 3D@ 0_0402_5% R113 SN74AHC1G08DCKR_SC70-5
L60 @ 10K_0402_5%
+LCD_INV F3 B+ B+ USB20_P13_R 1 2
1 2 USB20_P13 <20>
L2 3A_32V_S1206-F-3.0A For EMI

2
2 1 1 2 1 2
1 1 FBMA-L11-201209-221LMA30T_0805 USB20_N13_R 4 3 USB20_N13 <20> R147 0_0402_5%
4 3 LVDS@
C234 C235 Add F3 to prevent 1 1 1 1 WCM-2012-900T_0805 Reserve for LVDS panel
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

68P_0402_50V8J 0.1U_0402_25V6
2 2 burn on PVT C247 C269 C489 C490 1 2
@ @ @ @ R97 3D@ 0_0402_5%
2 2 2 2
Reserve for EMI request

LED_PWM 1 2 PCH_PWM <19>

D17 RB751V40_SC76-2 1 IEDP@ 2 CPU_EDP_HPD <6>
R360 0_0402_5%
1

R131 +3VS_LVDSDDC 2 LVDS@ 1

LVDS & eDP cable pine definition notice. 47K_0402_5% R1440 0_0603_5% 1
+3VS

Prevent to use wrong interface panel.

C248
2

4 4
LVDS cable eDP cable 0.1U_0402_10V7K
2
MB side MB side
Pin 22 Pin 22

LVDS GND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

eDP NC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 13 of 51
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils

3
1 1 2
1 3 RB491D_SOT23-3 0.5A_8V_KMC3S050RY 1 1

C237
0.1U_0402_10V7K
CRT_R_R L3 2
<19> UMA_CRT_R 1 2 1 2 NBQ100505T-800Y_0402 CRT_R_L @
R189 0_0402_5%
<19> UMA_CRT_G 1 2 CRT_G_R L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
R190 0_0402_5%
<19> UMA_CRT_B 1 2 CRT_B_R L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
R191 0_0402_5%
JCRT
6
T65 PAD 11

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
R138 R139 R140 CRT_R_L 1

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 1 1 1 1 7

1
CRT_DDC_DAT 12
C249 C250 C251 C238 C239 C240 C241 C242 C243 CRT_G_L 2
@ @ @ 8
2 2 2 2 2 2 2 2 2 HSYNC 13
CRT_B_L 3
2

2 +CRT_VCC 9
VSYNC 14 G 16
T66 PAD 4 G 17
10
By EMI demand CRT_DDC_CLK 15
5
C-H_13-12201513CP

2 2
+CRT_VCC @

1 2
C244 0.1U_0402_10V7K 2 1
R141 10K_0402_5%

5
1
P
OE#
2 4 D_CRT_HSYNC 1 2 HSYNC
<19> UMA_CRT_HSYNC A Y
+CRT_VCC L6 10_0402_5%

G
U6
SN74AHCT1G125GW_SOT353-5 1 2

5
1
C252
0.1U_0402_10V7K

P
OE#
2 A 4 D_CRT_VSYNC 1 2 VSYNC
<19> UMA_CRT_VSYNC Y

10P_0402_50V8J

10P_0402_50V8J
L7 10_0402_5% 1 1

G
U7
SN74AHCT1G125GW_SOT353-5 C245 C246

3
@ @
2 2

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A
<19> UMA_CRT_CLK 5 1 6 CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6
Q205B
<19> UMA_CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 14 of 51
A B C D E
 5 4 3 2 1

HDMI CEC Controller Address: 0011010X U16

1 11 CEC_INT#
+3VL +3VL <35,40,41> EC_SMB_CK1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 CEC_INT# <35> +3VL

+3VL 2 12 CEC_TEST 1 CEC@ 2

P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R168 4.7K_0402_5%

2
+3VL +3VL
R162 D9 2 CEC@ 1CEC_RST# 3 13 CEC_FSHUPD1 CEC@ 2
R169 4.7K_0402_5% RESET# P1_4/TXD0 R170 4.7K_0402_5%
10K_0402_5% CH751H-40PT_SOD323-2
CEC@ CEC@ CEC_FSHUPD (Pin13)

1
2 CEC@ 1CEC_XOUT 4 14 Low= Force to update flash.

1 1
HDMI_CECIN R171 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT R166 R164
+3VL 4.7K_0402_5% 4.7K_0402_5% Q47

2
R581 5 15 CEC@ CEC@ CEC@ BSH111_SOT23-3
VSS/AVSS P1_2/KI2#/AN10/CMP0_2

G
D 27K_0402_5% CEC@ D
1 2

2
1
D CEC@ C848 1U_0402_6.3V6K
Q49 2 2 CEC@ 1CEC_XIN 6 16 1 2 HDMI_CLK 3 1 HDMI_SCLK

2
XIN/P4_6 P4_2/VREF

2
2N7002_SOT23-3 G HDMI_CEC R174 47K_0402_5% C263 0.1U_0402_10V7K

D
CEC@ S CEC@
3

7 17 HDMI_CLK
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 HDMI_DATA HDMI_SDATA
3 1

1
D

D
HDMI_CECOUT 1 R163 2 2 Q50 2 CEC@ 1 8 18 HDMI_DATA Q48
27K_0402_5% G 2N7002_SOT23-3 R176 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0 BSH111_SOT23-3
CEC@ S CEC@ C262 1 CEC@
3
1

0.1U_0402_10V7K HDMI_CECIN 9 19 HDMI_HPD_R

R165 CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
100K_0402_5%
CEC@ 2 HDMI_CECOUT 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 <35,40,41>
2

R5F211A4C33SP-W4_LSSOP20 CEC@

JHDMI1 46@
+3VS
+HDMI_5V_OUT
HDMI Royalty +HDMI_5V_OUT HDMI@
RO0000003HM R145
HDMI_HPD_U 1 2 HDMI_HPD_C
HDMI W/Logo + HDCP 2 1K_0402_5%
C264 2

2
HDMI W/O Logo: RO0000001HM 0.1U_0402_10V7K R186 C265

1
HDMI@ U9 100K_0402_5% 0.1U_0402_10V7K
C C
HDMI W/Logo: RO0000002HM 1 HDMI@ HDMI@

OE#
1

1
HDMI_HPD_R 1
HDMI W/Logo + HDCP: RO0000003HM 2 A Y 4
R184 R185

1
G
2.2K_0402_5% 2.2K_0402_5% SN74AHCT1G125GW_SOT353-5
HDMI@ HDMI@ HDMI@

3
2
<19> UMA_HDMI_CLK

2
G
3 1 HDMI_SCLK

2
G

D
Q18
BSH111_SOT23-3
3 1 HDMI@ HDMI_SDATA HDMI@ HDMI@
<19> UMA_HDMI_DATA
+3VL 2 1 2 1 +3VS

D
R570 R571
Q19 100K_0402_5% 2.2K_0402_5%
BSH111_SOT23-3 D55
HDMI@ HDMI_HPD_R 1 2 HDMI_HPD <19,21>
CH751H-40PT_SOD323-2
HDMI@

UMA_DVI_TXC- 1 @ 2 HDMI_R_CK- HDMI_R_CK+ 1 HDMI@ 2

R157 0_0402_5% R195 680_0402_1%
HDMI_R_CK- 1 HDMI@ 2
4 L8
4
HDMI@
3 3 R197 680_0402_1% HDMI@
HDMI_R_D1- 1 HDMI@ 2 D53 F2
R198 680_0402_1% +5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
1 2 HDMI_R_D1+ 1 HDMI@ 2 1
CV308 1 2
<19> UMA_HDMI_TXC+ 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXC+ WCM-2012-900T_4P R202 680_0402_1% PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY C259
HDMI_R_D0+ 1 HDMI@ 2 HDMI@ HDMI@
CV304 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXC- UMA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ R201 680_0402_1% D54 0.1U_0402_10V7K
<19> UMA_HDMI_TXC- 2
B R173 0_0402_5% HDMI_R_D0- 1 HDMI@ 2 +5VL 2 1 B
CV306 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD0+ R203 680_0402_1%
<19> UMA_HDMI_TX0+
HDMI_R_D2- 1 HDMI@ 2 PMEG2010AEH_SOD123
CV302 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD0- UMA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ R205 680_0402_1% CEC@
<19> UMA_HDMI_TX0-
R175 0_0402_5% HDMI_R_D2+ 1 HDMI@ 2
CV303 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD1+ R206 680_0402_1%
<19> UMA_HDMI_TX1+

1
D
1 WCM-2012-900T_4P
1 2 2
CV301 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD1- +5VS 2 Q24
<19> UMA_HDMI_TX1-
G 2N7002_SOT23-3
CV307 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD2+ 4 3 S HDMI@
<19> UMA_HDMI_TX2+

3
4 L9 HDMI@3
CV305 1 2 0.1U_0402_10V7K HDMI@ UMA_DVI_TXD2-
<19> UMA_HDMI_TX2-
UMA_DVI_TXD0- 1 @ 2 HDMI_R_D0-
R180 0_0402_5%
HDMI Connector
JHDMI
UMA_DVI_TXD1- 1 @ 2 HDMI_R_D1- HDMI_HPD_C 19
R182 0_0402_5% HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
4 L10
4
HDMI@
3 3 HDMI_SDATA 16 SDA
HDMI_SCLK 15 SCL
14 Reserved
1 HDMI_CEC
1 2 2
WCM-2012-900T_4P HDMI_R_CK-
13 CEC
12 CK- GND 20
11 CK_shield GND 21
UMA_DVI_TXD1+ 1 @ 2 HDMI_R_D1+ HDMI_R_CK+ 10 22
R183 0_0402_5% HDMI_R_D0- CK+ GND
9 D0- GND 23
8 D0_shield
HDMI_R_D0+ 7
UMA_DVI_TXD2+ @ HDMI_R_D2+ HDMI_R_D1- D0+
1 2 6 D1-
R187 0_0402_5% 5
HDMI_R_D1+ D1_shield
4 D1+
1 WCM-2012-900T_4P
1 2 2
HDMI_R_D2- 3 D2-
A 2 D2_shield
A
HDMI_R_D2+ 1 D2+
4 4L11 HDMI@ 3 3
SUYIN_100042GR019M23DZL
@
UMA_DVI_TXD2- 1 @ 2 HDMI_R_D2-
R188 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 15 of 51
5 4 3 2 1
 5 4 3 2 1

UH1A

CMOS Setting, near DDR Door JCMOS @ PCH_RTCX1 LPC_AD0

2 1 A20 RTCX1 INT.PH 20K FWH0 / LAD0 C38 LPC_AD0 <35,36>
+RTCVCC RH23 1 2 PCH_RTCRST# 1 2 CH2 15P_0402_50V8J INT.PH 20K A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <35,36>

LPC
20K_0402_5% NOGCLK@ PCH_RTCX2 C20 INT.PH 20K B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <35,36>

1
10M_0402_5%

NOGCLK@
CH4 1 2 INT.PH 20K C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 <35,36>
1U_0402_6.3V6K AZ_BITCLK_HD YH1 PCH_RTCRST# D20 RTCRST#

RH2
32.768KHZ_12.5P_1TJF125DP1A000D D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <35,36>
NOGCLK@ PCH_SRTCRST# G22

1
SRTCRST# +3VS
iME Setting. INT.PH 20K LDRQ0# E36

RTC
JME @ 1 2 1 SM_INTRUDER# K22 INT.PH LDRQ1#
20K / GPIO23 K36
INTRUDER#
RH24 1 2PCH_SRTCRST# 1 2 CH3 15P_0402_50V8J
20K_0402_5% @ CH101 NOGCLK@ PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 2 1
INTVRMEN SERIRQ SERIRQ <35>
CH5 1 2 10P_0402_50V8J RH31 10K_0402_5%
1U_0402_6.3V6K 2
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 <25>
D RH27 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 D
<33> AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <25> +3VS
SATA_PTX_DRX_N0

SATA 6G
AP7
AZ_SYNC SATA0TXN SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 <25> HDD
Integrated SUS 1.05V VRM Enable L34 HDA_SYNCINT.PD 20K SATA0TXP AP5 SATA_PTX_DRX_P0 <25>
High - Enable Internal VRs PCH_SPKR SATA_PRX_C_DTX_N1
<33> PCH_SPKR T10 SPKR INT.PD 20K SATA1RXN AM10
SATA_PRX_C_DTX_P1
SATA_PRX_C_DTX_N1 <27>
SATA_LED# RH29 2
PCH_INTVRMEN (must be always pulled high) SATA1RXP AM8 SATA_PRX_C_DTX_P1 <27> 1 10K_0402_5%
RH30 1 2 33_0402_5% AZ_RST# SATA_PTX_DRX_N1
<33> AZ_RST_HD# K34 HDA_RST# SATA1TXN AP11
AP10 SATA_PTX_DRX_P1
SATA_PTX_DRX_N1 <27> m-SATA
SATA1TXP SATA_PTX_DRX_P1 <27>
PCH_GPIO21 RH34 2 1 10K_0402_5%
+RTCVCC AZ_SDIN0_HD SATA_PRX_C_DTX_N2
<33> AZ_SDIN0_HD E34 INT.PD
HDA_SDIN0 20K SATA2RXN AD7 SATA_PRX_C_DTX_N2 <25>
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 <25>
RH12 1 SM_INTRUDER# INT.PD 20K SATA_PTX_DRX_N2 PCH_GPIO19 RH28 1 2 10K_0402_5%
2
1M_0402_5%
G34 HDA_SDIN1 SATA2TXN AH5
AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 <25> ODD
SATA2TXP SATA_PTX_DRX_P2 <25>
RH33 1 2 PCH_INTVRMEN C34 INT.PD 20K
HDA_SDIN2

IHDA
330K_0402_5% PCH_SPK AB8
+3VS @ SATA3RXN
High = Enabled (No Reboot) +3VALW_PCH 2 1 A34 INT.PD
HDA_SDIN3 20K SATA3RXP AB10
@ RH272 1K_0402_5% AF3
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) SATA3TXP AF1
RH36 1K_0402_5% RH32 1 2 33_0402_5% AZ_SDOUT
<33> AZ_SDOUT_HD A36 HDA_SDO INT.PD 20K

SATA
SATA4RXN Y7
SATA4RXP Y5 +RTCVCC +RTCBATT
RH25 1 2 0_0402_5% C36 AD3
<35> PWRME_CTRL HDA_DOCK_EN# / GPIO33 SATA4TXN

0.1U_0402_10V7K

RB751V-40_SOD323-2
SATA4TXP AD1
N32 HDA_DOCK_RST# / GPIO13 1

CH8
SATA5RXN Y3

1
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS Y1 @
SATA5RXP DH7
HDA_SDO SATA5TXN AB3
2

DH1
PCH_JTAG_TCK J3 JTAG_TCKINT.PD 20K SATA5TXP AB1 RB751V-40_SOD323-2
ME debug mode,
PCH_JTAG_TMS
T67 PAD H7 JTAG_TMSINT.PH 20K Y11

2
this signal has a weak internal pull down SATAICOMPO

JTAG
PCH_JTAG_TDI SATAICOMP
*Low = Disable (default)
High = Enable (flash descriptor security overide)
T68 PAD K5 JTAG_TDI INT.PH 20K SATAICOMPI Y10 1
RH43
2
37.4_0402_1%
+1.05VS_VCC_SATA +RTCBATT +3VL

T69 PAD PCH_JTAG_TDO H1 JTAG_TDO

C SATA3RCOMPO AB12 C
If use GCLK, please delet DH1
SATA3_COMP
HDA_SYNC RH26 GCLK@ SATA3COMPI AB13 1
RH48
2
49.9_0402_1%
+1.05VS_SATA3
PCH_RTCX1
*This signal has a weak internal pull
H=>On Die PLL is supplied by 1.5V
down <27> PCH_RTCX1_R 1
0_0402_5%
2
PCH_SPICLK T3 SPI_CLK SATA3RBIAS AH1 RBIAS_SATA3 1 2
RH41 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS0# Y14 SPI_CS0#
Need to pull high for Huron River platform Placement near to YH1
PCH_SPICS1# T1 SPI_CS1#

SPI
+3VALW_PCH 2 1 AZ_SYNC P3 SATA_LED#
RH55 1K_0402_5% SATALED#
PCH_SPIDI V4 INT.PD 20K V14 PCH_GPIO21
+5VS SPI_MOSI SATA0GP / GPIO21
PCH_SPIDO U3 INT.PH 20K P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 <20>
2
G

INT.PH 20K
QH1 BOOT BIOS Strap Bit 0
1 2 AZ_SYNC_R 3 1 PANTHER-POINT_FCBGA989
<33> AZ_SYNC_HD
RH54 33_0402_5% HM76R3@
S

1 2 BSS138_NL_SOT23-3
RH56 1M_0402_5% 1 @ 2
RH274 0_0402_5%

+3VS

SPI ROM for BIOS & ME (4MByte )

1
1

47P_0402_50V8J UH3
CH19 CH6 8 4
4MB ROM P/N:
@ 0.1U_0402_10V7K VCC VSS
SA00003K800
2

2
B 3 W
B

7
SA00004LI00
HOLD
For RF
PCH_SPICS0# 1 S
PCH_SPICLK 1 2 PCH_SPI0_CLK 6
RH66 33_0402_5% C
PCH_SPIDI 1 2 PCH_SPI0_DI 5 2 PCH_SPI0_DO 1 2 PCH_SPIDO
RH67 33_0402_5% D Q RH68 33_0402_5%
MX25L3205DM2I-12G SO8

Socket: SP07000F500/SP07000H900
Please place U13 & U4 close to U2 PCH,
please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68. +3VS 47P_0402_50V8J For RF +3VALW_PCH +3VALW_PCH +3VALW_PCH
1 2
@ CH20
SPI ROM for Win8 (2MByte )

2
0.1U_0402_10V7K
1 2 RH46 RH45 RH38
UH4 CH100 200_0402_5% 200_0402_5% 200_0402_5%
PCH_SPICS1# 1 8 WIN8@
PCH_SPIDO 1 WIN8@ 2 PCH_SPI1_DO CS# VCC RH267 33_0402_5%
2 7

1
RH269 33_0402_5% +3VS SO HOLD# PCH_SPI1_CLK
3 WP# SCLK 6 1 WIN8@ 2 PCH_SPICLK PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
4 5 PCH_SPI1_DI 1 2 PCH_SPIDI
GND SI

2
RH271 33_0402_5%
MX25L1606EM2I-12G_SO8 WIN8@ RH44 RH39 RH40
WIN8@ 100_0402_1% 100_0402_1% 100_0402_1%
A A
2MB ROM P/N:

1
PCH_SPI0_CLK PCH_SPI1_CLK
for EMI for EMI
SA000041N00
1

RH65
10_0402_5%
SA00003FO10 RH69
10_0402_5%
1
RH50
2 PCH_JTAG_TCK
51_0402_1%
WIN8@
2

CH7
1
CH21
1 Security Classification Compal Secret Data Compal Electronics, Inc.
10P_0402_50V8J 10P_0402_50V8J 2011/12/14 2012/12/31 Title
WIN8@
Issued Date Deciphered Date
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

UH1B
+3VALW_PCH 2 RH72 1 2.2K_0402_5% +3VS
PCIE_PRX_C_LANTX_N1 BG34 2 RH70 1 2.2K_0402_5% RH102 4.7K_0402_5%
<28> PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# QH3B RH103 4.7K_0402_5%
<28> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN <28> PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_N1 AV32
CH11 2 PETN1
<28> PCIE_PTX_C_LANRX_P1 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETP1 SMBCLK H14 PCH_SMBCLK PCH_SMBDATA 3 4 PM_SMBDATA <11,12,27,37>

2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA QH3A 2N7002DW-T/R7_SOT363-6
<27> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34
<27> PCIE_PRX_WLANTX_P2 PERP2
WLAN <27> PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6 1
PETN2 PM_SMBCLK <11,12,27,37>
<27> PCIE_PTX_C_WLANRX_P2 CH17 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2 AY32 PETP2

SMBUS
A12 DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7,11>
BG36 PERN3
BJ36 C8 PCH_SMLCLK0
PERP3 SML0CLK
D AV34 PETN3 D
AU34 G12 PCH_SMLDATA0 +3VALW_PCH 2 RH78 1 2.2K_0402_5% +3VS
PETP3 SML0DATA
<29> PCIE_PRX_C_CRTX_N4 PCIE_PRX_C_CRTX_N4 BF36 2 RH74 1 2.2K_0402_5%
PERN4

5
<29> PCIE_PRX_C_CRTX_P4 PCIE_PRX_C_CRTX_P4 BE36 QH4B
CH18 1 PCIE_PTX_CRRX_N4 PERP4 LAN_EN
Card Reader <29> PCIE_PTX_C_CRRX_N4 2 0.1U_0402_10V7K AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13 LAN_EN <28>
CH16 1 2 0.1U_0402_10V7K PCIE_PTX_CRRX_P4 BB34 PCH_SMLDATA1 3 4
<29> PCIE_PTX_C_CRRX_P4 PETP4 EC_SMB_DA2 <35,36>
E14 PCH_SMLCLK1
SML1CLK / GPIO58

2
PCI-E*
<31> PCIE_PRX_C_USBTX_N5 PCIE_PRX_C_USBTX_N5 BG37 QH4A 2N7002DW-T/R7_SOT363-6
EUSB30@ PCIE_PRX_C_USBTX_P5 PERN5 PCH_SMLDATA1
<31> PCIE_PRX_C_USBTX_P5 BH37 PERP5 SML1DATA / GPIO75 M16
EX-USB30 CH12 1 2 0.1U_0402_10V7K PCIE_PTX_USBRX_N5 AY36 PCH_SMLCLK1 6 1
<31> PCIE_PTX_C_USBRX_N5 PETN5 EC_SMB_CK2 <35,36>
CH9 1 2 0.1U_0402_10V7K PCIE_PTX_USBRX_P5 BB36
<31> PCIE_PTX_C_USBRX_P5 PETP5
EUSB30@ 2N7002DW-T/R7_SOT363-6
<27> PCIE_PRX_C_TVTX_N6 PCIE_PRX_C_TVTX_N6 BJ38
EUSB30@ PCIE_PRX_C_TVTX_P6 PERN6
<27> PCIE_PRX_C_TVTX_P6 BG38 PERP6

Controller
TV tuner CH10 1 2 0.1U_0402_10V7K PCIE_PTX_TVRX_N6 AU36 M7
<27> PCIE_PTX_C_TVRX_N6 PETN6 CL_CLK1
CH1 1 2 0.1U_0402_10V7K PCIE_PTX_TVRX_P6 AV36
<27> PCIE_PTX_C_TVRX_P6 PETP6
EUSB30@ Control Link only for support Intel IAMT.

Link
BG40 PERN7 CL_DATA1 T11
BJ40 PERP7
AY40 +3VALW_PCH
+3VS PETN7
BB40 PETP7 CL_RST1# P10

RH99 1 2 10K_0402_5% PCH_GPIO20 BE38 PERN8

PCH_SMBALERT# RH2621 2 10K_0402_5%
BC38 PERP8
RH1041 2 10K_0402_5% CLKREQ_WLAN# AW38 PETN8
DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
AY38 PETP8
RH95 1 210K_0402_5% CLKREQ_LAN# LAN_EN RH75 1 2 10K_0402_5%
M10 PCH_GPIO47
CLK_LAN# PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 RH73 2
Intel Spec: <28> CLK_LAN# Y40 CLKOUT_PCIE0N 1 2.2K_0402_5%
LAN CLK_LAN Y39
PCIECLK_RQ0# is suspend well, <28> CLK_LAN CLKOUT_PCIE0P
AB37 PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%
CLKOUT_PEG_A_N
but we pull high to +3VS CLKREQ_LAN#

CLOCKS
<28> CLKREQ_LAN# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
PCH_GPIO47 2 1
C for LAN en/disable function RH89 10K_0402_5%
C

CLK_WLAN# AB49 AV22 CLK_CPU_DMI#

<27> CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <5>
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI
<27> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
CLKREQ_WLAN# M1
<27> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
AM12 CLK_CPU_EDP#
CLKOUT_DP_N CLK_CPU_EDP# <5>
AM13 CLK_CPU_EDP 120 MHz for eDP
CLKOUT_DP_P CLK_CPU_EDP <5>
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# PCH_CLK_DMI# RH79 1 2 10K_0402_5%
PCH_GPIO20 CLKIN_DMI_N PCH_CLK_DMI PCH_CLK_DMI RH82 1
V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%

CLKIN_GND1# RH85 1 2 10K_0402_5%

CLK_CR# Y37 CLKIN_GND1_N BJ30 CLKIN_GND1# CLKIN_GND1 RH86 1 2 10K_0402_5%
<29> CLK_CR# CLKOUT_PCIE3N CLKIN_GND1_N
Card Reader <29> CLK_CR Y36 CLKIN_GND1_P BG30 CLKIN_GND1
CLK_CR CLKOUT_PCIE3P CLKIN_GND1_P CLK_DOT# RH80 1 2 10K_0402_5%
CLKREQ_CR# A8 CLK_DOT RH81 1 2 10K_0402_5%
<29> CLKREQ_CR# PCIECLKRQ3# / GPIO25 CLK_DOT#
CLKIN_DOT_96N G24
E24 CLK_DOT From Clock Gen. CLK_SATA# RH83 1 2 10K_0402_5%
CLK_USBA30# CLKIN_DOT_96P CLK_SATA RH84 1
<31> CLK_USBA30# Y43 CLKOUT_PCIE4N 2 10K_0402_5%
CLK_USBA30 Y45
<31> CLK_USBA30 CLKOUT_PCIE4P
EX-USB30 AK7 CLK_SATA# CLK_14M_PCH RH87 1 2 10K_0402_5%
CLKREQ_USBA30# CLKIN_SATA_N CLK_SATA
<31> CLKREQ_USBA30# L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5
For EMI
CLK_TV# V45 K45 CLK_14M_PCH
<27> CLK_TV# CLKOUT_PCIE5N REFCLK14IN
CLK_TV V46 @
<27> CLK_TV CLKOUT_PCIE5P
TV tuner CLK_PCILOOP 2 @ 1 2 1
CLKREQ_TV# CLK_PCILOOP RH124 10_0402_5% CH28 22P_0402_50V8J
<27> CLKREQ_TV# L14 PCIECLKRQ5# / GPIO44 INT. PH 20K CLKIN_PCILOOPBACK H45 CLK_PCILOOP <20>
+3VALW_PCH
AB42 V47 PCH_X1
Please place under DDR SODIMM. CLKOUT_PEG_B_N XTAL25_IN PCH_X2
B AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 B
RH1071 210K_0402_5% CLKREQ_USBA30# 10/25
PASSWORD_CLEAR# E6 RH37
RH1101 CLKREQ_CR# PEG_B_CLKRQ# / GPIO56 PCH_X1
210K_0402_5% <27> PCH_X1_R 1 2
1

JPW Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN 0_0402_5%

RH1121 XCLK_RCOMP
210K_0402_5% CLKREQ_TV# @ V40 CLKOUT_PCIE6N
RH115 90.9_0402_1% GCLK@
V42
2

RH1191 LVDS@ 210K_0402_5% PANEL_SEL CLKOUT_PCIE6P

Placement near to YH2
LVDS_SEL T13 PCIECLKRQ6# / GPIO45
RH1141 210K_0402_5% PASSWORD_CLEAR# INT. PD 20K
V38 K43 CLK_FLEX0 T72 PAD NOGCLK@
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

V37 INT. PD 20K RH1172 1 1M_0402_5%

CLKOUT_PCIE7P CLK_FLEX1
CLKOUTFLEX1 / GPIO65 F47 T74 PAD
PANEL_SEL K12 INT.PH 20K INT. PD 20K NOGCLK@
PCIECLKRQ7# / GPIO46 CLK_FLEX2 YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66 H47 T73 PAD
AK14 CLKOUT_ITPXDP_N INT. PD 20K
AK13 K49 DGPU_PRSNT# PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 1 3
GND GND
1 1
PANTHER-POINT_FCBGA989 Compal common design SW request to CH26 CH27
HM76R3@ NOGCLK@ 2 4 NOGCLK@
add DGPU_Present on this GPIO67 27P_0402_50V8J 27P_0402_50V8J
+3VALW_PCH 2 2

LVDS_SEL PANEL_SEL DGPU_PRSNT#

1 HD@ 2 LVDS_SEL
RH116 10K_0402_5%
LVDS_SEL H L PANEL_SEL H L DGPU_PRSNT# H L
1 FHD@ 2 LVDS_SEL
RH282 10K_0402_5% DGPU_PRSNT# 1 2 +3VS
Single RH227 10K_0402_5%
RH282 Channel Dual Channel LVDS EDP M/B SKU UMA DIS/OPT
10K_0402_5% (Default) 1 @ 2
A 3D@ RH261 10K_0402_5% A

1 IEDP@ 2 PANEL_SEL
RH275 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 17 of 51
5 4 3 2 1
 5 4 3 2 1

UH1C

<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6>
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6>
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW_PCH DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <6>
<6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6>
<6> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
D DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> D
<6> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6>
<6> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
PCH_SUSPWRDN#_R DMI3RXP FDI_CTX_PRX_P0
2 1 FDI_RXP0 BG14 FDI_CTX_PRX_P0 <6>
RH234 10K_0402_5% DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
<6> DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6>
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
RH157 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
<6> DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6>
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4
<6> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6>

DMI
FDI
RH155 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<6> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6>
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
<6> DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
DMI_PTX_CRX_P2 AY18
<6> DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
<6> DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT <6>
RH163 10K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#
2 1 PM_PWROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 RH128 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
RH278 10K_0402_5% RH126 49.9_0402_1%
2 @ 1 SYS_PWROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
RH279 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
RH127 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <6>

0_0402_5% Reserve this signal to EC by SW demand A18 DSWVREN +RTCVCC

DSWVRMEN
1 RH280 2 2011/10/18a

System Power Management

+3VS @ SUSACK#_R PCH_DPWROK DSWVREN RH150 1 330K_0402_5%
<35> SUSACK# 1 2 C12 SUSACK# INT.PH 20K DPWROK E22 2
0.1U_0402_10V7K RH133 0_0402_5%
1 2 RH47 RH151 2 @ 1 330K_0402_5%
CH103 +3VS 2 1 XDP_DBRESET# K3 B9 EC_SWI#
SYS_RESET# WAKE# EC_SWI# <28,31>
5

UH5 1K_0402_5%
C C
1
P

<35,46> VGATE IN1

4 SYS_PWROK P12 N3 PCH_GPIO32 DSWVREN must be always pulled high to +RTCVCC
PM_PWROK O SYS_PWROK CLKRUN# / GPIO32
<5,35> PM_PWROK 2 IN2
G

DSWVREN - Internal Deep Sleep 1.05V regulator

SN74AHC1G08DCKR_SC70-5 PM_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T76 PAD
*
3

@ RH131 0_0402_5% PWROK SUS_STAT# / GPIO61 H：Enable

32.768 KHz L：Disable
L10 APWROK SUSCLK / GPIO62 N14 CLK_EC <35>

DRAMPWROK B13 D10 PM_SLP_S5#

<5> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <35>
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R
RH281 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<35> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <31,35>
Follow EC check list demand,
Stuff R137 if EC does not want to 1 @ 2 PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#
<35> PCH_SUSPWRDN#
RH132 0_0402_5% SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <35> but don't implement CLKRUN# this fuction
involve in the handshake mechanism
for the DeepSX state entry and exit PBTN_OUT# PM_SLP_A# T77 PAD
<35> PBTN_OUT# E20 PWRBTN# INT.PH 20K SLP_A# G10
+3VS

PCH_ACIN PM_SLP_SUS# T78 PAD

+3VALW_PCH 1
RH161
2
330K_0402_5%
H20 ACPRESENT / GPIO31INT.PD 20K SLP_SUS# G16
PCH_GPIO32 RH2561 @ 2 8.2K_0402_5%

DH2 PCH_LOW_BAT# H_PM_SYNC

E10 BATLOW# / GPIO72 INT.PH 20K PMSYNCH AP14 H_PM_SYNC <5>
<35,41> ACIN 1 2 1 2
RH160 10K_0402_5%
Reserve for SW-node noise issue CH751H-40PT_SOD323-2 RI# A10 K14 PCH_GPIO29
RI# SLP_LAN# / GPIO29
place close to PCH
Reserve this signal to EC by SW demand PANTHER-POINT_FCBGA989
B SYS_PWROK HM76R3@ B
1 2 2011/10/18a
CH23 0.01U_0402_25V7K +3VALW_PCH

1 2 PCH_RSMRST#
CH24 0.01U_0402_25V7K EC_SWI# RH1591 2 10K_0402_5%

1 2 PM_PWROK_R
CH25 0.01U_0402_25V7K PCH_GPIO29 RH1621 @ 2 10K_0402_5%
DH5
PM_PWROK 2 1 PCH_RSMRST#

CH751H-40PT_SOD323-2

DH6
<40,42> POK 1 2

CH751H-40PT_SOD323-2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

UH1D
UMA_ENBKL J47 INT.PD 50SDVO_TVCLKINN AP43
<13,35> UMA_ENBKL L_BKLTEN +3VS
UMA_ENVDD M45 INT.PD 50SDVO_TVCLKINP AP45
<13> UMA_ENVDD L_VDD_EN
PCH_PWM P45 INT.PD 50 AM42
<13> PCH_PWM L_BKLTCTL SDVO_STALLN
INT.PD 50
SDVO_STALLP AM40

1
<13> LCD_EDID_CLK LCD_EDID_CLK T40
LCD_EDID_DATA L_DDC_CLK RH140 RH139
<13> LCD_EDID_DATA K47 L_DDC_DATAINT.PD 20K SDVO_INTN AP39
AP40 2.2K_0402_5% 2.2K_0402_5%
LCTL_CLK SDVO_INTP HDMI@ HDMI@
D T45 L_CTRL_CLK D
LCTL_DATA P39

2
L_CTRL_DATA
1 2 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK UMA_HDMI_CLK <15>
RH143 2.37K_0402_1% AF36 M39
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA <15>
1 2 UMA_ENBKL T79 PAD INT.PD 20K
RH125 100K_0402_5% AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
AT40 HDMI_HPD HDMI_HPD 2 1
DDPB_HPD HDMI_HPD <15,21>
LCD_TXCLK- AK39 100K_0402_5%
<13> LCD_TXCLK- LVDSA_CLK#

LVDS
LCD_TXCLK+ AK40 AV42 UMA_HDMI_TX2- RH254
<13> LCD_TXCLK+ LVDSA_CLK DDPB_0N UMA_HDMI_TX2- <15>
AV40 UMA_HDMI_TX2+
+3VS DDPB_0P UMA_HDMI_TX2+ <15>
LCD_TXOUT0- AN48 AV45 UMA_HDMI_TX1-
<13> LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N UMA_HDMI_TX1- <15>
LCD_TXOUT1- AM47 AV46 UMA_HDMI_TX1+
<13> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P UMA_HDMI_TX1+ <15> HDMI

Digital Display Interface

LCD_TXOUT2- AK47 AU48 UMA_HDMI_TX0-
<13> LCD_TXOUT2- LVDSA_DATA#2 DDPB_2N UMA_HDMI_TX0- <15>
2 1 LCTL_CLK AJ48 AU47 UMA_HDMI_TX0+
LVDSA_DATA#3 DDPB_2P UMA_HDMI_TX0+ <15>
RH145 2.2K_0402_5% AV47 UMA_HDMI_TXC-
DDPB_3N UMA_HDMI_TXC- <15>
LCD_TXOUT0+ AN47 AV49 UMA_HDMI_TXC+
<13> LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P UMA_HDMI_TXC+ <15>
2 1 LCTL_DATA LCD_TXOUT1+ AM49
<13> LCD_TXOUT1+ LVDSA_DATA1
RH146 2.2K_0402_5% LCD_TXOUT2+ AK49
<13> LCD_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 1 LCD_EDID_CLK P42
RH149 2.2K_0402_5% DDPC_CTRLDATA
INT.PD 20K
LCD_TZCLK- AF40
<13> LCD_TZCLK- LVDSB_CLK#
2 1 LCD_EDID_DATA LCD_TZCLK+ AF39 AP47
<13> LCD_TZCLK+ LVDSB_CLK DDPC_AUXN
RH148 2.2K_0402_5% AP49
LCD_TZOUT0- DDPC_AUXP RH141
<13> LCD_TZOUT0- AH45 LVDSB_DATA#0 DDPC_HPD AT38 2 1 100K_0402_5%
2 1 UMA_CRT_CLK LCD_TZOUT1- AH47
<13> LCD_TZOUT1- LVDSB_DATA#1
C RH142 2.2K_0402_5% LCD_TZOUT2- AF49 AY47 C
<13> LCD_TZOUT2- LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
2 1 UMA_CRT_DATA AY43
RH144 2.2K_0402_5% LCD_TZOUT0+ DDPC_1N
<13> LCD_TZOUT0+ AH43 LVDSB_DATA0 DDPC_1P AY45
LCD_TZOUT1+ AH49 BA47
<13> LCD_TZOUT1+ LVDSB_DATA1 DDPC_2N
LCD_TZOUT2+ AF47 BA48
<13> LCD_TZOUT2+ LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

UMA_CRT_B N48 M43

<14> UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
1 2 UMA_CRT_B UMA_CRT_G P49 M36
<14> UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
RH156 150_0402_1% UMA_CRT_R T49 INT.PD 20K
<14> UMA_CRT_R CRT_RED
1 2 UMA_CRT_G AT45
DDPD_AUXN

CRT
RH152 150_0402_1% <14> UMA_CRT_CLK UMA_CRT_CLK T39 AT43
UMA_CRT_DATA CRT_DDC_CLK DDPD_AUXP RH255
<14> UMA_CRT_DATA M40 CRT_DDC_DATA DDPD_HPD BH41 2 1 100K_0402_5%
1 2 UMA_CRT_R
RH154 150_0402_1% BB43
UMA_CRT_HSYNC DDPD_0N
<14> UMA_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
UMA_CRT_VSYNC M49 BF44
<14> UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
DDPD_2N BF42
2 1 CRT_IREF T43 BE42
RH138 1K_0402_0.5% DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
PANTHER-POINT_FCBGA989
HM76R3@
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

UH1E

RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
AH38 TP6
D D
AH37 TP7 RSVD7 AU2
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
C18 TP10 RSVD10 AT1
N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
+3VS Y13 BA3
TP16 RSVD16
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
1 2 PCH_GPIO54 AB45 BE8
TP20 RSVD20

RSVD
RH318 8.2K_0402_5% BD4
PCH_GPIO4 RSVD21
1 2 RSVD22 BF6
RH319 8.2K_0402_5%
1 2 PCI_PIRQB# B21 AV5 NV_ALE
RH320 8.2K_0402_5% TP21 RSVD23
M20 TP22 AV10
1 2 PCI_PIRQC# AY16 TP23
DF_TVS RSVD24
RH321 8.2K_0402_5% BG46 AT8
PCH_GPIO52 TP24 RSVD25
1 2
RH324 8.2K_0402_5% AY5
PCH_GPIO53 RSVD26
1 2 RSVD27 BA2
RH323 8.2K_0402_5% U3RXDN1_R BE28
<30> U3RXDN1_R USB3Rn1
1 2 PCI_PIRQA# U3RXDN2_R BC30 AT12
<30> U3RXDN2_R USB3Rn2 RSVD28
RH325 8.2K_0402_5% U3RXDN3_R BE32 BF3
<25> U3RXDN3_R USB3Rn3 RSVD29
1 2 ODD_DA# U3RXDN4_R BJ32
<25> U3RXDN4_R USB3Rn4
RH322 8.2K_0402_5% U3RXDP1_R BC28
<30> U3RXDP1_R USB3Rp1
1 2 PCH_GPIO55 U3RXDP2_R BE30
<30> U3RXDP2_R USB3Rp2
RH326 8.2K_0402_5% U3RXDP3_R BF32 INT.PD 20K
<25> U3RXDP3_R USB3Rp3
1 2 PCH_GPIO2 U3RXDP4_R BG32 C24 USB20_N0
C <25> U3RXDP4_R USB3Rp4 USBP0N USB20_N0 <30> C
RH327 8.2K_0402_5% U3TXDN1 AV26 A24 USB20_P0 USB-RIGHT1 Intel Anti-Theft Techonlogy
<30> U3TXDN1 USB3Tn1 USBP0P USB20_P0 <30>
1 2 PCH_GPIO50 U3TXDN2 BB26 C25 USB20_N1
<30> U3TXDN2 USB3Tn2 USBP1N USB20_N1 <30>
RH328 8.2K_0402_5% U3TXDN3 AU28 B25 USB20_P1 USB-RIGHT2 High=Endabled
<25> U3TXDN3 USB3Tn3 USBP1P USB20_P1 <30>
1 2 RF_OFF# U3TXDN4 AY30 C26 USB20_N2 NV_ALE
<25> U3TXDN4 USB3Tn4 USBP2N USB20_N2 <25>
RH329 8.2K_0402_5% U3TXDP1 AU26 A26 USB20_P2 USB-Left1 Low=Disable(floating)
1 2 PCI_PIRQD# <30> U3TXDP1
<30> U3TXDP2
U3TXDP2 AY26
USB3Tp1
USB3Tp2
USBP2P
USBP3N K28 USB20_N3
USB20_P2
USB20_N3
<25>
<25>
*
RH283 8.2K_0402_5% U3TXDP3 AV28 H28 USB20_P3 USB-Left2
<25> U3TXDP3 USB3Tp3 USBP3P USB20_P3 <25> +1.8VS
1 2 PCH_GPIO5 U3TXDP4 AW30 EHCI 1 E28
RH290 8.2K_0402_5% <25> U3TXDP4 USB3Tp4 USBP4N
USBP4P D28
C28 NV_ALE 1 @ 2
USBP5N RH164 1K_0402_5%
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 <26>
PCI_PIRQD# G38 K30 USB20_P8 Finger Printer
PIRQD# USBP8P USB20_P8 <26>
G30 USB20_N9
USBP9N USB20_N9 <27>
PCH_GPIO50 C46 E30 USB20_P9 WiMax
REQ1# / GPIO50 USBP9P USB20_P9 <27>

USB
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <27>
PCH_GPIO54 E40 EHCI 2 A30 USB20_P10 TV Tuner #1
REQ3# / GPIO54 USBP10P USB20_P10 <27>
L32 USB20_N11
USBP11N USB20_N11 <13>
RF_OFF# USB20_P11
<27> RF_OFF#
PCH_GPIO53
D47 GNT1# / GPIO51INT.PH 20K USBP11P K32
USB20_N12
USB20_P11 <13> Int. Camera
E42 GNT2# / GPIO53INT.PH 20K USBP12N G32 USB20_N12 <27>
PCH_GPIO55 USB20_P12
F46 GNT3# / GPIO55INT.PH 20K USBP12P E32
USB20_N13
USB20_P12 <27> 3G/ TV tuner #2
USBP13N C32 USB20_N13 <13>
A32 USB20_P13 Glasses free 3D Panel
USBP13P USB20_P13 <13>
PCH_GPIO2 G42
ODD_DA# PIRQE# / GPIO2
<25> ODD_DA# G40 PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# RH165 22.6_0402_1%
D44 PIRQH# / GPIO5
B
Within 500 mils B
USBRBIAS B33
T80 PAD PCI_PME# K10 PME#
PLT_RST# INT.PH 20K USB_OC#0
<5,27,28,29,31,35,36> PLT_RST# C6 PLTRST# OC0# / GPIO59 A14 USB_OC#0 <30,35> USB-Right
USB_OC#1
OC1# / GPIO40 K20 USB_OC#1 <25,31,35>USB-Left & eSATA
B17 USB_OC#2
OC2# / GPIO41
<35> CLK_PCI_EC
22_0402_5% 1 2 RH167 CLK_EC_R H49 INT.PD
CLKOUT_PCI0 20K OC3# / GPIO42 C16 SLP_CHG_M3
SLP_CHG_M3 <25>
22_0402_5% 1 2 RH166 CLK_PCH H43 INT.PD 20K L16 SLP_CHG_M4
<17> CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43 SLP_CHG_M4 <25> +3VALW_PCH
<36> CLK_PCI_DDR
22_0402_5% 1 2 RH284 CLK_SIO J48 INT.PD
CLKOUT_PCI2 20K OC5# / GPIO9 A16 USB_OC#5
K42 INT.PD 20K D14 USB30_SMI#
CLKOUT_PCI3 OC6# / GPIO10
1

H40 INT.PD 20K C14 USBA30_SMI#

CLKOUT_PCI4 OC7# / GPIO14 USBA30_SMI# <31>
CH22 USB30_SMI# 1 2
47P_0402_50V8J RH209 10K_0402_5%
2

@ @ PANTHER-POINT_FCBGA989 SLP_CHG_M3 1 2
2 1 ODD_DA# HM76R3@ RH196 10K_0402_5%
180P_0402_50V8J CH15 SLP_CHG_M4 1 2
RH200 10K_0402_5%
USB_OC#1 1 2
by ESD requestion and place near CPU RH192 10K_0402_5%
Boot BIOS Strap
RF_OFF# PCH_GPIO19 Boot BIOS Loaction
@ USB_OC#2 1 2
0.1U_0402_10V7K 1 CH104 PLT_RST# LPC RH177 10K_0402_5%
2 0 0 USB_OC#5 1 2
Reserved RH183 10K_0402_5%
0 1 USBA30_SMI# 1 2
PCI RH201 10K_0402_5%
1 0 USB_OC#0 1 2
SPI RH188 10K_0402_5%
1K_0402_5% 2 @ 1 RH285 RF_OFF# 1 1 *
A 1K_0402_5% 2 @ A
1 RH286 PCH_GPIO19
PCH_GPIO19 <16>

A16 Swap Override Strap

Low= A16 swap override Enable
WL_OFF# * High= A16 swap override Disable
Security Classification Compal Secret Data Compal Electronics, Inc.
1K_0402_5% 2 @ 1 RH287 PCH_GPIO55 2011/12/14 2012/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW_PCH UH1F
INT.PH 20K ODD_EN# 1 2
HDMI_HPD T7 C40 ODD_EN# RH288 10K_0402_5%
<15,19> HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <38>
2 1 EC_LID_OUT# INT.PH 20K GATEA20 1 2
RH204 1K_0402_5% PCH_GPIO1 RH182 10K_0402_5%
EC_SMI#
A42 TACH1 / GPIO1INT.PH 20K TACH5 / GPIO69 B41
KB_RST#
1 2 INT.PH 20K 1 2
RH205 10K_0402_5% PCH_GPIO6 RH184 10K_0402_5%
PCH_GPIO12
H36 TACH2 / GPIO6INT.PH 20K TACH6 / GPIO70 C41
1 2 INT.PH 20K
RH289 10K_0402_5% EC_SCI# 3D_DET#
PCH_GPIO28
<35> EC_SCI# E38 TACH3 / GPIO7INT.PH 20K TACH7 / GPIO71 A40
D 1 2 D
RH202 10K_0402_5% EC_SMI#
HDD2_DET#
<35> EC_SMI# C10 GPIO8INT.PH 20K
1 2
RH207 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS EC_LID_OUT# GATEA20
<35> EC_LID_OUT# G2 INT.PD
GPIO15 20K A20GATE P4 GATEA20 <35>
INT.PD 350 PECI AU16
1 2 BT_ON# PCH_GPIO16 U2
RH180 10K_0402_5% SATA4GP / GPIO16 KB_RST#
RCIN# P5 KB_RST# <35>
1 @ 2 HDMI_HPD

GPIO
RH292 10K_0402_5% PCH_GPIO17 D40 INT.PH 20K AY11 H_PWRGOOD
TACH0 / GPIO17 PROCPWRGD H_PWRGOOD <5>

CPU/MISC
1 2 PCH_GPIO1
RH190 10K_0402_5% BT_DET# T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <5>
1 2 BT_DET# RH191 390_0402_5%
RH185 10K_0402_5% E8 INT.PH 20K T14
OPTIMUS_EN# GPIO24 INIT3_3V#
1 2
RH193 10K_0402_5% PCH_GPIO27 E16 INT.PH 20K INT.PD 20K AY1 NV_CLE This signal has weak internal
ODD_DETECT# GPIO27 DF_TVS RH203
1 2
RH178 200K_0402_5% PCH_GPIO28 P8 INT.PH 20K pull-up, can't be pulled low 10K_0402_5%
PCH_GPIO6 GPIO28 OPTHD@
1 2 TS_VSS1 AH8
RH197 10K_0402_5% BT_ON# K1 +3VS
<27> BT_ON# STP_PCI# / GPIO34
1 2 PCH_GPIO16 AK11 OPTFHD@
RH179 10K_0402_5% PCH_GPIO35 TS_VSS2 3D_DET#
T81 PAD K4 GPIO35 1 2
1 2 EC_SCI# AH10 RH203 10K_0402_5%
RH293 10K_0402_5% ODD_DETECT# TS_VSS3 3D@
<25> ODD_DETECT# V8 INT.PD
SATA2GP / GPIO36 20K
1 2 CIR_EN# AK10 1 2
RH194 100K_0402_5% PCH_GPIO37 TS_VSS4 RH304 10K_0402_5%
M5 INT.PD
SATA3GP / GPIO37 20K
1 @ 2 ISDBT_DET
C RH181 10K_0402_5% OPTIMUS_EN# N2 P37 C
PCH_GPIO49 SLOAD / GPIO38 NC_1
1 2
RH195 10K_0402_5% CIR_EN# M3
PCH_GPIO17 SDATAOUT0 / GPIO39
1 2
RH186 10K_0402_5% <27> ISDBT_DET ISDBT_DET V13 BG2 @
SDATAOUT1 / GPIO48 VSS_NCTF_15 PCH_THRMTRIP# 2 1
PCH_GPIO49 V3 BG48 CH30 1000P_0402_50V7K
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
HDD2_DET# D6 BH3
GPIO57 VSS_NCTF_17

VSS_NCTF_18 BH47 12/20 for ESD request

2 1 PCH_GPIO37
RH198 100K_0402_5% A4 BJ4
@ PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
2 1
RH199 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
2 CIR@ 1 CIR_EN# Follow Compal ORB
RH296 10K_0402_5% and Intel Check list 460603 V1.5 A45 BJ45
ISDBT_DET VSS_NCTF_3 VSS_NCTF_21
1 2

NCTF
RH297 47K_0402_5% A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2 DMI & FDI Termination Voltage

B47 VSS_NCTF_8 VSS_NCTF_26 C48
Set to VCC when HIGH
B
BD1 VSS_NCTF_9 VSS_NCTF_27 D1 NV_CLE B
GPIO28 Set to VSS when LOW
3D_DET# BD49 VSS_NCTF_10 VSS_NCTF_28 D49
On-Die PLL Voltage Regulator
BE1 E1
* H: Enable 3D_DET# H L
VSS_NCTF_11 VSS_NCTF_29 +1.8VS
L: Disable BE49 VSS_NCTF_12 VSS_NCTF_30 E49

1
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
RH206 1 @ 2 1K_0402_5% PCH_GPIO28 SKU Non3D 3D RH187
BF49 VSS_NCTF_14 VSS_NCTF_32 F49 2.2K_0402_5%

2
PANTHER-POINT_FCBGA989
HM76R3@ NV_CLE 2 1 H_SNB_IVB# <5>
RH189 1K_0402_5%

GPIO8 OPTIMUS_EN# HDD2_DET#

Integrated Clock Chip Enable (Removed)
H: Disable OPTIMUS_EN# H L HDD2_DET# H L
* L: Enable
SKU NonOPT Optimus SKU ONE HDD TWO HDD
RH298 1 @ 2 1K_0402_5% EC_SMI#

A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 21 of 51
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCP UH1G POWER +3VS

PJ4 @ 1300mA RH299 LH1 PCH Power Rail Table

2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 1 2+VCCA_DAC_R2 1
2 1
AC23
VCCCORE[1] 1mA VCCADAC
1 1 1_0603_1% BLM18PG181SN1D_0603 Refer to PCH EDS R1.0
JUMP_43X118 VCCCORE[2] CH35 CH36 CH37
1 1 1 1 AD21

CRT
CH32 CH33 CH31 CH34 VCCCORE[3] 0.01U_0402_25V7K 10U_0603_6.3V6M
AD23 VCCCORE[4] VSSADAC U47 S0 Iccmax
D Voltage Rail Voltage D
AF21 Current (A)

VCC CORE
10U_0603_6.3V6M VCCCORE[5] 2 2
AF23 VCCCORE[6]
2 2 2 2 +3VS
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V_PROC_IO 1.05 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 2
VCCCORE[9] VCCALVDS RH208 0_0603_5%
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 V5REF 5 0.001
AG29 VCCCORE[12]
AJ23 VCCCORE[13] +1.8VS

LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 V5REF_Sus 5 0.001
AJ27 LH2
VCCCORE[15] +VCCTX_LVDS 0.01U_0402_25V7K
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 2 1
AJ31 1 BLM18PG181SN1D_0603 Vcc3_3 3.3 0.228
+1.05VS_PCH VCCCORE[17] CH40
60mA VCCTX_LVDS[3] AP36
CH38 CH39 22U_0805_6.3V6M
VCCTX_LVDS[4] AP370.01U_0402_25V7K VccADAC 3.3 0.063
2
AN19 VCCIO[28]
VccADPLLA 1.05 0.08
+3VS
This pin can be left as NC if PAD T82 BJ22 VCCAPLLEXP
On-Die VR is enabled (Default) V33 VccADPLLB 1.05 0.08
VCC3_3[6]

HVCMOS
AN16 VCCIO[15]
1
AN17 CH42 VccCore 1.05 1.7
VCCIO[16] 0.1U_0402_10V7K
VCC3_3[7] V34
2 VccDMI 1.1 0.047
AN21 VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 RH221
VCCIO[18] 0_0603_5% VccIO 1.05 3.711
+VCCAFDI_VRM
C
AN27 VCCIO[19] 3709mA VCCVRM[3] AT16 1 2
C
+1.05VS_PCH AP21 +VCCP_VCCDMI RH213 +1.05VS_VCCP VccASW 1.05 0.903
VCCIO[20] 0_0603_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VccSPI 3.3 0.01
+1.05VS_PCH

DMI
1 1 1 1 1 AP24 VCCIO[22]

VCCIO
CH43 CH45 CH46 CH47 CH44 RH214 CH48
AP26 VCCIO[23] 75mA VCCCLKDMI AB36 +1.05VS_VCC_DMI 2 1 1U_0402_6.3V6K VccDSW 3.3 0.001
10U_0603_6.3V6M 1U_0402_6.3V6K 0_0805_5% 2
2 2 2 2 2 1
AT24 VCCIO[24] CH49 VccDFTERM 1.8 0.002
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
AN33 VCCIO[25]
VccRTC 3.3 N/A
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCDFTERM[1]
VccSus3_3 3.3 0.095
BH29 VCC3_3[3] VCCDFTERM[2] AG17

DFT / SPI
1 1
CH50 190mA VccSusHDA 3.3 0.01
0.1U_0402_10V7K AJ16 CH51
VCCDFTERM[3] 0.1U_0402_10V7K
2 +VCCAFDI_VRM 2 VccVRM 1.5 0.167
AP16 VCCVRM[2]
VCCDFTERM[4] AJ17
This pin can be left as NC if
PAD T83 BG6 VccAFDIPLL
VccCLKDMI 1.05 0.07
On-Die VR is enabled (Default) +3VS

+1.05VS_PCH AP17 VCCIO[27]

VccSSC 1.05 0.095
V1
FDI

20mA VCCSPI
+VCCP_VCCDMI AU20 VCCDMI[2] 1 VccDIFFCLKN 1.05 0.055
B B
CH53
PANTHER-POINT_FCBGA989 1U_0402_6.3V6K VccALVDS 3.3 0.001
HM76R3@ 2

VccTX_LVDS 1.8 0.04

+3VALW to +3V_PCH
Vgs=-4.5V,Id=3A,Rds<97mohm
+3VALW +3VALW_PCH
PJ2
@
2 2 1 1

JUMP_43X79

QH2 AO3413_SOT23
S

3 1
0.1U_0402_10V7K~D

0.01U_0402_25V7K

0.1U_0402_10V7K~D
G
2

20K_0402_5%~D

1 1
1
CH102
CH99

1
CH98

RH1

@
2 2
RH3 2
2

A PCH_PWR_EN# 2 A
<23,28,38> PCH_PWR_EN# 1
47K_0402_5%
0.1U_0402_25V6

1
CH97

@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 22 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS +5VALW JUMP_43X39 +5VALW_PCH

@ PJ5
LH5 2 1
+3VS_VCC_CLKF33 2 1
1 2
10UH_LB2012T100MR_20% 1 1 This pin can be left as NC if QH6
CH73 CH74 On-Die VR is enabled (Default) AO3413_SOT23
+3VALW_PCH

D
10U_0603_6.3V6M 1U_0402_6.3V6K 3 1
2 2 UH1J POWER +1.05VS_PCH

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

20K_0402_5%~D
PAD

1
G
1 T84 AD49 N26 1 1

2
VCCACLK VCCIO[29]

RH228
CH55 1

CH80

CH59
D 0.1U_0402_10V7K @ @ D
VCCIO[30] P26
T16 CH56
@ 2 VCCDSW3_3 3mA 1U_0402_6.3V6K 2 2
"@" Avoid leakage P28

2
CH58 VCCIO[31] 2 RH330
2 1 +PCH_VCCDSW V12 T27 2 1
DCPSUSBYP VCCIO[32] <22,28,38> PCH_PWR_EN#
47K_0402_5%
0.1U_0402_10V7K T29
+3VS_VCC_CLKF33 VCCIO[33] +3VALW_PCH
T38 VCC3_3[5]

VCCSUS3_3[7] T23
This pin can be left as NC if PAD T85 BH23 1
VCCAPLLDMI2 CH60 +3VALW_PCH
119mA VCCSUS3_3[8] T24
On-Die VR is enabled (Default) +1.05VS_PCH AL29 0.1U_0402_10V7K
VCCIO[14]
VCCSUS3_3[9] V23
2

USB
1
+VCCSUS AL24 V24 Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
DCPSUS[3] VCCSUS3_3[10] CH61
1
CH54 P24 0.1U_0402_10V7K
1U_0402_6.3V6K VCCSUS3_3[6] 2
@ AA19
+1.05VS_PCH 2 VCCASW[1] +5VALW_PCH +3VALW_PCH
VCCIO[34] T26 +1.05VS_PCH
AA21 VCCASW[2] 1010mA

2
AA24 1mA M26 +PCH_V5REF_SUS
VCCASW[3] V5REF_SUS RH232 DH3
1 1 AA26 @ 10_0402_5%

Clock and Miscellaneous

CH64 CH65 VCCASW[4] +VCCA_USBSUS CH62 1
DCPSUS[4] AN23 2 1U_0402_6.3V6K CH751H-40PT_SOD323-2
AA27

1
22U_0805_6.3V6M VCCASW[5] +PCH_V5REF_SUS
VCCSUS3_3[1] AN24 +3VALW_PCH
2 2
AA29 VCCASW[6] 1
22U_0805_6.3V6M 1 2 CH63
AA31 CH66 0.1U_0402_10V7K
C VCCASW[7] 0.1U_0402_10V7K C
1U_0402_6.3V6K +PCH_V5REF_RUN 2
AC26 VCCASW[8] P34
1 1 1
1mA V5REF +3VALW_PCH
CH67 CH68 CH69 AC27
+1.05VS_PCH VCCASW[9]
VCCSUS3_3[2] N20

PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K AC29 1
LH7 BLM18PG181SN1D_2P 2 2 2 VCCASW[10] CH70
VCCSUS3_3[3] N22
+1.05VS_VCCADPLLA 1U_0402_6.3V6K +5VS +3VS
1 2 AC31 VCCASW[11]
CH63 & CH71 are
VCCSUS3_3[4] P20 different by Intel CRB.
LH8 BLM18PG181SN1D_2P 2
AD29 VCCASW[12]

2
1 2 +1.05VS_VCCADPLLB P22
CH93 CH95 VCCSUS3_3[5] +3VS RH237 DH4
AD31 VCCASW[13]
1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 10_0402_5%
1 1 W21 AA16 CH751H-40PT_SOD323-2
VCCASW[14] VCC3_3[1]
1

1
+3VS CH72 +PCH_V5REF_RUN
W23 VCCASW[15] VCC3_3[8] W16
2 2 0.1U_0402_10V7K
2 CH94 2 CH96 1
W24 VCCASW[16] VCC3_3[4] T34
1U_0402_6.3V6K 1U_0402_6.3V6K 2 CH71
W26 1 2 1U_0603_10V6K
VCCASW[17] CH75 2
0.1U_0402_10V7K +3VS
W29 VCCASW[18]
W31 VCCASW[19] VCC3_3[2] AJ2
+1.05VS_PCH +1.05VS_SATA3 +1.05VS_PCH
1
RH244 W33 RH242
+VCCDIFFCLK VCCASW[20] CH76
2 1 VCCIO[5] AF13 2 1
0.1U_0402_10V7K
0_0603_5% +VCCRTCEXT 2 0_0805_5%
1 N16 DCPRTC 1
CH79 1 AH13 CH77
1U_0402_6.3V6K CH78 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
B 2 VCCVRM[4] VCCIO[13] 2 B
2

VCCIO[6] AF14
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA BD47 VCCADPLLA 80mA This pin can be left as NC if

SATA
RH247 AK1 T86 PAD
+1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLB VCCAPLLSATA +VCCAFDI_VRM On-Die VR is enabled (Default)
2 1 BF47 VCCADPLLB
1
80mA
0_0603_5% CH81 AF11 +VCCAFDI_VRM
1U_0402_6.3V6K +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
AF17 VCCIO[7] 55mA
AF33 RH246
2 VCCDIFFCLKN[1] +1.05VS_VCC_SATA
AF34 VCCDIFFCLKN[2] VCCIO[2] AC16 2 1
+1.05VS_VCCDIFFCLKN AG34 0_0805_5%
+1.05VS_PCH VCCDIFFCLKN[3]
VCCIO[3] AC17 1
CH82
AG33 AD17 1U_0402_6.3V6K
VCCSSC 95mA VCCIO[4]
1 2
CH84
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 RH3002 1 0_0402_5%
CH85 DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]
2
MISC

+1.05VS_VCCP V21 +VCCME_23 RH3012 1 0_0402_5%

RH249 VCCASW[23]
+1.05VS_PCH
1mA
CPU

1 2 0.1U_0402_10V7K +V_CPU_IO BJ8

RH303 @ V_PROC_IO +VCCME_21 RH3022
VCCASW[21] T19 1 0_0402_5%
2 1 +1.05VM_VCCSUS 0_0603_5% 1 1 1
CH87 CH88 +RTCVCC
0_0603_5% CH86 +3VALW_PCH
1
CH83 4.7U_0603_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32
RTC

2 2 2 VCCRTC VCCSUSHDA
HDA

1U_0402_6.3V6K
A @ A
2 1 1 1 1
CH89 CH90 CH91 PANTHER-POINT_FCBGA989 CH92
HM76R3@ 0.1U_0402_10V7K
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 23 of 51
5 4 3 2 1
 5 4 3 2 1

UH1I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
UH1H B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
D D
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
C C
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
B B
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
PANTHER-POINT_FCBGA989 G28
HM76R3@ VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]

PANTHER-POINT_FCBGA989
HM76R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 24 of 51
5 4 3 2 1
 5 4 3 2 1

SATA HDD SATA ODD Conn

Conn. +5VS
Place closely JHDD SATA CONN.
1.2A

1 1 1 1 JODD
C356 C357 C358 C359
10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 1
GND SATA_PTX_C_DRX_P2 C376 1
A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 <16>
2 2 2 2 SATA_PTX_C_DRX_N2 C377 1
A- 3 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 <16>
GND 4
5 SATA_PRX_DTX_N2 C378 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N2 <16>
6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P2 <16>
D GND 7 D

JHDD
Close to JHDD 8
DP ODD_DETECT# <21> +5VS_ODD
+5V 9 +5VS_ODD Place components closely ODD CONN.
GND 1 +5V 10 1.1A
2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K 11 ODD_DA#
A+ SATA_PTX_DRX_P0 <16> MD ODD_DA# <20>
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K 15 12 1 1 1 1 1
A- SATA_PTX_DRX_N0 <16> GND GND
4 14 13 C355 C354 C379
GND SATA_PRX_DTX_N0 C368 1 GND GND
B- 5 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N0 <16>
@ C380 C360
6 SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V6K 0.1U_0402_10V7K
B+ SATA_PRX_C_DTX_P0 <16> 2 2 2 2 2
7 SANTA_204901-1
GND @ 0.1U_0402_10V7K

V33 8 +3VS
V33 9
V33 10
GND 11
12
GND
GND 13
14
USB Right-Side U3TXDP4_C_L 9
JUSBRR
V5 +5VS SSTX+
V5 15 +USB_VCCA 1 VBUS
16 +USB_VCCA U3TXDN4_C_L 8
V5 USB20_N3_S_R SSTX-
GND 17
+5VALW W=80mils W=80mils 2 D-
18 7
23 GND
Reserved
GND 19 2.5A +USB_VCCA
For EMI 0.1U_0402_10V7K 4.7U_0805_10V4Z USB20_P3_S_R 3
GND
D+ GND 10
24 20 U14 1 U3RXDP4 6 11 W=80mils
GND V12 SSRX+ GND
V12 21 2 IN OUT 6 2 1 1 1 1 4 GND GND 12
22 3 7 C361 1000P_0402_50V7K + C897 C898 C899 C365 U3RXDN4 5 13 USB0_GND
V12 IN OUT @ SSRX- GND
<31,35> USB_CHG_EN# 4 EN/ENB OUT 8

C894
1 5 USB_OC#1 <20,31,35> OCTEK_USB-09EAEB 2
SANTA_190501-1 GND OCB 2 2 2 2 @ 0_0603_5% 0_0603_5%
1
@ SY6288DCAC_MSOP8 R1445
C SA00004KB00 C362 220U_6.3V_M_R15 1000P_0402_50V7K R1444 C
1

0.1U_0402_10V7K
4.7U_0805_10V4Z

2
SA00003TV00 2 @

USB Sleep & Charge Auto-Mode/Mode3 W=80mils

+USB_VCCC
W=80mils U3TXDP3_C_L 9
JUSBRF

+5VALW SSTX+
1
MAX14600 & MAX14617 2.5A +USB_VCCC
For EMI 0.1U_0402_10V7K
+USB_VCCC
U3TXDN3_C_L 8
VBUS
SSTX-
U15 1 USB20_N2_S_R 2 D-
CB0 CB1 CB2 2 IN OUT 6 2 1 1 1 7 GND
STATUS 3 7 C363 1000P_0402_50V7K + C911 C900 C901 USB20_P2_S_R 3 10
SLP_CHG_M4 SLP_CHG_M3 (14617 only) USB_CHG_EN# IN OUT U3RXDP3 D+ GND
4 EN/ENB OUT 8
USB_OC#1
6 SSRX+ GND 11 W=80mils
1 GND OCB 5 4 GND GND 12
2 2 2 U3RXDN3 USB1_GND
0 0 0 AUTO MODE 1 5 SSRX- GND 13
SY6288DCAC_MSOP8

C902
Force Dedicated charger mode SA00004KB00 C364 220U_6.3V_M_R15 1000P_0402_50V7K OCTEK_USB-09EAEB 2
1 4.7U_0805_10V4Z @ 0_0603_5% 0_0603_5%
0 0 (MODE3) SA00003TV00 2 @ R1447
Pass-Through (USB) Mode: R1446
1

0.1U_0402_10V7K
1 0 0 Connect DP/DM to TDP/TDM

2
Pass-Through (USB) Mode with CDP Emulation:
1 @2 R1448 U3RXDP4
1 1 0 Auto Connect DP/DM to TDP/TDM depending on CDP status <20> U3RXDP4_R 0_0402_5% U3RXDP4 <31>
KINGCORE WCM-2012HS-670T
Force Apple 2A Charger Mode: Apple 2A resistor dividers 1 2 R73 0_0402_5%
X X 1 1 2 @
1 2

4 3 L53
R1458 0_0402_5% IUSB30@ 4 3 USB20_P3_S USB20_P3_S_R
3 3 4 4
US20_N3 1 2 USB20_N3 L56 IUSB30@
USB20_N3 <20>
R1459 0_0402_5% IUSB30@ 1 2 R1449 U3RXDN4 D87 @
US20_P3 1 2 USB20_P3 <20> U3RXDN4_R @ 0_0402_5% U3RXDN4 <31> U3TXDP4_C_L 1 1 109 U3TXDP4_C_L USB20_N3_S 2 1 USB20_N3_S_R
USB20_P3 <20> 2 1
B B
R1462 0_0402_5% U3TXDP4 1 2U3TXDP4_C 1 @2 R1450 U3TXDP4_C_L U3TXDN4_C_L 2 2 98 U3TXDN4_C_L WCM-2012-900T_0805
<20> U3TXDP4 C903 0.1U_0402_10V7K U3TXDP4_C_L <31>
1EUSB30@ 2 U2D_DN3 U2D_DN3 <31> 0_0402_5%
R1463 0_0402_5% KINGCORE WCM-2012HS-670T U3RXDP4 4 4 77 U3RXDP4 1 @ 2
1EUSB30@ 2 U2D_DP3 U2D_DP3 <31> 1 2 R87 0_0402_5%
1 2 U3RXDN4 5 5 66 U3RXDN4
R77 0_0402_5%
4 4 3 3 3 3 1 @ 2

R1460 0_0402_5% IUSB30@ L57 IUSB30@ 8 L54

US20_N2 1 2 USB20_N2 USB20_N2 <20> U3TXDN4 1 2U3TXDN4_C 1 2 R1451 U3TXDN4_C_L USB20_P2_S 3 4 USB20_P2_S_R
<20> U3TXDN4 C904 0.1U_0402_10V7K U3TXDN4_C_L <31> 3 4
R1461 0_0402_5% IUSB30@ @ 0_0402_5% YSCLAMP0524P_SLP2510P8-10-9
US20_P2 1 2 USB20_P2 USB20_P2 <20>
USB20_N2_S 2 1 USB20_N2_S_R
R1464 0_0402_5% 2 1
1EUSB30@ 2 U2D_DN2 U2D_DN2 <31> WCM-2012-900T_0805
R1465 0_0402_5% 1 @2 R1452 U3RXDP3
1EUSB30@ 2 U2D_DP2 <20> U3RXDP3_R 0_0402_5% U3RXDP3 <31> D88 @ 1 @ 2
U2D_DP2 <31>
KINGCORE WCM-2012HS-670T U3TXDP3_C_L 1 1 109 U3TXDP3_C_L R88 0_0402_5%
1 1 2 2
U3TXDN3_C_L 2 2 98 U3TXDN3_C_L

U5 4 U3RXDP3 4 4 77 U3RXDP3
SLP_CHG_CB2 SLP_CHG_M4 4 3 3
1 14617@ 2 1 CEN CB0 8 SLP_CHG_M4 <20> D85 @
R1470 USB20_N3_S 2 7 US20_N3 L58 IUSB30@ U3RXDN3 5 5 66 U3RXDN3 USB20_P3_S_R 3
0_0402_5% USB20_P3_S DM TDM US20_P3 3
3 DP TDP 6 1 2 R1453 U3RXDN3
1 1
SLP_CHG_M3 4 5 <20> U3RXDN3_R @ 0_0402_5% U3RXDN3 <31> 3 3 USB20_N3_S_R 2
<20> SLP_CHG_M3 CB1 VCC +5VALW 2
9 PGND 1
C892 U3TXDP3 1 2U3TXDP3_C 1 @2 R1454 U3TXDP3_C_L 8 AZC199-02SPR7G_SOT23-3
<20> U3TXDP3 C905 0.1U_0402_10V7K U3TXDP3_C_L <31>
MAX14600ETA+T_TDFN-EP8_2X2 0_0402_5%
14600@ 0.1U_0402_10V7K KINGCORE WCM-2012HS-670T YSCLAMP0524P_SLP2510P8-10-9
U5 14617@ 2
1 1 2 2
@D86
@ D86
A 0_0402_5% USB20_P2_S_R 2 2 A
2 14617@ 1 4 4 3 3 1 1
R1471 USB20_N2_S_R 3
U8 L59 IUSB30@ 3
MAX14617ETA+T SLP_CHG_CB2A 1 8 SLP_CHG_M4 U3TXDN3 1 2U3TXDN3_C 1 2 R1455 U3TXDN3_C_L AZC199-02SPR7G_SOT23-3
CEN CB0 <20> U3TXDN3 C906 0.1U_0402_10V7K U3TXDN3_C_L <31>
USB20_N2_S 2 7 US20_N2 @ 0_0402_5%
USB20_P2_S DM TDM US20_P2
3 DP TDP 6
SLP_CHG_M3 4 5 +5VALW
U8 14617@ CB1 VCC
9 PGND 1
C893 Security Classification Compal Secret Data Compal Electronics, Inc.
MAX14600ETA+T_TDFN-EP8_2X2 2011/12/14 2012/12/31 Title
14600@ 0.1U_0402_10V7K
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
MAX14617ETA+T B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 25 of 51
5 4 3 2 1
 5 4 3 2 1

Screw cap for ESD request

D D

C C

B-CAS Circuit
+5VALW +5VS
1

1 BCAS@ Inrush current = 0A

BCAS@ RS2 CS1
0.1U_0402_10V7K
100K_0402_5%
3

RS5 2 S
QS1
2

G
2 1 2 AO3413_SOT23
47K_0402_5% BCAS@
3

BCAS@ 1
D
1

2N7002DW-T/R7_SOT363-6 +5VS_BCAS +5VS_L_BCAS

QS2B BCAS@ LS1 BCAS@
BCPWON 5 BCAS@ CS2 1 2
<27> BCPWON 2
0.01U_0402_25V7K +5VS_L_BCAS 1 1 FBMA-L11-201209-221LMA30T_0805
1

CS4 CS5
4

1 BCAS@ BCAS@
BCAS@ RS7 0.1U_0402_10V7K 1U_0402_6.3V6K
10K_0402_5% RS8 CS3 BCAS@ 2 2
2.2K_0402_5% 4.7U_0603_6.3V6K
2

BCAS@ 2
2

B +5VS_L_BCAS B
5

US1 BCAS@
1 Finger printer
P

IN1 B_R_BCRST 1 BCAS@ 2 B_BCRST

O 4 B_BCRST <27>
BCRSTM 2 RS9 100_0402_5%
<27> BCRSTM IN2
G

SN74AHC1G08DCKR_SC70-5 @
3

JFP
6 GND
5 GND
5

US2 BCAS@ +3VS 1 R134 2 +3VS_FP 4

0_0603_5% 1 USB20_N8 4
1 3
P

IN1 <20> USB20_N8 3

4 B_R_XBCCLK1 BCAS@ 2 B_XBCCLK FP@ C480 USB20_P8 2
O B_XBCCLK <27> <20> USB20_P8 2
XBCLKM 2 RS11 100_0402_5% 0.1U_0402_10V7K FP_GND 1
<27> XBCLKM IN2 D82 1
G

FP@

1
SN74AHC1G08DCKR_SC70-5 2 JOINT_F1017WR-S-04P
3
3

3 R133
1 1
2 0_0603_5%
2 FP@

2
AZC199-02SPR7G_SOT23-3
@
+5VS_L_BCAS
For ESD

A 1 2 A
RS12 BCAS@
3

RS1 BCAS@ E 10K_0402_5%

+5VS_L_BCAS 1 2 2 1 2 QS4 BCAS@ BCIO
BCIO <27>
RS13 BCAS@ B 2SB1197K_SOT23-3
10K_0402_5% 10K_0402_5% C
1
6

1 2
QS2A RS14 BCAS@ Security Classification Compal Secret Data Compal Electronics, Inc.
BCAS@ 1.5K_0402_5% 2011/12/14 2012/12/31 Title
CPLGP1
Issued Date Deciphered Date
2
<27> CPLGP1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
2N7002DW-T/R7_SOT363-6 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1

B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 26 of 51
5 4 3 2 1
 +3VS
120 mils For SED
WLAN&BT Combo module circuits Slot 2 Full PCIe Mini Card- 3G/ TV Tuner +1.5VS
For RF 47P_0402_50V8J 0.1U_0402_10V7K
Slot 1 Half PCIe Mini Card-WLAN/ WiMax Half PCIe Mini Card- JET 1 1 1

1
+3V_WLAN BT BT CM17 CM18 CM19 CM4 CM5 CM6 CM20
on module on module @ @ @ 47P_0402_50V8J
+3V_WLAN +1.5VS +3VS 47P_0402_50V8J @

2
1
JPCIF @ 2 2 2
Enable Disable
CM25 1 2 2.75A 47P_0402_50V8J 0.01U_0402_25V7K 4.7U_0805_10V4Z
1 2

2
47P_0402_50V8J 3 4
<26> XBCLKM

2
RM17 @ BCCDET 3 4 RM19
+3V_WLAN
BT_CRTL H L 5 5 6 6
8.2K_0402_5% CLKREQ_Q_TV# 7 8 +UIM_PWR USB20_P10_TV 1 3G@ 2 0_0402_5% PM_SMBCLK
7 8 UIM_DATA USB20_N10_TV
9 9 10 10 1 3G@ 2 0_0402_5% PM_SMBDATA
+1.5VS UIM_CLK RM20
BT_ON# L H <17> CLK_TV# 11 12
1
11 12

5
UM1 13 14 UIM_RESET
<17> CLK_TV 13 14
1 15 16 COMMON

P
<35,38> AOAC_EN# IN1 15 16

1
O 4WLAN_OFF# <26> BCRSTM 17 17 18 18 ISDBT_DET_R
2 CM26 19 20 RF_OFF# RM30
<35> WL_OFF# IN2 <26> BCPWON 19 20 RF_OFF# <20>

G
47P_0402_50V8J BT_CTRL 21 22 PLT_RST#_FULL 1 3G@ 2 PLT_RST# 0_0402_5%

2
SN74AHC1G08DCKR_SC70-5 @ SATA_PRX_DTX_P1 21 22 RM30 0_0402_5% TV@
23 24

3
23 24

3
@ For RF SATA_PRX_DTX_N1 25 26
QM1A QM1B 25 26 BCAS@
27 27 28 28
USB20_P10_TV
USB--TV#2
29 29 30 30 1 RM21 2 0_0402_5% USB20_P10 <20>
WL_OFF# 1 2 2 5 SATA_PTX_C_DRX_N1 31 32 USB20_N10_TV 1 BCAS@ 2 0_0402_5%
<21> BT_ON# 31 32 USB20_N10 <20>
RM18 0_0402_5% SATA_PTX_C_DRX_P1 33 34 RM22
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 33 34
40 mils 35 36 USB20_N12 <20>

4
+3V_WLAN +1.5VS 35 36 RM3 0_0402_5%
For SED For SED 37 37 38 38 USB20_P12 <20> USB--3G/TV#1
+3VS 39 39 40 40 1 3G@ 2 UIM_VPP
0.1U_0402_10V7K 0.1U_0402_10V7K 41 42 LED_WIMAX# COMMON
41 42 CPLGP1
1 1 1 1 1 1 <5,9,38,43> SUSP 43 43 44 44 CPLGP1 <26> 1 BCAS@ 2 BCIO
BCIO <26>
1

1
45 46 RM7 0_0402_5%
45 46 TMPTU1_SXP <35>
CM1 CM2 CM3 CM27 CM7 CM8 CM9 CM28 47 48
<35> TMPTU2_SXP 47 48
47P_0402_50V8J 47P_0402_50V8J 1 RM15 2 49 50 B-CAS
2

2
2 2 2 @ 2 2 2 @ BT_CTRL 49 50
1 RM27 2 E51_RXD_R 0_0603_5% 51 52
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 1K_0402_5% +16VS 1 RM16 2 BCAS@ 51 52 Close to JPCIF
0_0603_5% 53 54
BCAS@ GNDGND ISDBT_DET_R 1 TV@ 2 ISDBT_DET <21> +5VS_BCAS 1 BCAS@ 2 +VCC_SIM
+1.5VS +3V_WLAN For isolate Intel Rainbow Peak and RM13 0_0402_5% RM4 0_0603_5%
ACES_51711-0520W-001
JWLAN Compal Debug Card. +UIM_PWR 1 3G@ 2
+16VS 1 MSATA@2 RM1 0_0603_5%
<35> AOAC_WAKE# 1 1 2 2 Add BCCDET pull down
3 4 RM14 0_0402_5%
BT_CTRL 10_0402_5%2BT_CTRL_R 3 4 0.01U_0402_50V7K UIM_RESET
5 5 6 6 1 3G@ 2
@ RM24 7 8 BCCDET 1 BCAS@ 2 1 1 please place near J3GTV RM5 0_0402_5%
<17> CLKREQ_WLAN# 7 8

1
9 10 RM23 470_0402_5% +UIM_PWR B_BCRST 1 BCAS@ 2 SIM_RESET
9 10 <26> B_BCRST
11 12 CM12 CM11 CM10 RM8 0_0402_5%
<17> CLK_WLAN# 11 12
13 14 47P_0402_50V8J @ @
<17> CLK_WLAN

2
13 14 @ 2 2 UIM_CLK
15 15 16 16 1 3G@ 2

1
17 18 0.1U_0402_25V4Z RM9 0_0402_5%
17 18 WLAN_OFF# RM2 B_XBCCLK
19 19 20 20 <26> B_XBCCLK 1 BCAS@ 2 SIM_CLK SIM_CLK
21 22 PLT_RST# JSIM @ 4.7K_0402_5% RM10 0_0402_5%
21 22 PLT_RST# <5,20,28,29,31,35,36>
23 24 +VCC_SIM 1 4 @
<17> PCIE_PRX_WLANTX_N2 23 24 VCC GND
25 26 SIM_RESET 2 5 UIM_VPP UIM_DATA 1 3G@ 2
<17> PCIE_PRX_WLANTX_P2

2
25 26 SIM_CLK RST VPP SIM_DATA RM11 0_0402_5%
27 27 28 28 3 CLK I/O 6
29 30 PM_SMBCLK <11,12,17,37> 1 BCIO 1 BCAS@ 2 SIM_DATA
29 30

1
31 32 PM_SMBDATA <11,12,17,37> 1 7 8 CM14 RM12 0_0402_5%
<17> PCIE_PTX_C_WLANRX_N2 31 32 NC NC
33 34 CM13 DM1 1 1 22P_0402_50V8J
<17> PCIE_PTX_C_WLANRX_P2 33 34
35 36 USB20_N9 <20> 0.1U_0402_10V7K RLZ20A_LL34 MOLEX_47273-0001~D @
35 36 3G@ CM15 CM16 2
WLAN/ WiFi 37 37 38 38 USB20_P9 <20> WiMax 2 3G@
10P_0402_50V8J 10P_0402_50V8J
+3V_WLAN 39 40

2
39 40 LED_WIMAX# 3G@ 2 2 3G@
41 41 42 42 LED_WIMAX# <37>
43 43 44 44
45 45 46 46 1 @ 2 +3VS
RM25 47 48 RM6 100K_0402_5% RM31 1 TV@ 2 0_0402_5% PCIE_PRX_C_TVTX_P6
47 48 PCIE_PRX_C_TVTX_P6 <17>
<35,36> E51_TXD 10_0402_5%2 49 49 50 50 1 2 +5VS RM32 1 2 0_0402_5% PCIE_PRX_C_TVTX_N6
PCIE_PRX_C_TVTX_N6 <17>
1 2 E51_RXD_R 51 52 RM28 100K_0402_5% TV@
<35,36> E51_RXD 51 52
2

0_0402_5% WIMAX@
RM26 53 54 MSATA@
GNDGND RM29 SATA_PRX_DTX_N1 CM21 1
Debug card using 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_N1 <16>
ACES_51711-0520W-001 200K_0402_5% SATA_PRX_DTX_P1 CM22 1 2 0.01U_0402_25V7K SATA_PRX_C_DTX_P1
+3VS SATA_PRX_C_DTX_P1 <16>
WIMAX@ MSATA@
1

@ To avoid LED flashing +3VS TV@

2 1
RM35 10K_0402_5% RM33 1 TV@ 2 0_0402_5% PCIE_PTX_C_TVRX_N6
PCIE_PTX_C_TVRX_N6 <17>

2
G
RM34 1 2 0_0402_5% PCIE_PTX_C_TVRX_P6
PCIE_PTX_C_TVRX_P6 <17>
TV@
CLKREQ_Q_TV# 3 1 MSATA@
CLKREQ_TV# <17>
SATA_PTX_C_DRX_N1 CM23 1 2 0.01U_0402_25V7K SATA_PTX_DRX_N1

D
SATA_PTX_DRX_N1 <16>
SATA_PTX_C_DRX_P1 CM24 1 2 0.01U_0402_25V7K SATA_PTX_DRX_P1
SATA_PTX_DRX_P1 <16>
TV@QM2 MSATA@
2N7002_SOT23-3

RCL8
0_0603_5%
+3VALW 1 2 1 PCH_X1_R_R 1 GCLK@ 2 PCH_X1_R PCH_X1_R <17>
CCL11 RCL1 0_0402_5%
UCL1 GCLK@ 22U_0805_6.3V6M
+3VALW_PCH 1 2
RCL9 GCLK@
0_0603_5% @ +3VALW_GCLK 2
2 VDD VBAT 10 +RTCBATT
+3VL 15 +V3.3A NC 11 1 271@ 2 +3VS_280
RCL6 0_0402_5%
+3V_LAN 8 9 PCH_RTCX1_R LAN_X1_R_R 1 GCLK@ 2 LAN_X1_R
VDDIO_25M_A 32K PCH_RTCX1_R <16> LAN_X1_R <28>
+1.05VS_VCCP 3 12 OSC_IN_R_R RCL2 33_0402_5%
VDDIO_25M_B NC
1
CLK_X2 1 5 PCH_X1_R_R
CLK_X1 XTAL_OUT 25M_B LAN_X1_R_R CCL10
16 XTAL_IN 25M_A 6
5P_0402_50V8C
2 GCLK@
4 VSS
+1.05VS_VCCP +3VL 7 VSS
13 VSS EMI request 11/06
0.1U_0402_10V7K

0.1U_0402_10V7K

17 Thermal Pad VDD_RTC_OUT 14 +RTCVCC

1 1
CCL3 CCL1 SLG3NB271VTR_TQFN16_2X3 1
GCLK@ GCLK@ SA000058Z00
2 2 CCL6 OSC_IN_R_R 1 GCLK@ 2 OSC_IN_R OSC_IN_R <33>
2.2U_0603_6.3V6K RCL3 33_0402_5%
2 GCLK@ 1
+3VALW_GCLK +3V_LAN
CCL12
+3VALW +3VALW 4.7P_0402_50V8C
0.1U_0402_10V7K

0.1U_0402_10V7K

2 @
1 1
2

CCL13 CCL2
GCLK@ GCLK@ RCL4
EMI request 12/17
2 2 2
10K_0402_5% 271@
271@ CCL7 LAN_X1_R_R 1 @ 2
0.1U_0402_10V7K RCL5 0_0402_5%
1

1
3

S
RCL7 G 271@
1 271@ 2 2 AO3413_SOT23
GCLK@ 47K_0402_5% QCL1 Reserved for Swing Level adjustment
YCL1 25MHZ 12PF X3G025000DK1H-X 2
D
1

( Close GCLK side )

1

D 271@ 271@
CLK_X1 1 3 CLK_X2 HWEQ_EN 2 2N7002_SOT23-3 CCL8 CCL9 0.1U_0402_10V7K
1 3 <33> HWEQ_EN
G QCL2 0.01U_0402_25V7K 2 1
GND GND S 1 271@ Security Classification Compal Secret Data Compal Electronics, Inc.
3

1 2 4 1 Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

+3VS_280
CCL5 CCL4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
18P_0402_50V8J 18P_0402_50V8J Size Document Number Rev
2 GCLK@ 2 GCLK@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 27 of 51
 A B C D E

UL1 +3V_LAN CL3 to CL6 close to Pin 27,39,47,48

+LAN_VDD10 CL7 to CL8 close to Pin 12,42
<17> PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1 22 31
HSOP LED3/EEDO LL1 8111FVB@
LED1/EESK 37 1 2
<17> PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1 23 40 +LAN_REGOUT 1 2 CL3 0.1U_0402_10V7K
HSON LED0 2.2UH +-5% NLC252018T-2R2J-N 1 2
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_10V7K
<17> PCIE_PTX_C_LANRX_P1 HSIP EECS
LAN_EN PCIE_PTX_C_LANRX_N1 18 32 RL1 2 1 10K_0402_5% Layout Note: LL1 must be 1 2
<17> LAN_EN <17> PCIE_PTX_C_LANRX_N1 HSIN EEDI

2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_10V7K

G
8105ELDO@ 2N7002_SOT23-3 CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_10V7K 1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ 200mil to LL1 8111FVB@ 2 2 8111FVB@ CL6 0.1U_0402_10V7K
<17> CLKREQ_LAN# CLKREQB MDIP0
QL53 2 LAN_MDI0- 1 2

S
PLT_RST# MDIN0 LAN_MDI1+ 8111FVB@ CL7 0.1U_0402_10V7K
<5,20,27,29,31,35,36> PLT_RST# 25 PERSTB MDIP1 4
1 LAN_MDI1- 1
MDIN1 5 1 2
CLK_LAN 19 7 LAN_MDI2+ 8111FVB@ CL8 0.1U_0402_10V7K
<17> CLK_LAN REFCLK_P NC/MDIP2
CLK_LAN# 20 8 LAN_MDI2-
<17> CLK_LAN# REFCLK_N NC/MDIN2
18111FVB@ 2 NC/MDIP3 10 LAN_MDI3+
RL28 0_0402_5% 11 LAN_MDI3-
LAN_X1 NC/MDIN3
43 CKXTAL1 +LAN_VDD10 +LAN_EVDD10
LAN_X2 44 13 +LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
CKXTAL2 DVDD10 +LAN_VDD10
29 1 2 CL22 close to pin 3, respectively
DVDD10 LL2 0_0603_5%
DVDD10 41 CL23,CL24,CL25 close to pin 6,9,41, respectively
EC_SWI# 28 1 1
<18,31> EC_SWI# LANWAKEB
8105ELDO@ 1 2
+3VS RL24 2 1 10K_0402_5% LANCLK_REQ# ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
+3V_LAN RL25 2 @ 1 10K_0402_5% EC_SWI# 8111FVB@ 14 12 1 2
NC/SMBCLK AVDD33 +3V_LAN
RL21 2 1 10K_0402_5% 15 42 CL21 0.1U_0402_10V7K
RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 1 2
@ 48 8111FVB@ CL22 0.1U_0402_10V7K
AVDD33
1 2
ENSWREG 33 8111FVB@ CL23 0.1U_0402_10V7K
+3VS LAN_EN ENSWREG +3V_LAN +LAN_VDDREG
1 2 EVDD10 21 +LAN_EVDD10 1 2
RL26 0_0402_5% +LAN_VDDREG 34 8111FVB@ CL24 0.1U_0402_10V7K
8111FVB@ VDDREG
35 VDDREG AVDD10 3 +LAN_VDD10 1 2 1 2
6 8111FVB@ LL3 0_0603_5% 1 1 8111FVB@ CL25 0.1U_0402_10V7K
AVDD10
1

AVDD10 9
1 2 46 45 CL28 CL29
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10 4.7U_0603_6.3V6K 0.1U_0402_10V7K
RL6 +LAN_REGOUT 8111FVB@ 2 2 8111FVB@
24 GND REGOUT 36
@ 49 60 mils
2

PGND
SA00004Y710 For P/N and footprint
ISOLATE# 1 2 WOL_EN# RL8 GCLK@
2 RL433 0_0402_5% RTL8111F-CGT_QFN48_6x6 LAN_X2
Please place them to ISPD page 2
<27> LAN_X1_R 1 2
8111FVB@ 0_0402_5%

CL43 10PF_0402_50V9 UL1

RL7 1 2 1 2
15K_0402_5% RTL8105E RTL8111E/F RL29 22_0402_5%
Sx Enable Sx Disable S0 GCLK@ GCLK@
Wake up Wake up Pin14 NC NC 8105E-VL/VD 8105E-VL/VD
+3V_LAN
Pin15 NC 10K ohm PD
EMI request 11/06 Placement near to YH2 8111F/F-VB
8105E-VD 10/100M
PWM Mode LDO Mode 8105ELDO@
WOL_EN# LOW HIGH HIGH

1
Pin38 NC 1K ohm PH NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL4 0 ohm NC
RL4 (Pull High)
LAN_X1 1 3 LAN_X2 0_0402_5%
1 3 8111FVB@ NC 0 ohm
+3VALW TO +3V_LAN GND GND RL23 (Pull Down)

2
1 1 ENSWREG
CL26 2 4 CL27

1
+3VALW 27P_0402_50V8J 27P_0402_50V8J
NOGCLK@ NOGCLK@ RL23
+3VALW 2 2 0_0402_5%
8105ELDO@

2
1

2
RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm
100K_0402_5% @
@ 0.1U_0402_10V7K
2

1
2

S
@ RL432 @ QL51 PJ29 UL3 8105ELDO@
LAN Conn.
2

G
1 @ 2 1 2 2 JUMP_43X79 For ESD
<35> WOL_EN#

1
RL434 0_0402_5% @ LAN_MDI0+ 1 16 RJ45_MIDI0+
+3V_LAN TD+ TX+
1

47K_0402_5% 2 AO3413_SOT23 D LAN_MDI0- 2 15 RJ45_MIDI0- DL1

1
1

3 @ @ TD- TX- 3
2,23,38> PCH_PWR_EN# 1 2 3 14 AZC199-02SPR7G_SOT23-3
1

RL435 0_0402_5% CL482 CT CT

4 NC NC 13

3
0.01U_0402_25V7K 5 NC NC 12
1 JRJ45
2 6 11

3
LAN_MDI1+ CT CT RJ45_MIDI1+ RJ45_MIDI3-
1 7 RD+ RX+ 10 8 PR4-
CL682 LAN_MDI1- 8 9 RJ45_MIDI1- 14
CL681 RD- RX- RJ45_MIDI3+ GND
1U_0402_6.3V6K 7 PR4+ GND 13
4.7U_0805_10V4Z 1
2 SP050007K00
@ 10/100M transformer_HD245 RJ45_MIDI1- 6 PR2-

2
LED_GREEN_B2 12
RJ45_MIDI2- 5 DL2

2
UL4 PR3-
LED_GREEN_B1 11 AZC199-02SPR7G_SOT23-3
CL39 1000P_0402_50V7K 8111FVB@ RJ45_MIDI2+ 4 @
PR3+

1
1 TCT1 MCT1 24 2 1 1 2
LAN_MDI3- 8111FVB@ RL11 75_0402_1% RJ45_MIDI3- RJ45_MIDI1+
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. 2 23 3

1
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ PR2+
3 TD1- MX1- 22 LED_YELLOW_A2 10 For ESD
CL40 1000P_0402_50V7K 8111FVB@ RJ45_MIDI0- 2 PR1-
4 TCT2 MCT2 21 2 1 1 2 LED_YELLOW_A1 9
LAN_MDI2- 5 20 8111FVB@ RL12 75_0402_1% RJ45_MIDI2- RJ45_MIDI0+ 1
LAN WOL
LAN_EN ISOLATEB LAN_MDI2+ 6
TD2+ MX2+
19 RJ45_MIDI2+ PR1+
TD2- MX2-
S0 Sx S0 Sx CL41 1000P_0402_50V7K @ SANTA_130451-F
7 TCT3 MCT3 18 2 1 1 2
---------------------------------------------- LAN_MDI1- 8 TD3+ MX3+ 17 RL13 75_0402_1% RJ45_MIDI1-
LAN_MDI1+ 9 16 RJ45_MIDI1+
0 0 0 0 1 1 TD3- MX3- CL42 1000P_0402_50V7K
10 15 2 1 1 2
0 1 0 0 1 1 LAN_MDI0- 11
TCT4 MCT4
14 RL15 75_0402_1% RJ45_MIDI0-
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+
1 0 1 1 1 1 12 TD4- MX4- 13

1 1 1 1 1 0* SP050007400 RJ45_GND 1 2 LANGND

1 CL36 1000P_1808_3KV7K 1 1
SUPERWORLD_SWG150401 CL37 CL38
4 CL34 8111FVB@ @ 4
* 2
0.1U_0402_25V6
2
CAP NP
2
4.7U_0603_6.3V6K

S3: after SUSP# assert low over 100ms Place CL34 colse
to LAN chip
S4/S5: after SYSON assert low over 100ms
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 28 of 51
A B C D E
 5 4 3 2 1

D +AV12 +3VS +DV12 D

20 mils 40 mils 20 mils

1 1 1 1 1 1
CW1 CW2 CW3 CW4 CW5 CW6
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
2 2 2 2 2 2

All of cap. close to chip

UW1
+3VS 9 3V3_IN
2 1 +DV33_18 20 mils 15 DV33_18
CW7 1U_0402_6.3V6K +AV12 7 AV12
+DV12 11 DV12_S
C C
+VCC_2IN1 10 Card_3V3
GND 25
2 1 12mils, lengths < 200mils8 RREF
RW1 6.2K_0402_5%

PCIE_PTX_C_CRRX_P4 1 12 SD_DATA1_R RW6 1 2 0_0402_5% SD_DATA1

<17> PCIE_PTX_C_CRRX_P4 PCIE_PTX_C_CRRX_N4 HSIP SP1 SD_DATA0_R RW5 0_0402_5% SD_DATA0
<17> PCIE_PTX_C_CRRX_N4 2 HSIN SP2 13 1 2
<17> PCIE_PRX_C_CRTX_P4 CW8 1 2 0.1U_0402_16V7K PCIE_PRX_CRTX_P4 5 14 SDCLK_R RW4 1 2 33_0402_5% SDCLK
CW9 1 0.1U_0402_16V7K PCIE_PRX_CRTX_N4 HSOP SP3 SDCMD_R RW7 0_0402_5% SDCMD
<17> PCIE_PRX_C_CRTX_N4 2 6 HSON SP4 16 1 2
17 SD_DATA3_R RW8 1 2 0_0402_5% SD_DATA3 1
SP5 SD_DATA2_R RW9 0_0402_5% SD_DATA2
SP6 18 1 2
CLK_CR 3 CW10
<17> CLK_CR CLK_CR# REFCLKP 5P_0402_50V8C
<17> CLK_CR# 4 REFCLKN colse to chip 2
23 20 SDWP
<5,20,27,28,31,35,36> PLT_RST# PERST# SD_WP
For EMI
24 21 SDCD#
<17> CLKREQ_CR# CLK_REQ# SD_CD#
+3VS 1 2 19 GPIO MS_INS# 22
RW2 10K_0402_5%
RTS5229-GR_QFN24_4X4
SA00004Z900

< 2 in 1 Card Reader >

B
Connector on bottom side B
JREAD
SD_DATA0 7
SD_DATA1 DAT0 SDWP +VCC_2IN1
8 DAT1 WP 10
SD_DATA2 9 11 SDCD#
SD_DATA3 DAT2 CD
1 DAT3 40 mils
4 +VCC_2IN1
SDCMD VDD
2 CMD
SDCLK 5 3 2 1
CLK VSS1
VSS2 6
12 CW11 CW12
GND 10U_0805_10V6K 0.1U_0402_16V4Z
13 GND 1 2
TAITW_PSDBTD-09GLBS1N14N0
@

CW12, CW11 colse to socket VDD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 29 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS

Note：
RR29
4.7K_0402_5%
1) keep differential trace mismatch less than +/- 5mil UR1
+5VALW 2.5A W=60mils

1
2) keep USB3 impedance follow Intel SPEC +USB_VCCB

RR10 PRUR@

RR17 @

RR6

RR15 @

RR9

RR13 @

RR27 @

RR28 @
PCUR@ For EMI

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
SA000056E00 UR3
3) Power / GND pin trace 10mil

1
RR7 2 6 2 1
IN OUT

PRUR@

@
4.7K_0402_5% 3 7 CR38 1000P_0402_50V7K
PCUR@ PI3EQX7502IZDEX_TQFN 24P USB_EN# IN OUT
<35> USB_EN# 4 8

2
PCUR@ EN/ENB OUT
1 GND OCB 5 USB_OC#0 <20,35>
RR21 +3VS
1

2
A1_EQ0 0_0402_5% CR27 0.1U_0402_10V7K SY6288DCAC_MSOP8
A1_EQ1 PCUR@ IUSB30@
1 2 UR1 SA00004KB00 CR39
CR28 4.7U_0805_10V4Z
B1_EQ0 RR34 IUSB30@
1 2 0.01U_0402_25V7K
SA00003TV00 2 @
B1_EQ1 0_0402_5% SA00004YI00
PCUR@ UR1
D A1_DE0 D
1 VDD
A1_DE1 13 SN65LVPE502CPRGER_VQFN24_4X4 +USB_VCCB
VDD TIUR@
B1_DE0
W=80mils
B1_DE1 A1_EQ1 B1_EQ1 4.7U_0805_10V4Z
4.7U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K
TI: A_DE1、B_DE1 need 0ohm to GND. A1_DE0
15
16
A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 4
3 B1_DE0 1
A_DE0/SCL_CTL B_DE0/I2C_ADDR0
If use Parade and need control A1_EQ0 17 A_EQ0/NC B_EQ0/NC 2 B1_EQ0 1 1 1 1 1 1
1

1
RR29 TIUR@

RR11 @

RR7

RR8

RR12 @

RR21 TIUR@

RR35 @

RR34 TIUR@
A1_DE1 18 6 B1_DE1 CR46 CR42 + CR40 CR43 CR41 CR44 CR45
A_DE1/NC B_DE1/NC

1
A_DE1 & B_DE1 please use 4.7K
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
CR19 IUSB30@

0_0402_5%

0_0402_5%

0_0402_5%
U3RXDP1_U_C 19 12 U3RXDP1_R_R 1 2 0.1U_0402_10V7K U3RXDP1_R
A_INp A_OUTp U3RXDP1_R <20> 2 2 2 2 2 2 2
TIUR@

@
U3RXDN1_U_C 20 11 U3RXDN1_R_R 1 2 0.1U_0402_10V7K U3RXDN1_R
A_INn A_OUTn CR18 IUSB30@ U3RXDN1_R <20>
2

2
IUSB30@ CR22 IUSB30@ 220U_6.3V_M_R15 1000P_0402_50V7K 1000P_0402_50V7K

2
U3TXDP1 CR24 1 2 0.1U_0402_10V7K U3TXDP1_C 9 22 U3TXDP1_U 1 2 0.1U_0402_10V7K U3TXDP1_U_C
<20> U3TXDP1 B_INp B_OUTp
U3TXDN1 CR25 1 2 0.1U_0402_10V7K U3TXDN1_C 8 23 U3TXDN1_U 1 2 0.1U_0402_10V7K U3TXDN1_U_C
<20> U3TXDN1 B_INn B_OUTn CR23 IUSB30@
IUSB30@
RR33 1 @ 2 0_0402_5% 5
+3VS RR14 PD#
1 PRUR@ 2 3.3K_0402_5% 7 REXT GND 10
RR18 2 @ 1 4.7K_0402_5% 14 21 USB20_P0 1 @ 2 RR26 USB20_P0_L
TEST GND <20> USB20_P0
+3VS RR16 1 @ 2 4.7K_0402_5% 24 25 0_0402_5%
I2C_EN GPAD LR3 IUSB30@
PS8710BTQFN24GTR-A1_TQFN24_4X4 3 3 4 4
1

1
RR58 PRUR@

RR63 @

RR56 PRUR@

RR62 @

RR55 @

RR61 @

RR51 @

RR52 @
PRUR@
REXT - swing pin(2.5K~10K) SA00004VQ00
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
1

1
RR65 2 1
4.7K_0402_5% UR2 2 1
PCUR@ When test RX need add RR18 WCM-2012-900T_0805
2

USB20_N0 1 2 RR25 USB20_N0_L

<20> USB20_N0
RR57 SA000056E00 @ 0_0402_5%
2

2
A2_EQ0 4.7K_0402_5%
A2_EQ1 PCUR@
PI3EQX7502IZDEX_TQFN 24P
B2_EQ0 RR64 +3VS PCUR@ JUSBLR
B2_EQ1 0_0402_5% CR36 0.1U_0402_10V7K +USB_VCCB 1
PCUR@ IUSB30@ USB20_N0_L VBUS
1 2 2 D-
A2_DE0 CR37 UR2 USB20_P0_L 3
A2_DE1 RR50 IUSB30@ D+
C 1 2 0.01U_0402_25V7K 4 GND C
0_0402_5% U3RXDN1_U_C_L 5
B2_DE0 PCUR@ UR2 U3RXDP1_U_C_L StdA-SSRX-
SA00004YI00 6 StdA-SSRX+ GND 10
B2_DE1 1 7 11 W=80mils
VDD U3TXDN1_U_C_L GND-DRAIN GND
13 VDD 8 StdA-SSTX- GND 12
SN65LVPE502CPRGER_VQFN24_4X4 U3TXDP1_U_C_L 9 13 USB2_GND
StdA-SSTX+ GND
1

1
RR65 TIUR@

RR59 @

RR57 TIUR@

RR54 @

RR60 @

RR64 TIUR@

RR53 @

RR50 TIUR@

TIUR@
TI: A_DE1、B_DE1 need 0ohm to GND.
1

1
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

CR26
A2_EQ1 15 4 B2_EQ1 LOTES_AUSB0015-P001A 2
A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1
0_0402_5%

0_0402_5%

0_0402_5%

If use Parade and need control A2_DE0

A2_EQ0
16
17
A_DE0/SCL_CTL B_DE0/I2C_ADDR0 3
2
B2_DE0
B2_EQ0
@ 0_0603_5% 0_0603_5%
RR24
A_EQ0/NC B_EQ0/NC
A_DE1 & B_DE1 please use 4.7K A2_DE1 18 6 B2_DE1 RR23
2

A_DE1/NC B_DE1/NC 1

0.1U_0402_10V7K
CR31 IUSB30@
2

2
U3RXDP2_U_C 19 12 U3RXDP2_R_R 1 2 0.1U_0402_10V7K U3RXDP2_R
U3RXDN2_U_C A_INp A_OUTp U3RXDN2_R_R 0.1U_0402_10V7K U3RXDN2_R U3RXDP2_R <20>
20 A_INn A_OUTn 11 1 2
CR30 IUSB30@ U3RXDN2_R <20> JUSBLF
IUSB30@ CR32 IUSB30@ +USB_VCCB 1
U3TXDP2 VBUS
TI suggest EQ1(Pin2) & EQ2(Pin17) to pull Down use 7dB <20> U3TXDP2
CR34 1 2 0.1U_0402_10V7K U3TXDP2_C 9 B_INp B_OUTp 22 U3TXDP2_U 1 2 0.1U_0402_10V7K U3TXDP2_U_C USB20_N1_L 2 D-
U3TXDN2 CR35 1 2 0.1U_0402_10V7K U3TXDN2_C 8 23 U3TXDN2_U 1 2 0.1U_0402_10V7K U3TXDN2_U_C USB20_P1_L 3
<20> U3TXDN2 B_INn B_OUTn D+
DE1(Pin3) & DE2(Pin16) NC use 0dB IUSB30@
CR33 IUSB30@
U3RXDN2_U_C_L
4
5
GND
StdA-SSRX-
OS1(Pin4) & OS2(Pin15) NC use 1042mV RR49
RR44
1 @
PRUR@ 2
2 0_0402_5%
3.3K_0402_5%
5 PD#
U3RXDP2_U_C_L 6 StdA-SSRX+ GND 10

RR46
1
@ 4.7K_0402_5%
7 REXT GND 10
U3TXDN2_U_C_L
7 GND-DRAIN GND 11 W=80mils
OUTPUT SWING AND EQ CONTROL (at 2.5 GHZ) 2 1 14 TEST GND 21 8 StdA-SSTX- GND 12
+3VS RR45 1 @ 2 4.7K_0402_5% 24 25 U3TXDP2_U_C_L 9 13 USB3_GND
I2C_EN GPAD StdA-SSTX+ GND

CR29
TRANSISTION BIT AMPLITUDE EQUALIZATION PS8710BTQFN24GTR-A1_TQFN24_4X4 LOTES_AUSB0015-P001A 2
OSx EQx PRUR@ @ 0_0603_5% 0_0603_5%
(TYP mVpp) (dB) REXT - swing pin(2.5K~10K) SA00004VQ00 RR36
RR37
1

0.1U_0402_10V7K
When test RX need add RR18

2
NC(default) 1042 NC(default) 0
U3RXDN1_U_C 1 @ 2 RR19 U3RXDN1_U_C_L
0 908 0 7 0_0402_5%
KINGCORE WCM-2012HS-670T USB20_P1 1 @ 2 RR39 USB20_P1_L
<20> USB20_P1
0_0402_5%
1 1127 1 15 1 1 2 2
LR4 IUSB30@
B OUTPUT DE CONTROL (at 2.5GHZ) 3 3 4 4 B
4 4 3 3
DEx LR1 IUSB30@
OSx = NC OSx = 0 OSx = 0 U3RXDP1_U_C 1 2 RR20 U3RXDP1_U_C_L
2 2 1 1

@ 0_0402_5% WCM-2012-900T_0805
NC(default) USB20_N1 2 RR38 USB20_N1_L
0 dB 0 dB 0 dB U3TXDN1_U_C 1 @ 2 RR32 U3TXDN1_U_C_L
<20> USB20_N1 1
@ 0_0402_5%
0_0402_5%
KINGCORE WCM-2012HS-670T
0 -3.5 dB -2.2 dB -4.4 dB
BOM Structure 1 1 2 2
DR7 @
1 -6.0 dB -5.2 dB -6.0 dB U3TXDN1_U_C_L 1 1 109 U3TXDN1_U_C_L
CONTROL PINS SETTINGS Pericom PCUR@ 4 4 3 3
LR2 IUSB30@ DR1
@ U3TXDP1_U_C_L 2 2 98 U3TXDP1_U_C_L
U3TXDP1_U_C 2 RR22 U3TXDP1_U_C_L USB20_P0_L
EN_RXD DEVICE FUNCTION TI TIUR@ 1
@ 0_0402_5%
2 2 U3RXDN1_U_C_L 4 4 77 U3RXDN1_U_C_L
DEVICE FUNCTION CM USB20_N0_L 3
1 1
3 U3RXDP1_U_C_L 5 5 6 6 U3RXDP1_U_C_L
1(default) 0(default) Normal Operation Parade PRUR@
Normal Operation AZC199-02SPR7G_SOT23-3
3 3
U3RXDP2_U_C 1 @ 2 RR42 U3RXDP2_U_C_L
Compliance Test Mode USB3.0 USB30R@ 0_0402_5% 8
0 Sleep Mode 1 KINGCORE WCM-2012HS-670T
1 2 Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9
1 2
Parade suggest EQ1(Pin2) & EQ2(Pin17) to pull High use 7dB. All control has internally pulled down at ~150Kohm,
If add ESD Diode A_DE0(Pin16) and B_DE0(Pin3) need pull high to 7dB otherwise 3dB 4 4 3 3
A_EQ1(Pin15) A_EQ0(Pin17) B_EQ1(Pin4) B_EQ0(Pin2) LR5 IUSB30@
U3RXDN2_U_C 1 2 RR40 U3RXDN2_U_C_L DR8 @
@ 0_0402_5% U3TXDP2_U_C_L 1 1 109 U3TXDP2_U_C_L
L L adaptive EQ enable L L adaptive EQ enable
DR4
U3TXDP2_U_C 1 @ 2 RR43 U3TXDP2_U_C_L @ U3TXDN2_U_C_L 2 2 98 U3TXDN2_U_C_L
L H Loss up to 7dB L H Loss up to 7dB 0_0402_5% USB20_P1_L 2
KINGCORE WCM-2012HS-670T 2 U3RXDP2_U_C_L 4 4 77 U3RXDP2_U_C_L
H L Loss up to 14.5dB H L Loss up to 14.5dB 1 2 USB20_N1_L 3
1 1
1 2 3 U3RXDN2_U_C_L 5 5 6 6 U3RXDN2_U_C_L
A
H H Loss up to 11.5dB H H Loss up to 11.5dB A

AZC199-02SPR7G_SOT23-3
4 4 3 3 3 3

A_DE1(Pin18) A_DE0(Pin16) B_DE1(Pin6) B_DE0(Pin3) LR6 IUSB30@ 8

U3TXDN2_U_C 1 2 RR41 U3TXDN2_U_C_L
@ 0_0402_5% Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9
L L 3.5dB L L 3.5dB
L H No de-emphasis L H No de-emphasis
H L 7dB H L 7dB Security Classification Compal Secret Data Compal Electronics, Inc.
H H 5dB with boost H H 5dB with boost Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

output swing output swing THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 30 of 51
5 4 3 2 1
 A B C D E

EUSB30@
+1.5V to +1.05V Transfer +3V_USB 1 RT5
4.7K_0402_5%
2 USBA30_POK
+3V_USB +3VA_USB
+1.5V +3V_USB +1.5V +1.05V_USB

10U_0603_6.3V6M
UT3 EUSB30@ 1A EUSB30@

CT43
1 5 3 LT9
VIN VOUT
9 VIN VOUT 4 1 2
6 BLM18AG601SN1D_2P
EUSB30@USBA30_POK VCNTL
7 POK FB 2 2 EUSB30@1 2
2 RT6

10U_0603_6.3V6M
8 1 10K_0402_1% CT59 EUSB30@
+3V_USB EN GND

CT25
1
APL5930KAI-TRG_SO8 RT8 10U_0603_6.3V6M 1 +3V_USB +1.05V_USB +3VA_USB
32.4K_0402_1%
1 EUSB30@ UT6 1
Vout=0.8(1+10K/32.4K)

2
EUSB30@2 EUSB30@
1.042 ~ 1.0469 ~ 1.0519V

12

22

34

43

21

30

33

39

42

25
6

3
Spec: 0.9975 ~ 1.05 ~ 1.1025

VDD33

VDD33

VDD33

VDD33

VDD10

VDD10

VDD10

VDD10

VDD10

VDD10

VDD10

AVDD33

AVDD33
+3VALW to +3V Transfer +3VALW
1 CT61 EUSB30@
+3VALW <17> CLK_USBA30 PECLKP TI_U3TX_C_DP3
2 PECLKN U3TXDP2 37 1 2 0.1U_0402_16V7K TI_U3TXDP3
<17> CLK_USBA30# EUSB30@ CT41 CT87 EUSB30@
0.1U_0402_16V7K 2 1 PCIE_PRX_USBTX_P5 4 38 TI_U3TX_C_DN3 1 2 0.1U_0402_16V7K TI_U3TXDN3
<17> PCIE_PRX_C_USBTX_P5 PETXP U3TXDN2
0.1U_0402_16V7K 2 1 PCIE_PRX_USBTX_N5 5 PETXN U2DM2 45 U2D_DN2 U2D_DN2 <25>
2

EUSB30@ <17> PCIE_PRX_C_USBTX_N5 EUSB30@ CT81

2
RT12 EUSB30@ CT42 7 44 U2D_DP2 U2D_DP2 <25>
EUSB30@ 100K_0402_5% CT40 0.1U_0402_16V4Z <17> PCIE_PTX_C_USBRX_P5 PERXP U2DP2 TI_U3RXDP3_R
8 PERXN U3RXDP2 40
0.1U_0402_16V7K <17> PCIE_PTX_C_USBRX_N5

3
1
S
EUSB30@ 41 TI_U3RXDN3_R
1

QT3
G U3RXDN2
1 2 2
RT13 47K_0402_5% 2 AO3413_SOT23 47
<5,20,27,28,29,35,36> PLT_RST# PERSTB
CT26 D EC_Q_SWIA# 48
1
PEWAKEB
1

D 0.01U_0402_25V7K EUSB30@ CLKREQ_Q_USBA30# OCL1#

10 PECREQB OCI2B 17
2 EUSB30@ 19
<18,35> PM_SLP_S4# 1 OCI1B
G @
+3V_USB
QT5 S 2N7002_SOT23-3 UPD720202: UPD720202K8-701-BAA_QFN48_7X7 18 USB30PWRON0 RT60 1 2 USB_CHG_EN# <25,35>
3

EUSB30@ USBA30_SMI#_IC PPON2 0_0402_5%

SMIB Low active 46 SMIB PPON1 20
+3V & +1.05V has power sequence timing: SA000051C10
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms RT14 1
+3V_USB 2 10K_0402_5% 11 PONRSTB
CT65 EUSB30@
EUSB30@ 28 TI_U3TX_C_DP4 1 2 0.1U_0402_16V7K TI_U3TXDP4
1SS355TE-17_SOD323-2 U3TXDP1 CT71 EUSB30@
1 2
1 1 2 2 RT65 10K_0402_5% 15 29 TI_U3TX_C_DN4 1 2 0.1U_0402_16V7K TI_U3TXDN4
2 +3V_USB +3VA_USB Close to U32.3 Close to U32.25 +1.05V_USB DT2 SPISCK U3TXDN1 U2D_DN3 2
1 2 14 SPICSB U2DM1 36 U2D_DN3 <25>
EUSB30@ RT66 10K_0402_5% 16 SPISI U2D_DP3
1 2 1 2 13 SPISO U2DP1 35 U2D_DP3 <25>
CT74 RT67 10K_0402_5% 31 TI_U3RXDP4_R
EUSB30@1U_0603_10V6K U3RXDP1
1 2
CT49 0.01U_0402_25V7K

CT50 0.01U_0402_25V7K

CT48 0.01U_0402_25V7K

CT47 0.01U_0402_25V7K

CT53 0.01U_0402_25V7K

CT44 0.01U_0402_25V7K

CT51 0.1U_0402_16V7K

CT54 0.1U_0402_16V7K

CT58 10U_0603_6.3V6M

CT55 0.1U_0402_16V7K

CT57 0.01U_0402_25V7K

CT52 0.1U_0402_16V7K

CT56 0.01U_0402_25V7K

CT64 0.1U_0402_16V7K

CT69 0.01U_0402_25V7K

CT70 0.1U_0402_16V7K

CT66 0.01U_0402_25V7K

CT60 0.01U_0402_25V7K

CT68 0.1U_0402_16V7K

CT62 0.01U_0402_25V7K

CT63 0.01U_0402_25V7K

CT67 0.01U_0402_25V7K
2 2 2 2 2 2 1 1 1 1 2 1 2 1 2 1 2 2 1 2 2 2 RT68 10K_0402_5% 32 TI_U3RXDN4_R
U3RXDN1
24 XT1
23 XT2
1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 2 1 1 2 1 1 1 RT15 EUSB30@
27 IC(L) RREF 26 1 2

1.6K_0402_1%

GND
EUSB30@
YT2

49
EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@ EUSB30@ EUSB30@ EUSB30@EUSB30@EUSB30@EUSB30@EUSB30@ 1 2
EUSB30@EUSB30@EUSB30@EUSB30@ EUSB30@ EUSB30@ EUSB30@EUSB30@EUSB30@EUSB30@
24MHZ_12PF_X5H024000DC1H

12P_0402_50V8J

12P_0402_50V8J
+3V_USB
1 1

CT75

CT76
10K_0402_5% 2 2
+3V_USB 2 RT62 1 EUSB30@ EUSB30@
5

EUSB30@ QT7B

EC_Q_SWIA# 4 3 EC_SWI# <18,28>

2

2N7002KDWH_SOT363-6 QT7A
EUSB30@
3 CLKREQ_Q_USBA30# 3
1 6 CLKREQ_USBA30# <17>
10K_0402_5% 2N7002KDWH_SOT363-6
+3V_USB 2 RT61 1 EUSB30@
EUSB30@
TI_U3RXDN3_R 1 @ 2 RT52 U3RXDN3 TI_U3RXDN4_R 1 @ 2 RT40 U3RXDN4
+3V_USB U3RXDN3 <25> U3RXDN4 <25>
0_0402_5% 0_0402_5%
KINGCORE WCM-2012HS-670T KINGCORE WCM-2012HS-670T
1 1 2 2 1 1 2 2

10K_0402_5%
+3V_USB 2 RT54 1 4 4 3 3 4 4 3 3
5

EUSB30@ QT6B
LT8 EUSB30@ LT12EUSB30@
USBA30_SMI#_IC 4 3 TI_U3RXDP3_R 1 2 RT38 U3RXDP3 TI_U3RXDP4_R 1 2 RT53 U3RXDP4
USBA30_SMI# <20> U3RXDP3 <25> U3RXDP4 <25>
@ 0_0402_5% @ 0_0402_5%
2

2N7002KDWH_SOT363-6 QT6A
EUSB30@
OCL1# 1 6 USB_OC#1 <20,25,35>
10K_0402_5% 2N7002KDWH_SOT363-6 TI_U3TXDN3 1 @ 2 RT47 U3TXDN3_C_L TI_U3TXDN4 1 @ 2 RT48 U3TXDN4_C_L
2 RT51 1 EUSB30@ 0_0402_5% U3TXDN3_C_L <25> 0_0402_5% U3TXDN4_C_L <25>
+3V_USB EUSB30@ EUSB30@
EUSB30@ LT14 LT10
1 1 2 2 1 1 2 2

4 4 3 3 4 4 3 3
KINGCORE WCM-2012HS-670T KINGCORE WCM-2012HS-670T
TI_U3TXDP3 1 2 RT50 U3TXDP3_C_L TI_U3TXDP4 1 2 RT39 U3TXDP4_C_L
@ 0_0402_5% U3TXDP3_C_L <25> @ 0_0402_5% U3TXDP4_C_L <25>

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF B
Date: Thursday, February 16, 2012 Sheet 31 of 51
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF B
Date: Thursday, February 16, 2012 Sheet 32 of 51
A B C D E
 5 4 3 2 1

2W 4ohm =40mil placement near Audio Codec

1W 8ohm =20mil
LA2
+3VL SPKL+ 2 1
+3VL +DVDD_IN +5VALW SPK_L1 <34>
0_0603_1% 2
LA1 CA28
1 2 +PVDD 1 2 0.1U_0402_10V7K @ 2
RA29 0_0603_5% 1 2 PBY160808T-601Y-N_2P 1 1 10U_0603_6.3V6M CA40
1

CA5 0.1U_0402_10V7K 1 1U_0402_6.3V4Z

2
RA25 CA43 +3VS CA6 CA7 CA8 @
2 1
100K_0402_5% @ close to pin 41 CA29
0.1U_0402_10V7K 0.1U_0402_10V7K +DVDD_IO 2 1 2 2 @
1 2
1 RA1 0_0603_5% 10U_0603_6.3V6M 10U_0805_10V4Z LA3 10U_0603_6.3V6M
D D
2

3
1
S
2 1 close to pin 3 SPKL- 2 1
G SPK_L2 <34>
1 2 2 AO3413_SOT23 0_0603_1%
QA2 CA1 CA2 1 LA4
47K_0402_5% 2
D CA9 0.1U_0402_10V7K SPKR+ 2 1 SPK_R1 <34>

1
RA24 1 2 0_0603_1% 2
CA44 CA45 0.1U_0402_10V7K 10U_0603_6.3V6M close to pin 46 CA30
2 @
0.01U_0402_25V7K 2 1
1 +5VALW 10U_0603_6.3V6M
1 2
close to pin 27 close to pin 38 RA2 CA41
+DVDD_IN 1 2 0.1U_0402_10V7K +DVDD +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 2 2 1U_0402_6.3V4Z
RA12 0_0603_5% 2 1 2 1 1 0_0603_5% CA31 @
close to pin 9 @ 1
2 1
CA10 CA11 CA12 CA13 CA38 LA5 10U_0603_6.3V6M
CA3 CA4 @ SPKR- 1

41

46

27

38
10U_0603_6.3V6M 2 1 SPK_R2 <34>
6

3
1 2 1 2 2 0_0603_1%
QA3A QA3B 1 2 UA1 10U_0603_6.3V6M 10U_0603_6.3V6M

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
10U_0603_6.3V6M
2 2N7002DW-T/R7_SOT363-6 5
5> SM_EN SUSP# <35,38,44,45>
2N7002DW-T/R7_SOT363-6
1

4
2

28 42 SPKL+
LINE1_L SPK_OUT_L+ SPKL-
29 LINE1_R SPK_OUT_L- 43
RA43
100K_0402_5% 39 45 SPKR+
40
LINE2_L SPK_OUT_R+
44 SPKR- PCI Beep Beep sound
1

LINE2_R SPK_OUT_R-
MIC1_R_L 4.7U_0603_6.3V6K CA14 MIC1_R_C_L 19 31 RA5 75_0402_1%
MIC1_L HP_OUT_L HP_L <34>
MIC1_R_R MIC1_R_C_R 20 32 RA6 75_0402_1%
MIC1_R HP_OUT_R HP_R <34>
C 4.7U_0603_6.3V6K CA15 CA27 C
RA10 MONO_IN
For EMI 2 1 36 CBP <16> PCH_SPKR 1 2 1 2
CA16 2.2U_0603_10V6K 35 47K_0402_5%
RA41 CBN 0.1U_0402_10V7K
SYNC 10 AZ_SYNC_HD <16>
INT_MIC_CLK_R
<13> INT_MIC_CLK
FBMA-10-100505-301T 4 6 AZ_BITCLK_HD EC_MUTE# Internal AMP
<13> INT_MIC_DATA GPIO1/1st DMIC BCLK AZ_BITCLK_HD <16>
CAM@ Hight Enable
INT_MIC_CLK_R 2 +3VALW LOW Disable
1 GPIO0/DMIC-CLK

2
5 AZ_SDOUT_HD <16> @
CA49 CAM@ SDATA_OUT RA11 CA22
1 2
220P_0402_50V7K 7 8 AZ_SDIN0_HD_R 2 1 RA3 10K_0402_5% 4.7K_0402_5% 100P_0402_50V8J
2 GPIO4 SDATA_IN AZ_SDIN0_HD <16>
RA7 33_0402_5%

1
AZ_RST_HD# 11 48 EC_MUTE#
<16> AZ_RST_HD# RESET# EAPD+PD# EC_MUTE# <35>

2
GPIO3/SPDIFO 1
1 2 MONO_IN 12 @ CA48 RA4
+3VL CA17 100P_0402_50V8J PCBEEP AZ_BITCLK_HD 2
MONO_OUT 37 1 1 2 @ 4.7K_0402_5%
0.1U_0402_10V7K 10_0402_5% RA27
1 2 SENSE_A 13 10P_0402_50V8J To solve noise issue

1
CA46 SENSE A
LINE1_VREFO 23
5

UA3 1 RA42 2 14 For EMI

SM_EN 10K_0402_5% SENSE B
1 30 close to pin 21
P

IN1 AGPO/MIC1_VREFO +MIC1_VREFO please place near codec

4HWEQ_EN 1 RA19 2 HWEQ_EN_D 24 21 2 1
O NC LDO_CAP
Ext.MIC/LINE IN JACK
1

JACK_SENSE 2 1K_0402_5% D CA18 10U_0603_6.3V6M

IN2 2
G

2 2N7002_SOT23-3 18 25 AC_VREF
SN74AHC1G08DCKR_SC70-5 CA47 QA5 NC VREF
G close to pin 22
3

0.1U_0402_25V6 S HWEQ_EN_D 47 22 AC_JDREF 2 RA8 1 20K_0402_1% RA13 2 1 +MIC1_VREFO

3

1 AUX mode/GPIO2 JDREF 1K_0402_5% RA15 2.2K_0402_5%

B
1 1 B
17 34 CPVEE 2 1 MIC1_R_R 2 1
+3VL NC CPVEE MIC1_R <34>
16 26 CA19 2.2U_0603_10V6K CA20 CA21
XA1 NC AVSS1
AVSS2 33 2.2U_0603_6.3V6K
OSC_OUT 2 2
4 VDD OUT 3 1 RA28 2 OSC_IN 15 AUX_CLK_In DVSS 49 @ MIC1_R_L 2 1 MIC1_L <34>
OSC@ 1 2 10_0402_5% 1 0.1U_0402_10V7K 1K_0402_5%
0.1U_0402_10V7K CA39 ALC280Q-GR_QFN48_6X6 RA14 2 1 +MIC1_VREFO
CA42 SA000051D00 MIC_SENSE# RA16 2.2K_0402_5%
HWEQ_EN 1 2 10P_0402_50V8J
DGND AGND
<27> HWEQ_EN VCOUNT GND

6
2 RA26
12.288MHZ_15PF_SSW012288D3CH 1 271@ 2 OSC_OUT QA1A
<27> OSC_IN_R
OSC@ 0_0402_5% RA17 100K_0402_5%
SJ000001A00 Placement near to UA1.15 2N7002DW-T/R7_SOT363-6 2

1
Sense Pin Impedance Codec Signals Function RA18 100K_0402_5%
place close to chip CA23 1 2 0.1U_0603_50V7K
+3VL

39.2K PORT-A (PIN 31, 32) Headphone out MIC_SENSE# SENSE_A CA24 1
2 1 2 0.1U_0603_50V7K
RA20 20K_0402_1%
20K PORT-B (PIN 19, 20) Ext. MIC CA25 1 2 0.1U_0603_50V7K EC <35> SM_SENSE#

3
SENSE A CA26 1 2 0.1U_0603_50V7K QA1B
10K PORT-C (PIN 28, 29)
<34> NBA_PLUG 1 2 5 JACK_SENSE <34>
RA21 39.2K_0402_1% RA22 10_0603_5% 2N7002DW-T/R7_SOT363-6
5.1K PORT-E

4
A A

39.2K

SENSE B 20K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title
10K SCHEMATICS, MB A8392
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 33 of 51
5 4 3 2 1
HeadPhone/LINE OUT JACK

JLINE
6
5

<33> NBA_PLUG 4
LA6 1 2 HP_R_L 3
<33> HP_R
CHILISIN PBY100505T-121Y-N 0402
LA7 1 2 HP_L_L
<33> HP_L
CHILISIN PBY100505T-121Y-N 0402 2
1
1
3 SINGA_2SJ-0960-D06
1 CA32 CA33 CA34 @ @
2 100P_0402_50V8J 100P_0402_50V8J
2
DA3 @ 0.1U_0402_10V7K
PJDLC05_SOT23-3
For EMI

EXT.MIC/LINE IN JACK +3VL

RA23
4.7K_0402_5%

JEXMIC
6
5

<33> JACK_SENSE 4

LA8 1 2 MIC1_L_R 3
<33> MIC1_R
CHILISIN PBY100505T-121Y-N 0402
LA9 1 2 MIC1_L_L
<33> MIC1_L
CHILISIN PBY100505T-121Y-N 0402 2
1

3 1 SINGA_2SJ-0960-D06
1 @
2 CA35 CA36 CA37 @
100P_0402_50V8J 100P_0402_50V8J
DA4 @ 2
PJDLC05_SOT23-3 0.1U_0402_10V7K

For EMI

SPK CONN.

@
DA5 PJDLC05_SOT23-3
3
1
2

JSPK
<33> SPK_L1 1 1
<33> SPK_L2 2 2
<33> SPK_R1 3 3
<33> SPK_R2 4 4
5 G1
PJDLC05_SOT23-3 6 G2
3
1 ACES_50278-00401-001
2 @

DA6
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 34 of 51
 5 4 3 2 1

+3VL +3VL 0_0402_5% RB1

PVT change RF LED control
<46> VR_HOT# 1 2 H_PROCHOT# <5,40>
0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3 pin from PCH to EC 1
1 1 1 1 1 1 0.1U_0402_10V7K D
<37> WL_BT_LED#
CB1 CB2 CB5 CB7 1 2 QB1 1
0.1U_0402_10V7K H_PROCHOT#_EC 2 CB8

1
CB4 CB6 D G 47P_0402_50V8J
For EMI 2 2 2 2 2 2 EC_WL_BT_LED 2

111
125
0.1U_0402_10V7K 1000P_0402_50V7K QB2 G SSM3K7002F_SC59-3 S 2

22
33
96

67
9
CLK_PCI_EC UB1 2N7002_SOT23-3 S 3

3
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
1
RB3 BATT_TEMPA 1 2
10_0402_5% CB9 100P_0402_50V8J
@ GATEA20 1 21 FUNCTION_LED#
D <21> GATEA20 GATEA20/GPIO00 GPIO0F FUNCTION_LED# <37> D
KB_RST# 2 23 EC_WL_BT_LED ACIN_D 1 2
<21> KB_RST#
2
SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 FANPWM CB10 100P_0402_50V8J
1 <16> SERIRQ 3 SERIRQ GPIO12 26 FANPWM <5>
CB11 LPC_FRAME# 4 27 GPUPWR_SKIN#
<16,36> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
10P_0402_50V8J LPC_AD3 5
<16,36> LPC_AD3 LPC_AD3
@ LPC_AD2 7 PWM Output
2 <16,36> LPC_AD2 LPC_AD2 +3VS
LPC_AD1 8 63 BATT_TEMPA
<16,36> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA <40>
LPC_AD0 10 LPC & MISC 64 TMPTU1_SXP
<16,36> LPC_AD0 LPC_AD0 GPIO39 TMPTU1_SXP <27>
65 ADP_I TMPTU1_SXP 1 2
ADP_I/GPIO3A ADP_I <40,41>
CLK_PCI_EC 12 AD Input 66 ADP_V RB4 10K_0402_5% TV tuner
<20> CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_V <41>
PLT_RST# 13 75 TMPTU2_SXP
<5,20,27,28,29,31,36> PLT_RST# PCIRST#/GPIO05 GPIO42 TMPTU2_SXP <27> temperature
EC_RST# 37 76 TMPTU2_SXP 1 2
+3VL RB2 EC_SCI# EC_RST# IMON/GPIO43 RB5 10K_0402_5%
<21> EC_SCI# 20 EC_SCII#/GPIO0E
47K_0402_5% AOAC_EN# 38
<27,38> AOAC_EN# GPIO1D
1 2 EC_RST# 68 HDPINT H_PROCHOT#_EC 1 @ 2
DAC_BRIG/GPIO3C HDPINT <36>
70 PCH_PWR_EN RB6 10K_0402_5%
EN_DFAN1/GPIO3D PCH_PWR_EN <38>
1 2 DA Output 71 PCH_SUSPWRDN# PCH_SUSPWRDN# <18>
CB12 0.1U_0402_10V7K KSI0 IREF/GPIO3E SUSACK# GPUPWR_SKIN#
55 KSI0/GPIO30 CHGVADJ/GPIO3F 72 SUSACK# <18> 1 2
KSI1 56 RB28 100K_0402_5%
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
Reserve this signal to EC by SW demand
KSI3 58 83 EC_MUTE#
KSI4 KSI3/GPIO33 EC_MUTE#/GPIO4A USB_EN#
EC_MUTE# <33> 2011/10/18a +3VL
59 KSI4/GPIO34 USB_EN#/GPIO4B 84 USB_EN# <30>
KSI5 60 85 SM_SENSE#
KSI5/GPIO35 CAP_INT#/GPIO4C SM_SENSE# <33>
KSI6 61 PS2 Interface 86 HDPLOCK CEC_INT# 1 2
KSI6/GPIO36 EAPD/GPIO4D HDPLOCK <36>
KSI7 62 87 TP_CLK RB7 100K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <37>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37>
KSO1 40 +3VS LID_SW# 1 2
KSO2 KSO1/GPIO21 RB35 47K_0402_5%
41 KSO2/GPIO22
KSO3 42 97 VGATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <18,46>

2
KSO4 43 98 WOL_EN# AOAC_WAKE# 1 2
KSO4/GPIO24 WOL_EN/GPXIOA01 WOL_EN# <28>
KSO5 PWRME_CTRL RB37 RB29 10K_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 99
VCIN0_PH
PWRME_CTRL <16>
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 VCIN0_PH <40> 10K_0402_5%
KSO7 46 SPI Device Interface VCIN0_PH connect to
C KSO8 KSO7/GPIO27 C
47 power portion (9012 only)

1
KSO9 KSO8/GPIO28 LNB_OC# +3VS
48 KSO9/GPIO29 SPIDI/GPIO5B 119 LNB_OC# <44>
KSI[0..7] KSO10 49 120
<36,37> KSI[0..7] KSO10/GPIO2A SPIDO/GPIO5C
KSO11 50 SPI Flash ROM 126 LNB_EN TP_CLK 1 2
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 LNB_EN <44>
KSO12 51 128 RB8 4.7K_0402_5%
<36,37> KSO[0..17] KSO12/GPIO2C SPICS#/GPIO5A AOAC_WAKE# <27>
KSO13 52
KSO14 KSO13/GPIO2D TP_DATA
53 KSO14/GPIO2E 1 2
KSO15 54 73 UMA_ENBKL RB9 4.7K_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 UMA_ENBKL <13,19>
RB12 2.2K_0402_5% KSO16 81 74 CPSETIN
KSO16/GPIO48 PECI_KB930/GPIO41 CPSETIN <40>
+3VL 1 2 EC_SMB_CK1 KSO17 82 KSO17/GPIO49 FSTCHG/GPIO50 89 HDPACT
HDPACT <36>
1 2 EC_SMB_DA1 BATT_CHG_LED#/GPIO52 90 BATT_FULL_LED#
BATT_FULL_LED# <37>
SYSON 1 2
RB13 2.2K_0402_5% 91 CAPS_LED# RB10 4.7K_0402_5%
CAPS_LED#/GPIO53 CAPS_LED# <36>
EC_SMB_CK1 77 GPIO 92 PWR_ON_LED#
<15,40,41> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_ON_LED# <37>
RB15 2.2K_0402_5% EC_SMB_DA1 78 93 BATT_CHG_LOW_LED# LNB_EN 1 BCAS@ 2
<15,40,41> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# <37>
+3VS 1 2 EC_SMB_CK2 <17,36> EC_SMB_CK2
EC_SMB_CK2 79 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 95 SYSON
SYSON <43>
RB11 10K_0402_5%
1 2 EC_SMB_DA2 <17,36> EC_SMB_DA2
EC_SMB_DA2 80 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 121 VR_ON
VR_ON <46>
RB16 2.2K_0402_5% 127 USB_OC#0 EC_WL_BT_LED 1 2
PM_SLP_S4#/GPIO59 USB_OC#0 <20,30>
RB14 10K_0402_5%

PM_SLP_S3# 6 100 PCH_RSMRST#

<18> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <18>
RB17 SLP_S5# EC_LID_OUT#
14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 101 EC_LID_OUT# <21> PROCHOT_IN connect
0_0402_5% EC_SMI# PROCHOT_IN
<21> EC_SMI# 15 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 102 PROCHOT_IN <40> to power portion (9012 only)
<25,31> USB_CHG_EN# 1 2 USB_CHG_EN#_R CIR_IN 16 GPIO0A H_PROCHOT#_EC/GPXIOA06 103 H_PROCHOT#_EC
USB_OC#1 17 104 VCOUT0_PH_L VCOUT0_PH connect
<20,25,31> USB_OC#1 GPIO0B VCOUT0_PH/GPXIOA07 VS_ON <40,42>
USB_CHG_EN#_R 18 GPO 105 BKOFF# to power portion (9012 only)
GPIO0C BKOFF#/GPXIOA08 BKOFF# <13>
SM_EN 19 GPIO 106 PBTN_OUT# RB18
<33> SM_EN GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <18>
KB_LED 25 107 NV-GPU GPS function control pin 330K_0402_5%
<36> KB_LED EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
FAN_SPEED1 28 108 SA_PGOOD connect to a OR-gate 2 1 +3VL
<5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <45>
WL_OFF# 29 in the power portion
<27> WL_OFF# EC_PME#/GPIO15
E51_TXD 30
<27,36> E51_TXD EC_TX/GPIO16
E51_RXD 31 110 ACIN_D ACIN_D 2 1
<27,36> E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <18,41>
PM_PWROK 32 112 EC_ON_R RB751V40_SC76-2 DB1
B <5,18> PM_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 B
PWR_SUSP_LED# 34 114 ON/OFFBTN#
<37> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <37>
NUM_LED# 36 GPI 115 LID_SW#
<36> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <36>
116 SUSP#
SUSP#/GPXIOD05 SUSP# <33,38,44,45>
117 CEC_INT#
GPXIOD06 CEC_INT# <15>
RB20 118 EC_PECI 1 2 H_PECI
PECI_KB9012/GPXIOD07 H_PECI <5>
AGND/AGND

0_0402_5% 122 RB19 43_0402_1% SUSP# 1 2

XCLKI/GPIO5D +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND

<18> CLK_EC 1 2 123 XCLKO/GPIO5E V18R 124

@ 1
GND0

1 2 PLT_RST# VR_ON 1 2
CB13 1U_0402_6.3V6K CB15 RB23 10K_0402_5%
1

1 4.7U_0805_10V4Z
@ RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113

69

1 2 SUSP# 100K_0402_5% 20P_0402_50V8 SA00004OB20

CB14 180P_0402_50V8J
2
CIR
2

+5VL

Close to EC

1
+3VALW CB17 EC_ON_R 1 2 RB24
EC_ON <42>
0.1U_0402_10V7K RB36 2.2K_0402_5% 10K_0402_5%
1 2 1
CB50

2
5

UB2 Voltage Comparator Pins FOR 9012 A3 1U_0402_6.3V6K UB3 CIR@

1 CIR_IN 1
P

<18> PM_SLP_S5# B 2 Vout

4 SLP_S5# CIR@
Y
<18,31> PM_SLP_S4# 2 A
VCIN0 pin109 >1.2V <1.2V +5VL 1 2 +5VL_CIR 2 VCC
G

VCIN1 pin102 RB26 100_0805_5% 1

TC7SH08FUF_SSOP5 3
3

CB18 GND
A VCOUT0 pin104 4.7U_0805_10V4Z A
HIGH LOW 2
4 GND
@ For KB9012 EC_ON low pulse work around CIR@
1 2 IRM-V538/TR1_3P
RB25 0_0402_5% VCOUT1 pin103 LOW HIGH

RB27
100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 E51_TXD 2011/12/14 2012/12/31 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 35 of 51
5 4 3 2 1
 SPI Flash (128KB) LPC Debug Port
Lid SW Place the JDB under DDR DIMM.

18 G18 16 16
17 G17 15 15
14 14 E51_RXD_DB @
13 13 1
E51_TXD_DB R21 1 @
2 E51_RXD <27,35>
12 12 2 0_0402_5% E51_TXD <27,35>
R23 0_0402_5%
+3VL 11 11
10 10 CLK_PCI_DDR
PLT_RST# <5,20,27,28,29,31,35>
U21 9 9 CLK_PCI_DDR <20>
APX9132ATI-TRL_SOT23-3 8 8 LPC_AD0 <16,35>
7 7 LPC_AD1 <16,35>
6 6 LPC_AD2 <16,35>
2 3 5 5

GND
VDD VOUT LID_SW# <35> LPC_AD3 <16,35>
4 4 LPC_FRAME# <16,35>
3 3 +3VS
1 1 2 2

1
C453 C452 1 1 +3VALW
0.1U_0402_16V4Z 10P_0402_50V8J @ JDB C457 R393
2 2 ACES_88512-1641 CLK_PCI_DDR
1 2 1 2

22P_0402_50V8J 22_0402_5%
@ @

For EMI

UG1 GSENSOR@ GSENSOR@

Keyboard LED JBLG G-Sensor +3VS_HDP 2
12
Vdd1
Vdd2
Voutx
Vouty
3
5
VOUTXCG1
VOUTYCG2
VOUTZCG3
1
1
2
2
0.033U_0402_16V7K
0.033U_0402_16V7K
1 1 +5VS_LED Voutz 7 1 2GSENSOR@
0.033U_0402_16V7K
2 GSENSOR@
Q38 KBL@ 2 SELF_TEST
3 3 4 ST NC1 10
+5VS AO3413_SOT23 4 6 11
4 PD NC2
8 FS NC3 14
S

3 1 +5VS_LED G1 5 NC4 15
1 G2 6 NC5 16
1

R587 C836 E-T_6905K-Q04N-00R +5VS +3VS_HDP

G

+3VS_HDP 9 1
2

10K_0402_5% 0.1U_0402_10V7K @ Rev GND1

GND2 13
KBL@ 2 KBL@
1 1 TSH352TR LGA 16P
2

For EMI CG12 UG3 GSENSOR@ CG13 SA00004GB00

1U_0402_6.3V6K 1U_0402_6.3V6K
Close to JKB GSENSOR@ 1 5 GSENSOR@
VIN VOUT
1

D 2 2
2 Q52 KSO16 1 2 2
<35> KB_LED GND
G 2N7002_SOT23-3 C401 100P_0402_50V8J CG14
S KBL@ KSO17 1 2 3 4 2 1
3

C402 100P_0402_50V8J SHDN# BP

KSO2 1 2 @
C404 100P_0402_50V8J G9191-330T1U_SOT23-5 0.22U_0402_10V4Z
KSO1 1 2 SA000022I00
C405 100P_0402_50V8J
KEYBOARD CONN. KSO0 1
C406
2
100P_0402_50V8J
KSO4 1 2
C407 100P_0402_50V8J UG5
KSI[0..7] KSO3 1 2
KSI[0..7] <35,37>
C408 100P_0402_50V8J 1 11 HDPACT <35>
KSO[0..17] <17,35> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
KSO5 1 2
KSO[0..17] <35,37>

2
C409 100P_0402_50V8J
KSO14 1 2 SELF_TEST 2 12 RG9
C410 100P_0402_50V8J P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
36 GND2
35 KSO6 1 2 GSENSOR@
GND1 JKB34 C411 100P_0402_50V8J RG3 2
34 34 1 2 +3VS +3VS_HDP 1 3 13

1
KSO16 R372 300_0402_5% KSO7 GSENSOR@ 4.7K_0402_5% RESET# P1_4/TXD0
33 33 1
C412
2
100P_0402_50V8J
32 32 KSO17 KSO13 RG4 2
31 31 1 2 1GXOUT 4 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT 14 HDPLOCK <35>
C413 100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
30 30 KSO8 RG10 47K_0402_5%
29 29 KSO2
1
C415
2
100P_0402_50V8J VOUTZ
28 28 KSO1 KSO9
5 VSS/AVSS P1_2/KI2#/AN10/CMP0_2 15 2
GSENSOR@
1
27 27 KSO0
1
C416
2
100P_0402_50V8J
26 26 SA00003A600
KSO4 KSO10 RG5 2 1GXIN
25 25 KSO3
1
C417
2
100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP
24 24 KSO5 KSO11
23 23 KSO14
1
C418
2
100P_0402_50V8J VOUTX
1
CG6
22 22 7 VCC/AVCC P1_1/KI1#/AN9/CMP0_1 17
KSO6 KSO12 0.1U_0402_10V7K
21 21 KSO7
1
C419
2
100P_0402_50V8J GSENSOR@
20 20 KSO13 KSO15 RG6 2
19 19 1 2 2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY
18 KSO8 C420 100P_0402_50V8J GSENSOR@
18 KSO9 KSI7
17 17 KSO10
1
C421
2
100P_0402_50V8J HDPINT RG7
16 16 <35> HDPINT 2 1 1K_0402_5% 9 P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 19
KSO11 KSI2 GSENSOR@
15 15 KSO12
1
C422
2
100P_0402_50V8J
14 14
KSO15 KSI3
13 13 KSI7
1
C423
2
100P_0402_50V8J
1 1
CG8
10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 <17,35>
12 12 KSI2 KSI4 CG7 GSENSOR@
11 11 KSI3
1
C424
2
100P_0402_50V8J 0.1U_0402_10V7K 0.1U_0402_10V7K R5F211B4D34SP GSENSOR@
10 10
KSI4 KSI0 GSENSOR@ 2 2
9 9 KSI0
1
C425
2
100P_0402_50V8J
8 8 KSI5 KSI5
7 7 1 2
KSI6 C427 100P_0402_50V8J
6 6 KSI1 KSI6
5 5 JKB4
1
C429
2
100P_0402_50V8J
4 4 2 1
CAPS_LED# R376 300_0402_5%
+3VS
KSI1
3 3 CAPS_LED# <35> 1 2
C431 100P_0402_50V8J
2 2 NUM_LED# CAPS_LED# Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 NUM_LED# <35> 1
C433
2
100P_0402_50V8J
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title
JKB NUM_LED# 1 2
HB_A803419-SBHR21 C435 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 36 of 51
 5 4 3 2 1

+3VL
Power Button +5VS +1.8VS

2
1 1
R395 C463 C464
0.1U_0402_25V6 0.1U_0402_25V6
100K_0402_5%
2 2
Touchpad Connector

1
ON/OFFBTN#
ON/OFFBTN# <35>
1
C458 JTP Add C463/C464 for ESD request 12/20
For debug 0.1U_0402_25V6 1
@ +3VS 1
<35> TP_DATA 2 2
2 +CRT_VCC B+ B+ +5VS +3VS +3VS +3VS +3VS +3VS +3VS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
D83 3
<35> TP_CLK 3

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
SW3 ON/OFFBTN# 2 4 4
1 2 1 <11,12,17,27> PM_SMBCLK 5 5 1 1 1 1 1 1 1 1 1 1 Near UH1

C469

C472

C473

C474

C478

C479

C481

C482

C483

C484
PWR_ON_LED# 3 6 Near CRT side
D <11,12,17,27> PM_SMBDATA 6 D
3 4 For EMI request
L30ESD24VC3-2_SOT23-3
G
G

7 GND
NTC017-DA1J-D160T_4P 2 2 2 2 2 2 2 2 2 2
8
6
5

GND
ACES_88058-060N
@
@

@
+5VS +5VS +5VS +3VALW_PCH +3VALW_PCH +3VALW_PCH B+ B+

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
JPOWER D89

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_25V6

0.1U_0402_25V6
1 PWR_ON_LED# TP_DATA 2
1
2 2 1 2 +5VALW 1 1 1 1 1 1 1 1 1

C475

C476

C477

C485

C486

C487

C488

C491
3 ON/OFFBTN# R22 390_0402_5% TP_CLK 3 Near Q24 Near PC268
3
4 4
YSDA0502C_SOT23-3
@ 2 2 2 2 2 2 2 2
GND 5
GND 6

JOINT_F1017WR-S-04P
please place near JFUNCTION
Add C469~C487 for ESD request 02/01

Screw Hole
BATT CHARGE /FULL LED & AC IN WiMAX LED
LED_WIMAX# <27>
D21 CPU VGA

2
White
R48 R819 H1 H2 H3 H7
2 1 2 +3VS 2 1 6 1 H_4P2 H_4P7 H_4P2x4P7 H_4P0N
BATT_FULL_LED# <35>
390_0402_5% 10K_0402_5% @ @ @ @

5
+5VALW 1 R52 D23 WIMAX@ Q156A

1
3 1 2 2N7002DW-T/R7_SOT363-6
BATT_CHG_LOW_LED# <35>
510_0402_5% +5VALW 1 2 2 1 3 4 WIMAX@
R66 A
Amber 510_0402_5% Q156B 2N7002DW-T/R7_SOT363-6
C C
HT-210UD5/BP5-A1681 _AMBER-WHITE HT-110UD5_AMBER WIMAX@

3
White LED bright when AC-adaptor is plugged and a Battery is full charged WL_BT_LED# <35>
MINI CARD -- 3G MINI CARD -- WLAN
Amber LED bright when charging battery from AC-adaptor
Amber LED blink during Critical Low battery
H28 H29
H_3P3 H_3P3
@ @
POWER LED

1
D22
White
R49
2 1 2 PWR_ON_LED# <35>
390_0402_5% NPTH
+5VALW 1 R53
3 1 2 PWR_SUSP_LED# <35>
510_0402_5% H10 H13 H14 H15 H16 H20 H21 H23 H24 H30 H22
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2x3P7N H_3P2N
Amber @ @ @ @ @ @ @ @ @ @ @
HT-210UD5/BP5-A1681 _AMBER-WHITE

1
PCB Fedical Mark PAD
B FD1 FD2 FD3 FD4 B

FUNCTION/B Connector @ @ @ @

1
@
JFUN
6 R8 390_0402_5%
GND
GND

4
5

4
+5VS_FUNC 2 1 +5VS
ISPD
3 3 FUNCTION_LED# <35>
2 KSO0
2 KSO0 <35,36>
1 KSIFUNCTION
1
D90
JOINT_F1017WR-S-04P 1 3D@ 2 R1467 KSI7 KSI7 <35,36>
ZZZ UH1 HM77R1@ UH1 HM76R1@
0_0402_5% KSIFUNCTION 1 4 KSO0
I/O1 I/O3
1 ECO@ 2 R1466 KSI6 KSI6 <35,36> R1 R1
0_0402_5% DAZ0OT00200 SA00005AGH0 SA00005FHA0
SLJ8C SLJ8E
2 GND VDD 5
PCB LA-8392P Panther Point 82HM77 C-1 HM77 Panther Point HM76 SLJ8E C1
Green LED SC500009S00 VF=2.8V~3.15V, Isink<15mA
3 6 FUNCTION_LED# PJP1 45@
I/O2 I/O4
White LED SC500004W00 VF=2.75V~3.15V, Isink<15mA
AZC099-04S.R7G_SOT23-6
DC30100AA00 R3
SA00005FHE0
SLJ8E
please place near JFUNCTION PJP1 HM76R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 37 of 51
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +5VALW

2
4.7U_0805_10V4Z +5VS

2
1 1 1 1 R470
Q29 C460 4.7U_0805_10V4Z Q30 C462 R5545 470_0805_5%

470_0805_5%

470_0805_5%
8 1 C459 8 1 C461 For EMI 10K_0402_5%
D S D S

2
7 2 1U_0402_6.3V6K 7 2 1U_0402_6.3V6K

1
D S 2 2 R406 D S 2 2 R407

0.1U_0402_10V7K

0.1U_0402_10V7K
6 3 6 3

1
D S D S PCH_PWR_EN#
5 D G 4 5 D G 4 2 2 <22,23,28> PCH_PWR_EN#
C822 C821

1
SI4800BDY_SO8 D
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB Q190

3 1

3 1
1 120K_0402_5% 200K_0402_5% @ @ SUSP 1

0.01U_0402_25V7K
0.022U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 2

1
C466 1 1 D G
C465 R412 Q10A C467 C468 R413 Q11A 1 R5534 2 2 Q5527 S 2N7002_SOT23-3
<35> PCH_PWR_EN

3
820K_0402_5% Q10B 820K_0402_5% Q11B 0_0402_5% G

1
2 2 SUSP 2 2 @ SUSP S SB570020110
2 5 2 5

3
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002E-T1-E3_SOT23-3
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 R5529

4
100K_0402_5%

2
Un-used Dual MOS Add Q41 for S3
resume problem +3VALW
12/14 For S3 CPU Power Saving
3

Q6B

2
+5VALW +0.75VS +1.05VS_VCCP
5 <43> 0.75VR_OFF# R425
100K_0402_5%

2
2N7002DW-T/R7_SOT363-6 Q44A
4

2N7002DW-T/R7_SOT363-6 R422 R421 R468

1
100K_0402_5% 22_0805_5% 470_0805_5%
0.75VR_EN# <43>
SUSP 2

3
For filter noise

1
SUSP
<5,9,27,43> SUSP

1
Q44B

6
Reserve for SW-node noise <44,45> VCCP_PWRGOOD 1 2 0.75VR_EN 5 2N7002DW-T/R7_SOT363-6

1
R158 100K_0402_5% Q6A D Q189 D Q60
place at noise source
2 SUSP 2 2N7002_SOT23-3

4
2 G G
2 +5VALW +1.8VS <33,35,44,45> SUSP# 2
S 2N7002_SOT23-3 S

3
2N7002DW-T/R7_SOT363-6

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

1 1 2 1 1
C470 C366 C371 C381 C382

@ @
2 2 1 2 2

C372,C373 near to PQ352 C389 near to Q49

C387,C388 near to D84 +5VS_ODD
+5VALW
+5VALW +3VALW TO +3V_WLAN
+5VS TO +5VS_ODD

2
for AOAC and WOWL R457
10U_0603_6.3V6M

0.1U_0402_10V7K

1 2
C372 C373 470_0805_5%
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2 2
C387 C388 C389
@ @

6 1
2 1
2 1 1
Q53A

2 ODD_EN#

C374,C383 near to 2N7002DW-T/R7_SOT363-6

1
PQ402 and place on TOP +5VS
C391 near to CH93 +3VALW
3 3
+5VS +5VS +3VALW +3VS +5VS

2
1

2
C471 Vgs=-4.5V,Id=3A,Rds<97mohm
0.1U_0402_10V7K

0.1U_0402_10V7K

2
R1456 C907 Vgs=-4.5V,Id=3A,Rds<97mohm R441 0.1U_0402_10V7K
10U_0603_6.3V6M

1 2 2
C374 100K_0402_5% 10K_0402_5%

2
C383 C391 0.1U_0402_10V7K 1

3
1 R440 Q45
S
PJ28

2
2

1
3
2 1 1 S
R105
G
G <21> ODD_EN# 4 3 1 2 2 JUMP_43X79
1 2 2 AO3413_SOT23 0_0805_5% @
<27,35> AOAC_EN# +5VS_ODD

1
Q210 @ 2N7002DW-T/R7_SOT363-6 47K_0402_5% 2
D

1
47K_0402_5% 2 1 D Q53B AO3413_SOT23

1
C217
R1457 C908 +3V_WLAN 0.01U_0402_25V7K
C384 near to RW2 C392,C390 near to PL332 1
0.01U_0402_25V7K 1
1
1
+5VS +3VALW C680
need mount R105 if system C679 1U_0402_6.3V6K
4.7U_0805_10V4Z 2
don't support AOAC or WOWL 2
@
10U_0603_6.3V6M

0.1U_0402_10V7K

1
C384
10U_0603_6.3V6M

1 2
C392 @
@ C390
2 @
2 1

C386,C385 near to PC364

+3VS
0.1U_0402_10V7K
10U_0603_6.3V6M

4 1 2 4
C386 @
C385
@
2 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 38 of 51
A B C D E
 A B C D

VIN
@ PJP1 PL1
PF1 SMB3025500YA_2P
1 DC_IN_S1 1 2 DC_IN_S2 1 2
+
2 10A_125V_451010MRL
+

1000P_0402_50V7K

1000P_0402_50V7K

100P_0402_50V8J
100P_0402_50V8J
- 3

1
1 1

PC4
PC1

PC2

PC3
-
SINGA_2DW-0005-B03

2
RTC Battery
2 2

- PBJ1 + PR5 PR6

560_0603_5% 560_0603_5%
2 1 1 2 1 2 +RTCBATT +RTCBATT

@ MAXEL_ML1220T10

SP093MX0000

@ PJ333 @ PJ332
+3VLP 2 2 1 1 +3VL +3VALWP 2 2 1 1 +3VALW
JUMP_43X39 JUMP_43X118
(100mA,40mils ,Via NO.= 2) (5A,200mils ,Via NO.= 10)
OCP=6.2A
@ PJ353 @ PJ352
3 3

VL 2 2 1 1 +5VL +5VALWP 2 2 1 1 +5VALW

JUMP_43X39 JUMP_43X118 @ PJ162
+16VSP 2 2 1 1 +16VS
(10.63A,425mils ,Via NO.= 20)
OCP=12.3A JUMP_43X79

@ PJ72
+VSBP 2 2 1 1 +VSB
JUMP_43X39 @ PJ402
(120mA,40mils ,Via NO.= 1) 2 2 1 1

JUMP_43X118

@ PJ182 @ PJ403
+1.8VSP 2 2 1 1 +1.8VS +1.05VS_VCCPP 2 2 1 1 +1.05VS_VCCP
JUMP_43X118 JUMP_43X118
(1.65A,70mils ,Via NO.= 4) (14A,560mils ,Via NO.=28)
OCP=4.2A OCP=16.92A
ACIN
Precharge detector
Min. typ. Max.
H-->L 14.42V 14.74V 15.23V
@ PJ76 @ PJ152
4
2 1 2
L-->H 15.39V 15.88V 16.39V 4

+0.75VSP 2 1 +0.75VS +1.5VP 2 1 1 +1.5V

JUMP_43X79 JUMP_43X118
(0.5A,40mils ,Via NO.= 1) (6A, 240mils ,Via NO.= 12)
OCP=9.5A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 39 of 51
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 56 degree C

1
Rset = 3 * Rtmh 1

VMB Rhyst = (Rset* Rtml) / (3*Rtml - Rset)

PL2
SUYIN_200045MR009G171ZR PF2 SMB3025500YA_2P
13 9 BATT_S1 1 2 1 2
Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K
GND 9 BATT+
12
11
GND 8 8
7 15A_65V_451015MRL
Rset = 3 * 7.87K = 23.61K ==> 23.7K
GND 7 BATT_P4
10 GND 6 6
5 BATT_P5
Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
5

1
4 EC_SMDA PC8
4 PC7

1
3 EC_SMCA @ PC15
3 PR14 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K
2

2
2 1K_0402_1%
1 1

@ PJP2

2
PD6 +3VLP
1

PJSOT24C_SOT23-3

10.7K_0402_1%
PD5 2 VL

9012@ PR17
PJSOT24C_SOT23-3 1

1
3

1
PR16
6.49K_0402_1%
2

1
2 1 930@ PR15
+3VL 930@ PC9 23.7K_0402_1%

2
0.1U_0603_25V7K

2
1 2 VCIN0_PH <35>
1

11.3K_0402_1%
2
PR19 9012@ PR33 2

2
930@ PR18
0_0402_5%
1K_0402_1%

1
ADP_I <35,41>

+3VS PH1
2
2

1
100K_0402_1%
930@ PU2

2
PR20 PR21 1 8 9012@PR22
9012@ PR22 100K_0402_1%_NCP15WF104F03RC
BATT_TEMPA <35>

1
VCC TMSNS1

930@ PR29
100_0402_1% 12.7K_0402_1%
100_0402_1%

2
2 7 @PC17
@ PC17
<5,35> H_PROCHOT# GND RHYST1 .1U_0402_16V7K
1

2
EC_SMB_DA1 <15,35,41> 3 6 1 2

1
OT1 TMSNS2

1
D
930@ PQ7 2 4 5 1 2 1 2
OT2 RHYST2 PROCHOT_IN <35>
SSM3K7002FU_SC70-3 G
S G718TM1U_SOT23-8 930@ PR28 9012@ PR32
EC_SMB_CK1 <15,35,41>

3
30.9K_0402_1% 0_0402_5%

QC@ PQ8A

6
D DMN66D0LDW-7_SOT363-6

100K_0402_1%
<35,42> VS_ON 2

2
G

9012@ PR27
S

2 1
QC@ PR30
56.2K_0402_1%
1
PQ5
TP0610K-T1-E3_SOT23-3

1
QC@ PR35
B+ 3 1 100K_0402_1%
3
+VSBP 2 1
3

VL
0.22U_0603_25V7K
100K_0402_1%
1

QC@ PQ8B
PC10
1

1
PR23

PC11 @ DMN66D0LDW-7_SOT363-6
QC@ PC16

3
D
VL @ 0.1U_0603_25V7K .1U_0402_16V7K
2

2
5
G
2

CPSETIN <35>
PR24
2

4
1 2
PR25 22K_0402_1%
100K_0402_1%
1

D
PR26
1 2 2 PQ6
<18,42> POK
G SSM3K7002FU_SC70-3 Adaptor protection
0_0402_5%
S
3

Adaptor Throttling point ADP_I Recovery point ADP_I

1

@ PC12
.1U_0402_16V7K
90W 113.5W 1.783V 86.4W 1.357V
2

65W 71.8W 1.504V 62.5W 1.308V

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 40 of 51
A B C D
 A B C D

for reverse input protection

1
D
2 PQ206
G SI1304BDL-T1-E3_SC70-3
S

3
1 2 1 2
1 1

PR212 PR213
1M_0402_5% 3M_0402_5%

VIN P1 B+ PQ205
PQ203 PQ204 P2 PL201 PR215 MDS2659URH_SO8
TPCA8057-H 1N PPAK56-8 MDS2659URH_SO8 1UH_10.3A_20% 0.01_2512_1%
1 1 8 1 2 1 4 8 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2 2 7 7 2

100P_0402_25V8K

220P_0402_25V8K
10U_0805_25V6K

10U_0805_25V6K

68P_0402_50V8J
0.1U_0402_25V6
5 3 3 6 2 3 6 3

0.1U_0402_25V6

PC224

PC225

PC226

PC227

PC219

PC220

@ PC229

@ PC230

@ PC231
5 5
1

1
0_0402_5%

PC221

PC222

0.01U_0402_50V7K
@ PR220

1
VIN

0_0402_5%
PC208

PR216
4

1
2200P_0402_50V7K

PC216
2

2
1 2 @
2
1

2
3

2
PC213

PC212 @

2
0.1U_0603_25V7K
0.1U_0402_25V6 PD201
2

0.1U_0402_25V6
BQ24725_ACDRV_1 BAS40CW_SOT323-3

1
PC217
BQ24725_BATDRV 1 2BQ24725_BATDRV_1

PC218
0.047U_0402_25V7K

SIS412DN-T1-GE3_POWERPAK8-5
PR203

1 1

10_1206_1%
4.12K_0603_1%
PC205

PR210
1 2

5
0_0603_5%
PR205
PD202

BQ24725_VCC
2

PQ201
RB751V-40_SOD323-2

BQ24725_BST 2

BQ24725_REGN2
2
DH_CHG1 2DH_CHG1 4 2
4.12K_0603_1%

4.12K_0603_1%

PC207 PR217

BQ24725_LX
1

1 2 0_0402_5%

DH_CHG
PR221

PL202
PR222

1U_0603_25V6K PC214 4.7UH_ETQP3W4R7WFN_5.5A_20% PR225

3
2
1
0.01_1206_1%

BQ24725_ACN
1 2

BQ24725_ACP
BQ24725_LX 1 2 CHG 1 4 BATT+
2

1U_0603_25V6K

5
6
7
8
20

19

18

17

16
2 3

AO4468L_SO8
PU200

1 CSOP1

1 CSON1
0.1U_0402_25V6

0.1U_0402_25V6
1

4.7_1206_5%
VCC

PHASE

HIDRV

BTST

REGN

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PQ202

220P_0402_25V8K
PR206

68P_0402_50V8J
21 PAD

@ PC232

@ PC233
PC215

PC223

PC203

PC202

PC201
1

1
1 15 DL_CHG 4
ACN LODRV @

2
2 14 @
ACP GND PR218

3
2
1

1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1% @PC206
@ PC206
BQ24725_CMSRC 3 13 SRP1 2 CSOP1 680P_0603_50V7K
CMSRC SRP

1
PR214

2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN

+3VL 1 2 BQ24725_ACOK 5 ACOK BATDRV 11 BQ24725_BATDRV PC209

PR219 10K_0402_1% 0.1U_0603_16V7K
ACDET

IOUT Remember to change PC124 from SE000006S80

SDA

ILIM
SCL
1 2 to SE025104K80 (2011-02-22)
<18,35> ACIN PR204 10K_0402_1%
+3VALW
6

10
3 3

PR209
BQ24725_ILIM 1 2

0.01U_0402_25V7K
100K_0402_1%
402K_0402_1%
1

PC204
PR201

1
BQ24725_ACDET

VIN 1 2

2
154K_0402_1%

PR208
2
1

270K_0402_1%
VIN
PR207
2

1
Vin Dectector PC269 PR226
66.5K_0402_1%
0.1U_0402_25V6

100P_0402_50V8J
EC_SMB_CK1 <15,35,40> 309K_0402_1%
1

100_0402_5%

Min. Typ Max. 2 1

1

2
PC211

PR202

PR227

2
PR211

H-->L 17.3V 10K_0402_1%

EC_SMB_DA1 <15,35,40> 1 2 ADP_V <35>
2

L--> H 17.8V
2

PC210
1

1
2 1 ADP_I <35,40>

1
PC228
ILIM and external DPM 100P_0402_50V8J
PR228
47K_0402_1% .1U_0402_16V7K
3.97A

2
2
Please locate the RC
4
Near EC chip 4

2011-02-22

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 41 of 51
A B C D
 5 4 3 2 1

2VREF_8205

D D

1
PC363
1U_0603_10V6K

2
PR362 PR364
14K_0402_1% 30K_0402_1%
1 2 1 2

PR363 PR365
3/5V _B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 3/5V _B+
PL331
FBMA-L11-201209-121LMA50T_0805

ENTRIP1
ENTRIP2
B+ 2 1 +3VLP PR337
100P_0402_25V8K

220P_0402_25V8K
68P_0402_50V8J

PR357
2200P_0402_25V7K

2200P_0402_25V7K
150K_0402_1%
@ PC234

@ PC235

@ PC236

10U_0805_25V6K
4.7U_0805_25V6K

165K_0402_1%
1

1
PC367

PC360

4.7U_0805_25V6K
SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5
1 2 1 2

1
PC369

PC368
PC366
2

5
4.7U_0805_10V6K

2
6

1
PU330

1
PC361

VREF
ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
PQ331

C C

PQ351
25

2
P PAD
4 4

7 VO2 VO1 24 POK <18,40>

PC335 8 23
1
2
3

3
2
1
0.1U_0603_25V7K VREG3 PGOOD PC355
PR335 PR355
1 2 1 2 BST_3V 9 VBST2 VBST1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 PR338 0_0603_5%
UG_3V UG_5V
0_0603_5% PR358 PL352 +5VALWP
1 2 10 DRVH2 DRVH1 21 1 2
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% 2.2UH_PCMC063T-2R2MN_8A_20%
0_0603_5% 0_0603_5%
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1

680P_0603_50V7K 4.7_1206_5%
FDMC7692S_MLP8-5
LG_3V 12 19 LG_5V
DRVL2 DRVL1
1

8
7
6
5

@ PR356
SKIPSEL

220U_6.3V_M

220U_6.3V_M
PQ332

VREG5
220P_0402_25V8K

220P_0402_25V8K
PQ352
68P_0402_50V8J

330U_6.3V_M

68P_0402_50V8J
VCLK
1 @ PR336

GND
1 1

EN0

VIN
4.7_1206_5%
@ PC237

@ PC238

@ PC239

@ PC240
1

1
+ + +
PC331

PC351

PC352
4
1 2

1 2
4 PR360 TPS51125

13

14

15

16

17

18
499K_0402_1%

@ PC356
@ PC336
2

2
2 680P_0603_50V7K 2 2
B+ 1 2
2

3
2
1

2
15mohm AO4468L_SO8

100K_0402_5%
1
2
3

1
1
VL

PR361
PC362

1
1U_0402_6.3V6K
PC364
2
B B
4.7U_0805_10V6K

2
3/5V _B+

2
Ipeak=5A Ipeak=10.63A
Imax=3.5A ENTRIP1 ENTRIP2 Imax=7.44A
F=305KHz F=245KHz

1
PC365
Total Capacitor 330uF 2VREF_8205
Total Capacitor 440uF
6

D D 0.1U_0603_25V7K
ESR 15mohm ESR 8.5mohm

2
2 5
PQ360A G G PQ360B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
S S
1

SB00000EO00
PR370
VL 2 1
100K_0402_1%
1

<35,40> VS_ON

2
0.01U_0402_16V7K
42.2K_0402_1%

PQ361
1

A A
1

DTC115EUA_SC70-3
PR372

@PC370

1 2
<35> EC_ON
2

9012@ PR373
2

0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 42 of 51
5 4 3 2 1
 A B C D

UMA DIS
Ipeak=8.5A Ipeak=20A
HW side: Imax=5.95A Imax=14A
C106 330uF 17m Rtrip=5.9K, OCP=11.338A Rtrip=14K, OCP=24.136A
C218 390uF 10m F=315KHz F=315KHz
VGA@ CV122 390uF 10m Total Capacitor 1050uF, Total Capacitor 1440uF,
@ C189 330uF 15m ESR 4.43mohm ESR 3.07mohm

1 1

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A

1
@PC156
@ PC156
680P_0603_50V7K

2 SNUB_+1.5VP
4.7_1206_5%
2
PR156
PL151 PL152

1
4
HCB1608KF-121T30_0603 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1 2 1.5V_B+ 10 2 1 2
+5VALW

PG
2
PVIN LX +1.5VP 2
9 PVIN LX 3

220P_0402_25V8K
150K_0402_1%

68P_0402_50V8J
22U_0805_6.3V6K

22U_0805_6.3V6K

22U_0805_6.3V6K

22U_0805_6.3V6K
8 SVIN
100P_0402_25V8K

220P_0402_25V8K

2200P_0402_50V7K

22U_0805_6.3VAM

PR164

@ PC245

@ PC244
68P_0402_50V8J

22P_0402_50V8J
22U_0805_6.3V6K
PR163

1
@ PC242

@ PC243

@ PC241 0_0402_5% 6
FB
1

PC160

PC155

PC157

PC158

PC159
1 2 EN_1.5V 5
<35> SYSON EN

PC152

PC153

PC154
PU150

SS
TP

LX

2
SY8036DBC_DFN10_3x3
2

1
@PC166
@ PC166

11

1
0.1U_0402_10V7K

2
100K_0402_1%
2

PR165

1
Mode Level +0.75VSP VTTREF_1.5V
+1.5V
S5 L off off
S3 L off on
1

S0 H on on @PJ75
@ PJ75
1

3 3

JUMP_43X79
Note: S3 - sleep ; S5 - power off
2 2

PU75
1 VIN VCNTL 6 +3VALW
PC265 2 5
<38> 0.75VR_OFF# GND NC
2

1
4.7U_0805_6.3V6K
1

3 7 PC264
@ PR282
@PR282 PR280 VREF NC
1

2
0_0402_5% 1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
1 2
<5,9,27,38> SUSP 9
2

TP
G2992F1U_SO8
.1U_0402_16V7K

PR279
+0.75VSP
1

D
SSM3K7002FU_SC70-3

75K_0402_1%
PQ260

1K_0402_1%

PC263

1 2 2
<38> 0.75VR_EN#
1

G
2

S PR281 PC262
3
1

10U_0805_6.3V6M
2

PC261
.1U_0402_16V7K
2

For shortage changed

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 43 of 51
A B C D
 5 4 3 2 1

PL401
FBMA-L11-201209-121LMA50T_0805
+1.05VSP_B+ 2 1
B+

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

4.7U_0805_25V6-K

100P_0402_25V8K

220P_0402_25V8K
68P_0402_50V8J
@ PC247

@ PC248

@ PC246
1

1
PC402

PC403

@ PC404

PC411
D D

PR401

2
3.4K_0402_1% DIS

5
2 1
+5VALW Ipeak=14A

MDV1525URH
PR402
Imax=9.8A
F=300KHz

PQ401
6.49K_0402_1% PR405 PC405
2 1 2.2_0603_1% 0.1U_0603_25V7K 4
<38,45> VCCP_PWRGOOD
1 2 BST1_+1.05VSP 1 2
Total Capacitor 1320uF,
ESR 2.5mohm
PU400
PR404 1 10 BST_+1.05VSP PR403

3
2
1
64.9K_0402_1% PGOOD VBST 0_0402_5%
1 2 TRIP_+1.05VSP 2 TRIP DRVH 9 UG_+1.05VSP 1 2 UG_+1.05VSP1 PL402 +1.05VS_VCCPP
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
EN_+1.05VSP 3 8 SW_+1.05VSP 1 2
EN SW

4.7_1206_5%
PR407 FB_+1.05VSP 4 7
VFB V5IN
+5VALW

PR406
TPCA8059-H_PPAK56-8-5
0_0402_5%
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP
<33,35,38,45> SUSP# TST DRVL

68P_0402_50V8J

0.1U_0402_25V6K
1

@ PC250
330U_2.5V_M

PC249
11

1SNUB_+1.05VSP 2
TP
1

1
PQ402
+

PC401
PC407 4
TPS51212 1U_0603_10V6K

2
1

PR408

2
@ PC408 470K_0402_1% 2
0.1U_0402_16V7K
2

3
2
1

.1U_0402_16V7K
C C

PC410
PC406

2
680P_0603_50V7K
@ PC409 @ PR409

2
1000P_0402_50V7K 1.2K_0402_1%
1 2 +1.05VSP1 1 2 +1.05VS_VCCPP

PR411 PR413
4.99K_0402_1% 100_0402_1%
2 1 VCCIO_SENSE1 2 1 VCCIO_SENSE <8>
2

PR410
10K_0402_1%
1

B B

TV@ PD203
TV@ PL161 BAT43WS-7-F_SOD323-2 TV@ PL162
TV@ PU161 10UH_MLPS-5020-100M-E_1.5A_20% MCK1608471YZF_0603 +16VSP
1 1 2 LX_AVDD 2 1 1 2
VOUT

1
22U_0805_6.3V6M

22U_0805_6.3V6M

100P_0402_25V8K

100P_0402_25V8K
604K_0603_1%

TV@ PC1036

TV@ PC1037
10U_0805_25V6K

10U_0805_25V6K
+5VALW 5 VIN 1 1

1
TV@ PC963

TV@ PC964

TV@ PR805

@ PC266

@ PC267
2.2U_0603_16V6K

GND 2

1
TV@ PC1035

2
1

4 TV@ PU160

2
EN# 2 2
3 1

2
OCB TV@ PR810 LX
5
2

47K_0402_1% VIN
GND 2

1
APL3511CBI-TRG_SOT23-5 1 2 4 EN

TV@ PR806
51.1K_0402_1%
FB 3
0.1U_0402_10V7K

TV@ PR807
1 2 APW7137BI-TRG_SOT23-5
<35> LNB_EN

2
1
@ PC1040

47K_0402_1%
100K_0402_1%
0.1U_0402_10V7K

<35> LNB_OC#
2
2
@ PC1039
1

@ PR808
2

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 44 of 51
5 4 3 2 1
 5 4 3 2 1

The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. VID [0] VID[1] VCCSA Vout
0 0 0.9V
D D
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network

1
PC456
680P_0603_50V7K

2 SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A

2
PR456 OCP current 7.2A
4.7_1206_5%

1
PL451 PU450 PL452
HCB1608KF-121T30_0603 SY8037BDCC 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+5VALW 1 2 +VCCSA_PWR_SRC 12 PVIN LX 1 +VCCSA_PHASE 1 2 +VCCSA
11 PVIN LX 2
PC457

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
68P_0402_50V8J 10 3 PR459 SA_PGOOD <35>
SVIN LX

2
PC451

PC452

PC453

PC454
2200P_0402_50V7K
100K_0402_5%

22U_0805_6.3VAM

22U_0805_6.3VAM
0.1U_0603_25V7K
C +VCCSAP_FB
2 1 9 4 2 1 C
2 FB PG +3VS

1
PC461

PC460

PC459

PC458

1
8 5 +VCCSA_EN 1 2
VOUT EN

GND
2

2
1 PR458
7 VID1 VID0 6
0_0402_5%

0.1U_0402_10V7K
13
PR455

PC455
100_0402_5%

2
1K_0402_5%

1K_0402_5%
<38,44> VCCP_PWRGOOD 2 1

PR460

PR461

2
PR457
0_0402_5%

1
2 1 +VCCSA_SENSE <9>

H_VCCSA_VID0 <9>

H_VCCSA_VID1 <9>

B B

PU180
PL181 SY8033BDBC_DFN10_3X3 PL182
4

HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
+5VALW 1 2 10 2 LX_1.8V 1 2 +1.8VSP Ipeak=1.308A
PG

PVIN LX
ILIM = 4A

68P_0402_50V8J
9 PVIN LX 3

1
F=1MHz
1

1
4.7_1206_5%

PC187
PC184 8 SVIN
PR186
22U_0805_6.3VAM PR183
FB=0.6Volt 20K_0402_1%

22U_0805_6.3VAM
6

22U_0805_6.3VAM
2

2
FB
5

2
EN

1
NC

NC
TP

PC183
PC182
2

FB_1.8V
11

2
680P_0603_50V7K
PR181 EN_1.8V
<33,35,38,44> SUSP# 1 2
1

1
PC186

150K_0402_1%
PR184
1

10K_0402_1%
1

@ PR182 PC185

2
499K_0402_1% 0.1U_0402_10V7K
2
2

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 45 of 51
5 4 3 2 1
 5 4 3 2 1

DISABLE GFX function 3D@ PC554 3D@ PC549 3D@ PR549 3D@ PR552 3D@ PC560 3D@ PR571
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
DCG@ PR552 GFX@ PC552
1K_0402_1% 1000P_0402_50V7K
DC/QC GFX SWITCH QCG@ PR549 QCG@ PR552 QCG@ PR560 QCG@ PR564 CSCOMPA 1 2 DROOPA 1 2 CSREFA
24K_0402_1% 1.65K_0402_1% 24K_0402_1% 39K_0402_1%

2P: 1.65K
1P: 1K
Disable: 0 Ohm Disable: 0 Ohm
GFX@ PR547 GFX@ PC547 GFX@ PC548 Disable: 0 Ohm
10_0402_1% 0.033U_0402_16V7K 2P: 24K .1U_0402_16V7K

1200P_0402_50V7K

680P_0402_50V7K
1 2 FBA3 1 2 1 2
1P: 24.9K

75K_0402_1%
GFX@ PC550

GFX@ PR551
D D

2
GFX@ PC549
GFX@ PR548 GFX@ PR550 TSENSEA TSENSE

1
8.06K_0402_1% 806_0402_1%

100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ
1 2
TRBSTA# 1 2 FBA1 1 2 GFX@ PH501
Disable: 0 Ohm DCG@ PR549 220K_0402_5%_ERTJ0EV224J

1
1
24.9K_0402_1%

137K_0402_1%
GFX@ PC551 GFX@ PR554 GFX@ PC553 GFX@ PC554

2 PR588 1

2
137K_0402_1%
0.033U_0402_16V7K 10_0402_1% 330P_0402_50V7K 10P_0402_50V8J 2 1 NTC_PH203

GFX@ PR561

GFX@ PH502

PH503
1 2 FBA2 1 2 1 2 GFX@ PR553
165K_0402_1% 2P: install
1 2 1 2 COMPA1 1 2 1 2 SWN2A 1P: @

1
QCG@PR557
QCG@ PR557
GFX@ PR555 GFX@ PR556 GFX@ PC555 64.9K_0603_1% CSREFA

0_0402_5%
1K_0402_1% 5.11K_0402_1% 3300P_0402_25V7K GFX@ PC556

2
@ PR603
1 2 SWN1A 0.047U_0402_16V7K

2P: 21.5K GFX@ PR558 GFX@ PR559 6.98K_0402_1%

1
16.5K_0402_1%
1P: 15.8K 63.4K_0603_1% CSP1A 1 2 SWN1A <47>

1
2

2
DCG@ PR560
<9> VCC_AXG_SENSE
GFX@ PC557

2
1000P_0402_50V7K CSREFA
<9> VSS_AXG_SENSE

0_0402_5%
GFX@ PC558 2P: install

2
0_0402_5%

0_0402_5%
3D@ PR602

3D@ PR601

@ PR604
1000P_0402_50V7K
CSREFA <47>

1
QCG@PC559
QCG@ PC559 1P: @
Disable: 0 Ohm 0.047U_0402_16V7K

1
CSP2A
CSP1A
CSP2A

CSCOMPA
1 2 1 2 SWN2A <47>

1
TRBSTA#

DROOPA

CSSUMA
QCG@PR562
QCG@ PR562

TSENSEA
COMPA
2

IMONA
FBA
GFX@ PC560 6.98K_0402_1%

DIFFA

ILIMA
.1U_0402_16V7K
DCG@ PR564
PR563 Disable: 0 Ohm 26.1K_0402_1% 2P: 36K
2_0603_5% 1 2
+1.05VS_VCCPP +5VS 1P: 26.1K

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
1 2
PU500 +5VS
C C
PC561

VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
6132_PWMA <47>
2.2U_0603_10V7K Disable: 0 Ohm
54.9_0402_1%

1 2 6132_VCC Option for

1

1
130_0402_1%

3D@ PR600

DC@ PR577
1 VCC PWMA 45 Option for 2 phase CPU

0_0402_5%

0_0402_5%

0_0402_5%
PR565

PR566

DCG@ PR571
PC562 PC563 PR567 2 44 BST3 1 2 BST3_1 1 2 1 phase GFX
VDDBP BSTA

1
.1U_0402_16V7K .1U_0402_16V7K 0_0402_5% 3 43 GFX@ PR525 GFX@ PC525
HG1A <47>
2

VR_ON_CPU VRDYA HGA 2.2_0603_5% 0.22U_0402_10V6K

<35> VR_ON 1 2 4 EN SWA 42 SW1A <47>
VR_SVID_DAT1 5 41 LG1A <47>
1

SDIO LGA
<8> VR_SVID_DAT 1 2VR_SVID_DAT1 VR_SVID_ALRT# 6
ALERT# BST2 40 BST2 1 2 BST2_1 1 2
PR568 0_0402_5% PR570 PR569 VR_SVID_CLK 7 39 PR515 PC515
<8> VR_SVID_ALRT# HG2 <47>

2
95.3K_0402_1% VBOOT SCLK HG2 2.2_0603_5% 0.22U_0402_10V6K CSP2A
<8> VR_SVID_CLK 1 2 8 VBOOT SW2 38 SW2 <47>
1 2 10K_0402_1% ROSC_CPU 9 NCP6132AMNR2G QFN 60P 37 PC564
ROSC LG2 LG2 <47>
VRMP 10 36 6132P_VCCP 1 2 1 2 CSP1A
VR_HOT# VRMP PVCC PR574 2.2U_0603_10V7K
0.01U_0402_25V7K

11 VRHOT# PGND 35
CPU_B+ 1 2 VGATE 12 34 0_0402_5% 1 PR5732 CSP3
VRDY LG1 LG1 <47>
0_0402_5% +5VS
13 VSN SW1 33 SW1 <47>
1

PR572 1K_0402_1% 14 32
+3VS VSP HG1 HG1 <47>
PC565

DIFF_CPU 15 31 BST1 1 2 BST1_1 1 2

CSCOMP
DIFF BST1

TRBST#
PR505 PC505

DROOP

CSSUM

DRVEN
CSREF
2

COMP

TSNS
CSP3
CSP2
CSP1
2.2_0603_5% 0.22U_0402_10V6K

PWM
IOUT
ILIM
2

PC566

FB
47P_0402_50V8J PR575
10K_0402_5% DC@ PR576
1

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
41.2K_0402_1% 3P: 73.2K
<35> VR_HOT# 1 2
2

COMP_CPU
FB_CPU 2P: 41.2K
TRBST#
<18,35> VGATE
PR578

DC@ PR581 12.4K_0402_1% DROOP

TSENSE
ILIM_CPU
1 2 VSN
6132_PWM <47>
0_0402_5% QC@ PR579
IMON
<8> VSSSENSE
1

PC567 6.98K_0402_1%
DRVEN <47>
PR580 1000P_0402_50V7K CSP3 1 2 SWN3 <47>

1
0_0402_5%
1 2 VSP PC568
<8> VCCSENSE
2

@ PR605
0_0402_5% 1 2 QC@ PC569 3P: install
3P: 22p 0.047U_0402_16V7K

2
B PR582 DC@ PC570 .1U_0402_16V7K 2P: @ B
1K_0402_1% 2P: 10p 10P_0402_50V8J CSP1 CSREF

1
1 2 2 1 CSP2
1

CSP3 CSP2 1 PR5832

SWN2 <47>

1
0_0402_5%
6.98K_0402_1%

@ PR606
PR584 DC@ PC572 DC@ PR585 PC571
49.9_0402_1% 1000P_0402_50V7K 4.32K_0402_1% 3P: 21K 0.047U_0402_16V7K

2
PR586 PC574 1 2FB_CPU1 1 2 2 1COMP_CPU12 1
10_0402_1% 0.033U_0402_16V7K 2P: 12.4K CSREF

1
1 2FB_CPU3 1 2 3P: 330p 3P: 6.04K DC@ PC573
3300P_0402_50V7K CSP1 1 PR5872
CSREF <47> SWN1 <47>
CSCOMP

2P: 1000p 2P: 4.32K

2

1
0_0402_5%
3P: 2200p 6.98K_0402_1%

@ PR607
PC575 PC576
TRBST# 1 2 FB_CPU2 1 2 2P: 3300p 1000P_0402_50V7K 0.047U_0402_16V7K
1

2
DC@ PR589 DC@ PR590 CSREF

1
8.06K_0402_1% 806_0402_1%
0.033U_0402_16V7K

CSSUM
PC577

3P: 348 3P: 3.65K

1 2
2

2P: 1.21K 2P: 9.53K 3P: 1500p 1 PR5912 SWN1

24.9K_0402_1%

DC@ PC578 130K_0603_1%

1200P_0402_50V7K 2P: 1200p
2

.1U_0402_16V7K
DC@ PR592

PC579

1 2 1 PR5932 SWN2
PC580 130K_0603_1%
1

470P_0402_50V7K
1 2 1 2 1 2 SWN3
1

DC@ PR597 PC581 PR594 PR595

1K_0402_1% 1000P_0402_50V7K 75K_0402_1% 165K_0402_1% QC@ PR596 3P: install
CSCOMP 1 2 DROOP 1 2 CSREF 3P: 23.7K 130K_0603_1%
2P: @
2P: 24.9K 2 1
3P: 806
PH504 220K_0402_5%_ERTJ0EV224J
2P: 1K
A A

DC/QC CPU SWITCH QC@ PR576 QC@ PR581 QC@ PC578 QC@ PR592 QC@ PC573
73.2K_0402_1% 21K_0402_1% 1500P_0402_50V7K 23.7K_0402_1% 2200P_0402_50V7K

QC@ PR585
6.04K_0402_1%
QC@ PC570
22P_0402_50V8J
QC@ PR590
806_0402_1%
QC@ PC572
330P_0402_50V7K
QC@ PR597
806_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
QC@ PR589 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
8.06K_0402_1% Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 46 of 51
5 4 3 2 1
 5 4 3 2 1

CPU_B+ PL501 CPU_B+

HCB4532KF-800T90_1812 B+
2 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5

5
68U_25V_M
100U_25V_M

100U_25V_M

0.1U_0402_25V4K

0.1U_0402_25V4K
1 1 1

PC268

PC270
100P_0402_25V8K

220P_0402_25V8K
68P_0402_50V8J
MDV1525URH

MDV1525URH

MDV1525URH

MDV1525URH
1

1
+ + +

@ PQ501

@ PQ505
PC501

PC502

@ PC252

@ PC253

@ PC251

PC513

PC517

PC520

PC507

PC508
1

1
PR504 PR514

PQ503

PQ507
2.2_0603_1% 2.2_0603_1%

2
2 2 2
<46> HG1 2 1 4 4 <46> HG2 2 1 4 4

2
+CPU_CORE
PL502
+CPU_CORE

3
2
1

3
2
1

3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL503
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<46> SW1 1 4 <46> SW2 1 4

1
220P_0402_25V8K
4.7_1206_5%

4.7_1206_5%
68P_0402_50V8J
2 3 2 3

5
@ PC254

@ PC255

PR516
<46> LG1 <46> LG2

1
PR506
TPCA8059-H_PPAK56-8-5

TPCA8059-H_PPAK56-8-5
SH00000HD00 V1N_CPU SH00000HD00

2
PR598 PR599

PQ502

PQ504
4 2 1 4 V2N_CPU 2 1 CSREF

1SNUB_CPU1

SNUB_CPU2
CSREF <46>
10_0402_1% 10_0402_1%

680P_0402_50V7K
SWN1 <46> SWN2 <46>

3
2
1

3
2
1

680P_0402_50V7K
PC506

PC516
2

2
CPU_B+

10U_0805_25V6K

10U_0805_25V6K
QC@ PC510

QC@ PC511
QC@ PR535

1
2.2_0603_5%
BSTA1 1 2 BSTA1_1
0.22U_0402_10V6K

2
5

5
QC@ PC535

MDV1525URH

MDV1525URH
1

QC@ PQ509

@ PQ511
2

4 4

C QC@ PU501 C
1 BST FLAG 9 QC@ PR534 +CPU_CORE
2.2_0603_1% QC@ PL504 QC 45W CPU DC 35W CPU

3
2
1

3
2
1
2 8 HG3 2 1 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<46> 6132_PWM PWM DRVH VID1=0.9V VID1=1.05V
QC@ PR517
<46> DRVEN 2 1EN_VCORE3 3 EN SW 7 SW3 1 4 IccMax=94A IccMax=53A
2K_0402_1%

1
Icc_Dyn=66A Icc_Dyn=43A

4.7_1206_5%
+5VS 2 1 2 1 VCC_VCORE3 4 VCC GND 6 2 3
5

PR536
QC@ PR518 QC@ PR527
0_0402_5% 0_0402_5% LG3 Icc_TDC=56A Icc_TDC=33A
2.2U_0603_10V7K

TPCA8059-H_PPAK56-8-5
DRVL 5
SH00000HD00 R_LL=1.9m ohm R_LL=1.9m ohm
1

QC@ PQ506
QC@ PC582

NCP5911MNTBG_DFN8_2X2
OCP~110A OCP~65A

2
4
2

SNUB_CPU3
V3N_CPU 2 1 CSREF
3
2
1

QC@ PR519

680P_0402_50V7K
10_0402_1%

PC536
1
2 SWN3 <46>

CPU_B+
CPU_B+
2Phase: install

10U_0805_25V6K

10U_0805_25V6K
B 1Phase:: @ B

QCG@ PC521

QCG@ PC522
1

1
10U_0805_25V6K

10U_0805_25V6K
5

100P_0402_25V8K

220P_0402_25V8K
68P_0402_50V8J

QCG@ PR545
@ PC256

@ PC258

@ PC257

2.2_0603_5%

0.22U_0402_10V6K
MDV1525URH

MDV1525URH

2
1

5
@ PQ515

PC518

PC519

BSTA2 1 2 BSTA2_1

QCG@ PC545
PR524

MDV1525URH

MDV1525URH
PQ513

@ PQ517

QCG@ PQ519
2.2_0603_1%
2

1
<46> HG1A 2 1 4 4

4 4
+GFX_CORE

2
QCG@ PU502
+GFX_CORE
3
2
1

3
2
1

PL505 1 9 QCG@ PR544

0.36UH_VMPI1004AR-R36M-Z03_30A_20% BST FLAG 2.2_0603_1%

3
2
1

3
2
1
1 4 2 8 HG2A 2 1 QCG@ PL506
<46> SW1A <46> 6132_PWMA PWM DRVH
4.7_1206_5%

QCG@ PR520 0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

220P_0402_25V8K
68P_0402_50V8J

2 3 DRVEN 2 1 EN_GFX2 3 7 SW2A 1 4

EN SW
5

PR526

@ PC259

@ PC260

2K_0402_1%
<46> LG1A
1

+5VS 2 VCC_GFX2
TPCA8059-H_PPAK56-8-5

1 2 1 4 VCC GND 6 2 3
V1N_GFX

5
SH00000HD00

V2N_GFX
1

4.7_1206_5%
QCG@ PR521 QCG@ PR528
2.2U_0603_10V7K

TPCA8059-H_PPAK56-8-5
5
2

DRVL

QCG@ PQ510
QCG@ PC583

PR546
0_0402_5% 0_0402_5% SH00000HD00
1
PQ508

4 2 PR522 1CSREFA NCP5911MNTBG_DFN8_2X2 QCG@ PR523

<46> CSREFA
10_0402_1%
SNUB_GFX1

10_0402_1% LG2A 4 2 1
2

SNUB_GFX2 2
SWN1A <46>
3
2
1

680P_0402_50V7K

3
2
1

680P_0402_50V7K
SWN2A <46>
1

PC526

PC546
2

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 47 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

5 x 22 µF (0805)
1

1
PC906 PC907 PC908 PC909 PC910
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M sites
2

2
D +GFX_CORE D

7 x 22 µF (0805)
Socket Top 2 x (0805) no-stuff
sites
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1

PC940

PC941

PC942

PC943

PC944

PC945

PC946

PC947
PC911 PC912 PC913 PC914 PC915
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2

2
2 2 2 2 2 2 2 2 +1.05VS_VCCP
+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1

PC952

PC953

PC954

PC955

PC956

PC957

PC958

PC959

PC960

PC961

PC962
PC916 PC917 PC918 PC919 PC920
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1

PC936

PC937

PC938

PC939
2 2 2 2

22U_0805_6.3V6M
1 1 1

330U_D2_2V_Y

@ PC948

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1 1 1

PC951

PC949

PC950
+ + +
PC921 PC922 PC923 PC924 PC925
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
C 2 2 2 2 2 2 2 2 2 C

QCG@ PC933
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
@ PC935
PC932

PC934
+ + + +

2 2 2 2
1 1 1 1 1 1
PC926 PC927 PC928 PC929 PC930 PC931
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2

+CPU_CORE
Chief River 330uF*9m 470uF*4.5m 22uF 10uF
1 1 1 1 1
+ PC901 + PC902 + PC903 + PC904 + PC905
330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y

2 2 2 2 2 8layer for DC CPU 16 10

4
B B

8layer for QC CPU 5 16 10

6layer for DC CPU 5 16 10

6layer for QC CPU 4 1 16 10

GFX_CORE DC 2 12

GFX_CORE QC 3 12

1.05V_VCCP 2 12
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019HF B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 16, 2012 Sheet 48 of 51
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
1. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Change PU330 to RT8205L Change source
2. 2011/09/29 P53-PWR_ +1.05VS_VCCP/+16VSP Change PU400 to RT8237C Change source
3. 2011/09/29 P54-PWR_+VCCSAP/1.8VSP Change PU450 to SY8037B Change source
4. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change HMOS to MDV1525 Change source
5. 2011/09/29 P53-PWR_ +1.05VS_VCCP/+16VSP Change HMOS to MDV1525 Change source
6. 2011/09/29 P49-PWR_BATTERY CONN / OTP Change PD5,PD6 to SCA00001G00 ESD team request
7. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR589 from 348 to 8.06k FAE suggestion
8. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR590 from 3.65k to 806 FAE suggestion
10. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PC574 from 680P to 0.033u FAE suggestion
11. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PC577 from 4700P to 0.033u FAE suggestion
12. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR548 from 1.21k to 8.06k FAE suggestion
13. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PR550 from 10.7k to 806 FAE suggestion
14. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PC547 from 680P to 0.033u FAE suggestion
15. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Change PC551 from 4700P to 0.033u FAE suggestion
16. 2011/09/29 P57-PWR +CPU_CORE DECOUPLING Add snubber and boost resistor For 3x3 H-MOS solution
17. 2011/09/29 P49-PWR_BATTERY CONN / OTP Add PR22 30k,PR27 100k, PR32 0 Ohm For 120W adapter protect(9012)
18. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Change PC360 to SE000006R80 Change source
19. 2011/09/29 P49-PWR_BATTERY CONN / OTP Add PR17 14k, PR33 0 Ohm For CPU temperature protect(9012)
20. 2011/09/29 P51-PWR_+3VALWP/+5VALWP Add PR373 0 Ohm For 3/5V always power on(9012)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 49 of 51
 5 4 3 2 1

HW PIR (Product Improve Record)

QFKAA LA-8392P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2011/11/11
-----------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-----------------------------------------------------------------------------------------------------------------------------------
1) 13 2011/9/29a by ESD demand change D84 to SCA00001L00
2) 26 2011/9/29a by ESD demand change D82 to SCA00001L00
3) 28 2011/9/29a by ESD demand change D92 to SCA00001L00
4) 05 2011/10/05a follow HW4 check list reserve decoupling cap CC66, CC71, CC70 for H_PM_SYNC & H_PECI, BUF_CPU_RST#
5) 19 2011/10/05a by Customer demand add LVDS dual channel signal
6) 13 2011/10/05a by Customer demand add LVDS dual channel signal and 0ohm: R267 R268 R269 R270 R283 R329 R333 R337 (OPTFHD@)
D D
and R500 R501 R502 R503 R504 R505 R507 R508 (3D@)
7) 17 2011/10/05a by Customer demand change RH116 to HD@
add RH282 FHD@
8) 35 2011/10/18a discuss with EC change Function_LED from EC_GPIO4D, PIN86 to EC_GPIO11, PIN25
change HDPLOCK from EC_GPIO11, PIN25 to EC_GPIO4D, PIN86
add GPUPWR_SKIN# on EC_GPIO13, pin27.
add RB28 for GPUPWR_SKIN#
change HDPACT from EC_GPIO43, PIN76 to EC_GPIO50, PIN89
reserve SUSACK# and PCH_SUSPWRDN# by SW demand
9) 18 2011/10/18a by SW ME demand. change PCH_SUSPWRDN_R to PCH_SUSPWRDN#_R
add PCH_SUSPWRDN# to EC and RH132
remove T75
change SUSACK# to SUSACK#_R
add RH133 and SUSACK# to EC
10) 30 2011/10/31a by Layout demand swap LR2, LR1, DR7
11) 32 2011/10/31a by Layout demand swap LT3, LT2
12) 20 2011/10/31a by PWR 16V OC control demand remove RH1, RH174, and change net-name from LNBPWR_MONITOR to LNB_OC
13) 37 2011/11/1a new touch pad add new function add JTP connector Pin 5 (PM_SMBCLK) , Pin6 (PM_SMBDATA)
14) 27 2011/11/1a TV tuner(BCAS) 16V reserve add RM15 and RM16 reserve for TV tuner (BCAS)
15) 33 2011/11/1a avoid SM_EN floating reserve RA43 for SM_EN 100K pull down reserve
16) 33 2011/11/1a for vendor request exchange location of RA28 and CA42
17) 33 2011/11/1a for vendor request RA26 pin2 change name from OSC_IN to OSC_OUT
18) 33 2011/11/1a for vendor request, S&M HP need shut down delete DA1. add RA19 ,QA5 ,RA42 ,
19) 23 2011/11/1a for lot6 0.5W power consumption delete CH57, PJ3 then add PJ5, QH6 ,CH59 , RH228
20) 38 2011/11/2a for lot6 0.5W power consumption add R5545, Q5527, R5529, R5534
21) 23 2011/11/2a for lot6 0.5W power consumption reserve RH228
22) 37 2011/11/2a for lot6 0.5W power consumption change D21 power from +5VL to +5VALW
23) 27 2011/11/6a by EMI demand add CCL10
24) 28 2011/11/6a by EMI demand add CL43, RL29
25) 29 2011/11/6a by EMI demand change RW4 from 0ohm to 33ohm, CW10 from 5pF to 6.8pF
26) 25 2011/11/7a common with ME define location change JUSB3RR to JUSBRR, JUSB3RF to JUSBRF
27) 30 2011/11/7a common with ME define location change JUSB3LR to JUSBLR, JUSB3LF to JUSBLF
28) 27 2011/11/7a common with ME define location change J3GTV to JPCIF
29) 37 2011/11/7a common with ME define location change JFUNCTION to JFUN
C
30) 22 2011/11/7a for lot6 0.5W power consumption delete CH105, CH106; add QH2, CH97, CH98, RH1, RH3 C
31) 35 2011/11/7a for lot6 0.5W power consumption add EC pin 70 for PCH_PWR_EN
32) 37 2011/11/7b by proto plan demand change PCH version to SA00004NQ90(B0) and BOM option to SA00005AG10(C0)
33) 20 2011/11/7b by PWR 16V OC control demand change net name from LNB_OC to LNB_OC#; add RH290 to pull high LNB_OC#
34) 37 2011/11/7b by Layout team demand delete H4, H8; modify H7, H22, H30 to NPTH
35) 20 2011/11/9a EC common core for WL_OFF# UH1.F46 and RH326 chagne net name from WL_OFF# to PCH_GPIO55
36) 35 2011/11/9a EC common core for WL_OFF# change UB1.29 net name from CPSETIN to WL_OFF#
37) 27 2011/11/9a EC common core for WL_OFF# add RM17 for WL_OFF# pull high to +3V_WLAN
38) 35 2011/11/9a EC common core for WL_OFF# CPSETIN signal change from UB1.29 to UB1.74
39) 35 2011/11/9a by PWR 16V OC control demand add RB37 10kohm pull high to +3VS for LNB_OC#
40) 13 2011/11/9d for dual-channel power support remove BOM selection IEDP@ for R109, R110, C230, C233, Q1
41) 13 2011/11/9d for dual-channel power support change R108, C228, Q17 to LVDS@; change Q1, C230, C233, R109, R110 to always mount
42) 13 2011/11/9d for dual-channel power support add R390, R1442, R1441, R106
43) 13 2011/11/9d for dual-channel power support change R106 to LVDS@, R1441 to @, R361 to @, R1442 to 3D@, R390 to @
44) 13 2011/11/9d for 3D panel camera add R79, R97, L60
45) 13 2011/11/9d for dual-channel power support add R361; change R62 from 100 to 0
46) 21 2011/11/9d for dual-channel power support add RH304
47) 27 2011/11/14a for vendor recommand change YCL1 from SJ10000CU00 to SJ10000EF00, CCL4 and CCL5 from 30pF to 15pF
48) 29 2011/11/15a by EMI demand change CW10 from 6.8pF to 5pF
49) 27 2011/11/15d by EMI demand change BOM structure of CCL10 from @ to GCLK@
50) 28 2011/11/15d by EMI demand change BOM structure of RL29, CL43 from @ to GCLK@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 50 of 51
5 4 3 2 1
 5 4 3 2 1

HW PIR (Product Improve Record)

QFKAA LA-8392P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3
GERBER-OUT DATE: 2011/12/22
-----------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-----------------------------------------------------------------------------------------------------------------------------------
1) 18 2011/11/29a For DVT hang Add CH23 CH24 CH25 for SW-node noise.
2) 13 2011/11/29a For ME request Change location from JLVDS to JLVDS4
3) 38 2011/11/29a For noise issue Add C366, C470 at +5VALW power rail; add C381 at +1.8VS power rail
4) 05 2011/12/07a For leakage Change from +3VALW to +3VALW_PCH of UC1
5) 38 2011/12/07a For design change Add C382 for +1.8VS
6) 33 2011/12/13a For Codec leakage Add RA29 for leakage
D D
7) 18 2011/12/13a For noise issue Mount CH23,CH24,CH25.
8) 05 2011/12/13a For leakage Change pin5 of UC1 from +3VALW to +3VALW_PCH
9) 15 2011/12/13a For leakage issue Change pin5 of U9 from +5VL to +HDMI_5V_OUT
10) 38 2011/12/13a For noise issue Add C372,C373,C374,C383,C384,C385,C386,C387,C388,C389,C390,C391,C392
11) 35 2011/12/13a For design change LNB_EN Change LNB_EN from PCH to EC
12) 35 2011/12/13a For design change RF LED Change RF LED control pin from PCH to EC
13) 38 2011/12/13a For S3 resume sequence Add Q41 for S3 sequence
14) 26 2011/12/15a For ME request Change JFP/JPOWER/JFUN from zif to non-zif
15) 31 2011/12/15a For adjust EXT 3.0 sequence Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
16) 32 2011/12/15a For adjust EXT 3.0 sequence Change +3V to +3V_USB control pin from syson to PM_SLP_S4#
17) 13 2011/12/17a For Prevent LVDS burn issue Add F3 (Poly fuse to prevent burn issue)
18) 37 2011/12/19a For ME delete stand-off Delete H25,H26,H27
19) 37 2011/12/19a For Wimax flash issue Change +5VS to +3VS of Wimax LED
20) 37 2011/12/19a For layout request Add net name +5VS_FUNC with Function conn power pin
21) 21 2011/12/22a For ESD request Reserve CH30(1000P) for PCH_THRMTRIP#
22) 13 2011/12/22a For ME request change C381, C382, C470, C366 from 0805 to 0603 size

QFKAA LA-8392P SCHEMATIC CHANGE LIST

REVISION CHANGE: 1.0
GERBER-OUT DATE: 2012/02/02
-----------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-----------------------------------------------------------------------------------------------------------------------------------
1) 27 2012/01/12a For GCLK Add CCL13(0.1u) for +3VALW
2) 27 2012/01/12a For MSATA pin define. Add RM30 (MSATA define that Pin22 is reserve, so other function need to add PLT_RST#).
3) 27 2012/01/18a For GLCK Change CCL13 from +3VLAW to +3VALW_GCLK
C 4) 27 2012/01/30a For TV tuner use PCIE interface Add RM31~RM35 and QM2 C

5) 17 2012/01/30a For TV tuner use PCIE interface Change PCIE 6 from USB to TV tuner
6) 17 2012/01/30a For TV tuner use PCIE interface Change CLK_USB30 to CLK_TV and CLKREQ_USB30# to CLKREQ_TV#
7) 37 2012/01/30a For MP Unmount SW3
8) 11 2012/01/30a For M1 only Unmount RC117/RC118/QC7/QC8
9) 32 2012/01/30a For Internal USB30 only Delete Page 32
10) 37 2012/02/01a For ESD request Add C469, C472~C479, C481~C488, C491

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/14 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8392
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019HF
Date: Thursday, February 16, 2012 Sheet 51 of 51
5 4 3 2 1