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T h i s M o n t h ’ s F e at u r e a r t i c l e s
28 IPC Designers
Council
Viewpoint:
Rick Hartley
Interview
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DECember 2015 The optimum
28 TM
volume 4 magazine
number 12 dedicated to
table of Contents
Articles shorts
62 Electrical Design Challenges for 9 Quantum Physics
Automotive PCBs Problem Proved
by Brad Brim Unsolvable
Columns
8 The Designers
Council: Elevating
PCB Design, and 58 New Nanomanufacturing
Designers Technique Advances Imaging,
by Andy Shaughnessy Biosensing Technology
44 Systematic Estimation of
Worst-Case PDN Noise: Target Highlights
Impedance and Rogue Waves 36 2015’s Most-Read Design News
by Istvan Novak
60 2015’s Most-Read Articles
56 Why Do Different Test Methods
Yield Different Electrical Values? 76 PCBDesign007 News
by John Coonrod
departments
78 Events Calendar
It was a different time. Internet as we know it was still a few years away.
PCB West had just launched; it was the only or-
When the seeds of the Designers Council ganized PCB design event, and the only chance
were first sown in 1991, PCB designers were for designers to do any networking. What was a
still considered red-headed stepchildren, earn- designer to do?
ing less respect than Rodney Dangerfield. The Then, as the “Founder of the Designers Coun-
PCB was seen as just an interconnect platform, cil” Gary Ferrari recounts in this month’s issue,
soulless and boring. And PCB designers were di- Dieter Bergman asked him what IPC could do
nosaurs toiling away on a “mature” technology for PCB design. They traveled around the United
that would soon be replaced by multichip mod- States, talking to designers and getting a feel for
ules, or some other cool technology. their interest in forming a design organization.
Back then, the integrated circuit was king; IC Yes, there was plenty of interest. And by 1992,
design was considered “sexy” and IC designers the first DC chapter had formed in Atlanta, fol-
were the rock stars of electronics design. (Years lowed by dozens more in rapid succession.
ago, I told that story to a newly hired assis- Now there are DC chapters around the
tant editor, a cute 22-year-old girl right U.S. and Canada, as well as Australasian
out of college. She said, “I have bad and Southeast Asian chapters. There
news for you: Nothing about is no longer any fee to join the
this industry is ‘sexy.’”) council, and the DC counts
But the lowly PCB de- thousands of members.
signer was looked The local chapters are
down upon by ev- completely autono-
eryone. mous; some chap-
It didn’t help ter meetings draw
that PCB design- huge crowds,
ers were spread and a few chap-
out across so many ters are nearly
various segments dormant.
of the electronics As the De-
industry. It’s a signers Council
vertical occupa- enters its 25th
tion in a hori- year, we decided
zontal industry. to talk to some
Designers often of the people
felt like outsiders in who helped make
their own companies; it all happen. In this
none of their co-workers issue, we have an inter-
really understood what the view with IPC’s tireless Anne
designers did all day. Marie Mulvihill, who gives us a run-
Worst of all, there was no unity, down on the DC of today. We also have
no real community of designers. The a discussion with Gary, who takes us all
the way back to the beginning and shares a next DC chapter meeting, but the results speak
little “inside baseball” on the forming of the for themselves.
council. It’s been quite a year. In 2015, we covered a
Design instructor Rick Hartley discusses lot of big news. We also said goodbye to some
how he helped start a DC chapter in Ohio, good people, like Gary Smith and Steve Weir.
and he lays out the many educational and net- In this issue, don’t forget to check out the
working benefits of being involved with your most popular PCB design articles and news items
local chapter. San Diego PCB’s Mike Creeden of 2015.
talks about his work with the DC, and he ex- I hope you have a great holiday. I’ll see you
plains how the executive board functions as in 2016! PCBDESIGN
well.
And Zentech’s Judy Warner interviewed
Freedom CAD’s Scott McCurdy, president of Andy Shaughnessy is
the Orange County Designers Council Chap- managing editor of The
ter. The Orange County chapter meetings rou- PCB Design Magazine. He
tinely draw nearly 100 attendees, and Scott has been covering PCB
was happy to share his “playbook” for starting design for 16 years. He can
and sustaining an active DC chapter. I think be reached by clicking here.
Scott spends part of each week planning the
Mulvihill: Absolutely. Shaughnessy: Tell us about the CID and CID+ cer-
a. IPC presents the Design Forum every year, tifications. I understand the curriculum has been
within the premier industry event IPC APEX “updated,” if that’s the right word.
EXPO. This activity features technical presenta-
tions from industry thought leaders, in a full- Mulvihill: That is the right word! Course content
day conference format that allows for both edu- for both the CID module and the CID+ module
cation and networking. The Design Forum 2016 have been updated, to help meet design chal-
runs on Monday, March 14, 7:30 a.m. – 1:30 lenges of today’s environment. The 2016 edi-
p.m. in Las Vegas, at the Convention Center tions of CID and CID+ modules are available.
with IPC APEX EXPO.
b. Half-day and full-day technical courses • New content has been added to the
with an emphasis on design are also on the Pro- course textbook (the Study Guide), slides
fessional Development slate at IPC APEX EXPO. used for classroom presentation, and the
Courses of particular interest to designers run exam. For example: the latest lead-free
on March 13–14, Sunday and Monday after- and other environmental regulatory
noon. More information about Professional De- issues associated with materials.
velopment courses and the Design Forum can • Information has been re-organized, for
be found at www.ipcapexexpo.org. improved flow.
c. Designer Certification sessions consist of • Exam format has been aligned with today’s
two days of instruction, plus one day of review best practices in testing.
with an exam. These sessions are delivered by
IPC-licensed training centers, in classrooms all Shaughnessy: Is there still a plan to add HDI CID
over the world. Successful completion of the certification?
Mulvihill: Not at this time. When the program able that this question might be raised, as the
was first developed 20+ years ago, the original incredible amount of time and effort that goes
plan was to expand the offering to a course into association “products” like standards and
module on HDI, and one on high-speed design. certifications is not always apparent at first
These topics are introduced in the 2016 edition glance.
of CID, and covered in more depth within the
2016 edition of CID+. Publication of a formal Shaughnessy: What resources (book stores, etc.)
certification module takes a long time, due to are most important to your members?
requirements for multiple reviews. Develop-
ments in HDI and high-speed design happen Mulvihill: IPC industry standards are our core
so fast that formal certification module content offering. We are the only association in this
could be outdated as soon as it is published. electronics manufacturing industry to provide
For the most up-to-date information on HDI a platform for development and application of
and other technologies that require advanced- standards for all phases of product realization:
level design, individuals concerned with de- design, manufacturing, inspection and test. IPC
sign are encouraged to participate in tutorials, standards focus on manufacturability and reli-
courses, and technical conferences. Examples ability of the finished product, notably the high
include the professional development courses reliability required of products for the automo-
at IPC APEX EXPO, and the recent IPC Flexible tive, medical, military and aerospace sectors, as
Circuits-HDI Forum. well as products like satellites and servers.
Shaughnessy: Many of our readers feel standards Shaughnessy: How do you satisfy members’ need
and certifications should be free to members. How for technical information?
do you address the “free” contingent?
Mulvihill: Our mission is to provide industry
Mulvihill: While it would be possible to con- standards and technical education, including
struct a membership fee that would include all training and certification, education with a de-
standards and certifications, the fee would be sign focus.
too high because not every employee of every
member company would utilize all IPC prod- Shaughnessy: Highlight some of the Designers
ucts and services constantly. It is understand- Council’s success stories.
Intercept’s complete design flow gives you the power to keep moving, full speed ahead.
Use M ozaix for flexible schematic capture and Pantheon f or a dvanced, i ntuitive PCB/Hybrid/RF design
to move quickly and seamlessly from concept to manufacturing. Our 30+ import transla tors make
it easier tha n ever to switch tools. Let Pantheon and Moz ai x drive your next innovation.
Mulvihill: Veteran designers tell us that IPC De- Mulvihill: No. The IPC Government Relations
signer Certification is the best educational pro- team handles issues associated with environ-
gram for design practices in the industry. The mental and governmental regulations that af-
CID and CID+ are professional designations re- fect the electronics industries.
spected throughout the industry, specified for
major projects and utilized by major corpora- Shaughnessy: What are your most successful pro-
tions for selection and promotion. grams and why?
Shaughnessy: Do you have partnerships with oth- Mulvihill: The IPC 2581-Consortium was formed
er industry organizations? nearly 10 years ago. Persuading all of the major
CAD software vendors to put aside their differ-
Mulvihill: IPC works on projects in partnership ences and bringing them to the table for good
with other industry organizations, notably: of the industry was a major effort. Drawing in
OEM users to provide input and consent to uti-
• CALCE (Center for Advanced Lifecycle lize the standard for beta-testing was the next
Engineering—University of Maryland) step. The next phase will be to apply the IPC-
• SMTA (Surface Mount Technology 2581 to a larger number of facilities, using a
Association) variety of CAD software design and assembly
• EIPC (European Institute of Printed tools.
This industry standard consists of generic
Circuits)
protocols for consistent capturing and trans-
• FED (Fachverband für Design,
mission of design data through all phases of
Leiterplatten- und Elektronikfertigung— product manufacture—the Holy Grail. This is a
association for PCB design and great achievement, culminating in a quiet revo-
manufacturing) lution that could result in quality and efficiency
• AIA (Aerospace Industries Association) improvements throughout the entire electron-
• NAM (National Association of ics industry.
Manufacturers)
• WECC Shaughnessy: Why should someone join the DC? It
• SEMI sounds like there are no risks, only rewards.
• DDMII
Mulvihill: Individuals in the electronics indus-
Shaughnessy: Does the DC help members deal try should have an awareness of the importance
with government agencies? of design. Up to 75% of a product’s cost and
performance can be attributed to design.
McCurdy:
How to Build
a Successful
IPC Designers
Council Chapter
IPC by clicking here. Kris Roberson is the point • If you can, get a member company to
of contact for Designers Council chapters at IPC. open up a meeting space at no charge to
The essentials of running a good meeting help keep costs to a minimum.
consist of the following: • Include opening slides that include:
– A greeting and welcome
• Although some chapters hold evening – IPC information and website link
meetings, Scott has found that holding – Information and links for industry
the “Lunch and Learn” events from11:30 magazines/news sources
a.m. – 1:30 p.m. works well. This makes – Share information regarding upcoming
little impact on a busy professional’s local events, such as tradeshows
working hours, and does not infringe on – Open the floor to ask if anyone is
personal or family time in the evenings. hiring or looking for a design job in
Traffic patterns in busy cities are also order to make potential matches
lighter in that time slot. Most companies • Encourage feedback and ask attendees
will support time away from the office about topics and speakers they would like
when it is the equivalent to a long lunch to hear from.
to serve continuing education. • Give handouts to gather contact informa-
• Find relevant speakers who are valuable tion about the attendees, and add new
to the PCB design community. Choose info to the database.
one speaker to talk for 80 minutes, or two • Provide the website links mentioned in
speakers to talk for 40 minutes each. the opening slides in written form.
• Meeting times run two hours; 80 minutes • Ask the speakers to provide the slides from
are reserved for speakers. Lunch and an- their talk, removing any proprietary infor-
nouncements account for another 30 mation, and forward to the attendees via
minutes, and the remainder is set aside for email or a customized website.
questions, raffle and closing.
• Always make name tags that are easily Give with Purpose: Educate,
readable and that also include the com- Network, Inspire
pany name for ease of networking. While Scott McCurdy’s “recipe” is a fairly
• Provide box lunches from a local sand- simple one, there is one intangible quality that
wich shop, and charge approximately $10 I observed that appears to have contributed
at the door to help cover costs of facility greatly to his success with the Orange County
and food/drinks.
• Proactively network between and dur-
ing meetings to build rapport and keep a
growing database for the chapter.
• Occasionally take on-site field trips to pro-
vide learning opportunities and to raise
awareness of member companies (i.e.,
PCB fabrication facilities, design bureaus,
OEMs, or contract manufacturers).
• Get member companies to sponsor some
simple prizes to raffle at the end of the
meeting.
• The president should greet members as
they arrive and as they depart, and thank
them for attending.
• Get help from a few volunteers to help
shoulder the work involved. It takes a
team to grow a chapter!
Chapter: He’s a giver. Scott doesn’t give to get your efforts and to grow meeting attendance.
something in return—he gives for the joy of No matter how much we rely on our electron-
contributing to our industry. And he has sur- ic devices to inform and connect us, nothing
rounded himself with like-minded contributors compares to the power and value of meaningful
like Terri Kleekamp, Kathy Palumbo and others. face time. Scott’s playbook, and his support of
He enjoys providing designers with resources local design professionals, are keys to his chap-
that will educate, inspire and allow them to net- ter’s success. PCBDESIGN
work with their peers. Subsequently, designers
become better at what they do, which empow-
ers them to compete well globally. Generosity Judy Warner is director of
and altruism are at the heart of Scott’s and his business development for
team’s success. the Western Region and
If you want to follow in Scott’s shoes and RF/microwave markets for
set up your own Designers Council chapter, be Zentech Manufacturing.
a purposeful giver. Beyond that, carve out some
time to build relationships in order to support
Nanostructured Metal Coatings “It has been long known that structuring
the surface of a material can increase light trans-
Let the Light through for mission,” said study co-author Viktor Podolskiy,
Electronic Devices a professor at the University of Massachusetts
at Lowell. “Among such structures, one of the
more interesting is similar to structures found in
Light and electricity dance a complicated nature, and is referred to as a ‘moth-eye’ pat-
tango in devices like LEDs, solar cells and sen- tern: tiny nanopillars which can ‘beat’ the Fresnel
sors. A new anti-reflection coating developed by equations at certain wavelengths and angles.”
engineers at the University of Illinois at Urbana Although such patterned surfaces aid in light
Champaign, in collaboration with researchers at transmission, they hinder electrical transmission,
the University of Massachusetts at Lowell, lets creating a barrier to the underlying electrical
light through without hampering the flow of material.
electricity, a step that could increase efficiency The researchers demonstrated that their
in such devices. technique, which results in metal covering
The researchers, led by U. of I. electrical and roughly half of the surface, can transmit about
computer engineering professor Daniel Wasser- 90 percent of light to or from the surface.
man, published their findings in the journal Ad-
vanced Materials.
At the interface between two materials, such
as a semiconductor and air, some light is always
reflected, Wasserman said. This limits the effi-
ciency of optoelectronic devices. If light is emit-
ted in a semiconductor, some fraction of this
light will never escape the semiconductor mate-
rial. Alternatively, for a sensor or solar cell, some
fraction of light will never make it to the detec-
tor to be collected and turned into an electrical
signal. Researchers use a model called Fresnel’s
equations to describe the reflection and trans-
mission at the interface between two materials.
Designers
Council
Viewpoint:
Gary Ferrari
When we started putting together our cov- for board designers,
erage of the Designers Council, we knew we’d and anyone with a
have to get the real scoop from Gary Ferrari. vested interest in
He’s been helping to raise the status of the PCB board design.”
designer for decades. As co-founder and long- In 1991, we hit
time executive director of the Designers Coun- the road and trav-
cil, as well as an IPC Master Instructor, Gary has eled throughout the
dedicated a big part of his career to PCB design. U.S. to introduce
After decades of service, he was inducted into a new design stan-
the IPC Hall of Fame at IPC APEX EXPO this dard. It also gave us
year. an opportunity to
I caught up with Gary and asked him to fill poll the attendees
us in on the creation of the Designers Council, to hear their com- Gary Ferrari
and some of the changes he’s seen in the orga- ments on whether
nization in the last 24 years. an IPC Designers Council was a good idea. We
also asked them what they felt its charter should
Andy Shaughnessy: You’re often referred to as be. The primary feedback was designer educa-
the “Founder of the Designers Council.” How did tion, a forum to discuss common interests, and
you get involved and who else helped get the DC network building. In summary, they liked the
started? idea of a designer society.
However, an issue was IPC’s membership
Gary Ferrari: As you know, Dieter Bergman and structure. Their membership is company-based,
I worked together on many of the standards that whereas a society is generally individual-based,
affect designers. We also did several designer-ori- similar to SMTA. After consulting with IPC’s le-
ented workshops. One day, Dieter asked me what gal counsel, we were able to structure the De-
more IPC could do for the design community. signers Council as a chapter-based entity, thus
My answer was very simple: “Mechanical engi- allowing for individual membership.
neers have the ASME, electrical engineers have
IEEE, and the designers have sore eyes from star- Shaughnessy: Where was the first official DC meet-
ing at their monitors. What we need is a society ing held, and when?
Ferrari: Its official birth was in 1992. Shaughnessy: What do you think are
Dieter and I were making the rounds the biggest benefits that the Design-
doing design-related workshops at ers Council offers designers, and the
that time, and spreading the word. industry?
Chapters started forming at a tre-
mendous rate. We were up to 29 Ferrari: This answer is three-fold.
chapters within several months. The first is exposure to industry
What is interesting to note is standards, which includes many
that a group of Atlanta designers important processes that are af-
had been meeting together for about a year un- fected by design. Let’s face it, with today’s tech-
der the leadership of Fred Pescitelli, at Phoenix nologies, the designer cannot ignore what his
Designs. They met to learn from each other, design may do to the fabrication, assembly and
learn about new technologies, etc. Sounds fa- test segments.
miliar doesn’t it? They listened to what we of- The second is obtaining a professional cre-
fered, voted, and Atlanta became the first offi- dential that has international recognition.
cial chapter of the IPC Designers Council. The third is building a network of experts
No matter where I traveled, the local de- that one may call on when faced with a new or
signers basically said the same things. One that difficult design issue.
comes to mind was in Atlanta. One of the well-
known designers, when asked the how he felt Shaughnessy: What’s exciting about the DC today?
designers were viewed, indicated that the atti-
tude was that designers were “pond scum.” We Ferrari: In the certification program, we see
can certainly laugh at his colorful description, many new design challenges facing the de-
but I received similar answers no matter where signer. These are worldwide challenges that cre-
I traveled. ate new horizons. In other words, I see plenty
of growth for those who are coming into the
Shaughnessy: What are the biggest changes field, as well as those who have been around
you’ve seen at the DC in the past 24 years? for a while. As chairman for several IPC design-
related standards, I look for a path into the
Ferrari: There are fewer registered chapters in standards for these challenges, and ultimately
the U.S., whereas we have seen a much larger into the designer certification courses. For me,
growth internationally. However, we have re- I have to mention all the designers I have met
cently witnessed a few new chapters starting up. and helped in one way or another. To see them
We are also seeing more and more engineers tak- grow and be successful is amazing.
ing the certification courses. I recently taught a
class that consisted of over 90% engineers. In Shaughnessy: Why should someone consider join-
addition, we see a growth of new, younger de- ing the DC?
signers taking the courses.
Two reasons may be attributed to these Ferrari: Technology does not wait for designers
observations. The first is that technology has to catch up. It moves forward and designers need
become more sophisticated, and engineers are a venue that enables them to keep up with these
being asked to move further into the layout technology changes through education and
end of the development cycle. The second networking. Being involved in a local Design-
is that the average age of the designer keeps ers Council chapter may provide the catalyst for
climbing up, resulting in much larger num- their employers to allow them to attend various
bers getting ready for retirement. Companies conferences and help expand their knowledge.
are finally waking up to the fact that they will
be losing a significant part of their product Shaughnessy: Thanks, Gary.
development team, better known as the PCB
designer. Ferrari: Thank you. PCBDESIGN
Designers
Council
Viewpoint:
Rick Hartley
by Andy Shaughnessy Andy Shaughnessy: How and when did you get
involved in the Designers Council?
Rick Hartley has been in involved in PCB
design and design education for decades, so it’s Rick Hartley: I first learned about the Designers
no surprise that he started working with the Council at an IPC conference in the early 1990s.
IPC Designers Council early on. Now retired Shortly afterward, I was contacted by another
from his day job at L-3, Rick still teaches PCB central Ohio designer, Candice Antrett, of Bat-
design and shows no sign of slowing down. I telle Research Institute. Candice was also inter-
asked him to discuss his work with the Design- ested in the DC and suggested we collectively
ers Council, and what the group means to the start a chapter. Pete Waddell had Printed Circuit
design community. Design magazine do a mailing for us to help get
the word out, and we have always been grateful
for that generous act. We held our first meet-
ing at Battelle, and were off and running. Our
membership area was mainly Columbus, Day-
ton and Cincinnati.
Designers
Council
Viewpoint:
Mike Creeden
by Andy Shaughnessy to this day. There was some good food and it
was an event outside of work, so I really started
When covering the IPC Designers Coun- to enjoy the meeting.
cil, one quickly learns that it’s the volunteers What came next was profound. I was exposed
who make the train run on time. San Diego to IPC standards and the value they brought to
PCB CEO Mike Creeden, CID+, is one such my designs, my company and ultimately my ca-
volunteer, and as a member of the Designers reer! I saw that the charter of these meeting was
Council’s Executive Board, he was a must-have to bring this education out to the designer in
for this issue. I tracked him down and asked the workplace as a form of education. So being
him to give us a rundown of his involvement the naïve person I am, I asked, “What are we
with the DC, and to explain why designers doing to get this message out there to those that
might want to get involved with their local don’t know about this Designers Council chap-
DC chapters. ter?” The response was simple. “What do you
think we should do and how would you like to
Andy Shaughnessy: How and when did you get go about it?” I was nominated as the Education
involved in the Designers Council? board member and had the privilege to serve for
several years.
Mike Creeden: Around1993, I was presented
by a fellow designer an invitation to attend a Shaughnessy: What do you think are the most im-
new meeting called the “IPC Designers Coun- portant benefits that the Designers Council offers
cil,” which was being held at Qualcomm. I had designers and the industry?
known of IPC for most of my career of 17 years,
but I did not know anything about a Designers Creeden: The Designers Council is a multifac-
Council. So, being curious by nature, I attended eted organization and as such has been several
this meeting and immediately saw several fel- different things to me over the years. I assume
low designers I was well acquainted with, and this must be true for other people as well. The
then I met several new people whom I still see primary benefit that the DC brings is improve-
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E M B E D D E D C A PA C I TA N C E
cited Need to
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collaboration
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delays due to data
inconsistencies
cited
Better predictability
of design cost
beyond design
A high-speed digital power distribution net- confinement in the frigid computer room. This
work (PDN) must provide a low inductance, low monster machine had card after card with rows
impedance path between all ICs on the PCB of TTL logic chips. Figure 1 illustrates a typical
that need to communicate. In order to reduce Unibus board. It had 8K, 16-bit word core mem-
the inductance, we must also minimize the ory, which I believe could be expanded to 80K
loop area enclosed by the current flow. Obvi- if the need ever arose. The core had a 400ns ac-
ously, the most practical way to achieve this is cess time, which means the system clock would
to use power and ground planes in a multilayer have been a blazing 2.5MHz.
stackup. In this two-part column, I will look at I always used the “divide and conquer” meth-
the alternatives to planes, why planes are used odology. First, eliminate the power supplies then
for high-speed design and the best combination start dividing the system in half, then half again
for your application. until the fault was localized within a small cir-
Back in the mid-eighties, when I worked at cuit. But, as it took about half an hour to reboot,
the University of Western Australia, one of my with a specific sequence of octal latches, it was
duties was to fix the departmental mainframe: a very time consuming process. Plus, there were
the dreaded DEC PDP-11/40. When it broke always numerous engineering students banging
down, it was a two-week sentence to solitary on the window, to the terminal room, enquiring
when the “mother” might be fixed so they could
complete their assignments.
The boards were double-sided and used a
power finger, type A or B layout configuration
on the top side of the board, as shown in Figure
2. The bottom side could then be used entirely
for routing. This provided some mutual induc- as the return current must traverse several ca-
tive coupling between the wide power and pacitors to return to the source. If you are limit-
ground traces and saved on board area. How- ed to a double sided board, then this is the best
ever, it meant that the return current had to approach for providing power to the network of
flow all the way around the board perimeter, chips. But, solid copper planes, in a multilayer
creating a large loop area. Fortunately, the PDP- configuration, are of course a much, much bet-
11/40 was manufactured way before the era of ter solution for high-speed design.
FCC-mandated radiation guidelines. Needless Although it is true that a plane has signifi-
to say, this is not a good supply configuration cantly less inductance than a trace, plane in-
for high-speed design. Don’t try this at home! ductance is not negligible. The mechanism by
The power and ground grid configuration which a plane reduces the inductance is by al-
of Figure 3 also saves on board area, but at the lowing the current to spread out, effectively
expense of increased mutual inductance. In this creating numerous parallel paths. But at high
case, the ground (GND) traces are horizontal speeds, return currents flow the path of least in-
on the bottom of the board, while the power ductance which tends to direct the current di-
(VCC) traces are vertical on the top side. Con- rectly below the signal trace.
necting the two supplies, at every intersection, Also, due to skin effect, high-frequency cur-
with a decoupling capacitor forms a cross-hatch rents cannot penetrate a plane, and therefore, all
pattern. Current returns equally well, to its currents in conductors are surface currents. This
source, along either the ground or power traces. effect will begin to occur at frequencies above 30
The down-side here is that the capacitors used MHz for 1 oz. copper layers in a PCB. Therefore,
should be of particularly good quality (low ESL) at high frequencies, a plane in a PCB is really
two conductors—not one conductor. There will PCBs with at least two plane layers should be
be a current on the top surface of the plane, and seriously considered.
there can be a different current or no current at Multilayer boards reduce radiated emissions
all on the bottom surface of the plane. by more than 10 db compared to a double-sided
Figure 4 illustrates the cross-section on a board—all other factors being equal. Embed-
microstrip (outer layer) trace and its associated ding signals between the planes also reduces
plane return current distribution (red). Where susceptibility to radiation, as well as providing
the electric fields (blue) are more tightly coupled ESD protection. So not only do we prevent noise
to the plane—directly below the trace—the re- from being radiated, but we also reduce the pos-
turn current also exhibits tighter coupling. But sibility of being affected by an external source.
where the field spreads out from the trace, the The planes in a high-speed, digital board
larger loop area, between the signal and the re- perform five crucial functions:
turn current path, increases the inductance. Re-
turn current tends to couple to the signal con- 1. Allow the routing of controlled
ductor and on the same side, of the plane nearest impedance transmission lines in both
the signal, falling off in intensity, with the square microstrip and stripline configurations.
of increased distance. A stripline (inner layer) re- 2. Provide a reference voltage for the
turn current distribution is narrower with the exchange of digital signals.
fields more intense above and below the trace. 3. Distribute stable power to all logic
Any voltage drop across a ground plane will devices.
excite cables terminating on the board, which 4. Control crosstalk between switching
causes them to radiate as dipole or monopole signals.
antennae. The amount of current needed to 5. Provide a shield for electromagnetic
cause the radiation to exceed the FCC Class B radiation on internal layers.
emission requirements, in a one meter long an-
tenna, is extremely small—in the vicinity of just Next month, I will look at why solid power
a few µA. Therefore, even the smallest ground and ground planes encompass a distributed sys-
noise voltage is significant, since it only takes a tem of surprising complexity and how we can
few mV of potential to produce currents of this best use planar capacitance to reduce AC im-
magnitude. Power and ground planes reduce pedance of the PDN.
the loop area and hence the inductance and the
impedance, which in turn reduces the noise. Points to Remember:
Although single-sided and double-sided • Inductance may be reduced by minimiz-
boards have been used successfully in unshield- ing the loop area enclosed by the current
ed enclosures at frequencies of 20–25MHz, these flow.
cases are the exception rather than the rule. A • Double-sided boards, using a power finger
design of this type, also requires a high level layout configuration, should be avoided
of EMC expertise and thus is time consuming as they create a large loop area for the
and risky to produce. Above 10MHz, multilayer return current.
University of Twente Develops ficult and the process of making them involved
Versatile Method for Developing many steps. Researchers from the University of
Twente have now developed a new method that
New Materials makes creating wires of this kind easy. According
to University of Twente Professor Jurriaan Huskens,
Researchers at the University of Twente re- this has provided chemists with a versatile method
search institute MESA+ have devised an elegant for creating new materials.
method for fitting various functional coatings to In their experiments, the University of Twente
silicon microwires. The research has been pub- researchers first made microwires with a PN junc-
lished today in the prestigious scientific journal tion halfway along the wires. In the experiment,
Advanced Materials. the wires were submerged into a solution contain-
Microwires made of the semi-conductor sili- ing platinum in the dark, causing the ‘P side’ of
con are used in numerous fields. It is generally the wire to be covered in platinum. In the next
necessary to ‘functionalize’ them, by adding a lay- stage, silver was added to the other side in the
er of metal or a layer of a cata- light. The result was a mi-
lyst. In most cases, the wires crowire with silver on the top
are given a single layer, but in and platinum on the bottom.
specific instances it is useful The wires can be very valu-
to put a different material on able for the purpose of gen-
the bottom and on the top of erating energy from sunlight
the wires. However, creating or purifying water with the
these wires proved very dif- help of sunlight.
• Board Design
• Product Development
• Embedded Software
• IOT Solutions
• FPGA Design
• Test Engineering
sales@fastinterconnect.com | www.fastinterconnect.com
column
quiet power
Systematic Estimation of
Worst-Case PDN Noise:
Target Impedance and Rogue Waves
by Istvan Novak
Oracle
In the dark ages of power distribution de- case transient noise becomes. This raises the
sign, the typical advice was to use a bulk capac- question how to do a systematic design and also
itor and one 0.1uF bypass capacitor for every gives rise to speculations about rogue waves [2].
power pin on the digital circuit. This was very But there is a systematic, fast and efficient way
unscientific, but served the industry reasonably of calculating the worst-case noise for any arbi-
well in low-density and low-speed circuits. As trary impedance profile.
the designs got more demanding, the target The target impedance concept assumes that
impedance concept was developed [1]. Using a the power distribution network is hit by a se-
target impedance, designers had a metric and a ries of current steps, each current step having a
design goal to guarantee that the voltage tran- magnitude of DI and fastest transition time of
sients stay within specified limits. ttr. If up to the BW bandwidth of the excitation
Strictly speaking, the target-impedance con- the PDN impedance is Ztarget, the resulting volt-
cept is valid only for flat self-impedance pro- age transients are within the DV limits.
files; however, most of our practical designs do
not have that luxury. With non-flat impedance
profiles, the noise is different. Surprisingly and
counterintuitively, keeping the same maximum
impedance, the more we deviate from the flat
impedance by pushing the impedance down in
certain frequency ranges, the higher the worst-
The target-impedance concept and these was published in 2002 [5]. Without the need of
expressions assume a linear and time-invari- an optimization loop it provides a guaranteed
ant (LTI) PDN; moreover, assume that the way to determine the absolute worst-case tran-
PDN impedance is flat, frequency indepen- sient noise and its corresponding excitation
dent, from DC up to the BW bandwidth of pattern, what we still may call rogue wave. To
the excitation. illustrate the power and usefulness of the pro-
Interestingly, if the impedance profile is not cess, we take the rogue-wave example circuit in
flat, but still stays at or below the Ztarget limit, the [2]
and calculate the worst-case noise with the
worst-case transient noise gets bigger. For some reverse pulse technique.
of the typical PDN impedance profiles, this was Figure 1 shows the schematics from [2], re-
shown here [3]. When the impedance profile is drawn in a free circuit simulator [6]. Note that this
not flat and the worst-case transient noise is dif- particular simulator has the capability to repre-
ferent from what we can expect from the target sent a full RLC model of a single component,
impedance formula, we need to determine what but for sake of clarity the schematic shown here
the excitation pattern that yields worst-case explicitly calls out all parasitic elements and
noise is and what its value is. Recently modified their own parasitics are set to zero. For example,
target impedance approaches have been pro- component L2, having an inductance value of
posed (for instance [4]), or as I have written [3], a 2nH, has no series resistance or parallel capaci-
conservative correction factor can be used based tance. The series resistance of L2 is separately
on the degree of non-flatness of the impedance called out by R2 with 2mOhm value.
synthesis method. Using a conservative correc- We can run an AC simulation on this circuit
tion factor from the beginning makes it possible to find out its impedance. For this purpose we
to follow a straightforward design process with- run an AC sweep of the I1 current source with a
out the need of iterations. current magnitude of 1A. The V2 voltage source
For LTI PDNs with flat or any non-flat imped- with a voltage of zero is included only for con-
ance, a process called reverse pulse technique venience so that we can also plot the current
Figure 1: Rogue-wave example circuit from Steve Sandler’s DesignCon 2015 paper [2].
going through our circuit. The voltage as a re- er, leaving the timing adjustment to an opti-
sult of the 1A swept-frequency sine-wave excita- mizer to find the biggest noise.
tion gives us the complex impedance. Figure 2 The result is 750 mVpp for a series of 2A cur-
shows the impedance magnitude and phase at rent step, which is equivalent to 375 mVpp/A.
node Zout in the frequency range of 100Hz and Compared to a perfectly flat impedance profile
1GHz. The sweep was logarithmic with 100 fre- matching the largest peak, 126 mOhm, the op-
quency points per decade. timization from Sandler’s paper predicts a worst
The impedance profile shows three peaks case of almost exactly three times of that value.
with almost the same peak value, all slightly The question is: is this really the worst case,
above 100 mOhm. The series loss values are or is it possible to find a different sequence of
very low, 1–6 mOhm, resulting in deep val- current steps that would produce an even big-
leys in between the impedance peaks. The an- ger transient noise? We can turn to the reverse
tiresonance frequencies spread across almost pulse technique to get the answer.
three decades of frequencies. While this im- The reverse pulse technique starts with the
pedance profile would be very rare in practice, step response of the circuit. Since the basic as-
and would most likely be the result of either sumption is that the PDN is linear and time
careless design or lack of any systematic de- invariant (LTI), it does not matter whether we
sign whatsoever, we cannot rule out either look at the response for a positive or negative
the possibility that this could represent an ac- going current step excitation; they are mirror
tual circuit. Making use of the three distinct images of each other. Figure 3 shows the step
peaks separated by deep valleys, Sandler uses a response for a positive going current step. With-
semi-heuristic approach to find what is called out restricting generality, we assume that the
a rogue wave: it defines three repetitive bursts DC voltage on the supply rail is zero and there-
hitting the peak impedances one after the oth- fore most of the transient response will be neg-
Figure 2: Impedance magnitude and phase from the circuit shown in Figure 1. Note that both axes
are logarithmic; in particular, the frequency scale is logarithmic to clearly show the resonance peaks
separated by three orders of magnitude.
Figure 3: Simulated step response of the circuit shown in Figure 1. Note that both axes are linear,
as it would be shown on an oscilloscope or by a default simulation setup. Horizontal axis shows the
full 0 to 0.2 µs time interval.
ative. Because of the LTI assumption, any DC second time interval. On the right half of the
voltage on the rail can be taken into account as plot the step response has a smooth rise; this
a simple shift. is the beginning of the 67 kHz ringing. The left
The excitation current is a single current half of the response has a damped sinusoidal
step, stepping up from zero to one ampere with ringing with approximately 1 µs period; this is
1 ns rise time. Note that the 1 ns rise time cor- originated from the 1.02 MHz impedance peak.
responds to about 300 MHz excitation band- We see some further fast transients near the left
width, where the impedance profile has a ca- vertical axis, but on this horizontal scale we still
pacitive downslope and therefore the actual rise can’t see the details. We have to make another
or fall time of the excitation is less critical. adjustment to the horizontal scale to see those
The step response is shown up to 200 µs, details as well.
where it settles out to a -3 mV DC value. This In Figure 5 we further zoom into the wave-
is the result of the series equivalent of R1 and form and show only the first one microsecond
R3. The main signature we see on this scale is interval. From 0.1 to 1 µs we see a slow sine
a damped sinusoid ringing with approximately wave in the response; this is the 1MHz damped
15 µs period; this corresponds to the 67.6 kHz sinusoid. Near the left vertical axis now we see
lowest-frequency peak in the impedance pro- another damped sinusoidal waveform with ap-
file. We see more rapid changes near the left proximately 20 ns period; this comes from the
vertical axis, but we don’t see any details. To see 51 MHz peak.
more details of the faster transients, we need to To see all signatures on the same plot, we
change the time scale. need to switch to logarithmic horizontal axis,
Figure 4 shows the result. It is the same data, as shown in Figure 6. The logarithmic time
except now we show only the first ten micro- axis, just like the logarithmic frequency axis
Figure 4: Simulated step response of the circuit shown in Figure 1. Both axes are linear. The horizontal
axis shows the first 0 to 10 µs time interval.
Figure 5: Simulated step response of the circuit shown in Figure 1. Both axes are linear. The horizontal
axis shows the first 0 to 1 µs time interval.
Figure 6: Simulated step response of the circuit shown in Figure 1. Vertical axis is linear; the horizontal
axis is logarithmic.
on the impedance plot, allows us to see very With the data points in Figure 7 we can
different signatures on the same plot. We now continue in two different ways. If we do not
clearly see side by side all three damped sinu- need to identify the pattern of the rogue
soid responses. wave excitation and we need only the worst-
With the step response data in Figures 3 case transient noise magnitude, we just need
through 6 we can continue the process of the to sum up the peaks and valleys and take the
reverse pulse technique. (Note that Figures 3–6 difference. The sum of the peaks is -78 mV;
show the same exact data only in different the sum of the valleys is -275 mV. The dif-
forms.) Next, we have to identify the steady ference is -197 mV. The -197 mV value is the
state and the peaks and valleys in the step re- absolute worst-case one-sided noise when an
sponse. We have to do it in reverse order, start- arbitrary sequence of 1A current steps hits
ing with the right-most first extremum (peak or the PDN. The worst-case two-sided transient
valley) and step through the peaks and valleys noise is twice of this value minus the DC
one by one from right to left until we reach the steady-state value (-3 mV in this case). These
excitation time instance. Figure 7 shows the numbers give us 391 mVpp worst-case tran-
time stamps and voltage values of the peaks and sient noise. The other possible way of con-
valleys identified in the step response. Note that tinuing with the data points from Figure 7
in simulated waveforms, like in this case, iden- is to determine the time-domain sequence of
tifying the peaks and valleys automatically is excitation edges creating the worst-case noise
relatively easy; it would become more difficult (the rogue wave) and to actually simulate the
when we need to process step response wave- time-domain noise.
forms obtained by measurements. The measure- With the timing sequence from Figure 7,
ment noise makes the peak/valley identification Figure 8 shows the simulated waveforms on
a little trickier. logarithmic horizontal scale. The blue wave-
Figure 7: Peak and valley time stamps and voltages identified in the step response of the circuit shown
in Figure 1.
form on the bottom is the excitation waveform; mVpp/A predicted by the rogue-wave optimiza-
the black waveform on the top is the transient tion from [2].
response. The peak-to-peak transient value is We can also look at the transient noise by
391 mVpp, exactly matching the value that another popular test method: using a repetitive
we calculated just from the peaks and valleys stream of current steps with 1A magnitude and
of the step response. Note that to achieve the tune the repetition frequency (and possibly also
worst-case transient noise, we used 37 current the duty cycle) until we observe the maximum
steps and their spacing does not exactly follow noise. We just change the definition of the I1
the three resonance frequencies. This straight- current source to a stepped-frequency square-
forward process yields the worst-case noise very wave and run the simulations again. As we
fast, without the need of an optimization loop change the repetition frequency, we find that
and it guarantees to provide the worst-case we get the maximum noise magnitude when the
noise. In this particular example the true worst- repetition frequency matches one of the peak
case noise is 391 mVpp/A as opposed to the 375 frequencies. Figure 9 shows the result when we
Figure 8: Worst-case response simulated with an excitation sequence calculated from the reverse pulse
technique.
Figure 9b: Response waveforms. Note that the square-wave excitation frequencies map out the
middle resonance. The biggest response comes from the 1020 kHz square wave, matching the middle
resonance frequency in the impedance profile.
move the frequency around the middle peak in bers we obtained. Note that the reverse pulse
five values: 300 kHz, 900 kHz, 1020 kHz, 1100 technique yielded the highest noise, and it is
kHz and 5000 kHz. proven to be the absolute worst case. It is also
Figure 10 shows the schematics and wave- true that the rogue-wave optimization could
forms for the three repetition frequencies ex- provide the same (correct) answer, however,
actly matching the three peak frequencies. in a multi-resonance case like this example,
We see that in this case the transient noise without operator guidance it could take a lot
is higher, actually 4/p times higher, than the of computing resources and eventually it may
product of the impedance peak magnitude and not converge.
current magnitude. This is because the high- The first entry in the table is calculated
Q peak picks out the fundamental harmonic as twice the peak deviation of the step re-
and greatly attenuates the harmonics. In the sponse (from the last row in Figure 7) minus
Fourier series of a square wave with 50% duty the steady state response. This is the peak-to-
cycle, the fundamental-frequency sine wave peak noise as a result of a single rising edge
has a 4/p times higher magnitude than that of followed by a single falling edge with a large
the square wave. time separation in between. This estimate is
Finally the table in Figure 11 summa- 85.7% smaller than the true maximum. The
rizes the characteristic noise signature num- second entry equals the biggest peak in Figure
Figure 10b: Response waveforms. Note that the square-wave excitation frequencies exactly match the
three resonances.
Figure 11: Worst-case transient noise estimates of the circuit in Figure 1 based on different calculation
methods. All responses assume a sequence of 1A current steps.
2 (126 mOhm at 51.2 MHz) multiplied by 4/p. 3. Istvan Novak, “Comparison of Power
This is the result of sweeping a periodical cur- Distribution Network Design Methods: Bypass
rent pulse stream to find the maximum noise Capacitor Selection Based on Time Domain and
deviation. This estimate is 59.6% lower than Frequency Domain Performances,” DesignCon
the true worst case. The rogue-wave optimized 2006, February 6–9, 2006, Santa Clara, CA.
value is taken from [2]. It is 4.1% lower than the 4. Jingook Kim, Songping Wu, Hanfeng
true worst case. Wang, Yuzou Takita, Hayato Takeuchi, Kenji
In this particular example, when the imped- Araki, Gang Feng, and, Jun Fan, “Improved
ance profile has multiple, almost equal peaks, Target Impedance and IC Transient Current
the difference is dramatic. Estimating the worst- Measurement for Power Distribution Network
case noise just from the peak deviation or from Design,” proceedings of the IEEE EMC Sympo-
swept-frequency periodic excitation hugely un- sium, July 25–30, 2010, Fort Lauderdale, FL.
der-estimates the worst-case noise. The rogue- 5. Drabkin, et al, “Aperiodic Resonant Ex-
wave optimization, in theory, should be able to citation of Microprocessor power Distribution
find the true worst case, but at a price of signifi- Systems and the Reverse Pulse Technique,” pro-
cant run time and potential convergence fail- ceedings of EPEP 2002, p. 175.
ures. With a more flat impedance profile, with 6. Linear Technology device simulation and
fewer peaks and smaller peak-valley ratio, the models, click here.
errors in all of the approximations would be 7. Target Impedance and Rogue Waves, pan-
lower. Eventually for a perfectly flat impedance el discussion at DesignCon 2016, January 19–
profile all four calculation methods would pro- 21, 2016, Santa Clara, CA.
vide the same result. 8. Jae Young Choi, Ethan Koether, Istvan
Novak, “Electrical and Thermal Consequences
If you want to learn more about the subject, of Non-Flat Impedance Profiles,” DesignCon
follow [7] and [8] at DesignCon 2016. PCBDESIGN 2016, January 19–21, 2016, Santa Clara, CA.
References
1. Larry D. Smith, Raymond E. Anderson,
Douglas W. Forehand, Thomas J. Pelc, and Tan- Dr. Istvan Novak is a distin-
moy Roy, ‘‘Power distribution system design guished engineer at Oracle,
methodology and capacitor selection for mod- working on signal and power
ern CMOS technology,’’ IEEE Transactions on integrity designs of mid-range
Advanced Packaging, vol. 22, no. 3, pp. 284– servers and new technology de-
291, Aug.1999. velopments. With 25 patents to
2. Steve Sandler, “Target Impedance Limita- his name, Novak is co-author of “Frequency-
tions and Rogue Wave Assessments on PDN Per- Domain Characterization of Power Distribu-
formance,” paper 11-FR2 at DesignCon 2015, tion Networks.” To read past columns, or to
January 27–30, 2015, Santa Clara, CA. contact Novak, click here.
A variety of different test methods may be The laminates used in the PCB industry are
used for any one electrical concern. This arti- typically woven-glass reinforced, however there
cle will discuss the issues related to determin- are notable exceptions. The glass reinforcement
ing the dielectric constant (Dk) and dissipation layer typically has a different Dk and Df than
factor (Df or Tan-Delta). On a data sheet, a de- does the raw substrate of the laminate. The stan-
signer may see a Dk value for a material to be dard E-glass most often used in PCB laminates
3.5, as an example. Once the designer buys the has a typical Dk value of about 6 and a dissipa-
material and performs necessary evaluations, tion factor of around 0.004. The common FR-4
it may be found that the Dk of the material is laminates use relatively simple resin systems
3.8. In some applications this difference in Dk and the resin itself has a Dk that is around 3 and
is probably not meaningful; however, for many a Df of about 0.03. Different ratios of resin to
RF and high-speed digital applications, this dif- glass will cause the laminate to have a Dk that is
ference could be very significant. What is really somewhere between the value of the resin and
interesting about this example is that the two that of the glass. However, the glass-resin ratio
Dk values may both be correct, depending on impact on Dk is usually considered when evalu-
the test methods used. ating the material through the thickness axis
Most laminates used in the PCB industry are and if the x- or y-axis is evaluated, the Dk value
anisotropic and this means that the electrical may be very different than the z-axis result.
properties are not the same on all three axes of A large number of test methods are avail-
the material. Typically the thickness (z-axis) of able to evaluate materials for Dk and Df. The
the material will have a different Dk value than methods that are most often used in the PCB
the x or y axes of the material. The reasons for laminate industry for making these measure-
this depend on what type of material is being ments are typically tailored to evaluating mate-
considered. rials in very large volume. Because of this issue,
these test methods need to determine Dk and Df ating the z-axis of the material and the SPDR is
relatively fast, have good repeatability, and be evaluating the x-y plane of the material, both
used for quality control. A common test method results are obviously different but still correct.
used is the clamped stripline resonator, where a Essentially these measurements show to some
clamping fixture is used to form a stripline struc- degree how anisotropic the material is, where
ture; the layer structure of a stripline is ground- the z-axis Dk of the material is 3.5 and the x-y
signal-ground. This test method determines the plane Dk of the material is 3.8.
Dk and Df of the material in the clamped fixture Knowing the anisotropic Dk values of a
and more specifically, it is reporting these values laminate is typically critical for RF applications
related to the thickness axis of the material. with edge coupled features. In the case of high-
Other tests used in high-volume testing speed digital circuits, these values can be im-
include SPDR (split-post dielectric resonator), portant for differential pair structures. Having
rectangular cavity and open cavity resonance these values can be important, but also having a
methods. All three of these methods have elec- modeling software which can incorporate these
tric fields oriented perpendicular to the mate- values into predicted circuit performance is an
rial, which means these test methods will evalu- important supplement to the design process.
ate the x-y plane of the material and not the It is always recommended to contact your
z-axis. In the case of the common FR-4 material material supplier if you have questions about
which is a resin-glass composite, the Dk num- the Dk or Df of a laminate. You should ask
ber can be very different in the x-y plane than which test method is used and which axis or
in the z-axis due to the impact of the glass. axes of the material is being evaluated. Another
Returning to the original example, where good question to ask your material supplier is
a material is tested and found to have a Dk of the frequency at which these values are gener-
3.5 and then another test is done on the same ated, because the Dk and Df of a material is fre-
material and the Dk is found to be 3.8, both of quency dependent. Having the most accurate
these numbers can be correct when using two laminate information for the design phase of a
different test methods. These numbers are actu- project is critical to its success. PCBDESIGN
ally based on real life experience when testing
high frequency laminates that are PTFE based John Coonrod is a senior
with ceramic filler and have woven-glass rein- market development engineer
forcement. With this type of material it is pos- for Rogers Corporation. To read
sible to have the same piece of material tested past columns, or to reach
in the clamped stripline test and get a value of Coonrod, click here.
3.5 and then tested in SPDR and obtain a result
of 3.8. Since the clamped stripline test is evalu-
F
indoutmor
eat
www.
pads
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EchoStar’s Les Beller Shares the products. A low-flow prepreg is a prepreg that
PCB Design-to-Fab Process flows sufficiently to wet out and adhere to bond-
Recently, Barry Matties had the op- ing surfaces and to fill inner layer copper details,
portunity to meet and interview Les but does not flow so much as to fill in cut-out
Beller of EchoStar Technologies. In areas in a heat sink or run unevenly out of the
this interview, Beller focuses on the interface between rigid and flexible elements of a
many challenges circuit board de- rigid-flex PWB.
signers face, strategies for bridging
the gap between circuit design and fabrication, Make the Right Decisions at the Right
and the future of circuit designers. Time in the PCB Design Process
Martin Cotton of Ventec explains
Beyond Design: The Plain Truth why the right decisions are not
About Plane Jumpers always the easiest decisions, but
Moats, islands, cut-outs in the making them well and as early as
ground plane, isolated power possible often avoids errors and
planes, floating ground regions, addition costs. This is certainly the
and a host of other intricate lay- case in PCB design and a key decision influenc-
out techniques are often used by ing the design process and the eventual outcome
PCB designers to reduce crosstalk, is the selection of material and of the materials
EMI, and to otherwise improve overall system per- vendor.
formance. But a high-speed signal crossing a split
in the plane causes problems along at least three Nick Barbin: From Designer to
dimensions, including signal quality, crosstalk, and EMS Company Owner
EMI. Barry Olney explains. Many PCB designers would rather
do just about anything than pore
Cadence’s Brad Griffin Digs Deep Into DDR over a P&L spreadsheet. But Nick
Guest Editor Kelly Dack stopped by Barbin isn’t a typical designer. He
the Cadence Design Systems booth co-founded the design bureau Op-
at DesignCon 2015, where he sat timum Design Associates over two
down with Product Marketing Man- decades ago, and the company later expanded
ager Brad Griffin to discuss Cadence’s into contract manufacturing and Lean processes. I
advanced PCB design and signal in- caught up with Nick recently and asked him how
tegrity tools, and the company’s focus on DDR. he wound up leading an EMS company on the Inc.
5000 list.
Trending at Freedom CAD:
New Crop of Next-Gen Designers Broadcom PCB Design:
Scott McCurdy, director of sales and marketing Miniaturization on the Cutting Edge
at Freedom CAD Services, expresses his vision for Andy Shaughnessy recently attend-
what North America is bringing to the table in the ed the Orange County Designer’s
world of circuit design. I-Connect007 Publisher Council “Lunch and Learn” meet-
Barry Matties and McCurdy also discuss China, ing, held at the Broadcom offices
trends in product design, tools, and more. on the campus of the University
of California, Irvine. Afterward, he
Material Witness: Low-Flow Prepregs— sat down with Scott Davis, CID, the senior man-
Defining the Process ager of PC board design at Broadcom, to discuss
Let’s try to define “low flow” in terms that will the company’s savvy PCB design department and
make sense to both suppliers and users of the their approach to PCB design.
CONTACT YOUR
SUPPORT TEAM Greg Bull
Applications
Dale Doyle
Applications
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Manager
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article
ic interference (EMI), power integrity (PI) and case for an infotainment system that includes
thermal integrity (TI). multiple high-definition displays, high-defini-
tion audio and broadband Internet connectiv-
The Automotive Electrical System ity. The main ECU integrated circuit is typically
Figure 2 shows an abstract view of an auto- called a microcontroller. It has become a com-
motive electrical system with a few of the major plex, high-pin-count, high-speed, multicore
subsystems included. A single electronic control processor and is anything but “micro.”
unit (ECU) is labeled in the figure. This master Some automotive electrical systems have
ECU is supported hierarchically by ECUs with grown to have as many as 100 ECUs, which im-
local control over their respective subsystem plies a very complex system. There is a trend to
components. Past generations of automotive reduce this large number of ECUs by a factor of
ECUs were typically simple two-layer PCBs, even two to three. The trend is toward more complex
for the master ECU. PCB physical design (e.g., ECUs at the top of each hierarchical subsys-
layout) was accomplished with general drafting tem with smart sensors at the lowest level. This
tools and SI/PI/TI/EMI simulations were not of- trend implies more complex PCBs for each sub-
ten required. For modern automotive systems, system high-level ECU and potentially no PCB
the lowest-level ECUs still typically have small, for some of the local sensors. As automotive
two-layer PCBs, but a modern master ECU fea- system components, the master and high-lev-
tures a complex, multilayer PCB. Subsystem el subsystem ECUs must be absolutely reliable
ECUs might also be quite complex; this is the and low cost. Their PCBs must support higher
speed and higher pin-count microcontrollers, one below. Off-board high-speed signals are
greater bandwidth for on-board and off-board typically serialized (converted from parallel to
data communications, reduced size and weight, serial), which reduces cable harness complexity
and finally accommodate high levels of electro- and weight because a single unshielded twisted
magnetic noise unique to automotive environ- pair of wires might be applied for cabling.
ments. Electrical simulations of system-level SI, The system-level simulations must con-
PI and EMI effects are now unavoidable for au- sider the full hierarchy of chip/package/board
tomotive ECU boards. to properly judge performance as well as repre-
Though PCB-centric, these system-level sent the actual operating condition of the sys-
simulations involve both on-board and off- tem. “Bits-to-bits” simulations are performed
board interconnects, including the cable har- whether for parallel interconnect between a
ness and its associated connectors (both inline microcontroller and external memory on the
and to PCB). Two-layer PCBs are inexpensive same PCB or for serial interconnect between a
but not able to support the design complexity transmitter on one ECU board and a receiver
and electrical performance required for modern on another ECU. Therefore, serial interconnect
ECUs. Power delivery of multiple voltages with analyses involve multiple boards as well as the
minimal loss and low noise, reduced emissions physical signal channel between them.
and lower immunity, as well as controlled im-
pedance interconnect, require multiple plane Signal Integrity
layers for the power delivery network (PDN) The challenges involved in designing an
of ECU boards. The on-board interconnect for automotive infotainment subsystem that com-
these multi-layer boards is composed of inter- prises both in-dash components for the driver
layer vias, microstrip with one PDN plane and and remote components for the passengers, as
stripline with two PDN planes, one above and shown in Figure 3, serve as an excellent exam-
ple for system-level SI simulation. The “info” routing, (3) initial timing enforcement, (4)
qualifier implies an Internet connection, which board-level SI performance assessment and (5)
might be provided by another subsystem and power-aware SI compliance signoff. Constraint-
accessed via a high-speed Ethernet connection based physical design enables a correct-by-
or might be implemented by an RF section of construction flow. Physical as well as electrical
the PCB. In either case, it adds significantly to constrains are dynamically flagged as routing
the complexity of the board. The chipset re- occurs for instant feedback and on-the-fly cor-
quired to decode and process HD video and rection. The alternative is a much more time-
audio are high-speed, high-pin-count devices, consuming process of iteratively cleaning-up
usually requiring a fairly complex board. design rule check (DRC) errors after initial PCB
On-board memory is required with its asso- routing is completed. Autorouting is critically
ciated multibyte parallel bus, thereby indicating important and available for individual nets,
the need for controlled impedance and delay- differential pairs and entire buses. A bit of in-
teractive guidance for the autorouter, a process
“
dubbed “auto-interactive,” during device-local
breakout routing and bus-level delay tuning
The chipset required to greatly speeds these tasks. The electrical param-
eters of impedance and delay are computed in
decode and process HD video real time whether routing is performed manu-
and audio are high-speed, ally or automatically. These per-net electrical
parameters are available to support timing anal-
high-pin-count devices, usually ysis and rapid interactive tuning of the entire
”
requiring a fairly complex bus to comply with standard protocols (e.g.,
DDR3, DDR4). These tasks are all accomplished
board. by a layout designer before the final completed
board design is passed to an SI engineer for per-
formance verification.
PCB design team members first assess the
tuned signal routing during physical design as design for operating condition independent
well as timing analysis for performance signoff. characteristics, such as net impedance, cou-
The remote passenger displays require a simi- pling among nets and return path discontinui-
lar level of decoding capability and might be ties. The analysis is rapid and very high capac-
nearly as complex as the in-dash PCB. They also ity, enabling the entire board to be considered.
require a high-speed multi-drop interface, such The results are available in tables or as color-
as Ethernet, be available on both the in-dash shaded layout overlays for intuitive assessment.
and remote boards. The design requirements A power-aware analysis (including the effects
for such systems include complex multi-layer of the actual current return paths in the PDN)
boards and high-speed parallel bus routing, as might be performed to narrow down SI issues
well as high-speed serial interconnect with mul- to individual byte lanes or even a few nets. This
tiple boards. Designs must be simulated and rapid assessment applies ideal I/O buffers with
analyzed including full serial channel charac- piecewise linear signals and examines a small
terization. These challenges for physical design set of SI metrics defined by received signal, far-
and SI simulation are not unique to automotive end crosstalk and intersymbol interference.
applications and are available with enterprise- SI issues with routing are quickly and reli-
class PCB physical design software. ably identified to be addressed in layout or ex-
First consider routing and performance veri- amined further with more detailed SI simula-
fication of the high-speed memory buses. There tion. Layout-based detailed simulations of a few
are five key aspects of PCB design software for nets might be performed relatively quickly to
high-speed parallel bus design: (1) constraint- judge performance or validate the performance
based physical design, (2) automation for bus improvement of design changes. Whole-bus
“
Just as memory subsystem design is not unique
to automotive applications, serial link design
is also common among many high-speed elec- Future infotainment needs,
tronics designs. However, unlike memory, au-
tomotive serial communications apply unique as well as many envisioned
protocols and physical channel hardware. ADAS capabilities, require very
Each of the system’s PCB and physical chan-
”
nel components is designed independently.
high bandwidth communication
Vendors provide cables and connectors to form internal to the vehicle.
the physical channel and commercially avail-
able chipsets are applied, which are likely to
use third-party IP blocks. These chipsets and IP
blocks might seem to simplify the PCB design
process for serial links, but in reality, it is more The factor of 10 increase in data rate has
complex. Design performance must be verified implications for PCB design and SI simulations
through characterization of the full system, required to ensure reliable operation. As pre-
from serialized digital output from the trans- viously observed for computing, telecom and
mitter (TX) to serialized digital input to the re- mobile designs, as signals approach the gigabit-
ceiver (RX). As for memory subsystems, a few per-second range, effects that were safely over-
nets might be characterized with layout-centric looked in the past start to matter. Things like
simulation, but these results are not the desired reflections, crosstalk, interconnect losses, and
performance and system-level block schematic equalization all become critically important.
simulations are a requirement. For serial links, vias are often the largest
Presently available capabilities supported by impedance discontinuity on the PCB, causing
automotive Ethernet include infotainment sys- potential reflections along the channel and
tems, sensors and backup cameras. A new IEEE crosstalk between channels. Methodologies to
standard, 100BASE-T1, defines 100Mbps auto- maintain high signal quality for routing within
via fields and to craft transparent inter-layer via to the IBIS (I/O Buffer Information Sheet) stan-
transitions have become expected capabilities dard. IBIS-AMI models are now readily available
of PCB design software. from chipset vendors and commonly applied
Automotive Ethernet standards allow for to serial-link simulation of computing and tele-
up to 15 meters of cable. At gigabit data rates, com designs. IBIS-AMI models are expected to
twisted-pair cables experience significant at- quickly become equally commonplace for auto-
tenuation due to high-frequency metal loss. motive Ethernet transceiver ICs.
Advanced equalization techniques, such as feed Serial links require compliance to a specific
forward equalization (FFE) or continuous time BER. For 1000BASE-T1, this value is 1.0e-10,
linear equalization (CTLE), are applied to com- or one error for every 10 billion bits received.
pensate. FFE and CTLE are complex DSP algo- Because it is impractical to directly simulate
rithms implemented with large and complex tens of billions bits of data with traditional cir-
transceiver ICs. For PCB system simulations, cuit simulation, high-capacity simulation ap-
these algorithms can be addressed with the al- proaches are applied to simulate hundreds of
gorithmic modeling interface (AMI) extension thousands or even millions of bits to generate
eye diagrams with stable signal density distribu- protocol compliance checks for serial link per-
tions. These distributions are processed to pro- formance. Draft-level prototype implementa-
duce bathtub curves to reliably predict BER per- tion of such compliance checks is now avail-
formance. These simulation approaches apply able. Second, vendors must openly provide
an impulse response to characterize the serial IBIS-AMI models for their chipset or IP blocks.
channel and then apply convolution methods This process is slow for computing and telecom
to achieve their high-capacity throughput. device vendors but has become standard prac-
Automotive Ethernet standards apply pulse tice and seems to be perceived as a market-en-
amplitude modulation (PAM). The 1000BASE- try requirement by automotive Ethernet chip-
T1 standard targets PAM-3, which means three set and IP vendors. Rapidly advancing market
logic signal levels exist on the channel instead forces for ADAS and infotainment systems are
of traditional two-level binary signals (Fig- driving (pun intended) these final steps to be
ure 4). PAM-3 has significant implications for completed sooner than many had envisioned
transceiver design as well as the modeling and necessary only months ago.
simulation algorithms. Serial-link simulation In summary, as the automotive market goes
software has been recently upgraded to support through rapid changes, PCB Design teams must
PAM for IBIS-AMI algorithms. As for transceiver rise to the electrical challenges. Unique signal
IC design, it is a complex task to accommodate integrity challenges are faced by design teams
PAM signals in the many equalization algo- due to the systemic nature of an automobile.
rithms, a task accomplished for PCB system de- With safety concerns at a premium, signal qual-
sign software in parallel as part of general multi- ity concerns take a front seat to these chal-
level PAM signal support. lenges. Modern PCB signal integrity tools must
Due to the application of PAM3, high at- advance the features originally developed for
tenuation and high levels of electromagnetic computing, telecom and mobile designs to sup-
interference, 1000BASE-T1 designs use forward port the automotive industry. Compliance tests
error correction (FEC). This technique applies for 1000BASE-T1 utilizing three logical signal
Reed Solomon algorithms to boost BER to the levels (PAM-3) is just one example. PCBDESIGN
required level. FEC is not applied for typical
computing or telecom designs but has recently Brad Brim is senior staff
been implemented for PCB system design soft- product engineer at Cadence
ware to enable automotive Ethernet design. Design Systems. He holds a
The final step to complete automotive Eth- PhD in electrical engineering.
ernet application for mainstream PCB system
design is twofold. First, the IEEE standard must
be finalized to fully know and implement the
Future Batteries Could on the Orbital ATK’s S.S. Deke Slayton II Cygnus
spacecraft atop a United Launch Alliance Atlas
Charge in 30 Seconds V rocket Dec. 3. A team of students attending
Desert Christian School in Lancaster, California,
with the support of NASA mentors and the Uni-
Future cell phones and other electronics versity of California, Los Angeles, developed the
could have batteries that charge in less than a experiment.
minute. This new capability will be in part thanks The experiment is designed to see how
to a space experiment using hard, flexible mate- graphene-based supercapacitors charge, dis-
rial as a clean power source. charge and deteriorate in a microgravity envi-
That potential future is scheduled for launch ronment.
Example:
GJ01911Rev2.1_Legend$Top.gbr
GJ01911Rev2.1_Soldermask$Top.gbr
GJ01911Rev2.1_Copper$L1$Top.gbr
GJ01911Rev2.1_Copper$L2$Inr$Plane.gbr
…
GJ01911Rev2.1_Copper$L10$Inr$Plane.gbr
…
So what should you do if your PCB layout This column has been excerpted from the
software is not capable of outputting the current Guide to PCB Fabrication Data: Design to Fabri-
Gerber version with attributes? This is a pro- cation Data Transfer.
blem, and indeed the temptation is to suggest
that you consider switching to layout software
that supports up-to-date Gerber output. Karel Tavernier is managing
X2 is the Gerber standard to transfer the director of Ucamco.
layer structure. If you cannot output X2, you
will need to use an informal method to defi-
ne the layer structure in a legible form that the
1
Mentor Graphics Reports
Revenues of $291M in 3
Digi-Key Partners with
Accelerated Designs to
Fiscal Q3 Provide Symbols and Footprints
for 7.2M Components
Mentor Graphics Corporation has announced fi-
nancial results for the company’s fiscal third quar- Digi-Key Electronics has announced an exclusive,
ter ended October 31, 2015. The company report- global agreement to distribute software and de-
ed revenues of $291 million. For the fourth quarter sign data from Accelerated Designs. Accelerated
of fiscal 2016, the company expects revenues of Designs focuses on providing engineers and elec-
about $336 million. tronics manufacturers EDA-tool-neutral software
and data that improves efficiency of adding and
managing new parts when designing circuits and
2
SnapEDA: The Female-Owned
Startup Revolutionizing
printed circuit boards.
CAD Data
SnapEDA founder Natasha Baker may mark the 4
Navigating the Global
Materials Supply Chain:
beginning of a new trend in EDA: young fe- A Roundtable Discussion
male entrepreneurs. (When was the last time
we heard about an EDA startup?) As her com-
At SMTAI, Andy Shaughnessy sat down for a
pany prepared for a major launch, Natasha took
roundtable discussion with some key players from
time to explain the philosophy behind SnapEDA,
the materials side of the supply chain. Participants
and how the company is helping designers and
included two executives from Ventec: Mark Good-
engineers manage an ever-increasing volume of
win, COO USA and Europe for Ventec Internation-
CAD data.
al Group; and Jack Pattie, president of Ventec USA.
Also participating in the roundtable were Schoeller
Electronics CEO Michael Keuthen, and Bob Willis
of the National Physics Laboratory.
8
Beyond Design: Stackup
Planning, Part 4
Events
For the IPC Calendar of Events, click here.
For the SMTA Calendar of Events, click here. ICT-UK Evening Seminar
March 1, 2016
For a complete listing, check out Tewksbury, England
The PCB Design Magazine’s event calendar.
IPC APEX EXPO 2016 and
the Design Forum
DesignCon 2016 March 13–17, 2016
January 19–21, 2016 Las Vegas, Nevada USA
Santa Clara, California, USA
25th China International PCB
EIPC Winter Conference & Assembly Show 2016 (CPCA)
January 21–22, 2016 March 15–17, 2016
Dresden, Germany Shanghai, China
FlexTech Alliance
February 29–March 3, 2016 For additional events,
Monterey, CA USA see our other magazines.
Las
Vegas
Santa Shanghai
China
Monterey Clara
Dresden Tewksbury
USA
The PCB Design Magazine® is published by BR Publishing, Inc., PO Box 50, Seaside, OR 97138
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December 2015, Volume 4, Number 12 • The PCB Design Magazine© is published monthly, by BR Publishing, Inc.
A d v er t i s er I n de x Coming Soon to
Accurate Circuit Engineering..... 13 Isola........................................... 5 The PCB Design
American Standard................... 25 Mentor Graphics...................... 59 Magazine:
ANS.......................................... 45 Miraco...................................... 17
Intercept................................... 15 Ventec...................................... 23
IPC........................................... 69