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Introduction to Computer Organization

KR Chowdhary Professor & Head

Email: kr.chowdhary@acm.org

Department of Computer Science and Engineering MBM Engineering College, Jodhpur

February 5, 2011

Processor level design

memoryProcessor level design CPU or processor (instruction sets) Input/output Devices networks Information transferred is in

CPU or processor (instruction sets)Processor level design memory Input/output Devices networks Information transferred is in words Control bus CPU Address

Input/output Deviceslevel design memory CPU or processor (instruction sets) networks Information transferred is in words Control bus

networksCPU or processor (instruction sets) Input/output Devices Information transferred is in words Control bus CPU Address

Information transferred is in words

Control bus

networks Information transferred is in words Control bus CPU Address bus databus Control bus memory Address

CPU

networks Information transferred is in words Control bus CPU Address bus databus Control bus memory Address
networks Information transferred is in words Control bus CPU Address bus databus Control bus memory Address

Address bus

databus

Control bus

is in words Control bus CPU Address bus databus Control bus memory Address bus databus Interconnection
is in words Control bus CPU Address bus databus Control bus memory Address bus databus Interconnection

memory

words Control bus CPU Address bus databus Control bus memory Address bus databus Interconnection networks (busses)

Address bus

bus CPU Address bus databus Control bus memory Address bus databus Interconnection networks (busses) provide dynamic

databus

Interconnection networks (busses) provide dynamic connection between components -handshake -synchronous/clocked

Instruction cycle

begin are instructions waiting NO executions? YES fetch execute NO interrupt waiting? is YES Service
begin
are
instructions waiting
NO
executions?
YES
fetch
execute
NO
interrupt waiting? is
YES
Service interrupt

CPU Architecture

ALU AC DR PC AR IR ctrl ckts ctrl lines
ALU
AC
DR
PC
AR
IR
ctrl ckts
ctrl lines
AC programcontrol unit
AC
programcontrol unit

f(AC,DR)

One CPU Cycle t c p u =smallest micro-operation of CPU, 1/ c c p u =maximum clock t cpu =smallest micro-operation of CPU, 1/c cpu =maximum clock freq. of CPU.Execution time=no. of cpu clock cycle t cpu

One memory cycle t m = time spent between address applied to memory, to data released by memory. t m = time spent between address applied to memory, to data released by memory.

t m / t c p u ≈ 1 0 . t m /t cpu 10.

kr chowdhary

Processor Architecture

4/ 12

detailed instruction cycle

start cpu activated? NO YES AR <-PC fetch DR<-M(AR) cycle IR<-DR(opcode) PC<-PC+1 decode opcode
start
cpu activated?
NO
YES
AR <-PC
fetch
DR<-M(AR)
cycle
IR<-DR(opcode)
PC<-PC+1 decode opcode
NO
NO
add instr.
JMP inst.
YES
YES
execute
AR<-DR(addr)
cycle
DR<-M(AR)
PC<-DR(addr)
AC<-AC+DR

Intel 8085 Bus structure

8-bit CPUIntel 8085 Bus structure Communicates with other units using 16-bit address lines, 8-bit data, and control

Communicates with other units using 16-bit address lines, 8-bit data, and control busIntel 8085 Bus structure 8-bit CPU Address: A 0 − A 1 5 , total addressable

Address: A 0 − A 1 5 , total addressable memory=2 1 6 = 65536 (64k). A 0 A 15 , total addressable memory=2 16 = 65536 (64k). Address locations 0 - 65535 (0000H - FFFFH).

Databus D 0 − D 7 , multiplexed with lower 8 bits of address bus ( D 0 D 7 , multiplexed with lower 8 bits of address bus (A 0 A 15 ).

Control bus: Various signal lines (binary) carrying signals like Read/write, enable, flag bits, etc., multiplexed with lower 8 bits of address bus ( A 0 − A 1 5

Intel 8085 Internal architecture

Stores 8-bit data (registers, accumulator)Intel 8085 Internal architecture performs arithmetic, logic, and data movement operations Tests for conditions (if/then)

performs arithmetic, logic, and data movement operationsarchitecture Stores 8-bit data (registers, accumulator) Tests for conditions (if/then) Sequence the execution of

Tests for conditions (if/then)performs arithmetic, logic, and data movement operations Sequence the execution of instructions Stores temporary data

Sequence the execution of instructionsand data movement operations Tests for conditions (if/then) Stores temporary data in RAM during execution kr

Stores temporary data in RAM during executionTests for conditions (if/then) Sequence the execution of instructions kr chowdhary Processor Architecture 7/ 12

Intel 8085 registers

6 general purpose registers, 8-bit, B,C, D, E, H, L, which can be used to form 3 - 16 bit registers, BC, DE, HL.Intel 8085 registers Accumulator is 8 - bit register Tests for conditions (if/then) Flag bits: Indicate

Accumulator is 8 - bit registerwhich can be used to form 3 - 16 bit registers, BC, DE, HL. Tests for

Tests for conditions (if/then)bit registers, BC, DE, HL. Accumulator is 8 - bit register Flag bits: Indicate the result

Flag bits:

Indicate the result of condition sets: C, Z, S, P,8 - bit register Tests for conditions (if/then) Flag bits: Program counter: Contains memory address of

Program counter: Contains memory address of next instruction, Stack register: holds the return address for subroutine call, can save registers(PUSH, POP Instructions)(if/then) Flag bits: Indicate the result of condition sets: C, Z, S, P, kr chowdhary Processor

Intel 8085 assembly language programming

Program to add two numbers:

MVI

A, 7BH

MVI

B, 67H

ADD B

HLT

Program to multiply a number 4:

MVI

A, 30H

RRC

RRC

MOV B, A

HLT

Intel 8085 assembly language programming

Find greater between two numbers:

MVI

B, 30H

MVI

C, 40H

MOV A, B CMP C JZ EQU JC GRT

MVI

D, 01H

HLT

EQU: MVI D, 00H

HLT

GRT: MVI D, 02H

HLT

Intel 8085 Architecture

Intel 8085 Architecture kr chowdhary Processor Architecture 11/ 12

Peripheral processor with ROM

CLK

RDY AD0-AD7 PA0-7 A8-A10 A CE 2k X 8 IO/M EPROM ALE PB0-7 RD B
RDY
AD0-AD7
PA0-7
A8-A10
A
CE
2k X 8
IO/M
EPROM
ALE
PB0-7
RD
B
IOW
Reset
IOR
Vcc
Prog/CE
VDD

8755 2kx8 bytes EPROM with I/O