Introduction to Computer Organization

KR Chowdhary
Professor & Head
Email: kr.chowdhary@acm.org

Department of Computer Science and Engineering

MBM Engineering College, Jodhpur

February 5, 2011

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Processor level design

memory
CPU or processor (instruction sets)
Input/output Devices
networks
Information transferred is in words

Control bus Address bus

CPU
databus

memory Address bus

Control bus
databus

Interconnection networks (busses) provide dynamic connection

between components
-handshake
-synchronous/clocked
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Instruction cycle

begin

are
instructions
waiting NO
executions?

YES

fetch

execute

NO is
interrupt
waiting?
YES
Service
interrupt

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CPU Architecture
ALU f(AC,DR)
AC

AC
DR b b b
b

program control unit

AR PC IR

ctrl ckts
b b

ctrl lines

One CPU Cycle tcpu =smallest micro-operation of CPU,

1/ccpu =maximum clock freq. of CPU.Execution time=no. of
cpu clock cycle Ötcpu
One memory cycle tm = time spent between address applied to
memory, to data released by memory.
tm /tcpu ≈ 10.
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detailed instruction cycle

start

cpu activated? NO
YES
AR <-PC
fetch
DR<-M(AR) cycle

IR<-DR(opcode)
PC<-PC+1
decode opcode

NO NO
add instr. JMP inst. b b b

YES
AR<-DR(addr) YES execute
cycle

DR<-M(AR) PC<-DR(addr)

AC<-AC+DR

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Intel 8085 Bus structure

8-bit CPU
Communicates with other units using 16-bit address lines,
8-bit data, and control bus
Address: A0 − A15 , total addressable memory=216 = 65536
(64k). Address locations 0 - 65535 (0000H - FFFFH).
Databus D0 − D7 , multiplexed with lower 8 bits of address bus
(A0 − A15 ).
Control bus: Various signal lines (binary) carrying signals like
Read/write, enable, flag bits, etc.

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Intel 8085 Internal architecture

Stores 8-bit data (registers, accumulator)

performs arithmetic, logic, and data movement operations
Tests for conditions (if/then)
Sequence the execution of instructions
Stores temporary data in RAM during execution

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Intel 8085 registers

6 general purpose registers, 8-bit, B,C, D, E, H, L, which can

be used to form 3 - 16 bit registers, BC, DE, HL.
Accumulator is 8 - bit register
Tests for conditions (if/then)
Flag bits:
Indicate the result of condition sets: C, Z, S, P,
Program counter: Contains memory address of next
instruction, Stack register: holds the return address for
subroutine call, can save registers(PUSH, POP Instructions)

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Intel 8085 assembly language programming

Program to add two numbers:

MVI A, 7BH
MVI B, 67H
ADD B
HLT

Program to multiply a number 4:

MVI A, 30H
RRC
RRC
MOV B, A
HLT

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Intel 8085 assembly language programming

Find greater between two numbers:

MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
MVI D, 01H
HLT

EQU: MVI D, 00H

HLT

GRT: MVI D, 02H

HLT

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Intel 8085 Architecture

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Peripheral processor with ROM

CLK

RDY

AD0-AD7

A8-A10 PA0-7
A
CE
2k X 8
IO/M EPROM
ALE
RD B PB0-7
IOW
Reset

IOR

Vcc
Prog/CE
VDD

8755 2kx8 bytes EPROM with I/O

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