USN 16EVE153

First Semester M.Tech. Degree Examination, June/July 2017

ASIC Design

Time: 3 hrs. Max. Marks: 80

Note: Answer FIVE full questions, choosing
ONE full question from each module.
2. Any revealing of identification, appeal to evaluator and /or equations written eg, 42+8 = 50, will be treated as malpractice.

Module-1

1 a. Explain standard cell-based ASIC with a neat diagram. (08 Marks)

b. Distinguish between channeled gate array and channellers gate array. (08 Marks)
Important Note : 1. On completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

OR
2 a. Explain carry save adder with relevant logic equations and cell diagram. (12 Marks)
b. Explain cell compilers. (04 Marks)

Module-2

3 a. Define logical effort. Predict delay of a 3-input NOR logic cell with 2x drive, driving a neat
with a fanout of four, with a total load capacitance (comprising the i/p capacitance plus inter
conned) of 0.3pF. [Give : tPD = (0.03 + 0.72 cout + 0.6)ns. (08 Marks)
b. Compute delay involved in implanting following function as a multistage A011221 logic.
Zn(A1, A2, B1, B2, c) = NOT (NAND(NAND(A1, A2), AOI21(B1, B2, C)))
Compare this delay with that of single stage implementation. (08 Marks)

OR
4 a. Compare ACT – 1 and ACT – 2 logic modules with examples. (08 Marks)
b. With help of neat diagram, explain Xilinx Xc3000CLB. (08 Marks)

Module-3

5 a. Explain schematic icons and symbols with examples. (08 Marks)

b. What is a netlist screener? List the errors that can be found by a netlist screener. (08 Marks)

OR
6 a. Explain physical design flow in ASIC design. (08 Marks)
b. Explain constrictive partitioning with rules and a relevant illustration. (08 Marks)

Module-4

7 a. Explain input/output power pads with relevant diagrams. (08 Marks)

b. Explain placement goals and objectives. (08 Marks)
1 of 2
 16EVE153

OR
8 a. Explain with a neat diagram timing driven floor planning and placement design flow.
b. (08 Marks)
Explain min-out placement with an illustration. (08 Marks)

Module-5

9 a. Explain global routing between blocks for a cell-based ASIC with neat diagram. (08 Marks)
b. What is detailed routing? Explain goals and objectives of detailed routing. (08 Marks)

OR
10 a. Explain the 2 types of design checks in details : DRC and LVS. (04 Marks)
b. Write short notes on :
i) Circuit extraction
ii) SPF, RSPF and DSPF. (12 Marks)

*****

2 of 2