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1 2 3 4 5 6 7 8

PCB STACK UP
SGN@---->Internal CLK GEN.
GN@ ---->External CLK GEN.
IV@ -----> iGPU
ZR8 SYSTEM DIAGRAM RAMP
LAYER 1 : TOP SW@ -----> dGPU
DDR3-SODIMM1 DDR3 channel A
SP@ -----> iGPU & dGPU notice CPU THERMAL
LAYER 2 : GND AMD Champlain
SPE@ ----->Only for dGPU notice
LAYER 3 : IN1 SIDE@ ----> Side port
P5
35mm X 35mm
SENSOR
A LAYER 4 : IN2 S1G4 Processor P4
A

DDR3-SODIMM2 DDR3 channel B


LAYER 5 : VCC
638P (PGA)45W/35W
LAYER 6 : IN3 P6 P2 ~ 4 CPU_CLK
LAYER 7 : GND NBGFX_CLK CLOCK GEN
LAYER 8 : BOT NBGPP_CLK From SB
SBLINK_CLK P11
HT3

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PCI-Express 16X ATI
PCI-E HDMI HDMI
Madison LP

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P25
128-bit M2 Pkg
NORTH BRIDGE 29mm X 29mm
CRT
SIDE port CRT
Mini PCI-E
MUXs P24
LAN RS880
Atheros Card (S.G)
P16 ~ 20 LVDS
PCIE-LAN A12 P7 LVDS
AR8151 (Wireless LAN) DDR3 800MHz P24
B 21mm X 21mm, 528pin BGA P24 B
(10/100/1000)
VRAM
P26 P27 CRT
64MX16X4,64 bit
LVDS
P7 ~ 10 64MX16X8,128 bit

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P22,23
RJ45
ALINK X4
P26

SATA0 150MB
Charger (ISL88731A) SATA - HDD1 BT
P35 P28 SOUTH BRIDGE P31

SATA1 150MB SB820


DC/DC ( 3VPCU / 5VPCU ) SATA - ODD

id
RT8206B P36 P28 21mm X 21mm, 528pin BGA USB1.1
4.5W(Ext)
C CPU_VCORE ( VCORE ) 4.3W(Int) USB2.0 C

ISL6265A P37

USB2.0 Ports Webcam


DC/DC ( +1.1V_S5 ) P11 ~ 14 CardReader
X1 P31 P24
UP6111AQD

DC/DC ( NB_CORE )
P38
nf LPC Azalia
AU6433/AU6437
P30

UP6111AQD P39

Winbond KBC Codec USB BOARD


DC/DC ( +1.5VSUS ) RTL ALC271X
NPCE781L USB2.0 Ports x 3
RT8207A P40
P31
P29
Co
P34
DC/DC ( GPU_CORE )
MAX8792ETD+T P41

D
DC/DC (+1.8V/+1V/+2.5V ) D

HPA00835RTER / RT9018A / RT9025-25PSP P42


FAN SPI Digital MIC AUDIO CONN Speaker
Keyboard P33 (Phone/ MIC)
DC/DC ( CPU_VDDR ) P31 P33 P34 P24 P29 P29
PROJECT : ZR8
RT9025-25PSP P43 Touch Pad
Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A

Date: Wednesday, May 27, 2009 Sheet 1 of 49


1 2 3 4 5 6 7 8
5 4 3 2 1

W/S= 15 mil/20mil SB check list tide to CPUVDDIO (+1.5VSUS)

03
+2.5V L40 +CPUVDDA
PBY201209T-221Y-N CPU_PWRGD_SVID_REG 300/F_4 R236
2.5V@250mA CPU_LDT_RST# 300/F_4 R261
+1.1V 1.1V@1.5A +1.1V_VLDT C447
4.7u/6.3V_6
C436
4.7u/6.3V_6
C428
0.22u/6.3V_4
C432
3300P/50V_4
C440
[11] CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
300/F_4
*300/F_4
R249
R463
+1.5V

A41 *10U/6.3V_8 [11] CLK_CPU_BCLKN_PR


R124 *SHORT_PAD
Keep trace from resisor to CPU within 0.6"
R121 *SHORT_PAD +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U29D
U29A W/S= 15 mil/20mil
P/N: DG0^8000004 CLK_CPU_BCLKP_C R464 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA F8 VDDA1 VSS M11 S1G4
DG0^8000005 C414 10U/6.3V_8 +1.1V_VLDT D1 VLDT_A0 HT LINK VLDT_B0 AE2 +1.1V_VLDT 10U/6.3V_8 C397 +CPUVDDA F9 VDDA2 RSVD11 W 18
C265 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22u/6.3V_4 C273
D DG0^8000009 C376 0.22u/6.3V_4 +1.1V_VLDT D3
VLDT_A1 VLDT_B1
AE4 +1.1V_VLDT 180P/50V_4 C387 CLK_CPU_BCLKP_PR C704 3900P/25V_4 CLK_CPU_BCLKP_C A9 A6 CPU_SVC D
C274 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C703 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD
DG0^80000013 D4 VLDT_A3 VLDT_B3 AE5 A8 CLKIN_L SVD A4

DG0^80000014 HT_CADINP0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUTP0


[11] CPU_LDT_RST#
CPU_LDT_RST# B7 RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD_SVID_REG
A7
HT_CADINP1 L0_CADIN_L0 L0_CADOUT_L0 HT_CADOUTP1 [11,37] CPU_PWRGD_SVID_REG CPU_LDT_STOP# PW ROK CPU_THERMTRIP_L#
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 [9,11] CPU_LDT_STOP# F10 LDTSTOP_L THERMTRIP_L AF6
HT_CADINN1 F1 AC3 HT_CADOUTN1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8
HT_CADINN2 G2 AA1 HT_CADOUTN2 SideBand Temp sense I2C [4] AF4
HT_CADINP[15..0] L0_CADIN_L2 L0_CADOUT_L2 CPU_SIC SIC
HT_CADINP3 G1 AA2 HT_CADOUTP3 AF5
[7] HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 [4] CPU_SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 [4] CPU_ALERT ALERT_L THERMDC H_THRMDC [4]
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
[7] HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA [4]
HT_CADINN4 K1 W3 HT_CADOUTN4 R207 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] L0_CADIN_L4 L0_CADOUT_L4 HT_REF0

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HT_CADINP5 L3 V1 HT_CADOUTP5 S1G4 R208 44.2/F_4 CPU_HTREF1 P6
[7] HT_CLKINP[1..0] L0_CADIN_H5 L0_CADOUT_H5 +1.1V_VLDT HT_REF1
HT_CADINN5 L2 U1 HT_CADOUTN5 place them to CPU within 1.5"
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 [37] CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 VDDIO_FB_H [40]
[7] HT_CLKINN[1..0] HT_CADINN6 HT_CADOUTN6 VDDIO_FB_L
M1 L0_CADIN_L6 L0_CADOUT_L6 U3 [37] CPU_VDD0_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L [40]
HT_CTLINP[1..0] HT_CADINP7 N3 T1 HT_CADOUTP7
L0_CADIN_H7 L0_CADOUT_H7

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[7] HT_CTLINP[1..0] HT_CADINN7 HT_CADOUTN7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1 [37] CPU_VDD1_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_FB_H [37]
HT_CTLINN[1..0] HT_CADINP8 E5 AD4 HT_CADOUTP8 AB6 G6
[7] HT_CTLINN[1..0] HT_CADINN8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUTN8 [37] CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L [37]
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
HT_CADOUTP[15..0] HT_CADINP9 F3 AD5 HT_CADOUTP9 CPU_DBRDY G10
[7] HT_CADOUTP[15..0] HT_CADINN9 L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUTN9 CPU_TMS DBRDY CPU_DBREQ# R247 *300/F_4
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 AA9 TMS DBREQ_L E10 +1.5V
HT_CADOUTN[15..0] HT_CADINP10 G5 AB4 HT_CADOUTP10 CPU_TCK AC9 R246 300/F_4
[7] HT_CADOUTN[15..0] L0_CADIN_H10 L0_CADOUT_H10 TCK +1.5VSUS
HT_CADINN10 H5 AB3 HT_CADOUTN10 CPU_TRST# AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
[7] HT_CLKOUTP[1..0] HT_CADINN11 HT_CADOUTN11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 PV stage:add +1.8VSUS option R3114
HT_CLKOUTN[1..0] HT_CADINP12 K3 Y5 HT_CADOUTP12 CPUTEST23 AD7 J7
[7] HT_CLKOUTN[1..0] L0_CADIN_H12 L0_CADOUT_H12 TEST23 TEST28_H for Caspian CPU power leakage issue
HT_CADINN12 K4 W5 HT_CADOUTN12 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 H10 TEST18
C [7] HT_CTLOUTP[1..0] HT_CADINN13 HT_CADOUTN13 CPUTEST19 CPUTEST17 C
M5 L0_CADIN_L13 L0_CADOUT_L13 V3 G9 TEST19 TEST17 D7 T28
HT_CTLOUTN[1..0] HT_CADINP14 M3 V5 HT_CADOUTP14 E7 CPUTEST16
[7] HT_CTLOUTN[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T27
HT_CADINN14 M4 U5 HT_CADOUTN14 R245 510/F_4 CPUTEST25H E9 F7 CPUTEST15
L0_CADIN_L14 L0_CADOUT_L14 +1.5VSUS TEST25_H TEST15 T26
HT_CADINP15 N5 T4 HT_CADOUTP15 R241 510/F_4 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T29
HT_CADINN15 P5 T3 HT_CADOUTN15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 C3

en
HT_CLKINP0 HT_CLKOUTP0 CPUTEST20 TEST21 TEST7
J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 AF7 TEST20 TEST10 K8
HT_CLKINN0 J2 W1 HT_CLKOUTN0 CPUTEST24 AE7
HT_CLKINP1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUTP1 CPUTEST22 TEST24
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 AE8 TEST22 TEST8 C4
HT_CLKINN1 K5 Y3 HT_CLKOUTN1 CPUTEST12 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 R422 1K/F_4 CPUTEST27 TEST12
+1.5VSUS AF8 TEST27
HT_CTLINP0 N1 R2 HT_CTLOUTP0 C9 CPUTEST29H
L0_CTLIN_H0 L0_CTLOUT_H0 TEST29_H T30
HT_CTLINN0 P1 R3 HT_CTLOUTN0 R430 *300/F_4 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_CTLINN1 P4 R5 HT_CTLOUTN1 R250
L0_CTLIN_L1 L0_CTLOUT_L1
A3 RSVD1 RSVD10 H18 80.6/F_4
FOX PZ63826-284R-41F A5 RSVD2 RSVD9 H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 CPUTEST29L
RSVD3 RSVD8 T31
+1.5VSUS B5 D5
MLX 47296-4131 [3,4,5,6,37,40,42,43,44,46] +1.5VSUS RSVD4 RSVD7
+1.5V C1 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) [7,10,27,29,40,43] +1.5V RSVD5 RSVD6
+1.1V
[7,8,9,10,14,38,44] +1.1V
TYC 4-1903401-2 +2.5V S1G4
[42] +2.5V

id
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN

CNTR_VREF [4] +3V


C446 0.1u/10V_4
S1G4 Serial VID VFIX MODE VID Override Circuit
+3V R256 20K/F_4 R251 34.8K/F_4
B R262 B
CNTR_VREF
SVC SVD Voltage Output
4.7K_4
0 0 1.1V
2

Q35 *BSS138_NL/SOT23
0 1 1.0V
2

CPU_LDT_REQ#_CPU 1 3 R238 1K/F_4


+1.5VSUS

R462 *0_4
CPU_LDT_REQ# [9,11]
CPU_LDT_RST# 1
nf Q23
3 CPU_LDT_RST_HTPA#

BSS138_NL/SOT23
+1.5V

+1.5VSUS
R235

R240
*1K/F_4

1K/F_4
1
1
0
1
0.9V
0.8V
1

G1 +1.5V R237 *1K/F_4


The RS880 family does not support CLMC architecture *SHORT_PAD1 S1G4
CPU_SVC
The LDTREQ# connection from the CPU to ALLOW_LDTSTOP CPU_SVC [37]
for debug only CPU_SVD
CPU_SVD [37]
2

of the Northbridge is no longer required. CPU_PWRGD_SVID_REG


CPU_PWRGD_SVID_REG [11,37]
+1.5VSUS R231 *220_4
S1g4 does not support MEMHOT# R232 *220_4
R244 *220_4
3

+1.5VSUS R101 *10K_4


Co
S1G4
2

R100 *1K_4 Q12 2 CPUTEST24 R428 1K/F_4


+1.5VSUS
CPU_MEMHOT_L# 3 1
*MMBT3904
CPU_MEMHOT# [5,6,11]
[34] HWPG
Q8008
FDV301N HDT Connector CPUTEST23
CPUTEST20
CPUTEST22
R426
R427
1K/F_4
1K/F_4
R429 1K/F_4
C01 CPUTEST12 R188 1K/F_4
1

R417 *10K_4 R8191 1K_4 CPUTEST15 R227 *300/F_4


+1.5VSUS
1 2 CPUTEST14 R243 *300/F_4
+1.5VSUS R425 1K_4 3 4 CPUTEST19 R233 1K/F_4
2

A Q32 R8189 CPUTEST18 R230 1K/F_4 A


C01 CPU_DBREQ#
5 6
CPUTEST21
MMBT3904 C01 100K_6 7 8 R139 1K/F_4
CPU_THERMTRIP_L# 1 3 R155 *0_4 CPU_DBRDY 9 10
CPU_THERMTRIP# [12]
CPU_TCK 11 12 S1G4
R420 *10K_4 R309 *Short_4 CPU_TMS 13 14
+1.5VSUS SYS_SHDN# [4,36,43,44] CPU_TDI 15 16
+1.5VSUS R424 300_4 CPU_TRST# 17 18 PROJECT : ZR8
2

A62 Q31 CPU_TDO 19 20


D12 21 22
CPU_PROCHOT_L# 1 3 PM_THERM# [4,12,33]
+1.5VSUS
C398 *0.1u/10V_4 23 24 CPU_LDT_RST_HTPA# Quanta Computer Inc.
*MMBT3904 25
KEY
R138 0_4 Size Document Number Rev
CPU_PROCHOT# [11]
*HDT_CONN S1G4 HT,CTL I/F 1/3 1A
CN7
Date: Wednesday, May 27, 2009 Sheet 2 of 49
5 4 3 2 1
A B C D E

04
VDDR=> 0.9V support 1066 / 800 DDR
VDDR=>1.75A VDDR= >1.05V support 1333 / 1066 / 800 DDR

CPU_VDDR D01
[6] M_B_DQ[0..63]
Processor Memory Interface
+1.5VSUS CPU_VDDR U29B CPU_VDDR

PLACE THEM CLOSE TO +SMDDR_VREF


D10 VDDR1 MEM:CMD/CTRL/CLKVDDR5 W 10 C18 U29C
CPU WITHIN 1" C10 VDDR2 VDDR6 AC10 M_A_DQ[0..63] [5,46]
R415 B10 AB10 R189 MEM:DATA
0_4 VDDR3 VDDR7 *0_4 M_B_DQ0 M_A_DQ0
AD10 VDDR4 VDDR8 AA10 C11 MB_DATA0 MA_DATA0 G12
A10 R184 M_B_DQ1 A11 F12 M_A_DQ1
R432 39.2/F_4 M_ZP VDDR9 M_B_DQ2 MB_DATA1 MA_DATA1 M_A_DQ2
AF10 MEMZP *0_4 A14 MB_DATA2 MA_DATA2 H14
R431 39.2/F_4 M_ZN AE10 Y10 CPU_VTT_SENSE C15 D01 M_B_DQ3 B14 G14 M_A_DQ3
4 MEMZN VDDR_SENSE M_B_DQ4 MB_DATA3 MA_DATA3 M_A_DQ4 4
G11 MB_DATA4 MA_DATA4 H11
C660 H16 W 17 MEMVREF_CPU M_B_DQ5 E11 H12 M_A_DQ5
[5,46] M_A_RST# MA_RESET_L MEMVREF MB_DATA5 MA_DATA5
10U/6.3V_8 M_B_DQ6 D12 C13 M_A_DQ6
M_B_DQ7 MB_DATA6 MA_DATA6 M_A_DQ7
[46] M_A_ODT0 T19 MA0_ODT0 MB_RESET_L B18 M_B_RST# [6] A13 MB_DATA7 MA_DATA7 E13
S1G4 V22 M_B_DQ8 A15 H15 M_A_DQ8
[46] M_A_ODT1 MA0_ODT1 MB_DATA8 MA_DATA8
U21 W 26 M_B_DQ9 A16 E15 M_A_DQ9
[5] M_A1_ODT0 MA1_ODT0 MB0_ODT0 M_B_ODT0 [6] MB_DATA9 MA_DATA9
V19 W 23 C347 C346 M_B_DQ10 A19 E17 M_A_DQ10
[5] M_A1_ODT1 MA1_ODT1 MB0_ODT1 M_B_ODT1 [6] MB_DATA10 MA_DATA10
Y26 0.1u/10V_4 1000P/50V_4 M_B_DQ11 A20 H17 M_A_DQ11
MB1_ODT0 M_B_DQ12 MB_DATA11 MA_DATA11 M_A_DQ12
[46] M_A_CS#0 T20 MA0_CS_L0 C14 MB_DATA12 MA_DATA12 E14
U19 V26 M_B_DQ13 D14 F14 M_A_DQ13
[46] M_A_CS#1 MA0_CS_L1 MB0_CS_L0 M_B_CS#0 [6] MB_DATA13 MA_DATA13
U20 W 25 M_B_DQ14 C18 C17 M_A_DQ14
[5] M_A1_CS#0 MA1_CS_L0 MB0_CS_L1 M_B_CS#1 [6] MB_DATA14 MA_DATA14
V20 U22 M_B_DQ15 D18 G17 M_A_DQ15

l
[5] M_A1_CS#1 MA1_CS_L1 MB1_CS_L0 MB_DATA15 MA_DATA15
M_B_DQ16 D20 G18 M_A_DQ16
M_B_DQ17 MB_DATA16 MA_DATA16 M_A_DQ17
[5,46] M_A_CKE0 J22 MA_CKE0 MB_CKE0 J25 M_B_CKE0 [6] A21 MB_DATA17 MA_DATA17 C19
J20 H26 M_B_DQ18 D24 D22 M_A_DQ18
[5,46] M_A_CKE1 MA_CKE1 MB_CKE1 M_B_CKE1 [6] MB_DATA18 MA_DATA18
M_B_DQ19 C25 E20 M_A_DQ19
MB_DATA19 MA_DATA19

tia
N19 P22 M_B_DQ20 B20 E18 M_A_DQ20
[46] M_A_CLKP1 MA_CLK_H5 MB_CLK_H5 M_B_CLKP1 [6] MB_DATA20 MA_DATA20
N20 R22 M_B_DQ21 C20 F18 M_A_DQ21
[46] M_A_CLKN1 MA_CLK_L5 MB_CLK_L5 M_B_CLKN1 [6] MB_DATA21 MA_DATA21
E16 A17 M_B_DQ22 B24 B22 M_A_DQ22
[5] M_A_CLKP3 MA_CLK_H1 MB_CLK_H1 MB_DATA22 MA_DATA22
F16 A18 M_B_DQ23 C24 C23 M_A_DQ23
[5] M_A_CLKN3 MA_CLK_L1 MB_CLK_L1 MB_DATA23 MA_DATA23
Y16 AF18 M_B_DQ24 E23 F20 M_A_DQ24
[5] M_A_CLKP4 MA_CLK_H7 MB_CLK_H7 MB_DATA24 MA_DATA24
AA16 AF17 M_B_DQ25 E24 F22 M_A_DQ25
[5] M_A_CLKN4 MA_CLK_L7 MB_CLK_L7 MB_DATA25 MA_DATA25
P19 R26 M_B_DQ26 G25 H24 M_A_DQ26
[46] M_A_CLKP2 MA_CLK_H4 MB_CLK_H4 M_B_CLKP2 [6] MB_DATA26 MA_DATA26
P20 R25 M_B_DQ27 G26 J19 M_A_DQ27
[46] M_A_CLKN2 MA_CLK_L4 MB_CLK_L4 M_B_CLKN2 [6] MB_DATA27 MA_DATA27
M_B_DQ28 C26 E21 M_A_DQ28
M_A_A0 M_B_A0 M_B_DQ29 MB_DATA28 MA_DATA28 M_A_DQ29
N21 MA_ADD0 MB_ADD0 P24 D26 MB_DATA29 MA_DATA29 E22
M_A_A1 M20 N24 M_B_A1 M_B_DQ30 G23 H20 M_A_DQ30
M_A_A2 MA_ADD1 MB_ADD1 M_B_A2 M_B_DQ31 MB_DATA30 MA_DATA30 M_A_DQ31
N22 MA_ADD2 MB_ADD2 P26 G24 MB_DATA31 MA_DATA31 H22
M_A_A3 M19 N23 M_B_A3 M_B_DQ32 AA24 Y24 M_A_DQ32
M_A_A4 MA_ADD3 MB_ADD3 M_B_A4 M_B_DQ33 MB_DATA32 MA_DATA32 M_A_DQ33
3 M22 MA_ADD4 MB_ADD4 N26 AA23 MB_DATA33 MA_DATA33 AB24 3
M_A_A5 L20 L23 M_B_A5 M_B_DQ34 AD24 AB22 M_A_DQ34
M_A_A6 MA_ADD5 MB_ADD5 M_B_A6 M_B_DQ35 MB_DATA34 MA_DATA34 M_A_DQ35
M24 MA_ADD6 MB_ADD6 N25 AE24 MB_DATA35 MA_DATA35 AA21
M_A_A7 L21 L24 M_B_A7 M_B_DQ36 AA26 W 22 M_A_DQ36

en
M_A_A8 MA_ADD7 MB_ADD7 M_B_A8 M_B_DQ37 MB_DATA36 MA_DATA36 M_A_DQ37
L19 MA_ADD8 MB_ADD8 M26 AA25 MB_DATA37 MA_DATA37 W 21
M_A_A9 K22 K26 M_B_A9 M_B_DQ38 AD26 Y22 M_A_DQ38
M_A_A10 MA_ADD9 MB_ADD9 M_B_A10 M_B_DQ39 MB_DATA38 MA_DATA38 M_A_DQ39
R21 MA_ADD10 MB_ADD10 T26 AE25 MB_DATA39 MA_DATA39 AA22
M_A_A11 L22 L26 M_B_A11 M_B_DQ40 AC22 Y20 M_A_DQ40
M_A_A12 MA_ADD11 MB_ADD11 M_B_A12 M_B_DQ41 MB_DATA40 MA_DATA40 M_A_DQ41
K20 MA_ADD12 MB_ADD12 L25 AD22 MB_DATA41 MA_DATA41 AA20
M_A_A13 V24 W 24 M_B_A13 M_B_DQ42 AE20 AA18 M_A_DQ42
M_A_A14 MA_ADD13 MB_ADD13 M_B_A14 M_B_DQ43 MB_DATA42 MA_DATA42 M_A_DQ43
K24 MA_ADD14 MB_ADD14 J23 AF20 MB_DATA43 MA_DATA43 AB18
M_A_A15 K19 J24 M_B_A15 M_B_DQ44 AF24 AB21 M_A_DQ44
[5,46] M_A_A[0..15] MA_ADD15 MB_ADD15 M_B_A[0..15] [6] MB_DATA44 MA_DATA44
+0.75V_DDR_VTT +0.75V_DDR_VTT M_B_DQ45 AF23 AD21 M_A_DQ45
+SMDDR_VREF M_B_DQ46 MB_DATA45 MA_DATA45 M_A_DQ46
[5,46] M_A_BANK0 R20 MA_BANK0 MB_BANK0 R24 M_B_BANK0 [6] [5,6,40] +SMDDR_VREF AC20 MB_DATA46 MA_DATA46 AD19
R23 U26 [43] CPU_VDDR CPU_VDDR M_B_DQ47 AD20 Y18 M_A_DQ47
[5,46] M_A_BANK1 MA_BANK1 MB_BANK1 M_B_BANK1 [6] MB_DATA47 MA_DATA47
J21 J26 [2,4,5,6,37,40,42,43,44,46] +1.5VSUS +1.5VSUS M_B_DQ48 AD18 AD17 M_A_DQ48
[5,46] M_A_BANK2 MA_BANK2 MB_BANK2 M_B_BANK2 [6] MB_DATA48 MA_DATA48
M_B_DQ49 AE18 W 16 M_A_DQ49
M_B_DQ50 MB_DATA49 MA_DATA49 M_A_DQ50
[5,46] M_A_RAS# R19 MA_RAS_L MB_RAS_L U25 M_B_RAS# [6] AC14 MB_DATA50 MA_DATA50 W 14
T22 U24 M_B_DQ51 AD14 Y14 M_A_DQ51
[5,46] M_A_CAS# MA_CAS_L MB_CAS_L M_B_CAS# [6] MB_DATA51 MA_DATA51
T24 U23 M_B_DQ52 AF19 Y17 M_A_DQ52

id
[5,46] M_A_WE# MA_W E_L MB_W E_L M_B_WE# [6] MB_DATA52 MA_DATA52
M_B_DQ53 AC18 AB17 M_A_DQ53
M_B_DQ54 MB_DATA53 MA_DATA53 M_A_DQ54
AF16 MB_DATA54 MA_DATA54 AB15
SOCKET_638_PIN M_B_DQ55 AF15 AD15 M_A_DQ55
M_B_DQ56 MB_DATA55 MA_DATA55 M_A_DQ56
AF13 MB_DATA56 MA_DATA56 AB13
CPU_VDDR M_B_DQ57 AC12 AD13 M_A_DQ57
Place close to socket M_B_DQ58 AB11
MB_DATA57 MA_DATA57
Y12 M_A_DQ58
M_B_DQ59 MB_DATA58 MA_DATA58 M_A_DQ59
Y11 MB_DATA59 MA_DATA59 W 11
M_B_DQ60 AE14 AB14 M_A_DQ60
M_B_DQ61 MB_DATA60 MA_DATA60 M_A_DQ61
AF14 MB_DATA61 MA_DATA61 AA14
C439 C282 C442 C281 C278 C279 C276 C277 M_B_DQ62 AF11 AB12 M_A_DQ62
2
4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.22u/6.3V_4 0.22u/6.3V_4 0.22u/6.3V_4 0.22u/6.3V_4 M_B_DQ63 MB_DATA62 MA_DATA62 M_A_DQ63 2
[6] M_B_DM[0..7] AD11 MB_DATA63 MA_DATA63 AA12 M_A_DM[0..7] [5,46]
CPU_VDDR
nf M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
A12
B16
A22
E25
AB26
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
E12
C15
E19
F24
AC24
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
C431 C434 C345 C275 C427 C435 C437 C430 M_B_DM5 AE22 Y19 M_A_DM5
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 M_B_DM6 MB_DM5 MA_DM5 M_A_DM6
AC16 MB_DM6 MA_DM6 AB16
M_B_DM7 AD12 Y13 M_A_DM7
MB_DM7 MA_DM7

[6] M_B_DQSP0 C12 MB_DQS_H0 MA_DQS_H0 G13 M_A_DQSP0 [5,46]


[6] M_B_DQSN0 B12 MB_DQS_L0 MA_DQS_L0 H13 M_A_DQSN0 [5,46]
[6] M_B_DQSP1 D16 MB_DQS_H1 MA_DQS_H1 G16 M_A_DQSP1 [5,46]
[6] M_B_DQSN1 C16 MB_DQS_L1 MA_DQS_L1 G15 M_A_DQSN1 [5,46]
[6] M_B_DQSP2 A24 MB_DQS_H2 MA_DQS_H2 C22 M_A_DQSP2 [5,46]
Co
[6] M_B_DQSN2 A23 MB_DQS_L2 MA_DQS_L2 C21 M_A_DQSN2 [5,46]
+1.5VSUS R201 0_4 F26 G22
[6] M_B_DQSP3 MB_DQS_H3 MA_DQS_H3 M_A_DQSP3 [5,46]
E26 G21
+3VPCU Reserved for AMD suggest [6] M_B_DQSN3
AC25
MB_DQS_L3 MA_DQS_L3
AD23
M_A_DQSN3 [5,46]
[6] M_B_DQSP4 MB_DQS_H4 MA_DQS_H4 M_A_DQSP4 [5,46]
C339 AC26 AC23
[6] M_B_DQSN4 MB_DQS_L4 MA_DQS_L4 M_A_DQSN4 [5,46]
*.1u_4 AF21 AB19
[6] M_B_DQSP5 MB_DQS_H5 MA_DQS_H5 M_A_DQSP5 [5,46]
R206 AF22 AB20
[6] M_B_DQSN5 MB_DQS_L5 MA_DQS_L5 M_A_DQSN5 [5,46]
1K/F_4 AE16 Y15
[6] M_B_DQSP6 MB_DQS_H6 MA_DQS_H6 M_A_DQSP6 [5,46]
[6] M_B_DQSN6 AD16 MB_DQS_L6 MA_DQS_L6 W 15 M_A_DQSN6 [5,46]
5

U14 AF12 W 12
[6] M_B_DQSP7 MB_DQS_H7 MA_DQS_H7 M_A_DQSP7 [5,46]
3 + [6] M_B_DQSN7 AE12 MB_DQS_L7 MA_DQS_L7 W 13 M_A_DQSN7 [5,46]
1 R197 *10_4 MEMVREF_CPU
4 -
2

1 *OPA343NA/3K SOCKET_638_PIN 1
R204 C352
2

1K/F_4 *0.47u/10V_4 R182


1

*10K/F_4

R194 *0_4

R193 *0_4 PROJECT : ZR8


Quanta Computer Inc.
Size Document Number Rev
S1G4 DDRIII MEMORY I/F 2/3 1A

Date: Wednesday, May 27, 2009 Sheet 3 of 49


A B C D E
5 4 3 2 1

+VCORE U29E +VCORE


AA4
AA11
AA13
AA15
U29F

VSS1
VSS2
VSS3
VSS66
VSS67
VSS68
J6
J8
J10
J12
+VCORE
BOTTOM SIDE DECOUPLING
05
VSS4 VSS69
G4 P8 AA17 J14
H2
VDD_1
VDD_2
VDD_24
VDD_25 P10 B2-TEST AA19
VSS5
VSS6
VSS70
VSS71 J16
J9 R4 PC54 AB2 J18
VDD_3 VDD_26 + *330u/2V_7343 VSS7 VSS72 C360 C351 C371 C413 C354 C355 C356
J11 VDD_4 VDD_27 R7 AB7 VSS8 VSS73 K2
J13 R9 AB9 K7 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.01U/25V_4 180P/50V_4
VDD_5 VDD_28 VSS9 VSS74
D
J15 VDD_6 VDD_29 R11 AB23 VSS10 VSS75 K9 D
K6 VDD_7 VDD_30 T2 AB25 VSS11 VSS76 K11
K10 VDD_8 VDD_31 T6 AC11 VSS12 VSS77 K13
K12 VDD_9 VDD_32 T8 Place under CPU bracket side. AC13 VSS13 VSS78 K15
K14 T10 AC15 K17 +VCORE
VDD_10 VDD_33 VSS14 VSS79
L4 VDD_11 VDD_34 T12 AC17 VSS15 VSS80 L6
L7 VDD_12 VDD_35 T14 AC19 VSS16 VSS81 L8
L9 VDD_13 VDD_36 U7 AC21 VSS17 VSS82 L10
L11 VDD_14 VDD_37 U9 AD6 VSS18 VSS83 L12
L13 U11 AD8 L14 C357 C388 C364 C399 C370 C378 C383 C368
VDD_15 VDD_38 VSS19 VSS84 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.01U/25V_4 180P/50V_4 0.01U/25V_4
L15 VDD_16 VDD_39 U13 AD25 VSS20 VSS85 L16
M2 VDD_17 VDD_40 U15 AE11 VSS21 VSS86 L18
M6 V6 AE13 M7

l
VDD_18 VDD_41 VSS22 VSS87
M8 VDD_19 VDD_42 V8 AE15 VSS23 VSS88 M9
M10 VDD_20 VDD_43 V10 AE17 VSS24 VSS89 AC6
N7 V12 AE19 M17 CPU_VDDNB_CORE +1.5VSUS
CPU_VDDNB_CORE VDD_21 VDD_44 VSS25 VSS90
N9 VDD_22 VDD_45 V14 AE21 VSS26 VSS91 N4

tia
N11 VDD_23 VDD_46 W4 AE23 VSS27 VSS92 N8
Y2 B4 N10
3A K16 VDDNB_1
VDD_47
VDD_48 AC4
+1.5VSUS
B6
VSS28
VSS29
VSS93
VSS94 N16
M16 AD2 B8 N18 C358 C406 C366 C415 C372 C367 C404 C369 C396
VDDNB_2 VDD_49 VSS30 VSS95 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 0.22u/6.3V_4 0.22u/6.3V_4 180P/50V_4 180P/50V_4
P16 VDDNB_3 B9 VSS31 VSS96 P2
+1.5VSUS T16 Y25 B11 P7
VDDNB_4 VDDIO27 VSS32 VSS97
V16 V25 B13 P9
VDDNB_5 VDDIO26
VDDIO25 V23 1.5V@2A B15
VSS33
VSS34
VSS98
VSS99 P11
H25 VDDIO1 VDDIO24 V21 B17 VSS35 VSS100 P17
J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8
K18 VDDIO3 VDDIO22 U17 B21 VSS37 VSS102 R10
K21 VDDIO4 VDDIO21 T25 B23 VSS38 VSS103 R16
K23 VDDIO5 VDDIO20 T23 B25 VSS39 VSS104 R18
C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C
L17 T18 D8 T9
M18
VDDIO7
VDDIO8
VDDIO18
VDDIO17 R17 D9
VSS41
VSS42
VSS106
VSS107 T11 DECOUPLING BETWEEN PROCESSOR AND DIMMs
M21 P25 D11 T13

en
VDDIO9 VDDIO16 VSS43 VSS108
M23 P23 D13 T15
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D15
VSS44
VSS45
VSS109
VSS110 T17 PLACE CLOSE TO PROCESSOR AS POSSIBLE
N17 VDDIO12 VDDIO13 P18 D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
D21 U8 +1.5VSUS
SOCKET_638_PIN VSS48 VSS113
D23 VSS49 VSS114 U10
D25 VSS50 VSS115 U12
+1.5VSUS E4 U14
VSS51 VSS116
F2 VSS52 VSS117 U16
F11 U18 C394 C425 C426 C405 C384 C359
VSS53 VSS118 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.22u/6.3V_4 0.22u/6.3V_4
F13 VSS54 VSS119 V2
F15 VSS55 VSS120 V7
R421 R423 R252 F17 V9
1K/F_4 1K/F_4 1K/F_4 VSS56 VSS121 +1.5VSUS
[2] CNTR_VREF F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
F23 V15

id
VSS59 VSS124
2

F25 VSS60 VSS125 V17


Q19 H7 W6
CPU_SMBCLK VSS61 VSS126 C377 C361 C408 C407 C385
3 1 CPU_SIC [2] H9 VSS62 VSS127 Y21
H21 Y23 0.22u/6.3V_4 0.22u/6.3V_4 0.01U/25V_4 0.01u/25V_4 180P/50V_4
VSS63 VSS128
2

BSS138_NL/SOT23 C17 H23 N6


Q18 VSS64 VSS129
J4 VSS65
CPU_SMBDATA 3 1 CPU_SID [2]
SOCKET_638_PIN
2

BSS138_NL/SOT23
Q17
B B
PM_THERM# 3 1
C17 CPU_ALERT [2]

PROCESSOR POWER AND GROUND


BSS138_NL/SOT23

+3V
nf
+3V R254
*200/F_6
C17

D05 R267
*10K/F_4 D05
Co
C450
C17 *0.1u/10V_4 SYS_SHDN# [2,36,43,44]
U16

[34] CPU_SMBCLK CPU_SMBCLK 8 1 D05


SCLK VCC H_THRMDA [2]
CPU_SMBDATA C344
C02
[34] CPU_SMBDATA 7 SDA DXP 2
*1000P/50V_4 D14
3

R479 6 3 *CH501H-40PT
*0_4 ALERT# DXN PWROK_EC_3904
H_THRMDC [2] 2 2 1 PWROK_EC [15,34]
[2,12,33] PM_THERM# PM_THERM# 4 5
OVERT# GND Q21
1

A C17 MSOP *MMBT3904 R255 *10K/F_4 A


+3V
*G786P8
SMBALERT#
3

R264 *10K/F_4
PROJECT : ZR8
Q22 2
*2N7002K
TEMP_FAIL [17]
Quanta Computer Inc.
ADD VGA TEMP_ FAIL function Size Document Number Rev
M93 is active Hi S1G4 PWR & GND 3/3 1A
1

Date: Wednesday, May 27, 2009 Sheet 4 of 49

5 4 3 2 1
5 4 3 2 1

+1.5VSUS
M_A_DQ[63:0] [3,46] CN15B
[3,46] M_A_A[15:0] CN15A
75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
M_A_A3 A2 DQ2 M_A_DQ3 VDD4 VSS19
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 +1.5VSUS 88 60
M_A_A5 A4 DQ4 M_A_DQ5 VDD6 VSS21
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
M_A_A8 A7 DQ7 M_A_DQ8 R589 VDD9 VSS24
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ9 1K/F_4 105 72
M_A_A10 A9 DQ9 M_A_DQ10 +0.75VSMVREF_SUSA VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
M_A_A12 A11 DQ11 M_A_DQ12 VDD13 VSS28
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
M_A_A14 A13 DQ13 M_A_DQ14 VDD15 VSS30
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 124 VDD18 VSS33 144
M_A_BANK0 109 41 M_A_DQ17 145
M_A_BANK1 BA0 DQ17 M_A_DQ18 VSS34
108 BA1 DQ18 51 +3V 199 VDDSPD VSS35 150

l
M_A_BANK2 79 53 M_A_DQ19 151
[3,46] M_A_BANK[0..2] BA2 DQ19 VSS36
114 40 M_A_DQ20 R590 77 155
[3] M_A1_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 1K/F_4 122 156
[3] M_A1_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
[3] M_A_CLKP3 CK0 DQ22 NCTEST VSS39

tia
103 52 M_A_DQ23 162
[3] M_A_CLKN3 CK0# DQ23 VSS40
102 57 M_A_DQ24 MEMHOT_MA# 198 167
[3] M_A_CLKP4 CK1 DQ24 [46] MEMHOT_MA# EVENT# VSS41
104 59 M_A_DQ25 30 168
[3] M_A_CLKN4 CK1# DQ25 [3,46] M_A_RST# RESET# VSS42
R585 *Short_4 R0_CKE0 73 67 M_A_DQ26 172
[3,46] M_A_CKE0 CKE0 DQ26 VSS43
R588 *Short_4 R0_CKE1 74 69 M_A_DQ27 173
[3,46] M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ28 +0.75VSMVREF_SUSA 1 178
[3,46] M_A_CAS# CAS# DQ28 VREF_DQ VSS45
A08 [3,46] M_A_RAS# 110 58 M_A_DQ29 +VREF_CA_A 126 179
RAS# DQ29 M_A_DQ30 VREF_CA VSS46
[3,46] M_A_WE# 113 WE# DQ30 68 VSS47 184
R198 10K_4 DIMM0_SA0 197 70 M_A_DQ31 185
R199 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ32 VSS48
+3V 201 SA1 DQ32 129 2 VSS1 VSS49 189
202 131 M_A_DQ33 3 190
[6,12,26,27,46] PCLK_SMB SCL DQ33 M_A_DQ34 VSS2 VSS50
200 141 8 195

(204P)
[6,12,26,27,46] PDAT_SMB SDA DQ34 M_A_DQ35 +1.5VSUS VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ36 13
[3] M_A1_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
[3] M_A1_ODT1 ODT1 DQ37 +SMDDR_VREF +VREF_CA_A VSS6

en
140 M_A_DQ38 19
M_A_DM0 DQ38 M_A_DQ39 R257 VSS7
11 DM0 DQ39 142 20 VSS8
+1.5VSUS M_A_DM1 28 147 M_A_DQ40 *2K/F_4 25
M_A_DM2 DM1 DQ40 M_A_DQ41 VSS9
46 149 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ43 R203 *Short_4 32
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS12
D08 M_A_DM6
153 DM5 DQ44 146
M_A_DQ45
37 VSS13 GND 205
170 DM6 DQ45 148 38 VSS14 GND 206
M_A_DM7 187 158 M_A_DQ46 R258 43
[3,46] M_A_DM[7:0] DM7 DQ46 VSS15
R584 R259 160 M_A_DQ47 *2K/F_4
*10K_4 *10K_4 M_A_DQSP0 DQ47 M_A_DQ48
12 DQS0 DQ48 163
M_A_DQSP1 29 165 M_A_DQ49 DDR3-DIMM0_H=4.0_RVS
M_A_DQSP2 DQS1 DQ49 M_A_DQ50
47 DQS2 DQ50 175
R0_CKE0 M_A_DQSP3 64 177 M_A_DQ51
R0_CKE1 M_A_DQSP4 DQS3 DQ51 M_A_DQ52
137 164

id
M_A_DQSP5 DQS4 DQ52 M_A_DQ53
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ54
M_A_DQSP7 DQS6 DQ54 M_A_DQ55
[3,46] M_A_DQSP[7:0]
M_A_DQSN0
188 DQS7 DQ55 176
M_A_DQ56
A51
10 DQS#0 DQ56 181
M_A_DQSN1 27 183 M_A_DQ57
M_A_DQSN2 DQS#1 DQ57 M_A_DQ58
45 DQS#2 DQ58 191
M_A_DQSN3 62 193 M_A_DQ59
M_A_DQSN4 DQS#3 DQ59 M_A_DQ60
135 DQS#4 DQ60 180
M_A_DQSN5 152 182 M_A_DQ61 +1.5VSUS R123 *2.2K_4
M_A_DQSN6 DQS#5 DQ61 M_A_DQ62
B 169 DQS#6 DQ62 192 B
M_A_DQSN7 186 194 M_A_DQ63
[3,46] M_A_DQSN[7:0] DQS#7
nf
DQ63

2
+1.5VSUS R122 *2.2K_4 Q10
*MMBT3904
MEMHOT_MA# 1 3 CPU_MEMHOT# [2,6,11]
DDR3-DIMM0_H=4.0_RVS
D12

Place these Caps near So-Dimm0.

+1.5VSUS
Co
+VREF_CA_A +0.75VSMVREF_SUSA
C400 C379 C401 C686 C417
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4

C390 C348 C260 C825 C826

.1u/16V_4 .1u/16V_4

10u/6.3V_6 C411 C380 C416 C402 C455 2.2u/6.3V_6 2.2u/6.3V_6


10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4

A A
+0.75V_DDR_VTT

C829
C224
1U/6.3V_4
C9224
1U/6.3V_4 10u/6.3V_6 PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
DDR2 SODIMMS: A/B CHANNEL 1A

Date: Wednesday, May 27, 2009 Sheet 5 of 49


5 4 3 2 1
5 4 3 2 1

[3] M_B_A[15:0] M_B_DQ[63:0] [3] +1.5VSUS


CN25A CN25B
M_B_A0 98 5 M_B_DQ0 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
M_B_A3 A2 DQ2 M_B_DQ3 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ4 +1.5VSUS 87 55
M_B_A5 A4 DQ4 M_B_DQ5 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 R591 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9 1K/F_4
2.48A 100
VDD9 VSS24
71
D

M_B_A10 A9 DQ9 M_B_DQ10 +0.75VSMVREF_SUSB VDD10 VSS25


107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

PC2100 DDR3 SDRAM SO-DIMM


84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ16

PC2100 DDR3 SDRAM SO-DIMM


DQ16 39 123 VDD17 VSS32 139
M_B_BANK0 109 41 M_B_DQ17 124 144
M_B_BANK1 BA0 DQ17 M_B_DQ18 VDD18 VSS33
108 BA1 DQ18 51 VSS34 145

l
M_B_BANK2 79 53 M_B_DQ19 199 150
[3] M_B_BANK[0..2] BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 R592 151
[3] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 1K/F_4 77 155
[3] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
[3] M_B_CLKP1 CK0 DQ22 NC2 VSS38

tia
103 52 M_B_DQ23 125 161
[3] M_B_CLKN1 CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 162
[3] M_B_CLKP2 CK1 DQ24 VSS40
104 59 M_B_DQ25 MEMHOT_MB# 198 167
[3] M_B_CLKN2 CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ26 30 168
[3] M_B_CKE0 CKE0 DQ26 [3] M_B_RST# RESET# VSS42
74 69 M_B_DQ27 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
A08 115 56 M_B_DQ28 173
[3] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +0.75VSMVREF_SUSB 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ30 +VREF_CA_B 126 179
[3] M_B_WE# WE# DQ30 VREF_CA VSS46
R131 10K_4 DIMM1_SA0 197 70 M_B_DQ31 184
+3V SA0 DQ31 VSS47
R130 10K_4 DIMM1_SA1 201 129 M_B_DQ32 185
SA1 DQ32 M_B_DQ33 VSS48
202 SCL DQ33 131 2 VSS1 VSS49 189
[5,12,26,27,46] PCLK_SMB 200 141 M_B_DQ34 3 190
[5,12,26,27,46] PDAT_SMB SDA DQ34 M_B_DQ35 +1.5VSUS VSS2 VSS50
143 8 195

(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
[3] M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
[3] M_B_ODT1 ODT1 DQ37 +SMDDR_VREF +VREF_CA_B VSS5

en
140 M_B_DQ38 14
M_B_DM0 DQ38 M_B_DQ39 R118 VSS6
11 DM0 DQ39 142 19 VSS7
M_B_DM1 28 147 M_B_DQ40 *2K/F_4 20
M_B_DM2 DM1 DQ40 M_B_DQ41 VSS8
46 149 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ42 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 R117 *Short_4 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 R110 VSS13 GND
[3] M_B_DM[7:0] 187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 *2K/F_4 43
M_B_DQSP0 DQ47 M_B_DQ48 VSS15
12 DQS0 DQ48 163
M_B_DQSP1 29 165 M_B_DQ49
M_B_DQSP2 DQS1 DQ49 M_B_DQ50
47 DQS2 DQ50 175 DDR3-DIMM1_H=4.0_Standard
M_B_DQSP3 64 177 M_B_DQ51
M_B_DQSP4 DQS3 DQ51 M_B_DQ52
137 164

id
M_B_DQSP5 DQS4 DQ52 M_B_DQ53
M_B_DQSP6
154 DQS5 DQ53 166
M_B_DQ54
A50
171 DQS6 DQ54 174
M_B_DQSP7 188 176 M_B_DQ55
[3] M_B_DQSP[7:0]
M_B_DQSN0 10
DQS7 DQ55
181 M_B_DQ56
2DIMM--->P/N:DGMK4000109
M_B_DQSN1 DQS#0 DQ56 M_B_DQ57 R202 *2.2K_4
27 DQS#1 DQ57 183 +1.5VSUS
M_B_DQSN2 45 191 M_B_DQ58
DQS#2 DQ58

2
M_B_DQSN3 62 193 M_B_DQ59 R195 *2.2K_4 Q14
M_B_DQSN4 DQS#3 DQ59 M_B_DQ60 *MMBT3904
135 DQS#4 DQ60 180
M_B_DQSN5 152 182 M_B_DQ61 MEMHOT_MB# 1 3
DQS#5 DQ61 CPU_MEMHOT# [2,5,11]
B M_B_DQSN6 169 192 M_B_DQ62 B
M_B_DQSN7 DQS#6 DQ62 M_B_DQ63
186 194 D12
[3] M_B_DQSN[7:0] DQS#7

DDR3-DIMM1_H=4.0_Standard
nf
DQ63

+1.5VSUS Place these Caps near So-Dimm1.


+VREF_CA_B +0.75VSMVREF_SUSB
C409 C690 C821 C689 C820
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
Co
C817 C230 C259 C828 C827

10u/6.3V_6 .1u/16V_4 2.2u/6.3V_6 .1u/16V_4 2.2u/6.3V_6

C819 C818 C822 C418 C454


10u/6.3V_6 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4

+0.75V_DDR_VTT

A C8158 C231 C830 A


1u/6.3V_4 1u/6.3V_4
10u/6.3V_6

PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
DDR2 SODIMMS: A/B CHANNEL 1A

Date: Wednesday, May 27, 2009 Sheet 6 of 49


5 4 3 2 1
5 4 3 2 1

U28A

SIDE PORT
11/4
HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
Y25
Y24
V22
V23
V25
V24
U24
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
D24
D25
E24
E25
F24
F25
F23
HT_CADINP0
HT_CADINN0
HT_CADINP1
HT_CADINN1
HT_CADINP2
HT_CADINN2
HT_CADINP3
HT_CADOUTP[15..0]

HT_CADOUTN[15..0]

HT_CLKOUTP[1..0]
HT_CADOUTP[15..0]

HT_CADOUTN[15..0]

HT_CLKOUTP[1..0]
[2]

[2]
[2]
08
HT_CADOUTN3 HT_RXCAD3P HT_TXCAD3P HT_CADINN3 HT_CLKOUTN[1..0]
U25 HT_RXCAD3N HT_TXCAD3N F22 HT_CLKOUTN[1..0] [2]
HT_CADOUTP4 T25 H23 HT_CADINP4
HT_CADOUTN4 HT_RXCAD4P HT_TXCAD4P HT_CADINN4 HT_CTLOUTP[1..0]
T24 HT_RXCAD4N HT_TXCAD4N H22 HT_CTLOUTP[1..0] [2]
HT_CADOUTP5 P22 J25 HT_CADINP5

HYPER TRANSPORT CPU I/F


HT_CADOUTN5 HT_RXCAD5P HT_TXCAD5P HT_CADINN5 HT_CTLOUTN[1..0]
P23 HT_RXCAD5N HT_TXCAD5N J24 HT_CTLOUTN[1..0] [2]
+1.5V_MEM_VDDQ +1.5V_MEM_VDDQ HT_CADOUTP6 P25 K24 HT_CADINP6
D
HT_CADOUTN6 HT_RXCAD6P HT_TXCAD6P HT_CADINN6 HT_CADINP[15..0] D
P24 HT_RXCAD6N HT_TXCAD6N K25 HT_CADINP[15..0] [2]
HT_CADOUTP7 N24 K23 HT_CADINP7
HT_CADOUTN7 HT_RXCAD7P HT_TXCAD7P HT_CADINN7 HT_CADINN[15..0]
N25 HT_RXCAD7N HT_TXCAD7N K22 HT_CADINN[15..0] [2]
HT_CADOUTP8 AC24 F21 HT_CADINP8 HT_CLKINP[1..0]
C9788 R599 C9789 R600 HT_CADOUTN8 HT_RXCAD8P HT_TXCAD8P HT_CADINN8 HT_CLKINP[1..0] [2]
AC25 HT_RXCAD8N HT_TXCAD8N G21
SIDE@1K/F_4 SIDE@1K/F_4 HT_CADOUTP9 AB25 G20 HT_CADINP9 HT_CLKINN[1..0]
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 HT_CADOUTN9 HT_RXCAD9P HT_TXCAD9P HT_CADINN9 HT_CLKINN[1..0] [2]
AB24 HT_RXCAD9N HT_TXCAD9N H21
HT_CADOUTP10 AA24 J20 HT_CADINP10 HT_CTLINP[1..0]
HT_CADOUTN10 HT_RXCAD10P HT_TXCAD10P HT_CADINN10 HT_CTLINP[1..0] [2]
AA25 HT_RXCAD10N HT_TXCAD10N J21
SPM_VREFDQ SPM_VREFCA HT_CADOUTP11 Y22 J18 HT_CADINP11 HT_CTLINN[1..0]
HT_CADOUTN11 HT_RXCAD11P HT_TXCAD11P HT_CADINN11 HT_CTLINN[1..0] [2]
Y23 K17

l
HT_CADOUTP12 HT_RXCAD11N HT_TXCAD11N HT_CADINP12
W 21 HT_RXCAD12P HT_TXCAD12P L19
C9790 R601 C9791 R602 HT_CADOUTN12 W 20 J19 HT_CADINN12
HT_CADOUTP13 HT_RXCAD12N HT_TXCAD12N HT_CADINP13
SIDE@1K/F_4 SIDE@1K/F_4 V21 HT_RXCAD13P HT_TXCAD13P M19
SIDE@0.1u/10V_4 SIDE@0.1u/10V_4 HT_CADOUTN13 V20 L18 HT_CADINN13 signals RS880 RX880
HT_RXCAD13N HT_TXCAD13N

tia
HT_CADOUTP14 U20 M21 HT_CADINP14
HT_CADOUTN14 HT_RXCAD14P HT_TXCAD14P HT_CADINN14
U21 HT_RXCAD14N HT_TXCAD14N P21
HT_CADOUTP15 U19 P18 HT_CADINP15 HT_TXCALP
HT_CADOUTN15 HT_RXCAD15P HT_TXCAD15P HT_CADINN15
U18 HT_RXCAD15N HT_TXCAD15N M18 Ra Ra
301 ohm 1% 1.21k ohm 1%
HT_CLKOUTP0 T22 H24 HT_CLKINP0 HT_TXCALN
HT_CLKOUTN0 HT_RXCLK0P HT_TXCLK0P HT_CLKINN0
T23 HT_RXCLK0N HT_TXCLK0N H25
HT_CLKOUTP1 AB23 L21 HT_CLKINP1
HT_CLKOUTN1 HT_RXCLK1P HT_TXCLK1P HT_CLKINN1
AA22 HT_RXCLK1N HT_TXCLK1N L20 HT_RXCALP
Rb Rb
U39 HT_CTLOUTP0 M22 M24 HT_CTLINP0 301 ohm 1% 1.21k ohm 1%
HT_CTLOUTN0 HT_RXCTL0P HT_TXCTL0P HT_CTLINN0
M23 HT_RXCTL0N HT_TXCTL0N M25 HT_RXCALN
SPM_VREFCA M9 E4 SPM_DQ5 HT_CTLOUTP1 R21 P19 HT_CTLINP1
SPM_VREFDQ H2 VREFCA DQL0 SPM_DQ3 HT_CTLOUTN1 HT_RXCTL1P HT_TXCTL1P HT_CTLINN1
C
VREFDQ DQL1 F8 Ra R20 HT_RXCTL1N HT_TXCTL1N R18 Rb C
F3 SPM_DQ4
SPM_A0 DQL2 SPM_DQ0 R183 301/F_4 HT_RXCALP HT_TXCALP R192 301/F_4
N4 A0 DQL3 F9 C23 HT_RXCALP HT_TXCALP B24 RES CHIP 1.21K 1/16W +-1%(0402)
SPM_A1 P8 H4 SPM_DQ6 HT_RXCALN A24 B25 HT_TXCALN P/N : CS21212FB18

en
SPM_A2 A1 DQL4 SPM_DQ1 HT_RXCALN HT_TXCALN
P4 A2 DQL5 H9
SPM_A3 N3 G3 SPM_DQ7 RS880M_A11
SPM_A4 A3 DQL6 SPM_DQ2
P9 A4 DQL7 H8
SPM_A5 P3
SPM_A6 A5
R9 A6
SPM_A7 R3 D8 SPM_DQ14 +1.8V
A7 DQU0 [9,10,15,24,37,42,43,44] +1.8V
SPM_A8 T9 C4 SPM_DQ9 +1.1V
SPM_A9 R4
A8
A9
DQU1
DQU2 C9 SPM_DQ15 This block is for UMA only , Discrete can remove all component [2,8,9,10,14,38,44] +1.1V
SPM_A10 L8 C3 SPM_DQ8
SPM_A11 A10/AP DQU3 SPM_DQ10 U28D +1.5V_MEM_VDDQ
R8 A11 DQU4 A8
SPM_A12 N8 A3 SPM_DQ11 PAR 4 OF 6
SPM_A13 A12/BC DQU5 SPM_DQ13 SPM_A0 SPM_DQ0
T4 A13 DQU6 B9 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
T8 A4 SPM_DQ12 SPM_A1 AE16 AA20 SPM_DQ1
A14 DQU7 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2
M8 A15 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
+1.5V_MEM_VDDQ SPM_A3 AE15 Y19 SPM_DQ3
SPM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) SPM_DQ4 C9792 R605
AA12 V17

id
SPM_BA0 SPM_A5 MEM_A4(NC) MEM_DQ4(NC) SPM_DQ5
M3 BA0 VDD#B3 B3 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17 SIDE@1K/F_4
SPM_BA1 N9 D10 A09 SPM_A6 AB14 AA15 SPM_DQ6 SIDE@0.1u/10V_4
SPM_BA2 BA1 VDD#D10 SPM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) SPM_DQ7
M4 BA2 VDD#G8 G8 AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
K3 SPM_A8 AD13 AC20 SPM_DQ8
VDD#K3 SPM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) SPM_DQ9 SPM_VREF1
VDD#K9 K9 AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

SBD_MEM/DVO_I/F
N2 SPM_A10 AC16 AE22 SPM_DQ10
SPM_CLKP VDD#N2 SPM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) SPM_DQ11
J8 CK VDD#N10 N10 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
R593 *SIDE@100/F_4 SPM_CLKN K8 R2 SPM_A12 AC14 AB20 SPM_DQ12 C9793 R606
SPM_CKE CK VDD#R2 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13
K10 CKE VDD#R10 R10 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22 SP@1K/F_4
+1.5V_MEM_VDDQ AC22 SPM_DQ14 SIDE@0.1u/10V_4
B
SPM_BA0 MEM_DQ14/DVO_D10(NC) SPM_DQ15 B
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21 R606
SPM_ODT K2 A2 SPM_BA1 AE17
ODT VDDQ#A2 MEM_BA1(NC) W/O side port
SPM_CS#
SPM_RAS#
SPM_CAS#
SPM_WE#
L3
J4
K4
L4
CS
RAS
CAS
WE
VDDQ#A9
VDDQ#C2
VDDQ#C10
VDDQ#D3
VDDQ#E10
A9
C2
C10
D3
E10
nf SPM_BA2

SPM_RAS#
SPM_CAS#
SPM_WE#
AD17

W 12
Y12
AD18
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_W Eb(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W 18
AD20
AE21
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
A41
-->change to 0 Ohm
CS00002JB38

F2 SPM_CS# AB13 W 17 SPM_DM0


SPM_DQS0P VDDQ#F2 SPM_CKE MEM_CSb(NC) MEM_DM0(NC) SPM_DM1
F4 DQSL VDDQ#H3 H3 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
SPM_DQS1P C8 H10 SPM_ODT V14
DQSU VDDQ#H10 MEM_ODT(NC) IOPLLVDD18_SIDE_PORT L75 PBY160808T-221Y-N
IOPLLVDD18(NC) AE23 +1.8V 15mA
SPM_CLKP V15 AE24 IOPLLVDD_SIDE_PORT L73 PBY160808T-221Y-N +1.1V 26mA
SPM_DM0 SPM_CLKN MEM_CKP(NC) IOPLLVDD(NC)
E8 DML VSS#A10 A10 W 14 MEM_CKN(NC)
SPM_DM1 D4 B4 AD23 IOPLLVDD18 - memory PLL
DMU VSS#B4 R597 SIDE@40.2/F_4 SPM_COMPP IOPLLVSS(NC) C9794
VSS#E2 E2 AE12 MEM_COMPP(NC) not applicable to RX881
G9 +1.5V_MEM_VDDQ R607 SIDE@40.2/F_4 SPM_COMPN AD12 AE18 SPM_VREF1 SIDE@2.2u/6.3V_6
VSS#G9 MEM_COMPN(NC) MEM_VREF(NC)
Co
+1.5V_MEM_VDDQ SPM_DQS0N G4 J3 C9781
SPM_DQS1N DQSL VSS#J3 SIDE@2.2u/6.3V_6
B8 DQSU VSS#J9 J9
M2 RS880M_A11
R603 SIDE@10K/F_4 VSS#M2
VSS#M10 M10
VSS#P2 P2
[12] SP_DDR3_RST# T3 RESET VSS#P10 P10
VSS#T2 T2
VMA_ZQ L9 T10
ZQ VSS#T10
40 mil~50 mil
R604 B2
VSSQ#B2 +1.5V_MEM_VDDQ +1.5V
SIDE@240/F_4 VSSQ#B10 B10
D2 SIDE@0.1u/10V_4 SIDE@1u/6.3V_4
VSSQ#D2 R598 SIDE@0_6
A
VSSQ#D9 D9 A

VSSQ#E3 E3
J2 E9 C9782 C9783 C9784 C9785 C9786 C9787
NC#J2 VSSQ#E9
L2 NC#L2 VSSQ#F10 F10
J10 G2 SIDE@10u/6.3V_6
NC#J10 VSSQ#G2
L10 NC#L10 VSSQ#G10 G10

100-BALL
SIDE@0.1u/10V_4 SIDE@10u/6.3V_6 SIDE@1u/6.3V_4
PROJECT : ZR8
SDRAM DDR3
SIDE@H5TQ1G63AFR-14C Quanta Computer Inc.
Size Document Number Rev
RS880M-HT LINK I/F 1/5 1A

Date: Wednesday, May 27, 2009 Sheet 7 of 49


5 4 3 2 1
5 4 3 2 1

PEG_RXP15 D4
U28B
A5 PEG_TXP15_C C669 SW@0.1u/10V_4 PEG_TXP15
[16] PEG_RXN[15:0]
PEG_RXN[15:0] PEG_TXN[15:0]
PEG_TXN[15:0] [16]
09
PEG_RXN15 GFX_RX0P GFX_TX0P PEG_TXN15_C C672 SW@0.1u/10V_4 PEG_TXN15 PEG_RXP[15:0] PEG_TXP[15:0]
PEG_RXP14
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
PEG_TXP14_C C662 SW@0.1u/10V_4 PEG_TXP14
[16] PEG_RXP[15:0] PEG_TXP[15:0] [16]
A3 GFX_RX1P GFX_TX1P A4
PEG_RXN14 B3 B4 PEG_TXN14_C C666 SW@0.1u/10V_4 PEG_TXN14
PEG_RXP13 GFX_RX1N GFX_TX1N PEG_TXP13_C C657 SW@0.1u/10V_4 PEG_TXP13
C2 GFX_RX2P GFX_TX2P C3 Close to North Bridge
PEG_RXN13 C1 B2 PEG_TXN13_C C659 SW@0.1u/10V_4 PEG_TXN13
D
PEG_RXP12 GFX_RX2N GFX_TX2N PEG_TXP12_C C652 SW@0.1u/10V_4 PEG_TXP12 D
E5 GFX_RX3P GFX_TX3P D1
PEG_RXN12 F5 D2 PEG_TXN12_C C654 SW@0.1u/10V_4 PEG_TXN12
PEG_RXP11 GFX_RX3N GFX_TX3N PEG_TXP11_C C641 SW@0.1u/10V_4 PEG_TXP11
G5 GFX_RX4P GFX_TX4P E2
PEG_RXN11 G6 E1 PEG_TXN11_C C640 SW@0.1u/10V_4 PEG_TXN11
PEG_RXP10 GFX_RX4N GFX_TX4N PEG_TXP10_C C643 SW@0.1u/10V_4 PEG_TXP10
H5 GFX_RX5P GFX_TX5P F4
PEG_RXN10 H6 F3 PEG_TXN10_C C642 SW@0.1u/10V_4 PEG_TXN10
PEG_RXP9 GFX_RX5N GFX_TX5N PEG_TXP9_C C645 SW@0.1u/10V_4 PEG_TXP9
J6 GFX_RX6P GFX_TX6P F1
PEG_RXN9 J5 F2 PEG_TXN9_C C644 SW@0.1u/10V_4 PEG_TXN9
PEG_RXP8 GFX_RX6N GFX_TX6N PEG_TXP8_C C625 SW@0.1u/10V_4 PEG_TXP8
J7 H4
PEG_RXN8 J8
GFX_RX7P GFX_TX7P
H3 PEG_TXN8_C C624 SW@0.1u/10V_4 PEG_TXN8
INT. HDMI

PCIE I/F GFX


PEG_RXP7 GFX_RX7N GFX_TX7N PEG_TXP7_C C647 SW@0.1u/10V_4 PEG_TXP7
L5 GFX_RX8P GFX_TX8P H1
PEG_RXN7 L6 H2 PEG_TXN7_C C646 SW@0.1u/10V_4 PEG_TXN7

l
PEG_RXP6 GFX_RX8N GFX_TX8N PEG_TXP6_C C627 SW@0.1u/10V_4 PEG_TXP6 PEG_TXP15_C
M8 GFX_RX9P GFX_TX9P J2 PEG_TXP15_C [25]
PEG_RXN6 L8 J1 PEG_TXN6_C C626 SW@0.1u/10V_4 PEG_TXN6 PEG_TXN15_C
GFX_RX9N GFX_TX9N PEG_TXN15_C [25]
PEG_RXP5 P7 K4 PEG_TXP5_C C649 SW@0.1u/10V_4 PEG_TXP5 PEG_TXP14_C
GFX_RX10P GFX_TX10P PEG_TXP14_C [25]
PEG_RXN5 M7 K3 PEG_TXN5_C C648 SW@0.1u/10V_4 PEG_TXN5 PEG_TXN14_C
GFX_RX10N GFX_TX10N PEG_TXN14_C [25]

tia
PEG_RXP4 P5 K1 PEG_TXP4_C C631 SW@0.1u/10V_4 PEG_TXP4 PEG_TXP13_C
GFX_RX11P GFX_TX11P PEG_TXP13_C [25]
PEG_RXN4 M5 K2 PEG_TXN4_C C628 SW@0.1u/10V_4 PEG_TXN4 PEG_TXN13_C
GFX_RX11N GFX_TX11N PEG_TXN13_C [25]
PEG_RXP3 R8 M4 PEG_TXP3_C C630 SW@0.1u/10V_4 PEG_TXP3 PEG_TXP12_C
GFX_RX12P GFX_TX12P PEG_TXP12_C [25]
PEG_RXN3 P8 M3 PEG_TXN3_C C629 SW@0.1u/10V_4 PEG_TXN3 PEG_TXN12_C
GFX_RX12N GFX_TX12N PEG_TXN12_C [25]
PEG_RXP2 R6 M1 PEG_TXP2_C C638 SW@0.1u/10V_4 PEG_TXP2
PEG_RXN2 GFX_RX13P GFX_TX13P PEG_TXN2_C C637 SW@0.1u/10V_4 PEG_TXN2
R5 GFX_RX13N GFX_TX13N M2
PEG_RXP1 P4 N2 PEG_TXP1_C C633 SW@0.1u/10V_4 PEG_TXP1
PEG_RXN1 GFX_RX14P GFX_TX14P PEG_TXN1_C C621 SW@0.1u/10V_4 PEG_TXN1
P3 GFX_RX14N GFX_TX14N N1
PEG_RXP0 T4 P1 PEG_TXP0_C C650 SW@0.1u/10V_4 PEG_TXP0
PEG_RXN0 GFX_RX15P GFX_TX15P PEG_TXN0_C C639 SW@0.1u/10V_4 PEG_TXN0
T3 GFX_RX15N GFX_TX15N P2

AE3 AC1 PCIE_TXP0_C C658 0.1u/10V_4


[26] PCIE_RX1+ GPP_RX0P GPP_TX0P PCIE_TX1+ [26]
AD4 AC2 PCIE_TXN0_C C655 0.1u/10V_4 To LAN
[26] PCIE_RX1- GPP_RX0N GPP_TX0N PCIE_TX1- [26]
C AE2 GPP_RX1P GPP_TX1P AB4 C
AD3 GPP_RX1N GPP_TX1N AB3
AD1 AA2 PCIE_TXP2_C C651 0.1u/10V_4
[27] PCIE_RXP2 GPP_RX2P GPP_TX2P PCIE_TXP2 [27]
AD2 PCIE I/F GPP AA1 PCIE_TXN2_C C653 0.1u/10V_4 TO WLAN-2

en
[27] PCIE_RXN2 GPP_RX2N GPP_TX2N PCIE_TXN2 [27]
V5 GPP_RX3P GPP_TX3P Y1 T107
W6 GPP_RX3N GPP_TX3N Y2 T108
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2

AA8 AD7 A_TXP0_C C676 0.1u/10V_4 A_TXP0 [11]


[11] A_RXP0 SB_RX0P SB_TX0P
Y8 AE7 A_TXN0_C C677 0.1u/10V_4 A_TXN0 [11]
[11] A_RXN0 SB_RX0N SB_TX0N
AA7 AE6 A_TXP1_C C673 0.1u/10V_4 A_TXP1 [11]
[11] A_RXP1 SB_RX1P SB_TX1P
Y7 AD6 A_TXN1_C C674 0.1u/10V_4 A_TXN1 [11]
[11] A_RXN1 SB_RX1N SB_TX1N
AA5 PCIE I/F SB AB6 A_TXP2_C C668 0.1u/10V_4 A_TXP2 [11]
[11] A_RXP2 SB_RX2P SB_TX2P
AA6 AC6 A_TXN2_C C670 0.1u/10V_4 A_TXN2 [11]
[11] A_RXN2 SB_RX2N SB_TX2N
W5 AD5 A_TXP3_C C661 0.1u/10V_4 A_TXP3 [11]
[11] A_RXP3 SB_RX3P SB_TX3P
Y5 AE5 A_TXN3_C C665 0.1u/10V_4 A_TXN3 [11]
[11] A_RXN3 SB_RX3N SB_TX3N

id
AC8 NB_PCIECALRP R154 1.27K/F_4
PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R147 2K/F_4
PCE_CALRN(PCE_BCALRN) AB8 +1.1V

RS880M_A11

B B

RS880 Display Port Support (muxed on GFX)

GFX_TX0,TX1,TX2 and TX3


nf
DP0
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7


DP1
AUX1 and HPD1
Co

A A

PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
RS880M-PCIE I/F 2/5 1A

Date: Wednesday, May 27, 2009 Sheet 8 of 49


5 4 3 2 1
5 4 3 2 1

10
U28C
110mA +3V_AVDD_NB F12 A22 LA_DATAP0 [24]
AVDD1(NC) TXOUT_L0P(NC)
UMA use 140 ohm 1%. E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LA_DATAN0 [24]
20mA +1.8V_AVDDDI_NB F14 A21
AVDDDI(NC) TXOUT_L1P(NC) LA_DATAP1 [24]
Discrete use 133 ohm 1%. G15 AVSSDI(NC) TXOUT_L1N(NC) B21 LA_DATAN1 [24]
4mA +1.8V_AVDDQ_NB H15 B20
Note : Only for RS880 series A11 ASIC errata. H14
AVDDQ(NC) TXOUT_L2P(NC)
A20
LA_DATAP2 [24]
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) LA_DATAN2 [24]
TXOUT_L3P(NC) A19
E17 B19

CRT/TVOUT
R126 4.7K_4 NBGFX_CLKP C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
C05 F17 Y(DFT_GPIO2)
B03 F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
R127 4.7K_4 NBGFX_CLKN A18
INT_CRT_RED TXOUT_U0N(NC)
[24] INT_CRT_RED G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
R438 IV@140/F_4 G17 B17
INT_CRT_GRE REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2)
[24] INT_CRT_GRE E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
R440 150/F_4 F18 D21
D
For Check list JTAG [24] INT_CRT_BLU INT_CRT_BLU E19
GREENb(NC)
BLUE(DFT_GPIO3)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5) D18
D

R442 150/F_4 F19 D19


R434 *4.7K_4 NB_PWRGD_IN BLUEb(NC) TXOUT_U3N(NC)
R153 *4.7K_4 INT_EDIDDATA INT_CRT_HSYNC
+3V
R433 *4.7K_4 INT_EDIDCLK
Only for UMA [24] INT_CRT_HSYNC
INT_CRT_VSYNC
A11 DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16 LA_CLK [24]
[24] INT_CRT_VSYNC B11 DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 LA_CLK# [24]
R141 *4.7K_4 HDMI_DDC_DATA E8 D16
+3V VGA (Not [24] INT_DDCDATA
F8
DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
D17
[24] INT_DDCCLK DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
applicable to
R160 715/F_6 DAC_RSET_NB G14
RX881) DAC_RSET(PWM_GPIO1)
A13 +1.8V_VDDLTP18_NB 15mA
+1.1V_PLLVDD VDDLTP18(NC)
A12 PLLVDD(NC) VSSLTP18(NC) B13
+1.8V_PLLVDD18 D14
For A11 version

LVTM
PLLVDD18(NC) +1.8V_VDDLT_18_NB
B12 PLLVSS(NC) VDDLT18_1(NC) A15 300mA

PLL PWR
+1.8V B15

l
R119 *SP_A11@49.9/F_4 CLK_SBLINKP +1.8V_VDDA18HTPLL VDDLT18_2(NC)
65mA H17 VDDA18HTPLL VDDLT33_1(NC) A14
R116 *SP_A11@49.9/F_4 CLK_SBLINKN B14
+1.8V_VDDA18PCIEPLL VDDLT33_2(NC)
20mA D7 VDDA18PCIEPLL1
B2-TEST R579 E7 C14
300_4 VDDA18PCIEPLL2 VSSLT1(VSS)
VSSLT2(VSS) D15

tia
[11,24,34] A_RST#_SB D8 SYSRESETb VSSLT3(VSS) C16
NB_PWRGD_IN A10 C18
[12,15] NB_PWRGD_IN POWERGOOD VSSLT4(VSS)
NB_LDT_STOP# C10 C20

PM
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
C12 ALLOW_LDTSTOP VSSLT6(VSS) E20
VSSLT7(VSS) C22
[11] CLK_NB_HTREFP_PR C25 HT_REFCLKP
[11] CLK_NB_HTREFN_PR C24 HT_REFCLKN

[11] CLK_NB_REF_CLKP E11 REFCLK_P/OSCIN(OSCIN)

CLOCKs
[11] CLK_NB_REF_CLKN F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 INT_LVDS_DIGON [24]
LVDS_BLON(PCE_RCALRP) F7 INT_DPST_PWM [24]
B2-TEST NBGFX_CLKP T2 G12
GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) INT_LVDS_BLON [24]
NBGFX_CLKN T1 GFX_REFCLKN
D06 GPP_REFCLKP
T69 U1 GPP_REFCLKP
C GPP_REFCLKN U2 C
T70 GPP_REFCLKN
CLK_SBLINKP V4
[11] CLK_SBLINKP GPPSB_REFCLKP(SB_REFCLKP)
CLK_SBLINKN V3
[11] CLK_SBLINKN GPPSB_REFCLKN(SB_REFCLKN)

en
INT_EDIDDATA A9
[24] INT_EDIDDATA I2C_DATA
INT_EDIDCLK B9 D9
[24] INT_EDIDCLK
HDMI_DDC_DATA B8
I2C_CLK MIS. TMDS_HPD(NC)
D10
INT_HDMI_HPD [25]
[25] HDMI_DDC_DATA DDC_DATA/AUX0N(NC) HPD(NC)
[25] HDMI_DDC_CLK A8 DDC_CLK/AUX0P(NC)
AUX1P B7 D12 SUS_STAT#_NB
T96 AUX1P(NC) TVCLKIN(PWM_GPIO5) SUS_STAT# [12]
A10 AUX1N A7
T72 AUX1N(NC)
THERMALDIODE_P AE8
+NB_CORE_ON B10 AD8 R88
[39] +NB_CORE_ON STRP_DATA THERMALDIODE_N
*3K_4
G11 D13 TEST_EN
RSVD TESTMODE
RS880_AUX_CAL C8 R172
T17 AUX_CAL(NC) 1.82K/F_4
RS880M_A11

A41 A41
RS880M --- ADD AVDD-DAC Analog
not applicable to RX780

id
L27 +3V_AVDD_NB L61 +1.1V_PLLVDD
STRAP_DEBUG_BUS_GPIO_ENABLEb +3V
PBY160808T-221Y-N
+1.1V
PBY160808T-221Y-N PLLVDD - Graphics PLL
C300 C485
C03 C679
not applicable to +1.8V A41
Enables the Test Debug Bus using GPIO. 2.2u/6.3V_6 2.2u/6.3V_6
RX780
1u/6.3V_4

RS880M L33 +1.8V_VDDLTP18_NB


INT_CRT_VSYNC R158 3K_4 +3V PBY160808T-221Y-N
1 Disable VDDLTP18 - LVDS or DVI/HDMI PLL
0 Enable C318 not applicable to RX780
+1.8V 2.2u/6.3V_6
B A41 B

R174 *Short_4 +1.8V_AVDDDI_NB


AVDDI-DAC Digital

RS880M: Enables Side port memory


RS880M:INT_CRT_HSYNC
nf A41
C312
0.1u/10V_4
not applicable to RX780
+1.8V
A41

L32
PBY160808T-221Y-N
+1.8V_PLLVDD18
PLLVDD18 - Graphics PLL
L62
PBY201209T-221Y-N

C683
4.7u/6.3V_6
C680
0.1u/10V_4
+1.8V_VDDLT_18_NB

VDDLT18 - LVDS or DVI/HDMI


digital
not applicable to RX780
L36 +1.8V_AVDDQ_NB not applicable to RX780
PBY160808T-221Y-N AVDDQ-DAC Bandgap Reference
Selects if Memory SIDE PORT is available or not not applicable to RX780 C324 C327
C335 10U/6.3V_8 2.2u/6.3V_6
1 = Memory Side port Not available 2.2u/6.3V_6
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]

A09 +1.8V
Co
INT_CRT_HSYNC R168 *SP@3K_4 +1.8V DDR3 based CPU : Level shifted to 1.8 V on the
A41
R166 SIDE@3K_4
+3V
20mils width +1.8V
R85
Northbridge side using an open-drain buffer and
pulled up to 1.8V_S0 through a 2.2k Ohm 5% resistor
2.2K_4
+1.8V_VDDA18PCIEPLL
on the Northbridge side.
L22

5
PBY160808T-221Y-N VDDA18PCIEPLL -PCIE PLL + U8

C268 2 Open 4 NB_LDT_STOP#


[2,11] CPU_LDT_STOP#
2.2u/6.3V_6 Drain

- 74LVC07

3
For extrnal EEPROM Debug only A41
RS780/RX780/RS880
A

+NB_CORE_ON R436 2K/F_4


20mils width R185 1K_4
A

+1.8V
L34 +1.8V_VDDA18HTPLL
PBY160808T-221Y-N VDDA18HTPLL -HT LINK PLL NB_ALLOW_LDTSTOP
[2,11] CPU_LDT_REQ#
A11
C329
2.2u/6.3V_6 [2,11] ALLOW_LDTSTOP
Display Port interface from PCIeGraphics (RS880/rs880M only)
The RS880 family does not support CLMC architecture PROJECT : ZR8
RS880_AUX_CAL R145 *150/F_4 The LDTREQ# connection from the CPU to
ALLOW_LDTSTOP of the Northbridge is no longer Quanta Computer Inc.
required.
Size Document Number Rev
RS880M-SYSTEM I/F 3/5 1A

Date: Wednesday, May 27, 2009 Sheet 9 of 49


5 4 3 2 1
5 4 3 2 1

11

AE14
AC3
AC4

M11
AA4
AB5
AB1
AB7

AE1
AE4
AB2

D11

E14
E15

K14

L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4

G8
D3
D5

H7

R7

N4

R1
R2
R4

U4
A2
B1

E4

P6

V7

V8
V6

Y6
RX881/RS880 POWER DIFFERENCE TABLE

L1
L2
L4
L7
J4
U28F
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
PIN NAME RX881 RS880 PIN NAME RX881 RS880
VDDHT +1.1V +1.1V IOPLLVDD +1.1V +1.1V

VDDHTRX +1.1V +1.1V AVDD GND +3.3V


PART 6/6

D D
GROUND VDDHTTX +1.2V +1.2V AVDDDI GND +1.8V

VDDA18PCIE +1.8V +1.8V AVDDQ GND +1.8V

VDDG18 +1.8V +1.8V PLLVDD GND +1.1V


VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VDD18_MEM GND +1.8V PLLVDD18 GND +1.8V
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDPCIE +1.1V +1.1V VDDA18PCIEPLL +1.8V +1.8V

VDDC +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V

l
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDD_MEM GND +1.8V/1.5V VDDLTP18 GND +1.8V

VDDG33 +3.3V +3.3V VDDLT18 GND +1.8V

tia
IOPLLVDD18 +1.8V +1.8V VDDLT33 NC NC

+1.1V 2A for RS880M


+1.1V 1.3A for RX881
+1.1V

C VDDPCIE - PCIE-E Main power C

0.6A L31 *Short_8 +1.1V_VDDHT


U28E
+1.1V_VDD_PCIE
2.5A R115 *Short_8
J17 VDDHT_1 VDDPCIE_1 A6 +1.1V
K16 PART 5/6 B6

en
VDDHT_2 VDDPCIE_2
L16 VDDHT_3 VDDPCIE_3 C6
C317 C321 C322 C323 M16 D6 C243 C291 C293 C294 C290
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDHT_4 VDDPCIE_4 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 4.7u/6.3V_6
P16 VDDHT_5 VDDPCIE_5 E6
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
H8
0.7A L37 *Short_8 +1.1V_VDDHTRX H18 VDDHTRX_1
VDDPCIE_8
VDDPCIE_9 J9
G19 VDDHTRX_2 VDDPCIE_10 K9
F20 M9
+1.1V 2A for RS880M C362 C338 C340 C334 E21
VDDHTRX_3
VDDHTRX_4
VDDPCIE_11
VDDPCIE_12 L9
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 D22 P9
+1.2V 0.4A for Rx881 B23
VDDHTRX_5 VDDPCIE_13
R9
VDDHTRX_6 VDDPCIE_14
A23 T9

L35 *Short_8 2A +1.1V_VDDHTTX


VDDHTRX_7 VDDPCIE_15
VDDPCIE_16 V9 0.95~1.1V 10A
+1.1V AE25 VDDHTTX_1 VDDPCIE_17 U9
AD24 VDDC - Core Logic power

id
VDDHTTX_2
AC23 VDDHTTX_3 VDDC_1 K12 NB_CORE
C333 C331 C337 C332 C341 AB22 J14
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDHTTX_4 VDDC_2
AA21 U16
B2-TEST Y20
VDDHTTX_5
VDDHTTX_6
VDDC_3
VDDC_4 J11 C315 C311 C310 C307 C314
W 19 K15 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10U/6.3V_8

POWER
VDDHTTX_7 VDDC_5
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14
T17 L11
+1.8V 1A for RS780M+SB700 R17
VDDHTTX_10
VDDHTTX_11
VDDC_8
VDDC_9 M13
B +1.8V 1A for RX881 A41 P17 VDDHTTX_12 VDDC_10 M15 B
M17 VDDHTTX_13 VDDC_11 N12
N14
0.7A VDDC_12
+1.8V L24
PBY201209T-221Y-N

C299
4.7u/6.3V_6
C297
4.7u/6.3V_6
C292
0.1u/10V_4
C295
0.1u/10V_4
C287
nf
+1.8V_VDDA18PCIE

0.1u/10V_4
C301
0.1u/10V_4
J10
P10
K10
M10
L10
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
P11
P13
P14
R12
R15
C316
0.1u/10V_4
C308
0.1u/10V_4
C306
0.1u/10V_4
C305
10U/6.3V_8
A09

W9 VDDA18PCIE_6 VDDC_18 T11 C831


H9 VDDA18PCIE_7 VDDC_19 T15
T10 U12 W/O side port
VDDA18PCIE_8 VDDC_20
R10 VDDA18PCIE_9 VDDC_21 T14 -->stuff 0 Ohm
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 SIDE@0.1u/10V_4 CS00002JB38 SIDE@0.1u/10V_4
VDDA18PCIE_11 +1.5V_VDD_MEM L74
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 +1.5V
AD9 AA11 SIDE@0_8
VDDA18PCIE_13 VDD_MEM2(NC) C832 C833 C831 C836
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
Co
U10 AD10 C834
VDDA18PCIE_15 VDD_MEM4(NC) SIDE@4.7u/6.3V_6
AB10
+1.8V R136 *Short_6 25mA +1.8V_VDDG18_NB F9 VDDG18_1(VDD18_1)
VDD_MEM5(NC)
VDD_MEM6(NC) AC10
G9 SIDE@0.1u/10V_4 SP@0.1u/10V_4
VDDG18_2(VDD18_2)
AE11 H11
VDD18-RS880 I/O Transform C286 AD11
VDD18_MEM1(NC) VDDG33_1(NC)
H12 +3V_VDDG33 R169 *Short_4 60mA +3V VDD_MEM For UMA RS780 only
1U/10V_4 VDD18_MEM2(NC) VDDG33_2(NC)
RS880M_A11 VDD33 - 3.3V I/O Not applicable to RX780
C302 C303 memory I/O transform
0.1u/10V_4 0.1u/10V_4 Not applicable to RX780

+1.8V R171 SIDE@0_6 25mA +1.8V_VDD18_MEM A09


A A
C835
SP@1U/10V_4

C835 PROJECT : ZR8


W/O side port
+1.1V
-->stuff 0 Ohm Quanta Computer Inc.
+1.1V [2,7,8,9,14,38,44] CS00002JB38
+1.8V +1.8V [7,9,15,24,37,42,43,44] Size Document Number Rev
NB_CORE NB_CORE [39,44] RS880M-POWER5/5 1A

Date: Wednesday, May 27, 2009 Sheet 10 of 49


5 4 3 2 1
5 4 3 2 1

MINI-PCIE,Card reader
NB & EC
[27,30] PCIE_RST#_SB_R
C350 180P/50V_4

R345 33_4 PCIE_RST#_SB


A_RST#_SB
P1
L1
U34A

PCIE_RST#
SB800 Part 1 of 5
PCICLK0 W2
W1
PCI_CLK0
PCI_CLK1
T59
PCI_CLK1 [15]
12

PCI CLKS
[9,24,34] A_RST#_SB A_RST# PCICLK1/GPO36
W3 PCI_CLK2 PCI_CLK2 [15]
C735 0.1u/10V_4 A_RX0P_C PCICLK2/GPO37 PCI_CLK3
[8] A_RXP0 AD26 A_TX0P PCICLK3/GPO38 W4 PCI_CLK3 [15]
PLACE THESE [8] A_RXN0 C736 0.1u/10V_4 A_RX0N_C AD27 Y1 PCI_CLK4 PCI_CLK4 [15]
C732 0.1u/10V_4 A_RX1P_C A_TX0N PCICLK4/14M_OSC/GPO39 +AVBAT
[8] A_RXP1 AC28 A_TX1P
PCIE AC C733 0.1u/10V_4 A_RX1N_C
COUPLING CAPS
[8]
[8]
A_RXN1
A_RXP2 C728 0.1u/10V_4 A_RX2P_C
AC29
AB29
A_TX1N PCIRST# V2
20MIL R582 499/F_4
D
C729 0.1u/10V_4 A_RX2N_C A_TX2P D

CLOSE TO SB820
[8]
[8]
A_RXN2
A_RXP3 C726 0.1u/10V_4 A_RX3P_C
AB28
AB26
A_TX2N
AA1 C792 20MIL
C727 0.1u/10V_4 A_RX3N_C A_TX3P AD0/GPIO0 R573 10_4 +3VRTC_1
[8] A_RXN3 AB27 A_TX3N AD1/GPIO1 AA4
1U/10V_4
[8] A_TXP0 AE24
AD2/GPIO2 AA3
AB1
20MIL D30
A_RX0P AD3/GPIO3 +3VRTC RB500V-40
[8] A_TXN0 AE23 A_RX0N AD4/GPIO4 AA5 +3VPCU

PCI EXPRESS INTERFACES


[8] A_TXP1 AD25 A_RX1P AD5/GPIO5 AB2
AD24 AB6 D23 1 2 PE_GPIO2_R D28
[8] A_TXN1 A_RX1N AD6/GPIO6
AC24 AB5 Change from 0ohm to 1K RB500V-40
[8] A_TXP2 A_RX2P AD7/GPIO7
AC25 AA6 *SW@RB501V-40 for safty issue
[8] A_TXN2 A_RX2N AD8/GPIO8
[8] A_TXP3 AB25 A_RX3P AD9/GPIO9 AC2
AB24 AC3 R559 +VCCRTC_2

l
[8] A_TXN3 A_RX3N AD10/GPIO10 BOARD_ID0 [13]
AC4 1K/F_4
R481 590/F_4 PCIE_CALRP_SB AD29
AD11/GPIO11
AC1
BOARD_ID1
BOARD_ID2
[13]
[13] A13 20MIL 20MIL
R279 2K/F_4 PCIE_CALRN_SB PCIE_CALRP AD12/GPIO12 +BAT
+1.1V_PCIE_VDDR AD28 PCIE_CALRN AD13/GPIO13 AD1 BOARD_ID3 [13]
AD14/GPIO14 AD2 BOARD_ID4 [13]

tia
AA28 GPP_TX0P AD15/GPIO15 AC6

1
+3V_S5 AA29 AE2 BAT1
GPP_TX0N AD16/GPIO16 BAT_CONN
Y29 GPP_TX1P AD17/GPIO17 AE1
C812 0.1u/10V_4 Y28 AF8
GPP_TX1N AD18/GPIO18 +3V +3V
Y26 AE3

2
GPP_TX2P AD19/GPIO19
5
R580 U36 Y27 AF1 AD23 [15]
33_4 A_RST#_SB GPP_TX2N AD20/GPIO20
2 W 28 GPP_TX3P AD21/GPIO21 AG1
A_RST#_SB_AND 4 W 29 AF2
[16,26,27] A_RST#_AND GPP_TX3N AD22/GPIO22
1 AE9 VDDR_1.05_EN R339
SB_GPIO_PCIE_RST# [12] AD23/GPIO23
VGA,LAN& MINI-IPCIE AA22 AD9 AD24 [15] R330 *2.2K_4
GPP_RX0P AD24/GPIO24
3

C813 TC7SH08FU Y21 AC11 AD25 [15] 2.2K_4


100p/50V_4 GPP_RX0N AD25/GPIO25
AA25 GPP_RX1P AD26/GPIO26 AF6 AD26 [15]

2
AA24 AF4 AD27 [15] Q26
GPP_RX1N AD27/GPIO27 *MMBT3904
C W 23 GPP_RX2P AD28/GPIO28 AF3 C
V24 AH2 SB820_MEMHOT# 1 3
GPP_RX2N AD29/GPIO29 CPU_MEMHOT# [2,5,6]
W 24 GPP_RX3P AD30/GPIO30 AG2
W 25 AH3

en
GPP_RX3N AD31/GPIO31

PCI INTERFACE
CBE0# AA8
CBE1# AD5
CBE2# AD8
CBE3# AA10
FRAME# AE8
DEVSEL# AB9
M23 AJ3 +3V
[9] CLK_SBLINKP PCIE_RCLKP/NB_LNK_CLKP IRDY#
[9] CLK_SBLINKN P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
[9] CLK_NB_REF_CLKP U29 AF5 R524
NB_DISP_CLKP STOP# SW@2K/F_4
[9] CLK_NB_REF_CLKN U28 NB_DISP_CLKN PERR# AE6
SERR# AE4
[9] CLK_NB_HTREFP_PR T26 NB_HT_CLKP REQ0# AE11
[9] CLK_NB_HTREFN_PR T27 AH5 D17 1 2 PE_GPIO2_R
NB_HT_CLKN REQ1#/GPIO40 PE_GPIO2_R [24]
REQ2#/CLK_REQ8#/GPIO41 AH4
V21 AC12 SW@RB501V-40

id
[2] CLK_CPU_BCLKP_PR CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 T46
[2] CLK_CPU_BCLKN_PR T21 CPU_HT_CLKN GNT0# AD12
R594 *10K_4
+3V A26
GNT1#/GPO44 AJ5 PCH_ODD_EN [28]
[16] CLK_PCIE_VGAP RP11 2 1 SGN@0_4P2R_4 SLT_GFX_CLKP V23 AH6 DGPU_VRON [12,40,41]
SLT_GFX_CLKN SLT_GFX_CLKP GNT2#/GPO45
[16] CLK_PCIE_VGAN 4 3 T23 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AB12 T44
AB11 CLKRUN#_R
CLKRUN# CLKRUN# [34]
[26] CLK_PCIE_LOM L29 GPP_CLK0P LOCK# AD7 T55
UMA don't stuff [26] CLK_PCIE_LOM# L28 GPP_CLK0N A12
INTE#/GPIO32 AJ6 dGPU_PWROK [19]
N29 AG6 R331 *8.2K_4 +3V
GPP_CLK1P INTF#/GPIO33
B
N28 GPP_CLK1N INTG#/GPIO34 AG4 B
INTH#/GPIO35 AJ4 PE_GPIO0 [16]
[27] CLK_PCIE_WLANP_2 M29 GPP_CLK2P A58

+3V
A59
[27] CLK_PCIE_WLANN_2
nf M28

T25
V25
GPP_CLK2N

GPP_CLK3P
GPP_CLK3N
CLOCK GENERATOR
LPCCLK0
LPCCLK1
H24
H25
LPC_CLK0
LPC_CLK1
R505
R499
22_4
22_4
LPC_CLK0 [15]
LPC_CLK1 [15]
PCLK_DEBUG [27]
CLK_PCI_775 [34]
L24 GPP_CLK4P LAD0 J27 LPC_LAD0 [27,34]
C533 0.1u/10V_4 L23 J26 C747
GPP_CLK4N LAD1 LPC_LAD1 [27,34]
LPC H29 C750 for EMI
LAD2 LPC_LAD2 [27,34]
5

P25 H28 *5.6p/50V_4 *22p/50V_4 suggestion


GPP_CLK5P LAD3 LPC_LAD3 [27,34]
[13] MEM_1V5 2 M25 GPP_CLK5N LFRAME# G28 LPC_LFRAME# [27,34]
4 J25 LDRQ0#_SB
VDDR_OPT [43] LDRQ0# T34
VDDR_1.05_EN 1 P29 AA18 LDRQ1#_SB
GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 T42
R317 P28 AB19
GPP_CLK6N SERIRQ/GPIO48 IRQ_SERIRQ [34]
3

U18 33_4 A62


Co
VDDR_1.05_EN: TC7SH08FU N26 GPP_CLK7P *10K/F_4 R286
1 : VDDR =1.05V N27 +3V_S5
R303 *0_4 GPP_CLK7N
0 : VDDR = 0.9V (Default) ALLOW _LDTSTP/DMA_ACTIVE# G21 ALLOW_LDTSTOP [2,9]
T29 GPP_CLK8P PROCHOT# H21 CPU_PROCHOT# [2]
T28 K19
CPU

GPP_CLK8N LDT_PG CPU_PWRGD_SVID_REG [2,37]


LDT_STP# G22 CPU_LDT_STOP# [2,9]
RTC_X1 A16 J24 CPU_LDT_RST# [2]
LDT_RST#
[16] GN_CLK_VGA_27M_NONSS L25 14M_25M_48M_OSC
3 2 C1 RTC_X1
Y8 32K_X1
INTRUDER_ALERT# Left not connected
32.768KHZ C730 SGN@22P/50V_4 25M_X1 L26 C2 RTC_X2 +AVBAT
25M_X1 32K_X2 (Southbridge has 50-kohm internal
RTC

RTC_X2
pull-up to VBAT).
A 4 1 RTCCLK D2 RTC_CLK [34]
A
2

Y5 B2 INTRUDER_ALERT# R545 *1M/F_4


R546 R480 25M_X2 INTRUDER_ALERT#
L27 25M_X2 VDDBT_RTC_G B1 +AVBAT
*20M_6 SGN@25MHZ SGN@1M_4
1

R547 20M_6 G2
1

SB820M_A12 *SHORT_PAD1 C793

C794 C795 C731 SGN@22P/50V_4


0.1u/10V_4 PROJECT : ZR8
2

18P/50V_4 18P/50V_4
Quanta Computer Inc.
Size Document Number Rev
SB820-PCIE/PCI/CPU/LPC 1/4 1A

Date: Wednesday, May 27, 2009 Sheet 11 of 49


5 4 3 2 1
5 4 3 2 1

+3V_S5

13
NC only ,Can't be install +3V_S5
[11,13,14,15,24,26,31,32,36,44] +3V_S5 USBCLK/41M_25M_48M_OSC pin is CLK input
R352 *2.2K_4 SB_TEST0 +3V pin when EXT CLKGEN mode.
[2,4,5,6,9,10,11,13,14,15,19,24,25,27,29,30,32,33,34,36,37,38,39,41,42,43,44,46] +3V
R350 *2.2K_4 SB_TEST1
It is output CLK source when INT CLKGEN mode.

R347 *2.2K_4 SB_TEST2 U34D


J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 T106
K1 RI#/GEVENT22#
D3 G19 USB_RCOMP_SB R293 11.8K/F_6
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
[34] SUSB# F1 SLP_S3#
[34] SUSC# H1 SLP_S5#

ACPI / WAKE UP EVENTS


[34] DNBSWON# F2

USB 1.1 USB MISC


D +3V SCL0/SDATA0 Clock gen/Robson/TV PW R_BTN# D
is 3V tolerance [15] SB_PWRGD_IN H5 PW R_GOOD SB800
AMD datasheet define it tuner [9] SUS_STAT# G6 SUS_STAT# USB_FSD1P/GPIO186 J10
/DDR2/DDR2 SB_TEST0 B3 Part 4 of 5 H11
R288 2.2K_4 PCLK_SMB SB_TEST1 TEST0 USB_FSD1N
thermal/Accelerometer C4 TEST1/TMS
SB_TEST2 F6 H9 USB_FDS12P
TEST2 USB_FSD0P/GPIO185 T47
R287 2.2K_4 PDAT_SMB AD21 J8 USB_FSD12N
[34] SIO_A20GATE GA20IN/GEVENT0# USB_FSD0N T49
[34] SIO_RCIN# AE21 KBRST#/GEVENT1#
LANLINK_STATE# K2 B12
T94 LPC_PME#/GEVENT3# USB_HSD13P USBP13+ [31]
J29 A12
+3V_S5 SCL1/SDATA1 is 3V/S5 tolerance
[34] SIO_EXT_SMI#
H2
LPC_SMI#/GEVENT23# USB_HSD13N USBP13- [31] USB board
[34] SIO_EXT_SCI# GEVENT5#
AMD datasheet define it SYS_RST# J1 F11
T95 SYS_RESET#/GEVENT19# USB_HSD12P USBP12+ [31]
PCIE_WAKE# H6 E11
USB board

l
[26] PCIE_WAKE# W AKE#/GEVENT8# USB_HSD12N USBP12- [31]
R348 10K_4 SB_SMBCLK1 IR_RX1 F3
T58 IR_RX1/GEVENT20#
R346 10K_4 SB_SMBDATA1 SB_THERMTRIP# J6 E14
[2] CPU_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
[9,15] NB_PWRGD_IN AC19 NB_PW RGD USB_HSD11N E12

tia
[34] ICH_RSMRST# G1 RSMRST# USB_HSD10P J12 USBP10+ [30]
+3V_S5 SCL2/SDATA2 is 3V/S5 tolerance J14
AMD datasheet define it AD19
USB_HSD10N USBP10- [30] USB card reader
CLK_REQ4#/SATA_IS0#/GPIO64
AA16 CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P A13 USBP9+ [31]
R290 10K_4 SB_SCLK2 AB21 B13
R283 10K_4 SB_SDATA2
[11] SB_GPIO_PCIE_RST#
[26] CLK_PCIE_LAN_REQ# AC18
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N USBP9- [31] BLUETOOTH
MXM_PWR_EN CLK_REQ0#/SATA_IS3#/GPIO60
AF20 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 USBP8+ [31]
SB_GPIO59 AE19 C13
T37
AF19
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USBP8- [31] USB board
[29] SPKR SPKR/GPIO66
PCLK_SMB AD22 G12

USB 2.0
+3V [5,6,26,27,46] PCLK_SMB SCL0/GPIO43 USB_HSD7P USBP7+ [27]
PDAT_SMB AE22 G14
[5,6,26,27,46] PDAT_SMB
SB_SMBCLK1 F5
SDA0/GPIO47 USB_HSD7N USBP7- [27] WLAN MINI CARD
SB_SMBDATA1 SCL1/GPIO227
F4 SDA1/GPIO228 USB_HSD6P G16 T61
C R338 4.7K_4 SUS_STAT# AH21 G18 C
[27] CLK_PCIE_2_REQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N T105
R306 *0_4 VGA_REQ#_GPIO61 AB18
[17] VGA_REQ# CLK_REQ1#/FANOUT4/GPIO61

GPIO
E1 IR_LED#/LLB#/GPIO184 USB_HSD5P D16
B2-TEST C04 AJ21 C16

en
+3V SMARTVOLT2/SHUTDOW N#/GPIO51 USB_HSD5N
[7] SP_DDR3_RST# H4 DDR3_RST#/GEVENT7# B2-TEST
D5 GBE_LED0/GPIO183 USB_HSD4P B14
D7 GBE_LED1/GEVENT9# USB_HSD4N A14
G5 GBE_LED2/GEVENT10#
dGPU_VRON R307 K3 E18
2ms GBE_STAT0/GEVENT11# USB_HSD3P
SW@4.7K_4 T41 AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
MXM_PWR_EN
USB_HSD2P J16
[19] MXM_PWREN [31] OC_7# H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18
D19 D1
[31] OC_6# USB_OC6#/IR_TX1/GEVENT6#
SW@RB501V-40 R149 *Short_4 E4 B17
USB CAMERA

USB OC
[2,4,33] PM_THERM# USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USBP1+ [24]
MXM_PWR_EN 1 2 C538 D4 A17
[31] OC_4# USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USBP1- [24]
SW@0.1u/10V_4 SB_JTAG_TDO E8
SB_JTAG_TCK USB_OC3#/AC_PRES/TDO/GEVENT15#
1 2 F7 A16
[11,40,41] DGPU_VRON
SB_JTAG_TDI E7
USB_OC2#/TCK/GEVENT14# USB_HSD0P
B16
USBP0+
USBP0-
[31]
[31]
On board USB connect
D18 SB_JTAG_RST# USB_OC1#/TDI/GEVENT13# USB_HSD0N
F8

id
>1mS delay is required between all MXM power rail stable *SW@RB501V-40 USB_OC0#/TRST#/GEVENT12#
and MXM_PWREN(enables the module internal power) HD audio interface is +3VS5 voltage
R555 *10K/F_4 ACZ_BCLK M3 D25 SB_SCLK2
ACZ_SDOUT AZ_BITCLK SCL2/GPIO193 SB_SDATA2
A14 [15] ACZ_SDOUT
R337 *10K/F_4 ACZ_SDIN0
N1 AZ_SDOUT SDA2/GPIO194 F23
SB_GPIO195
L2 B26

HD AUDIO
R336 *10K/F_4 ACZ_SDIN1 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 SB_GPIO196
M2 AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 E26
R571 *10K/F_4 ACZ_SDIN2 M1 F25
R327 *10K/F_4 ACZ_SDIN3 AZ_SDIN2/GPIO169 EC_PW M0/EC_TIMER0/GPIO197
M4 AZ_SDIN3/GPIO170 EC_PW M1/EC_TIMER1/GPIO198 E22
ACZ_SYNC N2 F22 GPIO199 [15]
B
ACZ_RST# AZ_SYNC EC_PW M2/EC_TIMER2/GPIO199 B
P2 AZ_RST# EC_PW M3/EC_TIMER3/GPIO200 E21 GPIO200 [15]
+3V_S5

+3V
A61
R474
R486
8.2K_4
8.2K_4
CLK_PCIE_LAN_REQ#
CLK_PCIE_2_REQ#
nf R553
R322

R558
10K_4
10K_4

10K_4
GBE_COL
GBE_CRS

GBE_MDIO
T1
T4
L6
L5
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
G24
G25
E28
E29
D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
U1 GBE_RXD3 KSI_6/GPIO207 C29
D03 U3 GBE_RXD2 KSI_7/GPIO208 C28
T2

GBE LAN
GBE_RXD1
U2 GBE_RXD0 KSO_0/GPIO209 B28

EMBEDDED CTRL
T5 A27 SB_GPIO195 R489 10K_4
R343 10K_4 GBE_RXERR GBE_RXCTL/RXDV KSO_1/GPIO210
V5 GBE_RXERR KSO_2/GPIO211 B27
P5 D26 SB_GPIO196 R275 10K_4
GBE_TXCLK KSO_3/GPIO212
M5 GBE_TXD3 KSO_4/GPIO213 A26
Co
P9 GBE_TXD2 KSO_5/GPIO214 C26
T7 GBE_TXD1 KSO_6/GPIO215 A24
ACZ_SDOUT R570 33_4 P7 B25
ACZ_SDOUT_AUDIO [29] GBE_TXD0 KSO_7/GPIO216
M7 GBE_TXCTL/TXEN KSO_8/GPIO217 A25
C815 *10P/50V_4 P4 D24
GBE_PHY_PD KSO_9/GPIO218
M9 GBE_PHY_RST# KSO_10/GPIO219 B24
R344 10K_4 GBE_PHY_INTR V7 C24
ACZ_SYNC R552 33_4 GBE_PHY_INTR KSO_11/GPIO220
ACZ_SYNC_AUDIO [29] KSO_12/GPIO221 B23
ADP_PRES0 E23 A23
T35 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
EMBEDDED CTRL

C800 *10P/50V_4 E24 D22


PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
F21 SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
ACZ_BCLK R569 33_4 B2-TEST B22
ACZ_BITCLK_AUDIO [29] +3V_S5 KSO_17/GPIO226
A D27 PS2KB_DAT/GPIO189
A
C814 *10P/50V_4 F28
CN24 PS2KB_CLK/GPIO190
DEL C816 F29 PS2M_DAT/GPIO191
1 E27 PS2M_CLK/GPIO192
ACZ_RST# R554 33_4 SB_JTAG_TCK
ACZ_RST#_AUDIO [29] 2 SB_JTAG_TDO
3
ACZ_SDIN0 ACZ_SDIN0 [29] 4
SB_JTAG_TDI
SB_TEST1 SB820M_A12 PROJECT : ZR8
5
If the VDDIO_AZ_S power rail is configured for 1.5V_S5
then AZ_SDIN[3:0] can not be connected to 3.3-V devices.
6
7
SB_JTAG_RST# Quanta Computer Inc.
8 Size Document Number Rev
SB820-ACPI/GPIO/USB 2/4 1A
*S/W_JTAG_DEBUG SB JTAG
Date: Wednesday, May 27, 2009 Sheet 12 of 49
5 4 3 2 1
5 4 3 2 1

14
SATA PORT 0,1,2,3
can support AHCI +1.1V_AVDD_SATA
[14] +1.1V_AVDD_SATA
mode U34B +3V_S5
[11,12,14,15,24,26,31,32,36,44] +3V_S5

C777 0.01u/16V_4 SATA_TX0+_C AH9


SB800 AH28
[28] SATA_TX0+ SATA_TX0P FC_CLK T80
C775 0.01u/16V_4 SATA_TX0-_C AJ9 Part 2 of 5 AG28
SATA1 [28] SATA_TX0- SATA_TX0N FC_FBCLKOUT
AF26
T81
FC_FBCLKIN T78
[28] SATA_RX0- AJ8 SATA_RX0N
[28] SATA_RX0+ AH8 SATA_RX0P FC_OE#/GPIOD145 AF28 T75
FC_AVD#/GPIOD146 AG29 T77
[28] SATA_TX1+ C774 0.01u/16V_4 SATA_TX1+_C AH10 AG26
D SATA_TX1P FC_W E#/GPIOD148 T82 D
[28] SATA_TX1- C769 0.01u/16V_4 SATA_TX1-_C AJ10 AF27
SATA_TX1N FC_CE1#/GPIOD149 T76
AE29
SATA ODD [28] SATA_RX1- AG10
FC_CE2#/GPIOD150
AF29
T74
TEMPIN0 R519 10K_4
SATA_RX1N FC_INT1/GPIOD144 T79
[28] SATA_RX1+ AF10 SATA_RX1P FC_INT2/GPIOD147 AH27 T84 IF THERE IS NO IDE, TEST
TEMPIN1 R511 10K_4
AG12 AJ27
POINTS FOR DEBUG BUS
SATA_TX2P FC_ADQ0/GPIOD128 T83
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26 T33 IS MANDATORY MB_THRMDA_SB R521 10K_4
FC_ADQ2/GPIOD130 AH25 T86
AJ12 AH24 SB_GPIO174 R313 10K_4
SATA_RX2N FC_ADQ3/GPIOD131 T85
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23 T90
AH23 SB_GPIO175 R526 10K_4
FC_ADQ5/GPIOD133 T88
AH14 AJ22

l
SATA_TX3P FC_ADQ6/GPIOD134 T91
AJ14 AG21 SB_GPIO176 R523 10K_4
SATA_TX3N FC_ADQ7/GPIOD135 T93
FC_ADQ8/GPIOD136 AF21 T92
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22 T87

FLASH
Signal Name Explanation AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23 T89

tia
FC_ADQ11/GPIOD139 AF23 T97
SB800 A11: 800 ohm 1% resistor to GND. AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24 T98
P/N:CS18062FB00(806 Ohm) AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25 T99
SATA_CALRP SB800 A12: 1k ohm 1% resistor to GND. FC_ADQ14/GPIOD142 AG25 T101
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26 T102

SERIAL ATA
AH17 SATA_RX4P
SB800 A11: 931-? 1% resistor to VDDAN_11_SATA.
AJ18 SATA_TX5P
SATA_CALRN SB800 A12: TBD-? 1% resistor to VDDAN_11_SATA. AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
W7 WWAN_DET#
+1.1V_AVDD_SATA FANIN0/GPIO56 T52
C V9 CPPE_NC1# C
FANIN1/GPIO57 T48
R300 SP_A12@1K/F_4 SATA_CALRP AB14 W8 CRD_REQ1#
SATA_CALRP FANIN2/GPIO58 T54
R298 SP_A12@931/F_4 SATA_CALRN AA14 SATA_CALRN TEMPIN0
B6

en
TEMPIN0/GPIO171 TEMPIN1
TEMPIN1/GPIO172 A6
AD11 A5 MB_THRMDA_SB
[32] SATA_ACT# SATA_ACT#/GPIO67 TEMPIN2/GPIO173
B5 SB_GPIO174
R302 10K_4 TEMPIN3/TALERT#/GPIO174
+3V TEMP_COMM C7
PLACE SATA_CAL
A3 SB_GPIO175

HW MONITOR
RES VERY CLOSE C760 GN@22P/50V_4 SATA_X1 AD16
VIN0/GPIO175
B4 SB_GPIO176
SATA_X1 VIN1/GPIO176
TO BALL OF SB820 VIN2/GPIO177 A4 SIDE_PORT_ID0
2

C5 SIDE_PORT_ID1
Y7 R507 VIN3/GPIO178
A60 GN@25MHZ GN@1M_4 VIN4/GPIO179 A7 MEM_1V5 [11]
VIN5/GPIO180 B7
B8
1

VIN6/GBE_STAT3/GPIO181
AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8
SATA_X2
C754 GN@22P/50V_4 BOARD_ID0 BOARD_ID0 [11]
BOARD_ID1

id
BOARD_ID1 [11]
BOARD_ID2 BOARD_ID2 [11]
SB_GPIO164 J5 G27 BOARD_ID3 BOARD_ID3 [11]
T53 SPI_DI/GPIO164 NC1
SB_GPIO163 E2 Y2 BOARD_ID4

SPI ROM
T60 SPI_DO/GPIO163 NC2 BOARD_ID4 [11]
SB_GPIO162 K4 A55
T56 SPI_CLK/GPIO162
SB_GPIO165 K9
T45 SPI_CS1#/GPIO165
SB_GPIO161 G2
T57 ROM_RST#/GPIO161
+3V R311 10K_4 BOARD_ID0 R314 *10K_4

SB820M_A12
B B
R324 SW@10K_4 BOARD_ID1 R323 *IV@10K_4

A05
nf HYX
ID1

0
ID0

0
A04
R517

R273
SP@10K_4

*SP@10K_4
BOARD_ID2 R304

BOARD_ID3 R274
*SP@10K_4

SP@10K_4
+3V_S5 R528 SP@10K_4 SIDE_PORT_ID0 R316 SP@10K_4

R437 *10K_4 SIDE_PORT_ID1 R320 10K_4 SAM 0 1 R272 *10K_4 BOARD_ID4 R271 10K_4
B2-TEST
ATI 1 0

Board ID
Co
DDR3 Sideport Memory Device BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
GPIO14 GPIO13 GPIO12 GPIO11 GPIO10
BOARD_ID2 SIDE_PORT_ID1 SIDE_PORT_ID0
Vendor Vendor P/N STN B/S P/N Size GPIO12 GPIO178 GPIO177 JV51-DN
N/A (3-DIMM)
0 (Default) WO/Sideport UMA 14"
(Default)
AKD5LZGTW04 0
Hynix H5TQ1G63BFR-12C (64M*16) 1GB (WO/Sideport) 0 0
JM51-DN W/Sideport Discrete
A 1 N/A (2-DIMM) (Default) (Default) 15.6" (Default) A

AKD5LGGT506 1
Samsung K4W1G1646E-HC12 (64M*16) 1GB (W/Sideport) 0 1

PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
SATA/IDE/HWM/SPI 3/4 1A

Date: Wednesday, May 27, 2009 Sheet 13 of 49


5 4 3 2 1
5 4 3 2 1

PLACE ALL THE DECOUPLING CAPS ON

15
THIS SHEET CLOSE TO SB AS POSSIBLE.

VDD-- S/B CORE power


VDDQ--3.3V I/O power U34C
131mA SB800 Part 3 of 5 510mA
+3V R325 *Short_8 +3V_VDDIO_PCIGP AH1 N13 +1.1V_VDDCR R295 *Short_6 +1.1V
VDDIO_33_PCIGP_1 VDDCR_11_1 U34E
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15
Y19 N17

CORE S0
VDDIO_33_PCIGP_3 VDDCR_11_3 C526 C527 C522 C525 C517
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13 SB800
C544 C543 C535 C534 C539 AC21 U17 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Y14 AJ2
*10U/6.3V_8 10U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDIO_33_PCIGP_5 VDDCR_11_5 VSSIO_SATA_1 VSS_1
AA2 V12 Y16 A28

PCI/GPIO I/O
D VDDIO_33_PCIGP_6 VDDCR_11_6 VSSIO_SATA_2 VSS_2 D
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 AB16 VSSIO_SATA_3 VSS_3 A2
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W 12 A41 AC14 VSSIO_SATA_4 VSS_4 E5
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W 18 AE12 VSSIO_SATA_5 VSS_5 D23
AA9 VDDIO_33_PCIGP_10 AE14 VSSIO_SATA_6 VSS_6 E25
AF7 VDDIO_33_PCIGP_11 xx mA +1.1V_VDDAN_CLK L48
AF9 VSSIO_SATA_7 VSS_7 E6
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 +1.1V AF11 VSSIO_SATA_8 VSS_8 F24
K29 UPB201212T-121Y-N_8 AF13 N15
VDDAN_11_CLK_2 VSSIO_SATA_9 VSS_9
VDDAN_11_CLK_3 J28 AF16 VSSIO_SATA_10 VSS_10 R13
K26 C496 C488 C497 C489 C458 C457 AG8 R17

CLKGEN I/O
VDDAN_11_CLK_4 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 *10U/6.3V_8 VSSIO_SATA_11 VSS_11
VDDAN_11_CLK_5 J21 AH7 VSSIO_SATA_12 VSS_12 T10
AF22 J20 AH11 P10

FLASH I/O
VDDIO_18_FC_1 VDDAN_11_CLK_6 VSSIO_SATA_13 VSS_13
AE25 K21 AH13 V11

l
VDDIO_18_FC_2 VDDAN_11_CLK_7 VSSIO_SATA_14 VSS_14
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 AH16 VSSIO_SATA_15 VSS_15 U15
AC22 VDDIO_18_FC_4 AJ7 VSSIO_SATA_16 VSS_16 M18
AJ11 VSSIO_SATA_17 VSS_17 V19
A41 VDDRF_GBE_S V1 AJ13 VSSIO_SATA_18 VSS_18 M11

tia
AJ16 L12
POWER VDDIO_33_GBE_S M10
VSSIO_SATA_19 VSS_19
VSS_20 L18

L46
43mA A9 VSSIO_USB_1 VSS_21 J7
AE28 B10 P3

GBE LAN
+3V VDDPL_33_PCIE VSSIO_USB_2 VSS_22
PBY160808T-221Y-N K11 V4
C490 C487 VSSIO_USB_3 VSS_23
A41 SB820 without GBE: Connected to GND plane. B9 AD6

PCI EXPRESS
2.2u/6.3V_6 *0.1u/10V_4 VSSIO_USB_4 VSS_24
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 D10 VSSIO_USB_5 VSS_25 AD4
+1.1V_PCIE_VDDR V22 L9 D12 AB7
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_6 VSS_26
L45
600mA V26 VDDAN_11_PCIE_3 D14 VSSIO_USB_7 VSS_27 AC9
+1.1V V27 VDDAN_11_PCIE_4 D17 VSSIO_USB_8 VSS_28 V8
UPB201212T-121Y-N_8 V28 M6 E9 W9
C495 C502 C479 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 VSSIO_USB_9 VSS_29
V29 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 P8 F9 VSSIO_USB_10 VSS_30 W 10
C478 C477 C481 W 22 F12 AJ28
*10U/6.3V_8 10U/6.3V_8 1U/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VDDAN_11_PCIE_7 VSSIO_USB_11 VSS_31
C W 26 VDDAN_11_PCIE_8 F14 VSSIO_USB_12 VSS_32 B29 C
F16 VSSIO_USB_13 VSS_33 U4
C9 VSSIO_USB_14 VSS_34 Y18
93mA G11 Y10

en
L54 +3V_VDDPL_SATA VSSIO_USB_15 VSS_35
32mA

GROUND
+3V AD14 VDDPL_33_SATA F18 VSSIO_USB_16 VSS_36 Y12
PBY160808T-221Y-N A21 +3V_VDDIO R292 *Short_6 +3V_S5 D9 Y11
VDDIO_33_S_1 VSSIO_USB_17 VSS_37
AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 H12 VSSIO_USB_18 VSS_38 AA11
C523 C524 AF18 B21 H14 AA12

SERIAL ATA
2.2u/6.3V_6 *0.1u/10V_4 VDDAN_11_SATA_4 VDDIO_33_S_3 C505 C504 C506 VSSIO_USB_19 VSS_39
A41 A41 AH20 K10 H16 G4

3.3V_S5 I/O
VDDAN_11_SATA_2 VDDIO_33_S_4 *0.1u/10V_4 2.2u/6.3V_6 2.2u/6.3V_6 VSSIO_USB_20 VSS_40
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10 H18 VSSIO_USB_21 VSS_41 J4
+1.1V_AVDD_SATA AE18 J9 J11 G8
VDDAN_11_SATA_5 VDDIO_33_S_6 VSSIO_USB_22 VSS_42
L49
567mA AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6 J19 VSSIO_USB_23 VSS_43 G9
+1.1V AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 K12 VSSIO_USB_24 VSS_44 M12
UPB201212T-121Y-N_8 K14 AF25
VSSIO_USB_25 VSS_45
K16 VSSIO_USB_26 VSS_46 H7
C510 C512 C516 C514 C513 113mA K18 AH29

CORE S5
10U/6.3V_8 0.1u/10V_4 0.1u/10V_4 1U/10V_4 1U/10V_4 +1.1V_VDDCR_11 R278 *Short_6 +1.1V_S5 VSSIO_USB_27 VSS_47
VDDCR_11_S_1 F26 H19 VSSIO_USB_28 VSS_48 V10
A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 VSS_49 P6
A19 VDDAN_33_USB_S_2 xx mA C498 C493 VSS_50 N4
A41 A20 M8 Y4 L4

id
VDDAN_33_USB_S_3 VDDIO_AZ_S +VDDIO_AZ EFUSE VSS_51
B18 197mA 1U/10V_4 1U/10V_4 L8
+3.3V_VDDAN_USB VDDAN_33_USB_S_4 VSS_52
B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 D8 VSSAN_HW M
658mA B20 B11

USB I/O
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 +1.1V_USB_PHY_R
+3V_S5 L67 C18 M19 M20
PBY160808T-221Y-N VDDAN_33_USB_S_7 VSSXL VSSPL_SYS
C20 VDDAN_33_USB_S_8
C753 C531 C511 C518
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +3V_VDDPL 47mA
For support USB D19 VDDAN_33_USB_S_10 P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
wakeup-->3V_S5 10U/6.3V_8 10U/6.3V_8 1U/10V_4 1U/10V_4 D20 L22 +1.1V_VDDPL 62mA P20 H26
VDDAN_33_USB_S_11 VDDPL_11_SYS_S VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
E19 VDDAN_33_USB_S_12 PLL M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
B VDDPL_33_USB_S F19 VDDPL_33_USB_S 17mA A41 M24 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 AA23 B
A41 M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
xx mA C11 VDDAN_11_USB_S_1 VDDAN_33_HW M_S D6 +3V_HWM_VDDAN 5mA P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23

If the VDDIO_AZ_S
+1.1V_S5 L52
PBY160808T-221Y-N
+1.1V_VDDAN_USB

C528
2.2u/6.3V_6
C532
0.1u/10V_4
nf D11 VDDAN_11_USB_S_2
VDDXL_33_S L20

C509 C515
L51
PBY160808T-221Y-N
+3V_S5
P24
P26
T20
T22
T24
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
AA26
AC26
Y20
W 21
W 20
power rail SB820M_A12 *0.1u/10V_4 2.2u/6.3V_6 V20 AE26
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
is configured for J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
VSSIO_PCIECLK_27 K20
1.5V_S5
then AZ_SDIN[3:0] +3V_VDDPL Part 5 of 5
+3V
A41
can not be
connected to 3.3-V +VDDIO_AZ +1.1V_S5 +1.1V_USB_PHY_R SB820M_A12
devices. L43
Co
PBY160808T-221Y-N
+3V_S5 R315 *Short_6 L53 0_6

C507 C468
*0.1u/10V_4 2.2u/6.3V_6
C521 C520 C530
C541 0.1u/10V_4 0.1u/10V_4 10U/6.3V_8
2.2u/6.3V_6

+3V_S5 A41 +3V_HWM_VDDAN A41


+1.1V_S5 +1.1V_VDDPL +3V_S5 VDDPL_33_USB_S +3V
D04 [2,4,5,6,9,10,11,12,13,15,19,24,25,27,29,30,32,33,34,36,37,38,39,41,42,43,44,46] +3V
+1.1V
A A
[2,7,8,9,10,38,44] +1.1V
+3V_S5
[11,12,13,15,24,26,31,32,36,44] +3V_S5
L56 L47 R289 0_4 +1.1V_S5
[38] +1.1V_S5
PBY160808T-221Y-N PBY160808T-221Y-N

C553 C550 C501 C499


0.1u/10V_4 2.2u/6.3V_6 *0.1u/10V_4 2.2u/6.3V_6 C623
0.1u/10V_4
C469
2.2u/6.3V_6 PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
SB820-PWR/DECOUPLING 4/4 1A

Date: Wednesday, May 27, 2009 Sheet 14 of 49


5 4 3 2 1
5 4 3 2 1

16
OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.
REQUIRED STRAPS For
internal
SB820M is clock GEN.
supported Gen1
mode only.

D +3V_S5 +3V +3V +3V +3V +3V_S5 +3V_S5 D

A15
R556 R342 R550 R340 R341 R500 R277
*10K_4 *10K_4 *10K_4 *10K_4 10K_4 10K_4 10K_4

[12] GPIO199
[12] GPIO200
[11] LPC_CLK1
[11] LPC_CLK0

l
[11] PCI_CLK4
[11] PCI_CLK3
[11] PCI_CLK2
[11] PCI_CLK1

tia
[12] ACZ_SDOUT

R294 R291
R557 R334 R551 R332 R333 R501 R498 2.2K_4 *2.2K_4
10K_4 10K_4 10K_4 10K_4 *10K_4 10K_4 *GN@10K_4

AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 GPIO200 GPIO199


D02
C This is required as ALLOW Watchdog USE non_Fusion EC INT. CLKGEN H, H=Reserved C
PULL
HIGH the low power mode PCIE Gen2 Timer Enable DEBUG CLOCK MODE ENABLED ENABLED
H, L=SPI ROM
is not supported on STRAPS

en
the SB8xx DEFAULT DEFAULT

PULL FORCE Watchdog IGNORE Fusion EC EXT. CLKGEN L,H=LPC ROM DEFAULT
LOW PERFORMANCE PCIE Gen1 Timer Disable DEBUG CLOCK MODE DISABLED ENABLE
MODE L, L=FWH ROM
STRAPS
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

internal have
pull Hi 10K
+3V_S5
[11,12,13,14,24,26,31,32,36,44] +3V_S5
+1.8V
DEBUG STRAPS [7,9,10,24,37,42,43,44] +1.8V

id
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

B
[11] AD23 B
[11] AD24
[11] AD25
[11]
[11]
AD26
AD27

R549
*2.2K_4
R312
*2.2K_4
R305
*2.2K_4
nf
R310
*2.2K_4
R301
*2.2K_4
NB_PWRGD_IN:
RS880/RX881 = 1.8V;
Do NOT share it with SB_PWRGD when use Internal Clk Gen (Need SB PLL initialize firstly)

+3V_S5 R567 10K_4 POWERGOOD_EC_CPU R568 *Short_4


SB_PWRGD_IN [12]
C809
*2.2U/6.3V_6 NB/SB POWER GOOD CIRCUIT
+1.8V

U38
Co
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 *BAS316 D29 1 5 C802 *0.1u/10V_4
[37,39] CPU_COREPG NC VCC
2
A
USE PCI DISABLE ILA USE FC DISABLE I2C DISABLE PCI
PULL BAS316 D24 3 4 R581 *33_4
PLL AUTORUN PLL ROM MEM BOOT [4,34] PWROK_EC GND Y NB_PWRGD_IN [9,12]
HIGH *NL17SZ17DFT2G
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT SOT-353

A63 AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353


PULL BYPASS ENABLE ILA BYPASS FC ENABLE I2C ROM ENABLE PCI
B2-TEST ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) SOT23-5
LOW PCI PLL AUTORUN PLL use REQ3# as SDA MEM BOOT
A use GNT3# as SCL A

PROJECT : ZR8
Quanta Computer Inc.
Size Document Number Rev
SB820-STRAPS 1A

Date: Wednesday, May 27, 2009 Sheet 15 of 49


5 4 3 2 1
5 4 3 2 1

17

D D

Park XT U23A +3V_D


+3V_D [17,19,21,24,25]
+1V
+1V [17,19,20,42]
P/N:AJ077400T08

AA38 Y33 PEG_RXP0_C C139 SW@0.1u/10V_4


[8] PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXN0_C PEG_RXP0 [8]
Y37 Y32 C155 SW@0.1u/10V_4
[8] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [8]

PEG_RXP1_C C131 SW@0.1u/10V_4

l
[8] PEG_TXP1 Y35 W33 PEG_RXP1 [8]
PCIE_RX1P PCIE_TX1P PEG_RXN1_C C137 SW@0.1u/10V_4
[8] PEG_TXN1 W36 W32 PEG_RXN1 [8] Add extra OSC for use SB clock.
PCIE_RX1N PCIE_TX1N

W38 U33 PEG_RXP2_C C129 SW@0.1u/10V_4


[8] PEG_TXP2 PCIE_RX2P PCIE_TX2P PEG_RXN2_C PEG_RXP2 [8]
V37 U32 C120 SW@0.1u/10V_4
[8] PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 [8]

tia
R62 *SPE@10K_4
PEG_RXP3_C [17] GPIO24_TRSTB
V35 U30 C116 SW@0.1u/10V_4
[8] PEG_TXP3 PCIE_RX3P PCIE_TX3P PEG_RXN3_C PEG_RXP3 [8]
U36 U29 C111 SW@0.1u/10V_4 R71 *SW@10K_4 +3V_D
[8] PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 [8] [17] GPIO27_TMS
R109 *SPE@0_4
PEG_RXP4_C [17] GPIO26_TCK GN_CLK_VGA_27M_NONSS [11]
U38 T33 C109 SW@0.1u/10V_4
[8] PEG_TXP4 PCIE_RX4P PCIE_TX4P PEG_RXN4_C PEG_RXP4 [8]
T37 T32 C103 SW@0.1u/10V_4 R33 *SW@10K_4 +3V_D
[8] PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 [8] [18] TESTEN

PCI EXPRESS INTERFACE


T35 T30 PEG_RXP5_C C99 SW@0.1u/10V_4 B2-TEST
[8] PEG_TXP5 PCIE_RX5P PCIE_TX5P PEG_RXN5_C PEG_RXP5 [8]
R36 T29 C94 SW@0.1u/10V_4
[8] PEG_TXN5 PCIE_RX5N PCIE_TX5N PEG_RXN5 [8]
JTAG SIGNAL STUFF OPTION FOR OPTION2
R38 P33 PEG_RXP6_C C89 SW@0.1u/10V_4
[8] PEG_TXP6 PCIE_RX6P PCIE_TX6P PEG_RXN6_C PEG_RXP6 [8]
P37 P32 C83 SW@0.1u/10V_4
[8] PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 [8]
C SIGNALS NORMAL MODE JTAG MODE (DEBUG) C
P35 P30 PEG_RXP7_C C82 SW@0.1u/10V_4
[8] PEG_TXP7 PCIE_RX7P PCIE_TX7P PEG_RXN7_C PEG_RXP7 [8]
N36 P29 C76 SW@0.1u/10V_4
[8] PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 [8]
GPIO24_TRSTB "0" (PD) "1" (PU)
N38 N33 PEG_RXP8_C C70 SW@0.1u/10V_4
[8] PEG_TXP8 PCIE_RX8P PCIE_TX8P PEG_RXP8 [8]

en
M37 N32 PEG_RXN8_C C68 SW@0.1u/10V_4
[8] PEG_TXN8 PCIE_RX8N PCIE_TX8N PEG_RXN8 [8]
GPIO27_TMS "1" (PU) "1" (PU)
M35 N30 PEG_RXP9_C C67 SW@0.1u/10V_4
[8] PEG_TXP9 PCIE_RX9P PCIE_TX9P PEG_RXN9_C PEG_RXP9 [8]
L36 N29 C60 SW@0.1u/10V_4
[8] PEG_TXN9 PCIE_RX9N PCIE_TX9N PEG_RXN9 [8]
GPIO26_TCK CLK "1" (PU)
L38 L33 PEG_RXP10_C C58 SW@0.1u/10V_4
[8] PEG_TXP10 PCIE_RX10P PCIE_TX10P PEG_RXN10_C PEG_RXP10 [8]
K37 L32 C55 SW@0.1u/10V_4
[8] PEG_TXN10 PCIE_RX10N PCIE_TX10N PEG_RXN10 [8]
TESTEN "1" (PU) "1" (PU)
K35 L30 PEG_RXP11_C C53 SW@0.1u/10V_4
[8] PEG_TXP11 PCIE_RX11P PCIE_TX11P PEG_RXN11_C PEG_RXP11 [8]
J36 L29 C50 SW@0.1u/10V_4
[8] PEG_TXN11 PCIE_RX11N PCIE_TX11N PEG_RXN11 [8]

J38 K33 PEG_RXP12_C C43 SW@0.1u/10V_4


[8] PEG_TXP12 PCIE_RX12P PCIE_TX12P PEG_RXN12_C PEG_RXP12 [8]
H37 K32 C48 SW@0.1u/10V_4
[8] PEG_TXN12 PCIE_RX12N PCIE_TX12N PEG_RXN12 [8]

H35 J33 PEG_RXP13_C C40 SW@0.1u/10V_4


[8] PEG_TXP13 PCIE_RX13P PCIE_TX13P PEG_RXN13_C PEG_RXP13 [8]
G36 J32 C42 SW@0.1u/10V_4
[8] PEG_TXN13 PCIE_RX13N PCIE_TX13N PEG_RXN13 [8]

id
+3V_D
G38 K30 PEG_RXP14_C C34 SW@0.1u/10V_4
[8] PEG_TXP14 PCIE_RX14P PCIE_TX14P PEG_RXN14_C PEG_RXP14 [8]
F37 K29 C36 SW@0.1u/10V_4
[8] PEG_TXN14 PCIE_RX14N PCIE_TX14N PEG_RXN14 [8]
R73
F35 H33 PEG_RXP15_C C38 SW@0.1u/10V_4
[8] PEG_TXP15 PCIE_RX15P PCIE_TX15P PEG_RXN15_C PEG_RXP15 [8]
E37 H32 C37 SW@0.1u/10V_4 SW@10K_4
[8] PEG_TXN15 PCIE_RX15N PCIE_TX15N PEG_RXN15 [8]

dGPU_PCIE_RST# D2 2 1 BAS316
CLOCK