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ISSN : 2229-6093

Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

COMPARISON OF COMPACTION TECHNIQUES IN VLSI PHYSICAL


DESIGN

Chetan Sharma1 & Shobhit Jaiswal2

(M.Tech-VLSI Department, JSS Academy of Technical Education, Noida)


1 2
( chetan2042@gmail.com ) & ( jaiswalshobhit19@gmail.com )

Abstract: The rapid growth in integration design, physical design, design verification,

technology has been made possible by the fabrication, packaging, testing and

automation of various steps involved in the debugging. The physical design is important

design and fabrication of VLSI chips. The step in the chip designing.

main factors which decide the quality of any The process of converting the specification

chip are power consumption, area and of an electrical circuit into a layout is called

performance of the chip. The demand of the physical design process. Due to

light weighted & compact chip is increase extremely small size of the individual

day by day. This paper reviewed the components, physical design is an extremely

different techniques of compaction of any tedious and error prone process. Almost all

chip and comparison among them because phases of physical design extensively use

different techniques have different tradeoffs. Computer Aided Design (CAD) tools,

The appropriate technique is used depending means steps are partially or fully automated.

upon requirements. The main steps in VLSI physical design are

Keywords: CAD Tool, Layout design partitioning, placement, routing and


compaction. Compaction is very important
rules, Shadow propagation, Scanline,
step in the physical design due to the
Flooring.
incereasively need of small size chips.
Introduction: In the VLSI design cycle The operation of layout area minimization
there are many steps: System specification, without violating the design rules and
functional design, logic design, circuit without altering the original functionality of

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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

layout is called as compaction. The input of Design style specific compaction


compaction is layout and output is also problem:
layout but by minimizing area. Compaction
The scope and impact of compaction is
is done by three ways: (a) By reducing space
different on different design styles:
between blocks without violating design
(a)Full custom style: There are large scope
space rule.(b) By reducing size of each
of compaction in full custom design style
block without violating design size rule.(c)
because of randomly sizes of block and
By reducing shape of blocks without
random space between blocks.
violating electrical characteristics of blocks.
(b) Standard cell design style: In this style
Therefore compaction is very complex
height of blocks are fixed. Therefore scope
process because this process requires the
is limited to channel compaction.
knowledge of all design rules. Due to the
(c) Gate array design style: In the gate array
use of strategies compaction algorithms are
design style position of gate is fixed so
divided into one-dimensional algorithms
scope is limited to optimizing wiring.
(either in x-dimension or y-dimension), two
dimensional algorithms (both in x-
Compaction Techniques:
dimension and y-dimension) and topological
There are different compaction techniques
algorithm (moving of separate cells
as shown in fig (a)
according to routing constraints) 3/2 -Dimensional
Problem formulation:
Given: Layout consists of set of geometrical
feature M = {M1, M2, M3,….Mn ) Compaction Hierarchical
Each Mi has minimum size = s (Mi) Techniques compaction Scan line
Algorith
Minimum space between Mi & Mj =
m
d (Mi, Mj) where 1<j, j<n
1- Dimensional
Objective: The objective of compaction is
Shadow
to minimize layout area by moving feature Path
close to each other and by resizing the Propagation
feature such that:
Size (Mi) ≥ s (Mi) 2- Dimensional

Distance (Mi, Mj) ≥ d (Mi,Mj) Fig (a)- Types of compaction techniques

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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

2
1-Dimensional compaction:

In this technique compaction is done only in 3 6


one dimension either in x-direction or y-
1
direction until no further compaction is 4
possible as discussed previous. There are
two types of constraints which relates to 5
these compaction techniques (i) Separation
constraint (ii) Connectivity constraint. The
techniques in 1-Dimensional compaction are Fig (b)- Shadow propagation method.
described below:

(a) Shadow propagation Technique: It is a


3
widely used technique for compaction. The
shadow is caused by shining of imaginary 1
4
light from behind the feature under
consideration. Now graph is formed by
5
making two lists, one has the blocks which
are covered by shadow and another one has
Fig (c)- Flow graph of shadow propagation
not covered blocks by shadow of light is
forwarding behind block no.1 then block no.
3,6,4,5 is covered by shadow which are
shown in fig (b) and the flow graph of
shadow propagation is shown in fig(c)
which is made by shaded blocks by shadow
i.e. block no.3, 6, 4, 5. Interval generation of
shadow propagation is shown in fig (d)

Fig (d)- Interval generation for shadow


propagation of fig (b)

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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

(b) Scanline Technique: The scanline is an The trade off in this technique is the much

imaginary horizontal or vertical line that time consumption. Thus we use 3/2-D

cuts through the layout in x or y compaction Compaction.

as shown below. 3/2-D Compaction:

In this technique we move the blocks in such


2
a way that it not only compact the circuit but
also resolve interferences. Since the
3 6 geometry is not as free as in 2-D

1
Compaction.
4
In this method two lists are formed one is

5 ceiling another is floor. First is formed by


the blocks which are appeared from the top
& second is formed by the blocks which are
appeared from the bottom. Selects the
Fig (e)- Example of Scanline method lowest block in the ceiling list and moves it
to the place on the floor which maximizes
In this method all the arranged blocks are
the gap between floor and ceiling. The
cut by this scanline. The scanline traverses
process is continued until all blocks are
from the top to bottom of the layout for x-
moved from ceiling to floor.
compaction. Similarly, for y-compaction the
scanline traverses from the left to the right Conclusion: This paper shows that how
of the layout as shown in fig (e). the compaction is useful in VLSI Design
cycle and various techniques using in
2-Dimensional compaction:
compaction and their tradeoffs. 1-Dimension
In this method compaction is done in both method is quite simple but provides less
dimension x-dimension as well as in y- compaction as compare to other method. 2-
dimension. 2-D compaction is in general D Compaction provides more compaction
much better than performing 1-D form but require more time. So 3/2-D
compaction. If 2-D compaction, solved Compaction is mostly used.
optimally, produces minimum-area layouts.

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ISSN : 2229-6093
Chetan Sharma,Shobhit Jaiswal, Int. J. Comp. Tech. Appl., Vol 2 (1), 160-164

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