Академический Документы
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Культура Документы
Jul. 2004
財團法人國家實驗研究院國家晶片系統設計中心
Module 1 Overview
Module 2 Design Understanding
Module 3 Watch Waveform
Module 4 Debug with Simulation Result
Module 5 Misc.
Module 6 nLint
Jul. 2004
財團法人國家實驗研究院國家晶片系統設計中心
Module 1 Overview
Module 2 Design Understanding
Module 3 Watch Waveform
Module 4 Debug with Simulation Result
Module 5 Misc.
Module 6 nLint
Module 1 Overview
Module 2 Design Understanding
Module 3 Watch Waveform
Module 4 Debug with Simulation Result
Module 5 Misc.
nState
Debussy
Supported Platforms
SUN SOLARIS 2.5 or later
HP-UX 10.X
IBM RS/6000 4.X or later
Linux
Windows NT
/home/debussy/share/symlib/artisan_u.lib++
/home/asic1/lib/faraday_l.lib++
Some options :
- vhdl | verilog : specify language type for import design
from source (verilog by default)
- top <topModule> : specify top module for import design
- lib <libName> : specify library name
- f <fileName> : specify a file which list all source files
Source
Window
Hierarchical
Browser
Message
Window
Language format
- VHDL-87
- VHDL-93
- Verilog
Select source files or the
file list to “Add”
Expand/Collapse design
tree by clicking on the
Plus / Minus icon
The Open Folder icon
indicate the current
scope displayed in the
source window.
Double click on a design
unit to view the content in
the source window.
Detail RTL
Browser Window
Flatten Window
Overview
Display Simulation Result
Open a simulation output file and Get signal waveform
Bus Operations
Search - Value, Constraint, Label Marker
Signal Processing - Logical Operation, Complex Event
Comparison
Analog Waveform
Overlap
Analog Expression
Create Bus
Formed from the selected signals to create a new bus inserted
at the signal cursor position.
Expand Bus
Double click on a bus name to expand / collapse the bus.
Browse
different
Alias Tables
Click OK to
apply alias for
selected signals
mismatch
List X / Trace X
Active Annotation in nTrace / nSchema
Active Trace / Bus Contention
Active Fan-In Cone
Show Memory
FSM Analysis
Search Next/Previous
You can select a signal first and use left / right icons to advance
forward / backward the cursor time by value change, rising edge
or falling edge.
Select a signal and move Cursor Time to the time point that
Unknown occurs and invoke Tools -> Trace X to generate Flatten
Window with tracing X to next storage element.
Select a signal and move Cursor Time to the time point that
Unknown occurs and invoke Tools -> Bus Contention to detect
whether it is caused by Bus Contention.
Use List X in nTrace / nWave to list tri-state output which has value X.
Double click tri-state bus in the list to invoke Trace X will generate
Flatten Window to show the cause of X.
Binary to
Hexadecimal
Restore Session...
– Recover previous debugging status from a session file.
fsdbextract
extract partial content of original FSDB to new FSDB by
scope or time range.
% fsdbextract verilog.fsdb –s /system –level 1 \
/system/I_cpu/I_ALUB –level 0 –o new.fsdb
fsdbmerge
merge multiple FSDB into one FSDB file.
% fsdbmerge 1.fsdb 2.fsdb –o all.fsdb
fsdbreport
Report value change of the specified signal to a text file
% fsdbreport verilog.fsdb –s /system/data –bt 0 –et 4000
Interactive
Toolbar
You can double click on the line number in source window to set a
breakpoint.
Double click on the line number again to delete the breakpoint.
Use Debug -> Breakpoints to set and control breakpoints.
- You can use the above commands to step though your source code in
different style.
- You can turn on Active Annotation to annotate signal values to source
code. The values annotated will be updated in real time.
Button Name : The button name of this command shown on the command window.
Command : The Verilog command.
Keyword in Command Line :
${Arg:<String>} - With such keyword in Verilog command Debussy will pop up
a form for user to enter a value , which is used as the argument
for this command , while user click this command button.
${SelVars} - Use the selected signals in the source window as arguments.
${SelVar} - Use the selected signal (only one signal allowed) in the source
window as arguments.
${treeSelScope} - Use the selected instance in Hierarchical Browser as argument.
\n - <CR Return> you have to add this at the end of your Verilog
command if you want this command be executed immediately.
- User needs to specify a number in Next Time Field and press OK.
- For this example, Modelsim will run 1000 Time Unit and stop.
Example 2:
Force Variable Force ${selVar} = ${Arg:New Value};\n
- User needs to select a signal in the source code window first and then
click this command button. A form will be popped up:
- User needs to specify a number in Next Time Field and press OK.
- For this example, Verilog will run 1000 Time Unit and stop.
Example 2:
Force Variable Force ${selVar} = ${Arg:New Value};\n
- User needs to select a signal in the source code window first and then
click this command button. A form will be popped up:
E/D
Rule enable / disable
TOFF
suppressed rule
Rule setting
Rule setting file (.rs)
Default nLint.rs in <nLint_inst_dir>/etc
nLint.rs in user’s home directory
nLint.rs in working directory
The file path in environment variable NLINTRS
The file path in command line option -rs
© 2000, Novas Software
Duplication, reuse or transfer of ownership requires advance written authorization Page 117
reportDB (File -> Save, File -> Save As ...)
Binary database to save complete information
User can load the result into nLint GUI
Default extension name is .rdb
violation list
General violation messages in ASCII format
File -> Export Violation List …
Batch mode: nLint -out <output_file>
Version
This manual supports Debussy 5.0 and higher versions.
Copyright
All rights reserved. No part of this manual may be reproduced in any form or
by any means without written permission of:
NOVAS Software, Inc.
2025 Gateway Place, Suite 480
San Jose, CA 95110 U.S.A.
Trademarks
Debussy is a registered trademark and Knowledge-Based Debugging is a
trademark of Novas Software, Inc.
The product names used in this manual are the trademarks or registered
trademarks of their respective owners.
Restricted Rights
The information contained in this document is subject to change without
notice.
Contents
Laboratory 1 1
Objective ............................................................................................................................. 1
1. Invoke and Quit Debussy.................................................................................. 1
2. Invoke Debussy with Importing a Verilog Design............................................ 2
3. Invoke Debussy with Replaying What You Had Done Before......................... 2
Laboratory 2-1 3
Objective ............................................................................................................................. 3
1. Build Library from Map File. ........................................................................... 3
2. Bulid a Symbol Library from Synopsys .lib File. ............................................. 4
3. View Your Symbol Libraries............................................................................ 4
Laboratory 2-2 7
Objective ............................................................................................................................. 7
1. Import Gate Level Design from File................................................................. 7
2. Set Library's Environment Variables and then Import Design from File again.8
3. Import Design from Library.............................................................................. 8
Laboratory 2-3 11
Objective ........................................................................................................................... 11
1. Import Design from File. ................................................................................ 11
2. Import Design from Library............................................................................ 12
Laboratory 2-4 15
Objective ........................................................................................................................... 15
1. Import Design from File. ................................................................................ 15
2. Import Design from Library............................................................................ 15
Laboratory 2-5 17
Objective ........................................................................................................................... 17
1. Import Mixed-Language Design..................................................................... 17
2. Invoke Debussy with Importing Design from Library.................................... 17
Laboratory 3 19
Objective ........................................................................................................................... 19
1. Compile a Mixed Language Design................................................................ 19
2. Import Design from Library to Debussy......................................................... 19
3. View Hierarchy and Traverse Your Design from Hierarchy Browser............ 20
4. From Source Code Window, You Can View Source Code, Traverse Design and
Trace Signals' Drivers/Loads/Connectivity......................................................... 21
5. Understanding Your Design from nSchema ................................................... 23
6. Understand FSM from nState.......................................................................... 25
7. Quit Debussy................................................................................................... 25
Laboratory 4-1 27
Objective ........................................................................................................................... 27
1. Invoke Debussy with Importing Mixed Language Design from Library. ....... 27
2. Load Simulation Result................................................................................... 27
3. Display Signals' Waveform............................................................................. 28
4. Now We Assume the Transition from 3 to 55 of ALU[7:0] at Time 1051 Was
Wrong and We Have to Find Out the Real Cause(s). ......................................... 28
Laboratory 4-2 33
Objective ........................................................................................................................... 33
1. Invoke Debussy and Load the Gate-Level Design. ......................................... 33
2. The Signal in Question is carry_flag. ............................................................. 33
3. Load Gate-Level and RTL Simulation Results ............................................... 34
4. Display the Waveform of the Instance, carry_flag_reg.................................. 34
5. Compare the Simulation Result ...................................................................... 35
6. Isolate the Problem.......................................................................................... 36
Laboratory 5-1 37
Objective ........................................................................................................................... 37
1. Run Verilog-XL Interactive Mode Simulation ............................................... 37
2. Invoke Debussy with the Verilog Design, then Choose Verilog-XL Simulator for
Running Verilog-XL Interactive Mode in Debussy. ........................................... 38
3. Set Breakpoints, Watch Interested Signals...................................................... 38
4. Run Verilog-XL Simulation............................................................................ 39
5. Re-Run Verilog-XL Simulation ...................................................................... 40
Laboratory 5-2 43
Objective ........................................................................................................................... 43
1. Run NC_Verilog Interactive Mode Simulation............................................... 43
2. Compile and Elaborate the Verilog Design for NC_Verilog .......................... 44
3. Invoke Debussy with the Verilog Design ....................................................... 44
4. Use User-Defined Commands to Run the Simulation..................................... 45
Laboratory 5-3 49
Objective ........................................................................................................................... 49
1. Run ModelSim VHDL Interactive Mode Simulation ..................................... 49
2. Compile and Elaborate the Verilog Design for NC_Verilog .......................... 49
3. Invoke Debussy with the VHDL Design......................................................... 50
4. Use User-Defined Commands to Run the Simulation..................................... 51
Laboratory 1
Objective
This lab is purposed to give you a brief on invoking Debussy. Please execute each action of
"%" below.
STEP 1:
Invoke Debussy.
% Debussy &
Note This action will open an nTrace window. Debussy will open a log directory,
DebussyLog, to keep some information.
They are Debussy.cmd and turbo.log. compiler.log will be opened if you
imported a design into Debussy. You can invoke Debussy by % debussy as
well.
STEP 2:
Quit the invoked Debussy.
STEP 1:
Invoke Debussy.
% debussy -f run.f &
Note This will open a log directory, debussyLog. Under it, there are three log files,
compiler.log, debussy.cmd and turob.log.
STEP 2:
Quit the invoked Debussy.
% File->Exit
STEP 1:
Invoke Debussy.
% Debussy -play Debussy.cmd &
STEP 2:
Quit the invoked Debussy.
% File->Exit
Objective
For your owned or licensed cell libraries, you need to have symbol libraries before importing
your Gate level design into Debussy. With symbol libraries, Debussy recognizes the required
properties, such as, input/output/inout pins, clock and data pins of storage elements, the
control pin of tri-state and mux, etc.
A. <Debussy_Inst_Dir>/share/symlib/default_l.lib++ and
B. <Debussy_Inst_Dir>/share/symlib/default_u.lib++
Under <Debussy_Inst_Dir>/p_symlib directory, there are some built standard cell libraries
for various foundries.
Below contains two examples of library building. Please follow each action of "%".
STEP 1:
Use map2SymDB utility to build a symbol library.
% map2SymDB simple.map
Note This will build simple_l.lib++ with lowercased cell and pin name. Please use -
help option to know map2SymDB's use model.
STEP 1:
Use syn2SymDB utility to build a symbol library.
% syn2SymDB synopsys.lib
Note This will build SIMPLE.lib++, where "SIMPLE" is the declared library name in
synopsys.lib.
STEP 2:
Bulid symbol library and create a map file with a specified library name.
% syn2SymDB -m -o simple_u synopsys.lib
Note This will build simple_u.map, and simple_u.lib++. With -help option, you will
know syn2SymDB's use model.
STEP 1:
Replay the steps those had been done in the lab of importing RTL level design.
% Debussy -play replay.cmd &
STEP 2:
View the built symbol library.
% On the opened Load Symbol form, fill "." in Library Path and "simple_l" in Library
Name, then click OK.
STEP 3:
Quit Debussy.
Note You can quit Debussy from nTrace window only. For other invoked windows,
you can use File->Close to close them.
Objective
Debussy provides two approaches to import your designs:
For Gate-Level Designs, you need to build your owned libraries and set two required
environment variables properly to import your design correctly and view your design in
nSchema. Please execute each action of % below as the labs of Gate level design importing.
STEP 1:
Import gate level design through a pre-prepared run file.
% Debussy -f run.f &
STEP 2:
View the compiled result from Debussy.
STEP 3:
Quit Debussy.
% File->Exit
STEP 1:
Set library's environment variables.
% setenv TURBO_LIBPATHS ../lab2-1
% setenv TURBO_LIBS SIMPLE
STEP 2:
Import gate level design.
% Debussy -f run.f &
STEP 3:
View schematic.
% Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon.
Note On the opened nSchema, you will see the schematic composed by the built
symbols.
STEP 4:
Quit Debussy.
% On nTrace, File->Exit
STEP 1:
Compile gate level design.
% vericom -f run.f
STEP 2:
Import design from pre-compiled library.
STEP 3:
View the schematic view.
% Drag & Drop i_ALUB(ALUB) from Hierarchy Browser to New Schematic icon
STEP 4:
Quit Debussy.
% On nTrace, File->Exit
Objective
This lab is purposed to give you a brief on importing a Verilog RTL design into Debussy.
Please execute each action of "%" below.
STEP 1:
Import design as the same way to run a Verilog simulation (specify all options and source
files on command line).
% Debussy +dump+strength \
../design_src/verilog/src/system.v \
../design_src/verilog/src/pram.v \
-v ../design_src/verilog/src/mem.v \
../design_src/verilog/rtl/TopModule.v \
../design_src/verilog/rtl/ALUB.v \
../design_src/verilog/rtl/CCU.v \
../design_src/verilog/rtl/PCU.v \
../design_src/verilog/rtl/alu.v \
../design_src/verilog/rtl/BJkernel.v \
../design_src/verilog/rtl/BJsource.v
STEP 2:
View the compiled result.
STEP 3:
Quit Debussy.
% File->Exit
STEP 5:
View the imported design.
Note After the action, i_ALUB, i_CCU and i_PCU will be expanded from
i_cpu(CPU).
Note You will see meaningful symbols, such as mux and storage elements in the
opened nSchema.
STEP 6:
Quit Debussy.
% On nTrace, File->Exit
STEP 1:
Compile the Verilog design.
% vericom -f ../design_src/verilog/rtl/run_rtl.f
STEP 2:
Import design from library by the specified library name and root (or top) module.
% Debussy -lib work -top system &
STEP 3:
View the imported design.
STEP 4:
Quit Debussy.
% On nTrace, File->Exit
Objective
This lab is purposed to give you a brief on importing a VHDL RTL design into Debussy.
Please execute each action of % below.
STEP 1:
Import design from a run file.
% Debussy -vhdl -f run.f &
STEP 2:
View the imported design on nSchema.
% On Set Top Module window, double click system to choose it as the top module.
STEP 3:
Quit Debussy.
% File->Exit
STEP 1:
Compile your VHDL design.
% vhdlcom -f run.f
STEP 2:
Import design from library by the specified library name and top architecture.
% Debussy -lib work -top system &
STEP 3:
View the imported design on nSchema.
STEP 4:
Quit Debussy.
% File->Exit
Objective
To import mixed-language design, only importing from library is supported. First, you have
to compile your design into Debussy. Then import your mixed-language design from library.
STEP 1:
Compile Verilog part.
% vericom -f run_verilog.f
STEP 2:
Compile VHDL part.
% vhdlcom -f run_vhdl.f
STEP 1:
Import design from library by specifying the library name and root (or top) module.
% Debussy -lib work -top system &
Note We will have some more detail analysis to understand this mixed language
design later.
STEP 2:
Quit Debussy.
Objective
This lab will give you a brief scenario on design understanding. The design is in mixed
language. Please execute each action of "%" below.
STEP 1:
Compile Verilog source code.
% vericom -f run_verilog.f
STEP 2:
Compile VHDL source code.
% vhdlcom -f run_vhdl.f
STEP 1:
Import design by the specified library and top module.
% Debussy -lib work -top system &
a. On the left side, it's the Hierarchical Browser to show design hierarchy.
b. On the right side, it's the Source Code window to display the design's content.
c. On the bottom, it's the Message window for reporting the result of operations.
STEP 1:
Collapse the design tree of system.
Note "-" will be change to "+". From Source Code window, you can see system is in
VHDL.
STEP 2:
Expand the design tree of system.
STEP 3:
Expand the design tree of i_cpu and change the viewing scope of Source Code window to
CPU module.
Note From Source Code window, you will know CPU is in Verilog.
STEP 4:
Expand the design tree of i_ALUB(ALUB) and change the viewing scope of Source Code
window to ALUB module.
Note On Source View Window, the scope will be changed to ALUB which is a
Verilog module. Also, the tree of i_ALUB(ALUB) was expanded.
STEP 5:
Change the viewing scope to arithlogic.
Note On Source View Window, design scope was changed to arithlogic which is a
VHDL entity.
4. From Source Code Window, You Can View Source Code, Traverse
Design and Trace Signals' Drivers/Loads/Connectivity.
STEP 1:
Jump to the first instantiation.
Note On Source Code window, the design scope had been changed to line 107 of
system. Line 107 is the Verilog instantiation of CPU.
STEP 2:
Jump to the module declaration.
Note Now, the design scope was changed back to CPU module.
STEP 3:
Trace signal's drivers.
Note This action is used to find the drivers of the clicked signal. You can see all the
traced drivers are reported in the Message Window.
STEP 4:
Trace the next or previous drivers in the same design scope.
Note This will jump to the drivers in the same design scope. For this case, it is
i_pram(pram2(pram)).
% Click Show Previous In Hierarchy and then Show Next In Hierarchy icons.
STEP 6:
Jump to the driver's location from Message Window.
Note This will directly jump to the driver you are interested.
STEP 7:
Change the viewing scope to i_cpu.
STEP 8:
Select a signal, data[7:0] bus.
STEP 9:
Add a bookmark.
% Source->Toggle Bookmark
STEP 10:
Trace loads of data[7:0].
Note This will list all of loads that are drove by data. You can do STEP 4 ~ 6 to
jump to the load in the same way as tracing signal's drivers.
% Source->Bookmark->1
STEP 12:
Trace the connectivity of data[7:0].
% Trace->Connectivity
Note This will trace all of connections of data and report them on Message Window.
STEP 1:
Invoke nSchema window.
STEP 2:
Know the content of extracted RTL symbols.
Note A View Source Code window will be opened to show the contents of the
symbol.
Note The respective code of the symbol will be highlighted and selected.
STEP 4:
Jump to the marked bookmark.
% (nTrace)Source->Bookmark->1
STEP 5:
Select data[7:0] bus again.
STEP 6:
Select data[7:0] bus on nSchema.
STEP 7:
Push down the design hierarchy of ALUB
STEP 8:
Pop up the design hierarchy.
STEP 9:
Generate the fan in cone logic of ALU[7:0] bus
% On nSchema, select second output from the top on the ALUB symbol.
Note The fan-in cone logic of ALU[7:0] will be displayed in another nSchema
window. The fan-in cone logic is in flatten mode. Click any extracted symbol
blocks to select them, you will know their design hierarchy.
STEP 1:
Invoke nState from nSchema.
% On the first opened nSchema, click PopView Up icon until it reaches to system level.
STEP 2:
Show states' behave.
STEP 3:
Show the FSM's properties.
STEP 4:
Show the content of a state.
% Drag and Drop ST0 from nState to nTrace's Source Code window to show its content.
7. Quit Debussy
% (nTrace)File->Exit
Objective
This lab will give you a brief scenario on how to debug your design with simulation result.
Please execute each action of "%" below.
STEP 1:
Use the library pre-compiled for the lab of understanding you designs.
% Debussy -lib work -top system &
STEP 1:
Invoke nWave window.
STEP 2:
Load the simulation result.
STEP 1:
Get signals from FSDB's tree structure.
% Click Get Signal icon and then select some signals and OK.
STEP 2:
Get IO boundary of i_ALUB.
STEP 1:
Annotate the simulation result onto nTrace's Source Code window.
% (nTrace)Source->Active Annotation
STEP 2:
Find out where is the transition from.
Note This action will show you the active drivers of the signal at the transition on
nTrace's Source Code window. For this example, it's line 96 of
i_alu(arithlogic(arithlogic)).
STEP 3:
Calculate VHDL variables' value. (So far, none of VHDL simulators provide functions to
dump VHDL's variables).
STEP 4:
Find out all drivers of result.
Note There are 14 drivers reported on the message window. It will be time
consumed if we trace back the logic of all drivers. Will you do that? Let's find
the real active drivers to reduce the efforts dramatically.
STEP 5:
Find the real driver (active trace) of result (Please note, the time is 1051 ns now.).
Note RMB means click the Right Mouse Button. Now, result in line 65 was selected.
It means the real driver is coming from this line.
Note There will pup-up a warning message since the time was changed back by
1ns. The changed back was resulted from the delay of after 1 ns; in line 96.
STEP 6:
Find the real drivers of the traced real drivers.
% Select a_var which is the real driver of result and RMB->Active Trace to find out the
real driver of a_var.
% Select "a" which is the real driver of a_var and RMB->Active Trace to find out the
real driver of "a".
Note signal "a" will be changed name to "X0" in ALUB.v since the design
connectivity.
STEP 7:
Generate the Fan-In Cone for "IDB".
% Select "IDB" in line 80 on Source Code window and then Tools->New Schematic-
>Fan-In Cone
Note An nSchema is opened with the logic driving "IDB". You can select some
blocks to know they are from different hierarchy and in flatten mode.
STEP 8:
Annotate simulation result on the generate Fan-In Cone window.
% (nSchema)Schematic->Active Annotation
STEP 9:
Analyze the generated Fan-In Cone to find the real cause. Please zoom into regions those
you want to know the value of nets detailly by yourself.
% IDB is driven by a MUX, so you have to know the value of the select line in order to
know which input is active. The select line is 0 now, so the first (the topest) input is what
we need to concentrate in advance.
% The top input of the MUX is coming from a storage element. Double click the input pin
of the storage element to trace the logic back. It is another mux with the select line value
is 1.
Note Fan-In Cone will stop at storage elements, functional blocks, FSMs and
primary IOs.
% Double click at the second input of the MUX, it's a functional block.
% Double click at the input of the functional block, it's the logic drove by a tri-state.
% Select the output of the tri-state and then, generate another Fan-In Cone to make
schematic more clean by Tools->New Schematic->Fan-In Cone.
% On the newly opened nSchema, it's schematic with the output is drove by a tri-state
and memory component.
STEP 10:
Analyze the memory's content to know what resulted in the transition (from 3 to 55 of
ALU[7:0]).
Note You can step through time and see the memory values change.
% Steps forward or backward on the memory content window until time is 900ns.
Note On the second Fan-In Cone schematic window, you can see the output value
is 34->55 which is 55 coming from. This is the cause of ALU[7:0] changing
from 3->55. (If you step forward on the memory content window again, the
time will shift to 1200ns that is not the cause since the timing is wrong.)
Objective
This lab will give you a scenario on how to debug your design when you find un-matches
between RTL and Gate-Level simulations. Please execute each action of "%" below.
STEP 1:
Build Gate-Level symbol library.
% syn2SymDB synopsys.lib
STEP 2:
Set environment variable for the built symbol library.
% setenv TURBO_LIBPATHS .
% setenv TURBO_LIBS SIMPLE
STEP 3:
Compile the Gate-Level design.
% vericom -f run.f
STEP 4:
Load the compiled design.
% Debussy -lib work -top system &
STEP 1:
Find carry_flag through a string search.
STEP 2:
On the nTrace's message window, you can find carry_flag is the output of carry_flag_reg.
STEP 1:
From nTrace, invoke an nWave.
STEP 2:
Load Gate-Level simulation result.
% (nWave)File->Open->gate.fsdb
STEP 3:
Open another nWave from the opened nWave.
% (nWave)Tools->New Waveform
STEP 4:
From the newly opened nWave, load the RTL simulation result.
% File->Open->rtl.fsdb
STEP 1:
Drag&Drop the instance carry_flag_reg to both nWave windows.
STEP 2:
Tile and synchronous both nWave windows.
STEP 1:
Select carry_flag on both nWave windows.
STEP 2:
Compare the simulation result.
Note One error was reported and the Search By toolbar will be changed to Search
By Mismatches.
STEP 3:
Locate the mismatch.
Note The input to the register in Gate-Level design (carry) changes right around the
clock edge to cause the mismatch.
STEP 1:
Show active driver of carry in nTrace.
STEP 2:
On nTrace, generate Fan-In Cone for carry.
Note It will take couple seconds since the Fan-In Cone is big.
STEP 3:
Since there are too much logic, we need to reduce it to easily analyze.
% On the Gate-Level nWave, select carry and the rising edge, then Tools->Active Fan-
In Cone, specify 10ns in Back Trace Time Period, then click Apply button.
Note Now, the Fan-in cone logic had been reduced and it is very clean for you to
do further analyses.
Objective
This lab will give you a scenario on how to control your Verilog-XL simulation in Debussy.
Before your start, modify ../../SOURCEME to set your working environment properly. In this
lab, Solaris2 platform will be taken as the working platform. Please execute each action of
"%" below.
a. CDS_INST_DIR, and
b. DEBUSSY_INST_DIR
STEP 1:
Generate shared libraries for linking PLIs
% source ../SOURCEME
% cr_vlog_sol2_dym
Note Two shared library libpli.so and libvpi.so will be created. For different
platforms, the configured file and the generate shared libraries will be
different. Take HP as an example, it will generate libpli.sl and libvpi.sl.
STEP 2:
Add the path of the shared library to LD_LIBRARY_PATH environment variable.
% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib
% setenv LD_LIBRARY_PATH \
.:$CDS_INST_DIR/tools.sun4v/lib:$LD_LIBRARY_PATH
STEP 1:
Invoke Debussy with the Verilog design.
% Debussy -f run.f &
STEP 2:
Choose the simulator to Verilog-XL and control the simulation to stop at 0 initially and
remember the Breakpoints.
% Tools->Options->Preferences->Simulation->Verilog-XL
% Click OK button.
Note If you run the simulation under the same directory, the setting will be kept until
you modify it. (The setting is kept in ./debussy.rc file.)
STEP 3:
Change Debussy's working mode to interactive mode.
% Tools->Interactive
STEP 1:
Set a line breakpoint.
Note If you double click in line 78 on Source Code Window, this won't set the line
breakpoint successfully.
STEP 3:
Set Time-based breakpoint.
% Fill in 350 in Time Field and click Break At Absolute Time button.
STEP 4:
Watch some interested signals.
% Tools->Watch Signals
STEP 1:
Compile the design.
Note You will see the design was compiled for Verilog-XL and some information,
such as, opened verilog_i.fsdb and the pre-set breakpoints on message
window. In Watch window, value of the watched signals is NF.
STEP 2:
Continue the Simulation.
% Source->Active Annotation
Note The value of all signals are NF (Not Found) since The simulation didn't start
yet.
Note The simulation still stop at 25 ns since the breakpoint, alu_mode changed
from X to 0, occurred.
Note It stooped at 550 ns which was caused by alu_mode[2:0] was changed from 0
to 3.
Note The simulation is terminated since it reaches 12500ns. The obviously declared
finish time in line 70 of system.v.
STEP 1:
Compile the design.
% Source->Active Annotation
Note The simulation will stop at 350, the time-based breakpoint since the
breakpoint of alu_mode[2:0] had been removed.
Note The simulation is terminated since it reaches 12500ns. The obviously declared
finish time in line 70 of system.v.
STEP 3:
Quit Debussy.
% File->Exit
Objective
This lab will give you a scenario on how to control your NC_Verilog simulation in Debussy.
Before your start, modify ../../SOURCEME to set your working environment properly. We
will use Solaris2 platform to go through the lab. Please execute each action of "%" below.
To execute Makefile to generate shared libraries, you have to source ../../SOURCEME or set
the correct environment variable for
a. CDS_INST_DIR
b. INSTALL_DIR, and
c. DEBUSSY_INST_DIR
STEP 1:
Generate shared libraries for linking PLIs.
% source ../SOURCEME
% make -f Makefile.sun4v shared_libs
Note Two shared library libpli.so and libvpi.so will be generated. For different
platforms, the customized options in Makefiles and the generate shared
libraries are different. Take HP as an example, it will generate libpli.sl and
libvpi.sl.
STEP 2:
Add the path of the shared libraries to LD_LIBRARY_PATH environment variable.
Note For ncxlmode and ncverilog executable, you have to use the same flow to link
the provided PLI.
STEP 1:
Prepare NC_Verilog working environment.
% ncprep -f run.f +overwrite
STEP 2:
Compile Verilog design with -LINEDEBUG option to enable line breakpoint and show
current position.
% ncvlog -f ncvlog.args -LINEDEBUG
STEP 3:
Elaborate Verilog design with -access +r to set default access visibility.
% ncelab -f ncelab.args -access +r
Note We won't run ncsim here since we will control the simulation in Debussy.
STEP 1:
Invoke Debussy with the Verilog design.
% Debussy -f run.f &
% Tools->Options->Preferences->Simulation->NC-Verilog
% Click OK button.
Note If you run the simulation under the same directory, the setting will be kept until
you modify it. (The setting is kept in ./debussy.rc file.)
STEP 3:
Change Debussy's working mode to interactive mode.
% Tools->Interactive
STEP 1:
Start the simulation.
STEP 2:
Open nWave window.
STEP 3:
Edit User-Defined Commands.
% On the Editing form, click the left side of the secondary line
% Type Next 500 Time and then Enter key to change command from Next 1000 Time
to Next 500 Time
% Type run 500 -relative\n and then Enter key to change command from run 1000 -
relative\n to run 500 -relative\n
STEP 4:
Add a User-Defined Commands.
% On the Editing form, click the left side of the bottom line
% Click OK
STEP 5:
Run the Verilog Simulation.
Note The simulation time is going to 500 ns and waveform of the displayed signals
is changing.
% Click Next > Time button and fill in 25, then OK.
STEP 6:
Finish the simulation.
STEP 7:
Terminate the simulation.
% Simulation->Finish
STEP 8:
Quit Debussy.
% File->Exit
Objective
This lab will give you a scenario on how to control your ModelSim/VHDL simulation in
Debussy. Before your start, modify ../../SOURCEME to set your working environment
properly. Then execute each action of "%" below.
a. DEBUSSY_INST_DIR, and
b. MTI_HOME
STEP 1:
Link the provided FLI shared library to ModelSim by adding the path of the provided FLI to
LD_LIBRARY_PATH.
% source ../SOURCEME
% setenv LD_LIBRARY_PATH \
$DEBUSSY_INST_DIR/share/PLI/modelsim_fli53/SOLARIS2
% setenv LD_LIBRARY_PATH /usr/dt/lib:/usr/lib:$LD_LIBRARY_PATH
STEP 1:
Use vlib to create work and novas library directories.
% vlib work
Note If work/ directory existed, please use rm -rf work to remove it.
% vlib novas
STEP 2:
Use vcom to compile design into modelsim's library directories.
% vcom -f run.f
% vcom -work novas ../design_src/vhdl/src/novas.vhd
STEP 1:
Compile the VHDL design into Debussy library.
% vhdlcom -f run.f
STEP 2:
Invoke Debussy with the VHDL design.
% Debussy -lib work -top system &
STEP 3:
Choose the simulator to ModelSim and control the simulation to remember the breakpoints on
next simulation.
% Tools->Options->Preferences->Simulation->ModelSim
% Click OK button.
Note If you run the simulation under the same directory, the setting will be kept until
you modify it. (The setting is kept in ./debussy.rc file.)
STEP 4:
Change Debussy's working mode to interactive mode.
% Tools->Interactive
STEP 1:
Start the simulation.
STEP 2:
Open nWave window.
Note Some signal's value are U or UU those are the initialized VHDL values.
STEP 3:
Run the VHDL Simulation.
Note The simulation time is going to 1000 ps since the time unit defined in
modelsim.ini is 1 ps.
% On the Message Window, in the VSIM n> prompt, keyin run 12500 ns, then return
STEP 4:
Terminate the simulation.
% Simulation->Finish
STEP 5:
Quit Debussy.
% File->Exit