Fundamental Logic Design

Instructor: Dr. Thuy T. Le, Professor & Associate Chair

Electrical Engineering Department
San Jose State University, California, U.S.A.
Email: Thuy.Le@sjsu.edu
Office Hours: Monday through Thursday: 11:30AM - 12:00PM (205-D6)
Class Days: Tuesday January 04 through Monday January 17, 2011 (10 meetings)
Class Time: 07:35AM - 08:20AM: Lecture (304-D6)
08:20AM - 08:30AM: Break
08:30AM - 09:15AM: Lecture (304-D6)
09:15AM - 09:20AM: Break
09:20AM - 10:05AM: Lecture (304-D6)
10:05AM - 10:15AM: Break
10:15AM - 11:30AM: Lecture (304-D6)
Examinations: Midterm 1: Thursday January 06, 01:00PM – 02:00PM
Midterm 2: Tuesday January 11, 01:00PM – 02:00PM
Final Exam: Monday January 17, 10:15AM – 12:15PM
(Note: On Monday January 17, the last lecture will end at 10:05AM)

Course Description
This course introduces the students to basic theory and techniques to design digital systems that
consist of logic circuits, the components of digital systems, and how these components are
interconnected to form the whole digital systems. The course provides a thorough background, at
the introductory level, of the logical (mathematical) and electrical basis for digital system design.
Major building blocks for designing digital systems will be examined and used, which include
basic gates, MUXes, DEMUXes, decoders, encoders, various arithmetic blocks, latches, flip-
flops, counters, registers, RAMs/ROMs, PLAs, PALs, and FPGAs. Students will also learn to
design digital circuits using schematic and Verilog Hardware Description Language (HDL). This
course is the gateway to all other digital system courses in the electrical and computer
engineering curriculum.

Student Learning Objectives

Upon successful completion of this course, students will be able to:
1. Understand the number system, including binary, octal and hexadecimal numbers, and
complement number representation.
2. Understand Boolean algebra and to apply various Boolean theorems to prove Boolean
identities and to simplify Boolean functions.
3. Understand the transistor-level structure of TTL and CMOS logic gates and their electrical
and timing characteristics.
4. Construct the K-map from a Boolean expression and to find the minimal SOP/POS forms.
5. Design some arithmetic and logic circuits including and to evaluate the resulting performance

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6. Use MSI devices such as decoders, encoders, multiplexers, etc. to design various logic
circuits.
7. Understand the behavior, timing issues, and internal structure of cross-coupled gates, latches,
flip-flops (RS, JK, D and T) and registers.
8. Identify and prevent various hazard and timing problems.
9. Analyze and design various flip-flop-based state machines (synchronous sequential circuits),
including registers, counters, and controller circuits.
10. Understand how ROM, RAM, PLA, PAL, and FPGA work and how to use them to design
complex logic circuits.
11. Model various logic circuits with Hardware Design Language (HDL) and to use CAD
software and instruments to debug, test, and evaluate their performance

Required Text
Fundamental Digital Design, Lecture Note by Thuy T. Le, San Jose State University, California,
U.S.A. (available for students to download)

Course Textbook
Digital Design (4th Edition), M. Morris Mano and Michael D. Ciletti, International ISBN-10:
0131989243 (ISBN-13: 9780131989245), Prentice Hall, 2007

Assignments and Grading Policy

Lectures
The course will follow the selected subjects as listed on the course description. Please note that
lecture materials are NOT solely based on the required note and textbook, so students are
responsible for following up the lecture in order to prepare themselves for the exams.
Examinations
There will be two midterm exams and one comprehensive final exam for the lecture. The
midterm and final exams are scheduled as shown on the first page of the course syllabus.
− All exams are OPEN-BOOK exams.
− Exams will cover the assigned reading materials and discussed materials in the lectures.
− There will be no make-up exams (in very special circumstances, written excuse and official
proofs are required for making-up exams).
− Exam solutions will be discussed in class. Written solutions will NOT be distributed.
Homework Assignments
− Homework assignments will be given at the end of every lecture and will be due in the
beginning of next lecture. NO late submission will be accepted and there is no make-up
homework
− To get credit for your homework assignments, submissions must be neat, clean, and must be
done professionally and seriously. Your official name (not nickname), course #, and
homework # must be visibly shown on each assignment.
Laboratory and Project Assignments

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The lab/project scores will be counted for 20% in calculating the course grade. The lab/project
scores will be combined with the lecture part to make up the final grade. There will be 4
laboratory/project assignments throughout the course. Lab/project assignments will be done
separately from the lecture and will be arranged after the class started.
Grading Policy
The overall course grades (letter-grades) will be assigned based on the overall class distribution
or grading standard, whichever that is better. If grading standard is used, overall score above
90% will be distributed for A and A+, 80% to 89% will be distributed for B, B+, A-, 70% to
79% will be distributed for C, C+, B-, and 60% to 69% will be distributed for D, D+, C-. If
overall class distribution is used for determining grade, overall scores above class average will
be distributed for C, C+, B-, B, B+, A-, A, A+ and overall scores below class average will be
distributed among C-, D+, D, etc. The weights of work assignments are listed as below:
Homework assignments: 10%
2 midterm exams: 35%
Comprehensive final exam: 35%
Laboratory Assignments: 20%

Tentative Course Schedule

Day Date Topics

1 01/04/2011 Chapter 1 - Digital and Number Systems:

A Brief History of Computers. Radix Positional Number Systems.
Number Base Conversions. Complements for Signed Numbers. Signed
Numbers in Binary Systems. Binary Addition/Subtraction. Binary
Sequential Multiplication/Division. Coding and Code Conversions, Codes
for Non-data Objects. Binary Logic, Register, and Storage.
2 01/05/2011 Chapter 1 (continue)
Chapter 2 - Boolean Algebra and Logic Gates:
Boolean (‘Switching’) Algebra. Representation of Logic Functions. Basic
Theorems and Properties of Boolean Algebra. Axiomatic Definition of
Boolean Algebra. Canonical (Standard) Forms. Other Basic Logic
Operations. Logic Family. NAND-NOR Structures. Alternative
Implementations.
3 01/06/2011 Chapter 2 (continue)
Chapter 3 - Gate-Level Minimization:
Combinational Circuit Analysis. Synthesis and Minimization. Boolean
Algebraic Minimization. The Karnaugh Map Method. Two- Three- Four-
and Five-Variable Maps. Don't-Care Conditions. Quine-McCluskey
Method. Multi-Level Logic. Hazards and Glitches
First midterm exam

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Day Date Topics

4 01/07/2011 Chapter 3 (Continue)

5 01/10/2011 Chapter 4 – Some Combinational Circuits:

Combinational Circuits. Code Converters. Decoders. Encoders.
Multiplexers. De-Multiplexers. Binary Adders/Subtractors. Carry-Look-
Ahead Adder, BCD Adder. Binary Multiplier.
6 01/11/2011 Chapter 4 (Continue)
Second midterm exam
7 01/12/2011 Chapter 5 - Synchronous Sequential Logic:
Overview of Sequential Circuit Devices. Characteristic of Clock Signal.
Latches. Flip-Flops. Flip-Flops Implementations. Finite State Machines
(FSM). Sequential Circuit Analysis. State Tables and State Diagrams.
State Minimization. Alternative State Machine (ASM). State Assignment.
8 01/13/2011 Chapter 5 (Continue)
Chapter 6 - Registers and Counters:
Registers (register with control signals, register transfer, shift register,
serial adder.) Counters (ripple binary counter, BCD ripple counter,
synchronous binary counter, synchronous BCD counter.) Implement
Counters with Different Flip-Flops
9 01/14/2011 Chapter 7 - Memory and Programmable Logic:
Random-Access Memory. Memory Decoding. Read-Only Memory.
Programmable Logic Array (PLA). Programmable Array Logic (PAL).
Field Programmable Gate Array (FPGA).
10 01/17/2011 Chapter 8 – Verilog HDL in Digital Design – An Overview:
Role of HDL in Digital Design. ASIC Design Flows. Software Model vs.
Hardware Model. Verilog Behavioral and Structural Languages. Verilog
Primitives and User Defined Primitives. Verification and Testbench.
Propagation Delay. Continuous Assignment Statement. Edge- and Level-
Triggered Cyclic Behavior. Non-blocking and Blocking. Coding for
Synthesis. Some Design Examples.
Final exam

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