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I t d ti

Introduction
(Computer) Organization – refers to the
Advanced Computer logical
g aspect
p of the implementation
p
Organization Architecture – refers to a computer’s
structure and behavior independent of the
implementation
Lecture
ectu e 1: Implementation – refers to logical and
Introduction physical design techniques used to realize the
Performance different aspects of a computer’s
computer s architecture

University of the Philippines Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

Hi t
History (1/2) Hi t
History (2/2)
I. FIXED POINT FORMAT III INCREASE IN ADDRESSING MODES AND
VERY LIMITED INSTRUCTION INSTRUCTION SET SIZE
S ((IBM))
SET MULTIPLE USER
USER-PROGRAMMABLE
PROGRAMMABLE REGISTERS
CACHE MEMORIES
PIPELINING
II. LONGER INSTRUCTION FORMATS (DEC, DATA GENERAL)
INCLUDE FLOATING-POINT
FLOATING POINT FORMATS IV RISC
USE OF INDEX REGISTERS MULTIPROCESSORS FOR
DRAMATIC INCREASE IN SIZE OF INSTRUCTION SET PARALLEL PROCESSING
IOP’s AND SECONDARY MEMORIES (APOLLO, SUN, SILICON
(NCR, Honeywell, Burroughs) GRAPHICS, APPLE)
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
Classic Components of a
R idl changing
Rapidly h i field…
fi ld
Computer
Vacuum tube… transistor… IC… VLSI Input
Doubling every 1.5 years: Output
Memory Memory – storage for programs being run
capacity Datapath – performs the arithmetic and logic
Processor operations of the processor
speed
Controll – determines
d h the
what h datapath,
d h
memory and I/O devices will do according to
the
h instructions off the
h program

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

L
Levels
l off Abstraction
Ab t ti M j Computer
Major C t Design
D i Levels
L l
principal technique for designing very Design Components Information Time Units
sophisticated
p computer
p systems
y Level Units

lower levels reveal more information Processor CPUs, IOPs, Blocks of 10-3 – 103 s
memories, IO words
simpler model at higher levels devices
Register Combinational Words 10-9 – 10-6 s
and simple
sequential
circuits
Gate Logic gates, Bits 10-10 – 10-8 s
flipflops
p p
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
Instruction Set Architecture Instruction Set Architecture
(ISA) (1/2) (ISA) (2/2)
one of the most important abstractions Advantages
interface between hardware and lowest level can have different implementations
p of the same
of software architecture
implementations of varying cost and performance
standardizes instructions
instructions, machine language run identical software
bit patterns, etc.
Disadvantage
sometimes prevents using new innovations

Modern ISAs: 80x86/Pentium, K6, PowerPC,


DECAlpha, SPARC, HP
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

E i
Engineering
i Design
D i Problem
P bl S l ti
Solutions
Given a desired range of behavior and a set MASS MARKET vs. SPECIALIZED
of available components,
p determine a low cost MARKET
structure formed from these components that high performance
achieves the desired behavior at an
acceptable cost.

Solutions may have (approx.) the same


architecture but differ in cost, depending
p g on
the method and cost of implementation.

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
P f
Performance S
Specifications
ifi ti D fi iti
Definitions off Performance
P f (1/3)
1) The computer should be capable of executing a
RESPONSE TIME
instructions of type b per second. time between the start and completion
p of an
event
2) The computer should be able to support c I/O execution time
devices of type d. latency (refers to the time delay to access
memory)
3) The computer should be hardware and/or
software compatible with computers of type e.
How long does it take for my job to run?
4) Total cost of the system should not exceed f. How long must I wait for the database query?

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

D fi iti
Definitions off Performance
P f (2/3) D fi iti
Definitions off Performance
P f (3/3)
THROUGHPUT RESPONSE TIME used when an entire
EXECUTION TIME computing task is
total amount of work done in a g
given time
THROUGHPUT discussed
bandwidth

How many jobs can the machine run at once? LATENCY used when discussing a
BANDWIDTH memory system
What ag execution
a is the aaverage u o rate?
a
How much work is getting done?
PERFORMANCE = 1
EXECUTION TIME

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
M
Measuring
i Performance
P f (1/2) M
Measuring
i Performance
P f (2/2)
RESPONSE TIME / ELAPSED TIME CPU TIME
latencyy to complete
p a task USER CPU TIME - time the CPU spent p executing
g
includes disk accesses, memory accesses, I/O lines of code that are in the program
activities, OS overhead, etc. SYSTEM CPU TIME - time spent in the operating
CPU TIME system performing tasks requested by the
program
time the CPUU spent
p in the program.
p og a Does
o not
o
include I/O, nor time spent running other
programs.

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

CPU Performance
P f (1/4) CPU Performance
P f (2/4)
CPU EXECUTION TIME FOR A PROGRAM/ CPU CPI (CLOCK CYCLES PER INSTRUCTION)
TIME = CPU CLOCK CYCLES FOR A PROGRAM
= CPU CLOCK CYCLES FOR A PROGRAM
* CLOCK CYCLE TIME INSTRUCTION COUNT
= CPU CLOCK CYCLES FOR A PROGRAM CPU TIME
CLOCK RATE = INSTRUCTION COUNT * CPI *
CLOCK CYCLE TIME
CPU CLOCK CYCLES = INSTRUCTIONS FOR A = INSTRUCTION COUNT * CPI
PROGRAM * AVE. CLOCK CYCLES PER CLOCK RATE
INSTRUCTION
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
CPU Performance
P f (3/4) CPU Performance
P f (4/4)
n

CPU CLOCK CYCLES = Σ (CPIi x Ii) Overall or Weighted Ave. CPI:


n

Σ (CPI
i=1
C =
CPI (C i x Ii)
Ii ⇒ number of times instruction i is i=1
Instruction Count
executed in a program n

CPIi ⇒ ave. number of clock cycles for instruction i = Σ [(CPIi


i=1
x Ii)/ Instruction Count]
n

CPU TIME = Σ (CPIi


i=1
x Ii) x CLOCK CYCLE TIME Must include cache misses and other
memory system inefficiencies.

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

D
Dependencies
d i A d hl’ Law
Amdahl’s L (1/2)
ALGORITHM ⇒ instruction count, possibly performance improvement to be gained from
CPI using some faster mode of execution is
li it d b
limited by the
th fraction
f ti off ti
time the
th faster
f t
PROGRAMMING LANGUAGE ⇒ instruction mode can be used
count, CPI
COMPILER ⇒ instruction count, CPI Speedup = Performance for entire task using
INSTRUCTION SET ARCHITECTURE ⇒ th enhancement
the h t when
h possible
ibl
instruction count, clock rate, CPI Performance for entire task without
HARDWARE ORGANIZATION ⇒ CPI, CPI clock
l k using
i the
th enhancement
h t
rate
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
A d hl’ Law
Amdahl’s L (2/2) S
Speedup
d
Speedup = Execution time for the entire task Execution tnew= Execution told *
without using
g the enhancement ((1 – Fraction Enhanced)) + Fraction enhanced))
((
Execution time for the entire task Speedup enhanced
using the enhancement when
possible Speedup Overall = Execution told
Execution tnew

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

R
Recall:
ll Example:
l Improving
i Performance
f
Dependencies of CPU time: Our favorite program runs in 10s on
clock rate computer A, which has a 400MHz clock. A
CPI
d i
designer wants
t to
t bbuild
ild machine
hi B that
th t will
ill
run this program in 6s. He has determined
instruction count
that a substantial increase in clock rate is
“When comparing two machines, you must possible but this increase will affect the rest
consider all three components to understand of the CPU design
design, causing machine B to
relative performance.” require 1.2 times as many clock cycles as
machine A for this pprogram.
g What clock rate
should you tell the designer to target?

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
Example: Comparing Code
Example:
l Comparing
C i Performance
f
Segments (1/2)
Suppose we have two implementations of A compiler designer is trying to decide
the same instruction set architecture. between two code sequences
q for a particular
p
Machine A has a clock cycle time of 1ns and a machine. The hardware designers have
CPI of 2.0 for some program and machine B supplied the following facts:
has a clock cycle time of 2ns and a CPI of 1.2 Instruction class A: CPI = 1
for the same program. Which machine is Instruction class B: CPI = 2
faster for this program, and by how much? Instruction class C: CPI = 3

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute

Example: Comparing Code


Oth Metrics
Other M t i (1/2)
Segments (2/2)
For a particular high-level language statement, the MIPS
compiler writer is considering two code sequences Million instructions p
per second of a given
g program
p g
that require the following instruction counts:
MIPS = Instruction count = Clock rate
Code Instruction counts for instruction class Execution time*10 6 CPI * 106
sequence A B C
Problems:
1 2 1 2
MIPS is dependent on the instruction set of the
2 4 1 1 computer
MIPS varies between programs on the same computer
Which code sequence executes the most
instructions? Which will be faster? What is the CPI for
each sequence?
University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute
Oth Metrics
Other M t i (2/2)
Instruction mix
measure of the dynamic
y frequency
q y of instructions
across one or many programs
affects CPI

University of the Philippines Joy Reyes-Madamba@2010 Electrical and Electronics Engineering Institute