TT26 SmartPowerAnalog V18b Zitta PDF

TT 26 Smart Power Analog
Technical
Training
Villach
Overcurrent
Overvoltage
on Overtemperature
Open load
feedback- measure
loop
switch - off
latch
reset
Vers. 18-b
June 2008
Heinz Zitta
H.Zitta
IFAT –AIM
Smart
AP Power Analog
COMPANY CONFIDENTIAL Intellectual Property of Infineon Technologies 1
Contents
0. Introduction
1. Overview of Smart Power Technologies
2. Components SPT 5, SPT 4
3. Basic Analog Circuits & Examples of realized circuits
3.1 Current Mirrors, Current Sources, Bias Concepts, Delay circuits
3.2 Voltage Reference – Bandgap Circuits
3.3 Comparators, Opamps
3.4 Diagnostic & Protection Circuits
3.5 Driver Circuits Lowside, Highside
3.6 Chargepumps & Oscillators

3.7 Linear Voltage Regulators
4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 2
Introduction
n The goal of the course is to present and to explain basic analog
circuits which are often used in analog smart power designs.
n The presentation will be as simple as possible because all more
complex circuits are based on simple circuits – but anyway there will
also be presented real circuits without simplification.
n Today many Smart-Power designs for automotive application in
production uses the SPT technology – a BCD (bipolar, CMOS,
DMOS) technology - therefore most examples from real projects will
use components from the SPT – libraries (SPT 4 or SPT5/6).
But the basic ideas of all circuits do not depend on specific
technology and can always be used, depending on avaibility of
bipolar, CMOS or power-DMOS devices in your process.
n Some examples are choosen from projects in SMART technology
(mainly Highside-Switches “Profet”), the new generations of this
technology (SMART 5, SMART 6) offers also bipolar devices
additional to CMOS and (Highside)-Trench-DMOS.
H.Zitta – Smart Power Analog 0 - Introduction 3

Definition of a „perfect“ design ...
(Antoine de Saint-Exupery)

What is a good design?
n A good design is a simple design.
n A good design fulfills the requirements,
but is not too perfect („für Schönheit wird nichts bezahlt“)
n A good design is that design,
which allows high yield in production
n A good design is a design, which you can explain to another how it
works, so that he/she can re-use your circuit
n A good design is a circuit, which is proved in production,
that it works. ( -> reuse recommended)
be careful with the interpretation of: „it works“ – many problems come out
very late e.g. if a customer switches to a new application,
or if fab-line parameters changes, e.g. 6 to 8 inch transfer or a complete
fab-transfer ( Vi -> Rgb, Vi -> Kulim etc. )
Target is always, that :

Electrical parameters will not be changed by any transfer of a technology

What is a good design? (2)
n A good design uses well-known characteristics of the

components as design parameter.
(hopefully documented)
but: no rule without an exception...
Exception to this rule is the use of a leakage-current for temperature
sensing, used and proved by experience in all Profet designs.
But for bipolar and SPT circuits the usage of bipolar base-emitter
voltage, which is a more accurate and well-known parameter, is
recommended (by the way: also first SMART5-designs start to use
bipolar VBE as temperature sensor)
n A good design is proved „by design“ that it is
insensitive to all kind of tolerances (wafer-production,
supply-voltage, temperature) as much as possible and it
should not be necessary to „improve“ it by testing.
A good device will not be altered during testing, so it is really not

„better“ after testing!

According Yield, a “6 Sigma” Design is a Good Design
min max
spec. limit in data sheet
all what you can see,
is inside +/- 3 sigma
parameter variation of (or cpk=1)
an analog circuit
try to have a margin of

6 sigma
3 sigma
faktor 2 to spec limit

99,73%
(cpk=2, 6 sigma)
LSL USL
-> this is then a
Cp=2.0
Cpk=2.0
„robust analog design“
−6σ −3σ µ +3σ +6σ

How to do analog design
1) use an existing cell, circuit, idea as a starting point („reuse“)
2) adapt it to your specification
3) change the circuit and „invent“ new things, if necessary
(reuse does not forbit to search for new solutions)
4) think about all possible application conditions
5) use alle available experience
to guess, to estimate what is not known exactly
6) beside precise equations and lot of simulations,
use Thumb Rules I will try to give you some ...
7) no risc, no fun! the world is analog ...
Content
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 1 - Technologies 9
Smart Power Technologies
Classification according to the isolation technique
device 1 device 2
n Selfisolation
– MOS substrate
n Junction Isolation p-isolation

n-well
– Bipolar p-substrat
– BCD / SPT
insulator
n Dielectric Isolation
– SOI (Silicon on Insulator) substrat

Self-Isolation
+Vdd device 1 device 2
p p p p
n- substrate
It is the simplest solution and is used in any MOS process. Isolation of

neighbouring components is only done by applying the right voltages to the
components in respect to the substrat or well connection. The smart power self-
isolation processes are based on a n-substrate/p-well CMOS approach.
Apply a positive voltage to the n-substrate to allow isolation of p-type devices.

Junction-Isolation
Gnd (-) device 1 device 2
p p n
p p p
iso n- Epi n
p - substrat
This kind of isolation is known from bipolar processes. A n-type epitaxial layer is
grown on a p-type substrat. The components are inside the epi-layer and they are
isolated by revers biased junctions realized by p-diffusions. This kind of smart
power process needs a higher mask count as the self isolation approach, but
gives you more flexibility according the available devices.
The substrate must be connected to GND or to the most negative voltage to
enable the isolation.
Dielectric-Isolation
oxid
device 1 device 2 isolation
p p n
n
n
substrat
This isolation is really done with an insulator (oxid).

It would give the best results in avoiding parasitics and for high voltage capability.
For power circuits you would have to calculate, that the thermal conductivity of
oxid is very low compared to silicon. Due to the fabrication process it is the most
expensive technology and therefore not (yet) the mainstream for smart power
circuits.
Partial Dielectric-Isolation ( Deep Trench Isolation)
oxid
device 1 device 2 isolation
p p n
n
n
p - substrat
A oxid isolation only to separate the n-wells is easier to realize than a fully dielectric
isolation, it could be done with trench etching. The advantage is a smaller chip-size
because of less area wasted für the well-isolation compared to the junction-isolation.
Against substrate there is no advantage related to parasitics („reverse current problem“)
Trench Isolation will be used for new technologies: SPT 7, SMART 6, SPT 9
Self-isolation: CMOS
+ VDD = substrat
+ VDD p-channel n-channel

p-channel
S G D S G D S G D
B
p-
p+
n+
n- Epi
n-channel
n+ Substrat
Drain D
Gate G Bulk Correct

Correctbiasing
biasingof
ofall
allparasitic
parasiticdiodes
diodes
isisnecessary
necessaryto
tomaintain
maintainself-isolation
self-isolation
Source S

MOS: expand voltage capability
low voltage MOS high voltage MOS
p-channel
S G D S G D S G D
p+ L p+ L p+ p- p+
n
drain extension
lightly doped drain, LDD
Higher voltage capability would require longer channels for lateral MOS Devices
-> increasing chip-area, increasing Rds-on
Introduce drain extension as a better solution:

a high-ohmic (low doped) diffusion of same type (n or p) as device typ (n or p-channel)
increase gate-oxid thickness near drain (allows higher drain-gate voltage)
LDD High Voltage Device: Electric Field
VS=0V VG=+5V VD=+50V
Lightly doped drain
extension area reduces
the electric field
strength in the channel
region.
Also called“RESURF“
device
„reduced surface field“
source:
Balan, High voltage devices and circuits
in standard CMOS technologies

Low Voltage and High Voltage Devices
HV-CMOS: can be on the same chip
low voltage high voltage
CMOS MOS
p-Kanal n-Kanal p-Kanal n-Kanal
S G D S G D S G D S G D
B
p-
p+ p+ p- p+
n+ p- n+ n- n+
n- Epi
n+ Substrat
Insert
Insertaalightly
lightlydoped
dopeddrain
draindiffusion
diffusionfor
for
higher
highervoltage
voltagecapability
capability(drain
(drainextension)
extension)
• p- for P-channel device
• n- for N-channel device
Double diffusion MOS = DMOS (lateral DMOS)
High Voltage: Vertical DMOS
S G
Use the epi-layer
as drain extension.
The vertical DMOS is born!

n+
p- p+
d Epi doping and thickness can be
Current flow adjusted to the required
n- epi breakdown voltage versus Rds-on
n+ substrate thumb-rule:
thumb-rule: dd==11um
umeach
each10
10VV
Drain Drain = Substrat +
Gate
Source
Current-flow in high voltage devices
S G D S G
n+
p- p+
p- n+ n- n+
Drain = Substrat
Lateral: channel & drift-region
Lateral: channel
Vertical: drift region
Selfisolation: Vertical SMART Power Technology
low voltage high voltage vertical DMOS
CMOS MOS Power Transistor
p-channel n-channel p-channel n-channel
S G D S G D S G D S G D S G
B
p-
p+ p+ p- p+ p- n+p+
n+ p- n+ n- n+
n- Epi
n+ Substrat
Source D + Vbatt Drain = Substrat
+
Gate G Bulk Drain
Drainof
ofPower-DMOS
Power-DMOS
always
alwaysconnected
connectedtotosubstrat
substrat Gate
S ==backside
backsideofofchip
chip
Drain
Source
From Lateral to Trench-DMOS
for further R-on*Area reduction
Lateral High-Voltage MOS Vertical Trench DMOS
S D
S G
vertical
channel
vertical
p- n+ n- n+ drift region
lateral lateral
D
channel drift region

Trench Power-Transistor (SMART5)
Powermetal
(Aluminum)
Source
Channel
Poly(Gate)
Complete
Completevertical
vertical
current
currentflow
flow
Drain
SMART5
Improved Selfisolation: MOS + Bipolar + Vertical Trench DMOS
Low Voltage MOS High Voltage MOS Isolated Bipolar Vertical power
Lateral Transistors Lateral Transistors Vertical Transistors Transistor
P-MOS N-MOS HV-P-MOS HV-N-MOS NPN PNP trench DMOS

G G G G G
S D D S S D S D B E C B E C S/B S/B
p+ p+ n+ n+ p+ p+ n+ n- n+ p+ n+ n+ n+ n+
p-diode
n+ n+
p-body p-body
n-well cp-well
cp-well p-well p-well
n+
p-iso-well
n-epitaxial layer SMART
p-iso-well
5
p-iso-well
trench
n+ Substrate Drain

Junction Isolation: Bipolar Technology
Bipolar
npn-Transistor pnp-Transistor (lateral)
C B E B C E
n+
p
n- epi-layer p+ n- p+ n- p p+
n+
p substrat
Isolation sinker buried layer

C B E E
All B C
Allcomponents
componentsare areinin
n-epi-wells,
n-epi-wells,isolated
isolatedby by
p+
p+isolation
isolationdiffusions
diffusions

Junction Isolation:
„Updrain“-Smart Power Technology BCD, SPT
DMOS
CMOS Bipolar Vertical "Updrain"
p-channel n-channel npn-Transistor Power Transistor
S G D S G D C B E D S G
B B
p- n+
p
p+
p+
p+ p- n+p+
n+ n- p+ p+
n- Epi
n+ n+
p Substrat
at GND level (-) Isolation sinker buried layer

Drain: no restrictions
S
p-channel C
D
B Gate
D
n-channel E
S Source
Vertical DMOS Cross-section (BCD)
Isolation is done with two

implantations:
Bottom isolation implanted
before growing the epitaxial
layer, top isolation implanted
from surface
Source: Smart Power Ics, Technologies and Applications, B. Murari et al (eds), Springer Verlag 1995, ISBN 3-540-60332-8

Available Components of Different Technologies
CMOS BIPOLAR Vertical Vertical BCD

Components Smart Smart
Self- Junction- Self- Improved Junction
Isolation Isolation Isolation Self-Isolation Isolation
npn X X X
Substrat-npn (X) (X)

Bipolar (C = Substrat)
pnp X X X
P-channel X X X X
Low Voltage
CMOS N-channel X X X X
P-channel X X X
High Voltage
MOS N-channel X X X
N-ch. vertical X X
Power Drain = Substrat
DMOS N-Kanal X
„updrain“
Possible Power Output Configurations with
Integrated Smart Power Technologies
High-Side Low-Side Half-

Switch Switch Bridge H - Bridge
+ Vs
Self-Isolation only 1 channel

Vertical Smart
ü ü
- -
Junction Isolation
BCD, SPT
ü ü ü ü
Examples of Smart Power ICs for Automotive Applications
Smart Power Switches Smart Power System ICs
Vertical Smart Technology Chip on chip

SPT (BCD) Technology Chip by chip SPT (BCD) Technology
Profet Highside Switch: Vertical SMART Technology
(S-Smart)
DMOS
2 x 90 mOhm
12 A / 60 V
Analog MOS
Diagnostic
Protection

PROFET: 2 Chips = 4 Channels in one package
4 x 35mOhm
BTS 737 S2

Multichannel Highside-Switch with SPI: SPOC (Smart 5)

Multichannel Lowside Switch: SPT Technology (SPT4)
Analog:
Driver,
diagnostic and
Protection
CMOS Logic
DMOS
S 946 / TLE 6220 4 x 400 mOhm / 3A / 60V

Optimized Packaging: Realisation of a H-Bridge
High-Side:
Drain = VBAT = positive supply
well suited for Vertical Smart Technologie
Drain Drain
High-Side HS
LS: Source = GND

Source Low-Side LS
Drain = OUT Source
not possible in vertical techn.
On-chip Integration of both Highside and Lowside Power-DMOS is only possible in

Updrain Technologie (SPT, BCD)
Disadvantage: Rds-on is higher compared to vertical Smart-technology at same chipsize

Multi-Chip Packaging as Optimal Solution for High-Power H-Bridges
Hig
h-
Sid
e
FE -Sm
T art
-
Lowside-
MOSFET
„TRILITHIC“

Realisation of a Low Ohmic Smart Power Switch ( < 20 mOhm)
Including Full Protection and Diagnostic
a) monolithic solution: include power DMOS on same chip search for
b) multichip solution: smart circuit & power transistor cost optimum
4
+ V bb
Voltage Overvoltage Current Gate
source protection limit protection
V Logic
OUT 6, 7
Voltage Charge pump Limit for
unclamped IL
sensor Level shifter ind. loads Current
3 IN Rectifier Sense
Output
Voltage Load
ESD Logic detection
1 ST
R
O
Temperature
sensor
GND
5 IS
I IS

R GND PROFET
IS
2 Load GND
Signal GND

Multi Chip Packaging Example: Chip on Chip
Chip on Chip
Monolithic
Power Switch
Power Switch
Costs
On State Resistance
Chip on Chip Monolithic
Power-Transistor
Control / Top-Chip
Base-Chip

Smart Highside Switch
Comparison of two devices with same RDS-On (12 mOhm)
Chip on Chip solution Monolithic device
Smart control chip is glued

on top of power transistor

Chip on Chip
High Current Profet

U 6003
SPT6 control-chip
(S1274)
on top of
SFET 3
(L8275)
6 mOhm

Smart Ignition IGBT
Challenge: to combine IGBT and Smart Technology
BTS 2145 12 V
BTS 2140 VFL
SSD VS
Features: Top Chip OUT GND

• Vclp = 400 V
Base Chip
• Ic, max = 9 ... 15 A
• Tj,max = 175°C Protection,
IN
• Current limitation Limitation
• Current Feedback
• Voltage Feedback
• ESD Protection
• Soft Shutdown IFL Current feedback
• PT- IGBT Process

• µC compatible Input
GND

Example Chip on Chip: Smart IGBT = IGBT(base) + SPT4(top)
BTS 2145
400 V / 15 A switch
with current feedback
and overtemp. protection
Chip-on chip packaging

allows to integrate also
“Smart” functionality in
power switches which
would not be possible to do as a monolithic chip
High-Integration of 16 Power Switches for
new Generation of Engine Management Platform
High pincount power package
Highintegration
• Reduced Board Space
• Reduced Devices for Assembly
• Reduced Overall Package Costs
• Increased Reliability
System-Integration of an ABS System On Chip
All analog, digital and
power functions can be
integrated in one
smart power chip
(exluding the µ
microcontroller)
µ
Includes:
Sensor-Interface
CAN Tranceiver
Voltage regulator 5V
Voltage regulator 3V
Control-logik
Watchdog for ext. uC
Power Switches
Diagnostic functions
System Integration of an Airbag-System
Two on-chip integrated DC/DC converter to allow supply of electrical
airbag firing in case of a loss of battery during car accident
Boost Conv. 12v -> 30 V (Store in Capacitor ) Buck Conv. -> 5 V
12V
Input Serial Control

Buck Interface Interface Unit
and
Boost Airbag Power ASSP
Con- Squib
verter Diagnosis
5V 30V
Optional
IASG Outputs
curr./volt.
Microcontroller
ISO 9141 Diagnostics (e.g. C164CG-xFM)
Additional
Interface
Quad Belt
Squib Pretentioners
Sensor &
Electronic CAN
Drivers and
Crash Satellite
Interface Accelerator Transceiver Airbag
Sensors Belt

Airbag System Chip V1.3 SPT Technology (SPT4)
DMOS
High- & Lowside Switches
Bipolar & MOS(analog)

Diagnostic, Protection
Voltage Regulator,
Voltage Monitoring,
Sensor Inputs
CMOS (digital)
Control, Watchdog,
Serial Interface

More Channel Switches & Motorbridges:
DOMOPO (SPT6)
metal 3 =
copper
Direct bonding
on DMOS
possible

Chip by Chip:
8-Loop Airbag Firing-IC

SPT4 + SPT5
S1970 + S1969
Lowside + Logic (SPT5) interconnect Highside (SPT4)

Systemintegration (System On Chip) - Systempartitioning
µC Interface SMART-Part Power

Diagnostic and
Protection
over temperature Low-Side Switch
Controller serial overcurrent High-Side Switch
openload
parallel over voltage
Half - Bridge
Bus under voltage H - Bridge
di/dt limiting Voltage Regulator
sub-µ-CMOS CMOS-digital Analog DMOS

(>1µ) Vertical Smart Technology (50A)
(0.5µ) BCD Technology (10A)
(0.13 .. 0.35µ) sub-micron-BCD Technology (2A) Power FET
High-voltage CMOS Technology (1A) Power FET

SPT Technologies Family
SPT
SPT75
75 75
75VV (5-inch,
(5-inch,production
productionoutphased)
outphased)
SPT
SPT170
170 170
170VV (for
(fortelecom
telecomapplications)
applications)
SPT
SPT44 60
60VV
SPT
SPT44 90
90VV
SPT
SPT44 90–RC
90–RC (Rev.
(Rev.Current.,
Current.,6-inch,
6-inch,production
productionoutphased)
outphased)
SPT
SPT55 60
60VV 33metal
metallayers
layers ((22signal
signal++power)
power)
SPT
SPT66 60
60VV uses
usesCu
Cuasaspower
powermetal
metal
SPT
SPT6+
6+ 60
60VV 44metal
metallayer
layer ((33signal
signal++power)
power)
SPT
SPT77 60
60VV in
indevelopment
development//pilot-projects
pilot-projects
SPT
SPT88 50
50VV HV-CMOS
HV-CMOS(licenced
(licencedfrom
fromAMS)
AMS)
SPT
SPT99 50
50VV inindevelopment
development––high
highlogic
logicdensity
density(130
(130nm)
nm)
Smart Technologies Family
Smart
Smart3.3
3.3 80
80VV
m-Smart
m-Smart 60
60VV
S-Smart-60
S-Smart-60 60
60VV
S-Smart-80
S-Smart-80 75/80
75/80VV
SMART
SMART55 60
60VV Trench
TrenchDMOS,
DMOS,incl.
incl.bipolar
bipolar
Logic
Logicdensity
densityequ.
equ.SPT4
SPT4
SMART
SMART66 60V
60V in
indevelopment
development

Bipolar Technologies
DOPL
DOPL 60
60VV Bipolar
BipolarTechnology
Technology
special
special use
use for
for linear
linear regulators
regulators
with
withpnp
pnpasaspass
passelement
element
DOPL
DOPL44 60
60VV 8-inch
8-inch
SUPPLY1
SUPPLY1 60V
60V Bip.
Bip.++CMOS
CMOS in
indevelopment
development

Contents
0. Introduction
3. Basic Analog Circuits & Examples of Realized Circuits

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 2 - Components 53
Components of SPT-Technologies (1)
n MOS Transistors
– Logic / Analog
– N-Channel / P-Channel
– All Enhancement-type / No Depletion available
– Low-Voltage (5V) / Medium Voltage ( 10V- 40V) / High Voltage (60V)
– Digital CMOS logic:
0.8 µm gatelength (SPT5) comparable to C6 technology (process 0.5u)
– Analog MOS-circuits:
are usual smaller in chipsize compared to equivalent bipolar circuits
n DMOS Power Transistor
– N-Channel Vertical-DMOS
– N-Channel Lateral DMOS improved RdsON, not as robust as vertical DMOS
– for all power switches, very well suited for lowside switches
– No P-channel power-device available,
use DMOS + charge pump for higside switches
n Bipolar Components
– Transistors npn / pnp
– Diodes / Z-Diodes
– ESD-protection structures
usage:
– for bandgap-reference circuits use of bipolar is a must

(also in CMOS you can use a substrat bipolar for bandgap-ref)
– for low offset comparators

(very simple solution compared to MOS offset compensation)
– disadvantage of bipolar:
more parasitics („bulk parasitics“) compared to MOS
e.g. substrat currents, „reverse-current“ problem
needs more chip area, not so shrinkable as MOS
n Passive components
– Resistors
n poly-resistors (SPT5) are very usefull, no parasitics compared to
diffusion resistors
n diffusion resistors (SPT4, SPT7)
medium ohmic res. if no highohm-poly available
n p-well resistors (SPT4) or JFET (SPT5) for high ohmic resistor
devices – very high tolerances!
– Capacitors
n poly-poly caps (SPT5)
n GOX-caps (SPT4, SPT7)
n high-voltage caps: poly-metal, metal-metal
– Laser Fuses
n cut a metal line for adjustments at wafer level
Component Selection: Some Rules for Analog Design
n use large devices for low offset
n use bipolar instead of MOS (if available) for low offset
n use MOS instead of bipolar for lower chip area
n Resistors:
– high ohmic devices have more tolerance than low ohmic (thumb rule)
– use poly resistors (if available),
check temp.behaviour and well-voltage dependency (for diffusion resistors)
n use relative MATCHING, not absolute values
n Do not trust to much any information you get about tolerance
– add a factor of 2 (or whatever is possible) for a robust design
– bad examples of the past: p-well resistors (changed dramatically at transfer from 6 to 8 inch SPT4)
– always a challenge: accuracy of depletion-transistor current (SMART)
– use monte carlo simulations to get a feeling of the spread,
but simulation can not guarantee all possible changes in fab-line for the next years, where your
design will be in production
– Remark: almost all SPT4 designs, which are now in high volume production and have a good yield,
where done without the help of monte carlo simulation!

Not so Easy to Catch with Rules (or to verify with circuit-simulation)
n voltage capability - some warnings in simulation available,

n energy capability
– single pulse,
– repetitive clamping
n ESD robustness - ESD review recommended for any new design
n EMC behaviour
– emission (Abstrahlung)
– susceptibility = immunity against high frequency injection (Einstrahlung)
Consequence:
experience required, knowledge about parasitics, experience with designs in production,
knowledge to differ between customer „wishes“ and „musts“ (to be competitive)
„first time right“ cannot be guaranted only by simulation results!
Share experience with other designers! (design reviews, design symposium)

Smart Power Technologies – Available Components Overview
MOS devices
SPT 4 SPT 5/6 SPT 7 SMART 5 SMART 6
low voltage N-MOS mn mn mn (25nm) mnle, mnle2, mnne, mnne2 mmne, mnle
mnx (7.5nm)
depletion mnnd
-- -- -- mnnd, mnnd2
low voltage P-MOS mp mp mp (25nm) mple, mple2, mpne, mpne, mple
mpx (7.5nm) mpne2
medium voltage N-MOS mnm mnme, mnme2 --
medium voltage P-MOS mpm -- --
high voltage N-MOS udw mnh mnh mnhe, mnhe2 mnhe

depletion -- -- -- mnhd mnhd
high voltage P-MOS up mph mph mphe, mphe2 mphe, mphex
DMOS (always n-channel) udd dm dm mnte (Trench) mnte
low threshold DMOS udw --- --- -- --

Bipolar Devices
SPT 4 SPT 5 / 6 SPT 7 SMART 5 SMART 6
npn (standard) nd nst nst qnbl qnbl

(higher beta) nw qnbh (sub) qnbh
(fast) nhf qnbh temps
pnp (standard) pdd pst pst (possible) qpsl
(fast, low voltage) pbb phf
z-diodes zvd 6,8 V zd5 5,2 V zd5 dz6r dz6r
zvr 8,2 V ze5 6,0 V zd7 dz6s dz6s
zd6 6,6 V dz8r dz8r
diode low-voltage dds dst dst -- --
dws
diode high-voltage dw dfd dfd -- --
drp option:
poly-diode
low-leakage diode dll dll --- -- --

Passive Devices
SPT 4 SPT 5 / 6 SPT 7 SMART 5 SMART 6
capacitor GOX (low volt.) cm(v)q (55 nm) cst (15 nm) cst (25 nm) cgox cgox
cstx (7.5 nm) (30 nm) (30 nm)
cap. poly-poly (low volt.) cmcq (150 nm) cpp (33 nm) --- --
capacitor (medium volt.) cmcq (150 nm) cmp (150 nm) cmp (150 nm) ccox cfox
(200 nm) (500 nm)
capacitor (high volt.) cgm (700 nm) chh (500nm) chh
chp (1u) chp
resistor low-ohmic poly-res rm poly rpn poly rpp, rpn rpoly rpoly
n-diff rdn
resistor medium-ohmic p-diffusion rd poly rpm p-diff. rdp rpd, rpv rpd, rpdl
n-diff rdn
resistor high-ohmic p-well rw poly rph j-fet jpm,jph rpw rpw
j-fet jp option: rph
Metal Layers
SPT 4 SPT 5 SPT 6 SPT 6+ SPT 7 SMART5 SMART6
metal layer 1 alu 0,75 µm alu 0,8 µ alu 0,8 µ alu 0,8 µ alu ~0,5 µ alu 1,6 µ alu
metal layer 2 alu 1 µm alu 0,8 µ alu 0,8 µ alu 0,8 µ alu ~0,5 µ -- --
metal layer 3 alu 2 µm alu 3,5 µ cu 11 µ cu 11 µ cu 11 µ alu 2,5 µ cu

(power metal)
metal layer 4 (optional ) alu 0,8 µ alu ~0,5 µ
for higher logic density
Special
bonding on active no no yes yes yes Source Source
area DMOS DMOS
E2PROM available no no yes yes no no no

SPT5 Components: MOS – Transistors / Low voltage NMOS
H.Zitta – Smart Power Analog 2 - Components Source: Spt5_Databook_v3.0.2.pdf 63

Devicename: Classification of voltage class & guard rings SPT5
mn06pc
mn06pc
n-sinker-ring recommended if drain-source diode
is forward biased
poly-guard-ring for analog circuits to avoid leakage

currents from surface parasitics
voltage n-epi to substrat 0 ... max. 5,5V

6 ... max. 60V
voltage n-epi to bulk
low voltage device: VDSmax = 5.5V

Voltage Capability of Low Voltage MOS Transistors
S G D S G D
B B
p-
p+
p+ n+ p+
n- Epi
n-pocket
p Substrat
p-channel n-channel
mp x y mn x y
x: Drain / Source x: n-pocket / bulk(p-well)
y: n-pocket / sub mp 00 mn 00 y: n-pocket / substrat
mp 06 mn 06
mn 66
Components / MOS – Transistors / Low voltage PMOS
H.Zitta – Smart Power Analog 2 - Components Source: Spt5_Databook_v3.0.2.pdf 66

Typical Characteristics of MOS Transistors (1)
input characteristic
Id
(A) Id Id A
Id==f(Vgs)
f(Vgs)
Vds
Vgs
w
Id = k ⋅ ⋅ (Vgs − Vth) 2
l
in saturation: Vds > (Vgs – Vth)
(here: Vds = 5V)

Sqrt
Sqrt(Id)
(Id)==f(Vgs,Vbs)
f(Vgs,Vbs) Vds=5V
Id Vbs Id A
0 D
400µA -1 V G B Vds
-5 V
Vbs
Vgs
100µA
Body effect ( Substratsteuerung):

mn 2/2
Vth = f (SQRT(Vbs))
Vth = 0.6V
Id
Id==f(Vg,Temp)
f(Vg,Temp)
- 50°C
25°C
+ 150°C
temperaturstable point
approx. at 1,15 V
+ 150°C -> I= 7 µA (w=l=2µm)
- 50°C
mn 2/2

p-channel mp Id = f(Vg,Temp)
temperaturstable point
approx. at 1,85 V
- 50°C
+ 150°C w = l = 2µ -> I=13µA
- 50°C + 150°C

output characteristic
Id
Id==f(Vgs,Vds)
f(Vgs,Vds) Id A
D
Vgs=5V G
Vds
linear region (Ron) B
Vgs
saturation
Vds > (Vgs – Vth)
Vgs=2V
mn 2/2

Ron
Ron==f(Vgs)
f(Vgs)
Ron
Ron==f(Temp)
f(Temp)
mn 2/2
Recommended Channel Length for Analog MOS Design
SPT4: VDS-max n p
5V l = 2.8 µm l = 3.6 µm
7.5 V l = 4.8 µm l = 4.8 µm
10 V l = 6.8 µm l = 6.0 µm
SPT5/6: digital: l = 0.8 µm wmin= 0.8um

analog: l = 2.0 µm w = 2.0 µm
for matching: use not minimum devicesize
recommended: l = 4 µm .. 10 µm
SMART5: digital: l = 2.6 µm wmin= 2.4um

analog: l = 6 µm

Threshold of a Logic Inverter – How to size the MOS transistors
Vcc Vout
w=wp 2
l = 2u
3
IN OUT
w=wn
l = 2u Ivcc
1 2 3
wp 2u 5u 5u
wn 2u 2u 5u
Vin
1) Same size of n-, pmos wp=wn gives a threshold lower Vcc/2
because of the lower mobility of pmos compared to nmos.
2) make pmos approx factor 2.5 x nmos (2 .. 3) to compensate this dc-analysis,
models used: SPT7
3) cross current during switching increases with size of transistors
Threshold Voltage Shift with Channel Implantion SMART5
Id
Id
n-channel mnle2
enhancement mnle p-channel
enhancement
Vgs Vgs
Id
mple2
n-channel
mple
mnd2
depletion
mnd
Vgs
Bor (valeny=3) channel implant shift Vth always to more positive values
SMART Techn: Type „2“ = without channel implant
Medium & High Voltage MOS Devices SPT5
VDS-max examples
medium mnm 20 V mnm12p

voltage mnm16c
(lateral) mpm 20 V mpm22p

mpm26pc
high mnh 60 V mnh66p

voltage mnh66c
(lateral) mph 60 V mph66p

mph66pc
DMOS dm 60 V dm66p
dm66c
DMOS dm66 Vertical (updrain) DMOS as Power Device SPT5
ònx…number of poly gate stripes (optimum: 13; <30)
m….multiplication factor for nx
ny…number of norm width elements of 2,8 mm
W = variable: nx = 2
W= m x nx x (2 x 2,8mm x ny)
cell number = m x nx x ny Leff = 0,56 mm
ny = 4

Cross section of Vertical DMOS (one cell)
R-JF R-NS
R-epi
R-BL
Rds = R-channel + R-JF + R-epi + R-BL + R-NS

Multicell DMOS
G Drain
D S
p+ p+
n-sinker burried layer
due to the „updrain concept“ the inner cells have higher resistance as outer cells:
cells are not equal acc. Rdson. This gives limited accuracy by using part of the
DMOS as sens-cells e.g. for current measurement

DMOS: nx ˜ 13 for area/Ron optimum
drain-connections
source-
cells
ny
nx

DMOS Id = f(Vg,Temp)
temperature
temperaturestable
stablepoint
pointisisatataa
relative
relative high
highcurrent
currentlevel!
level!
- 50°C
ititcould cause thermal instability
could cause thermal 25°C
instability
T=50 to +150°C
VDS=5V

Lateral DMOS (SPT6)
G B G G B G
D S D S D
n++ n++ n n++ n n++ n++
p top n+ nsd, nsd p-shallow n+ p top

sinker n-source p-latchup sinker
n¯ n-Epi n-Epi n¯
Dbs
p bott p bott
n+ buried layer
QP1
Dsub QNPNReverse
p substrate
Epi thickness is choosen for highest voltage vertical DMOS, eg. 60V
Lower voltage DMOS, e.g. 40V, could be realized as lateral DMOS at smaller chiparea.
Vds-max of lateral DMOS can be adjusted by layout.
SPT6: vertical DMOS-60V, lateral DMOS 45V

SPT7: vertical DMOS-60V, lateral DMOS 60V & lateral DMOS 45V
Source: Course H.Rothleitner „Devices for Smart Power HV-BCD“

Bipolar devices - Transistors SPT5
VCE-0 VCE-R VC-sub beta max

(Ic for beta/2)
npn nst 146 10V 45V 60V 110

(1,6 mA)
nhf 112 10V 10V 20V 85

nhf 246 20V 45V 60V (3,6 mA)
pnp pst 346 35V 45V 60V 110

(50 µA)
phf 112 10V 10V 20V 70

phf 222 20V 20V 20V (50 uA)
... p with poly-guard ring

... c with c-sinker: recommended for operation in saturation
npn
C B E
Layout
Each
Eachbipolar
bipolardevice
device
need
needits
itsown
own epi-well
epi-well
->
->chip
chiparea
area
Cross-section

Typical Characteristics of Bipolar Transistors (1)
IC
IC==f(VBE)
f(VBE)
IC
IC==f(VCE)
f(VCE)
Beta
Beta==f(IC)
f(IC)
Beta
Beta==f(T)
f(T)

Typical Characteristics of Bipolar Transistors (2)
VBE log
log(IB,
(IB,IC)
IC)==f(VBE)
f(VBE)„Gummel-Poon“
VBE==f(T)
f(T) „Gummel-Poon“
IB
IB==f(VCE) Breaktrough:
f(VCE) Breaktrough:VCE
VCE==f(Rbe)
f(Rbe)

Bipolar-Characteristic IC = f(Vbe) SPT5
Ic
(A)
nst 146p
npn
nhf 112p
pnp
pst 346p
phf 112p
Vbe (V)

Bipolar Devices - Diodes SPT5
Current in forward direction

A K
Anode Cathode
standard diode dst06 based on npn low voltage device

Anode = Epi
reverse polarity diode drp66c based on DMOS high voltage device

Cathode = Epi
low leakage diode dll66c Cathode is no parasitic in forward

junction-isolated direction
from Epi

Bipolar Devices – Z-diodes SPT5
standard z-diode zd5s 5,2 V (5,0..5,4) CMOS gate protection

K
K=n-well zd6s 6,6 V (6,0..7,2) DMOS gate protection
A ze5s 6,0 V (5,8 ..6,2) incl. temp >5,5V
substrat z-diode
Anode zd5sub 5,2 V
= substrat
C 3-pol-diode zd5f 5,2 V
A n-well node (C) zd6f 6,3 V

programmable ze5f 6,0 V
K

Resistors SPT5
Ohm/sq tc1 max.

10-3/K current
rpn low ohmic poly 16 + 0,92 2,5 mA/µm
Poly resistors
rpm medium ohmic poly 100 + 0,14 800 µA/µm for general
high ohmic poly 1020 - 2,1 80 µA/µm
use
rph
rm1 metal resistor 2 34 m + 3,5
( alu 1= 0,8 µm)
Alu resistors
calculate with
metal resistor 2 34m + 3,5
for current
rm2
melidim
( alu 2 = 0,8 µm measurement
rm3 metal resistor 2 8m + 3,5 should not be used as
( alu 3 = 3,5 µm) accurate resistor
(metal 3 is often used
in SPT4 as resistor)

S (D)
Junction-FET jp66 G B
The p-JET is a depletion transistor, it can be used as a highohmic
(but not accurate) device to generate a low current. D (S)
S According to gate connection you S
can control the chracteristic
B B Vgs = Vds
G
G Vgs = 0V -> resistor
-> current source
D D
-50 µA -40 µA
-40 µA
-30 µA
W/L=3/4
-30 µA
W/L=3/4 G
W/L=3/7 -20 µA
-20 µA
W/L=3/7
-10 µA -10 µA
W/L=3/17 W/L=3/17
0 µA
0 µA

Capacitors SPT5
pF / mm2 max. Oxid

voltage thickness
cst 2130 5.5 V p-Iso / CMOS-Gox / Poly 15 nm
clp 1270 5.5 V p-Iso / DMOS-Gox / Poly 25 nm
cpp 1050 7V Poly / ONO / Poly 33 nm (*)

cmp 230 20 V n-sinker / COX / Poly 150 nm
chp 32 60 V Poly /BPSG / Metal1 1080 nm
36 + metal1 / IMOX1 / metal2 950 nm
35 + metal2 / IMOX2 / metal3 1000 nm
chh 60 60 V p-Iso / FOX / Poly 520 nm
poly/poly-cap cpp is the prefered low-voltage capacitor

*) electrical relevant thickness related to gateoxid, ONO = oxid + nitride + oxid
Layout-area comparison: SPT4 to SPT5 components
Capacitors
Capacitors ˜˜ 50%
50% DMOS
DMOS ˜˜ 70%
70%

Layout SPT4 vs. SPT5 (2)
Digital
DigitalCMOS-Logic
CMOS-Logic ˜˜ 10
10%%

Layout Size: Bipolar
in future:
SPT4
SPT4to
toSPT5:
SPT5:no
noshrink
shrink Deep
DeepTrench
TrenchIsolation
Isolation
allows
allowsalso
alsobipolar
bipolarshrink
shrink
SPT5 SPT4
nst146c ndl45c
SPT7 SPT7 SPT9
nst11 nst24 s9bn11

Overview Components of SPT4
n CMOS mn, mp
n DMOS udd, udw
n HVPMOS up
n NPN nd, nw
n PNP pdd, pbb, pds
n Zenerdiode zvd, zvr, znpn
n Diode dll, dw
n Resistor rd, rw, rm, rg, rj, ry
n Capacitor cmvq, cmq, ...
n Pads & ESD e0g, ...
H.Zitta – Smart Power Analog 2 – Components SPT4 96

Low Voltage MOS / CMOS SPT 4
mn MOS n-channel low-voltage Vth=+1.1V

mp MOS p-channel low-voltage Vth=-1.1V
VDS-max n p
Voltage class depends
on channel length 5V l = 2.8 um l = 3.6 um
7.5 V l = 4.8 um l = 4.8 um
10 V l = 6.8 um l = 6.0 um
mn01 VDS = „internal“ max. 5V (...0)

to substrat = „external“ max. 10V (...1)
mn11 VDS internal 10 V / external 10 V
mn15 VDS internal 10 V / epi well to p-well 10V / epi-well to substrate 55 V
mn55 VDS internal 10 V / epi well to p-well 55V / epi-well to substrate 55 V
mn11d for analog with poly-guard ring
for current mirrors, small currents or analog circuits in general
mn11v + ISO-guard ring ( seldom used)

mn, mp symbols SPT 4
(n) (p)
mn bulk connected with source mp bulk connected with source
mnb bulk terminal separated mpb bulk terminal separated
multigate for digital

DMOS SPT 4
udd DMOS n-channel high-voltage Vth=+2V power device

udw “Wannen-DMOS” n-channel high-voltage Vth=+1.1V lower threshold
uses p-well as body
Voltage class:
VDS-max to substrat udd55o1 1-cell (smallest size DMOS available)
udd22 udw22 20 V 20 V udd55c1 1-cell with n-sinker (Kollektor-Tief-Ring)

udd55 udw55 55 V 55 V use if reverse diode can be forward biased
udd66 60 V 60 V
udd55c power-dmos with number of cells nx x ny)
udd99 udw 99 90 V 90 V nx = 13 (optimium for ron / area)
ny ≥ 2 nblock = 1
or nx=1, ny=1, nblock>1
Ron @ 25C:
≈ 1.2 k /cell

HV - PMOS SPT 4
up MOS p-channel high-voltage Vth = -1.1V
Device VDS-max Bulk to substrate

Voltage up22 20 V 20 V
classes: up55 55 V 55 V
up99 90 V 90 V
channel length = 7.4u (fix)

max. voltages: Source to Gate 10V
Bulk to Gate 10V
Bulk to Source 10V
Source to Drain see voltage class
up_power optimized layout for larger devices

but not really a power device

NPN SPT 4
nd bipolar BJT npn medium-voltage β ≈ 70
nw bipolar BJT „Wannen-„npn medium-voltage β ≈ 300

uses p-well as base
nds small emitter area, minimum device

ndl large emitter
nw high beta (only at small currents)
voltage-class:
Device Vceo Vcer Vcb Veb to sub
nds22 20 V 20 V 20 V 8.5 V 20 V
nds45 20 V 45 V 45 V 8.5 V 55 V
nwl45 20 V 45 V 45 V 20 (27) V 20 V
Vcer > 20 V (max. 45V) only with resistor max. 100k Rbe
Veb breakdown (as zener diode) not allowed!
Emitter size(number of emitters) : 1, 2, 4, 8
PNP SPT 4
pdd bipolar BJT lateral pnp medium-voltage β ≈ 180 (10uA)

pbb bipolar BJT lateral pnp low-voltage, faster β ≈ 200
pds bipolar BJT vertical pnp medium-voltage β ≈ 350
Voltage class Device Vceo Vcer Vcb Vbe base to

sub
pbb12c 10 V 20 V 20 V 30 V 20 V
pdd45mc 45 V 25 V 45 V 45 V 55 V
pds44 45 V 25 V 45 V 45 V 45 V
number of
emitters:
1,2,4
collector-
splitting
to safe area:
2 collectors 4 collectors
Zenerdiodes zdio SPT 4
20V: 55V: Breakdown Remarks

cathode to substrate cathode to substrate Voltage
zvdl2m zvdl5m 6.8 V prefered type, stable (no drift)

zvds2m zvds5m 7.0 V prefered type, stable (no drift)
zvrl2m zvrl5m 8.2 V for gate clamping
zvrs2m zvrs5m 8.8 V for gate clamping
zvrs2c zvrs5c 9.7 V for clamping and forward operation
to reduce substrate current (B≈1)
Cathode = n-epi-well => Parasitic diode from cathode to substrate =>

in forward operation: High substrate current (B≈50)
pos. temp.coef.: +0.0032 (zvdl)

(compensation with bipolar Vbe possible)
Substrat z-diode (zdios): zers 8.8 V for gate clamping; no parasitics!
general remark: do not use z-diodes as voltage reference (better to use bandgap circuits)
typical usage of z-diodes are overvoltage limiting.
3-pin Zener-diodes znpn SPT 4
To avoid the parasitic diode from cathode to substrat, a 3-pin z-diode is

available, where the collector (= epi-well) can be connected to another voltage.
Device Breakdown βNPN ≈ Parasitic βPNP ≈

Voltage: E -B (PNP-Tr.: B – C – Sub.)
nvrs22m 8.0 V 0.1 100
nvrs35m 8.0 V 0.1 100
nvrs35c 8.0 V 0.1 0.2
Base-Emitter = z-diode, connect Collector to a always positive voltage.
usage: if you need a z-diode operation below ground level (e.g. for high-side switches
during clamping), than a 3-pole z-diode can be used.

Diodes SPT 4
high-voltage diodes: DMOS as hv-diode

dll55c Low leakage diode
Pro: Lowest substrate current

Con: Parasitic substrate diode to annode
The DMOS reverse-diode can

dw55c Free wheeling diode be used as high voltage diode
Attention: Only C-types (with n-
Pro: No parasitic substrate diode to annode sinker-ring) allowed, due to the
Con: Small substrate current (1 – 2% of IA) parasitic substrate-PNP
low-voltage diodes: npn as diode, reverse-voltage is limited by Vbe-breakthrough

Device Veb-max Remarks
dds12m 9.4 V No E-B breakdown!
dws15 27 V No E-B breakdown!
dvrs15 7.8 V zener diode E-B

Resistors SPT 4
“base” or “body”—resistor resb,rebw p-well-resistor respw, respww
rd45m4u4 55V to substrat, w=4.4u rw55m4u8 (3.2u), 4.8u or 8.4u
700 Ω/sq ( do not use w=3.2u – pinch off!)

standard resistor for kOhm range
approx.10 kΩ/sq
moderate voltage dependent
this device was found to be very
for accuracy:
use equal well voltage sensitive for a waferfab transfer
for a res.-divider highohmic, not accurate, nonlinear (pinch off)
pos. temperature coeffic.:
tc = 4.1e-3 (+100°C -> + 41 %) high pos. temp.coeff. tc = 7.5e-3
Poly-resistor resps rm 30 Ω/sq Aluminum or “metal”-resistor resmet

use as shunt for current measurements
small pos. temp.coeff. tc = 1e-3 rg = Alu 1 0.75 um 43 mΩ/sq
(only +10% increase for 100K) rj = Alu 2 1.0 um 30 mΩ/sq
ry = Alu 3 2.0 um 15 mΩ/sq
pos. temp.coeff. tc = +3.8 e-3
Capacitors SPT 4
cmvq 0.63 fF/um2 Poly / 55nm GOX / Top-Iso Poly

connect well to
a pos. voltage
standard gate-oxid cap. for general use, vmax = 10 V
attention: Parasitic junction capacity from well (epi) to substrate!
cmq 0.63 fF/um2 Poly / 55nm GOX / Epi

reduced parasitic cap to substrat,
for charge pump applications to max. 10V
cmcq 0.23 fF/um2 Poly / 150nm Oxid / n+ sinker

or charge pump applications > 10 V ( max. 20 V )
cgm 0. 0288fF/um2 Alu1 / 700nm / Poly

High voltage cap. max. voltage (90V) possible
the good message: temp.coeff. of all caps is practical zero!

Pads & ESD-Diodes SPT 4
pad Normal bondpad for 30u, 38u, 50u or 65u Au-wire
mpad testpad for measuring at wafer-test only
apad very small pad for analysing circuit at lab only
esd ESD-protection diode integrated in a pad 30u, 50u, 65u

examples: working voltage
e0g + 8V / -0.3V
e0v + 8V / -0.3V
e2g + 20V / -0.3V
e4g + 40V / -0.3V
e4n2g + 40V / - 20V
Attention acc. ESD:

Try always to catch the latest information before selecting the best ESD structures for your application
The improvement of ESD structures is an always ongoing process!

Intranet Technology documentation at AIM AP CAD Homepage
http://goto.infineon.com/powerflow
H.Zitta – Smart Power Analog 2 – Components-CAD 109

try to find some information using AIM.AP.CAD site:
examples
DOPL: max voltage for npn?
SMART6: typ. threshold of power DMOS?
SPT6: available z-diodes?
S-SMART: output charact. of low-voltage NMOS?

DOPL: max voltage for npn?
klick DOPL, klick Design Manual, scroll down to

4. Device Library
4.1. Device data sheets load pdf-file
find NPN, Dtype NB(65V)
Vcb C
Result: max 55V (Vceo) or 65V (Vcbo = Vces) B Vce

SMART6: Threshold of power DMOS?
klick SMART6, klick Design Manual, scroll down to

4. PEPS Preliminary Electrical Parameters
load pdf, find DMOS Cell mnte
(mos, n-channel,trench, enhancement)
Result: approx. 1,5 V (take care: it‘s preliminary)

SPT6: available z-diodes?
klick SPT5/6,
klick Design Manual -> empty
klick Library Information
1) goto SPT5&6 Device Overview (Hell Liste) 2)
find at page 13 a z-diodes overview:
zd5... 5,2V / zd6.. 6,6V / zd6f .. 6,3V
2) goto SPT5&6 Databook 5.2.0 find more details & cross-section/parasitics

S-SMART
Output characteristic
of Low-Voltage N-channel?
S-SMART
-> PEP
find char.
measured
and simulated

Contents
0. Introduction
3.1 Current Mirrors, Current Sources, Bias Concepts, Delay Circuits

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.1 – Current Mirrors 115
Basic Current Mirror - Overview
BIP MOS
Iin Iout Iin Iout

I1 I2
I1 I2
w1 / l1 w2 / l2
N T1 T2 M1 M2
1-emi n-emi
T1 T2
P M1 M2
I1 I2
I1 I2

Basic Current Mirror
Iref Iref
I1 I2 I1 I2
Bipolar MOS
The base-emitter (or gate-source) voltages of the two transistors are forced
to be equal.
This forces the collector (or drain) currents I1, I2 to be equal, if the
transistors have the same size.
Current Scaling with Current Mirrors
I1 I2
I1 I2
M1 M2
T1 T2
w1 / l1 w2 / l2
1-emi n-emi
(w / l ) M 2
I 2 = I1•
(w / l ) M 1
(Emitter Area)T 2 if length1 = length2 w2
I 2 = I1 •
(recommended)
I 2 = I1 •
(Emitter Area)T 1 w1
For matching: Use unit areas (Unit transistors) For matching: Use unit transistors
Bipolar MOS
The current ratio is proportional to the active-area-ratio of the devices

Transistor-size: Actice Area Definition
w = ...
Bipolar MOS l = ....
1,2,..
Size of emitter w/l width/length

C D
B
l w G
E
n=1
S
l w or l w w
n=2 E or E E
better for matching better for matching

Mismatch of Bipolar Current Mirror (1)
I C 2 = I REF − 2 ⋅ I B
Iref
2*Ib
IC
IB =
Ic1 Ic2 β
IC  2
Ib1 Ib2 I C 2 = I REF − 2 ⋅ ≈ I REF ⋅ 1 − 
β  β
Supplying of both base currents from one side causes a

mismatch, depending on the current gain of the bipolars.
e.g. beta = 50: error = 4%

Mismatch of Bipolar Current Mirror (2)
Iref
Ic
Ic2
Ic1 Ic2 Ic1
Ib1 Ib2
VCE1
VCE 2
VBE
VCE1 Vce
Vearly VCE 2
A second source of mismatch is the „early effect“ of the bipolar transistor:

Collector current depends on C-E-voltage.
According to bip parameter a high early voltage is required for low mismatch

Improvement of Bipolar Current Mirror
VBE 1 + VR1 = VBE 2 + VR 2

I1 I2
• Calculate R for VR ≥ 100 mV
• For I1 ≠ I 2 scale resistors and emitter areas

Q1 Q2
VBE1 VBE 2 1
• For R >> the circuit can be used to transform current
R1 R2 gm
VR1 VR2 characteristic by using different resistors
(e.g. „diffused“ „poly“)
I1 R1 ~ I 2 R 2
R
I 2 ~ I1 1
R2
For
Forbipolar
bipolarcurrent
currentmirrors
mirrors
Emitter-resistors
Emitter-resistors help
helpagainst
againstvoltage
voltagedrops
dropsinin the
theusage
usageofofthis
this
supply,
supply,temperature
temperaturegradient,
gradient,T-mismatch,
T-mismatch, „degeneration“
„degeneration“resistors
resistorsisis
noise,
noise,early
earlyeffect
effect very
veryrecommended
recommended
Widlar Current Mirror
I1 I2
T1 T2 VBE 1 = VBE 2 + VR 2
VBE 2
VBE1 I2 << I1 possible without extreme scaling of T1, T2.
VR2 R2
Disadvantage: temperature dependend
A simple method to generate low bias circuits (µA range)

without the need of highohmic resistors.
... this is a circuit for simplicity, not for accuracy ...

Wilson Current Mirror
I1 I2
(in) (out)
IB
T3
I1 − I B 2 ⋅ IB I2 + I B
I2 − I B
T1 T2
VCE1 VCE 2
IB IB
Compensation of the base-current error: Reduction of the early-effect error:

VCE 1 = 2 ⋅ VBE
I C1 = I1 − I B ⇒ I1 = I 2 VCE 2 = VBE
IC2 = I2 − I B VCE1 = VCE 2 + VBE difference is only one diode drop

Improved Wilson Current Mirror
I1 I2
T3
T4
T2
VCE1 T1 VCE 2
additional diode connected transistor T4 looks like a combination of

equalizes the voltages Vce1 and Vce2. wilson and cascode topologie
This leads to full early effect compensation
The most accurate
bipolar current mirror
Base Current Correction by Resistor
Want to make I1 = I2:

I1 I2
U2 – U1 ~ 2 . IB . R1
R2
Q1 Q2 R2 . IB = 2 IB R1
U1 R1 U2 R1 R2 = 2 R1
A simple base current compensation can done with a resistor in series to the base of that
current mirror transistor, from which side the base currents for both bipolars are taken.
For I1 = I2 Q1 has less emitter-current as Q2. So the voltage drop at R1(left) is lower
than at R1(right). Additional voltage drop at R2 compensates this to get same Vbe for
both mirror transistors.

Darlington-Supported Current Mirror
Base current compensated („unterstützter Stromspiegel“)
Iout A good combination of

Iout
Iin bipolar and MOS:
Iin
Bipolar: low offset

MOS: no gate current
NPN -Darlington Bicmos Implementation: npn & n-channel
PNP implementation with more outputs,

often used as „current bank“ for
biasing a number of circuits
This circuit includes a feedback loop:

check stability (with transient and AC-
Iin simulation), not only DC behaviour

Use of Split-collector pnp
In bipolar and SPT4 technology (not in SPT5) pnp‘s with more collector outputs are
available. Use of this devices could save chip-area, because pnps are huge components.
B C E C
1 1
= p p p
I1 I2 I1 I2
p+ n- p+
1 1 2
C1 C2
=
B E
10µA 10µA 20µA C4 C3
10µA 10µA 20µA
Check current capability, only for

currents < 100uA preferred

MOS Current Mirror
I1 I2
w2
I2 l2
M1 M2 =
I1 w1
l1
w1/l1 w2/l2
Recommended: Use always same channel length l1=l2

Scale currrent ratio with w2/w1
Use not minimum size devices. e.g. for 0.6 um technology use > 2u for analog circuits.
Use large devices to minimize offset caused by all kind of manufacturing tolerances.

Accuracy of MOS Current Mirror (offset error)
I1 = 10 uA calculate I2 with Monte Carlo simulation
I1 I2
M1 M2
I2 I2
Transistor size: w =10u, l = 4u w =40u, l = 10u
σ= 0,15uA = 1,5% σ= 0,06uA = 0,6 %

3σ = 4,5% 3σ = 1,8%
10 fold area reduces errror to 1/3
Mismatch of MOS Current Mirror
I1 I2 ID
∆I
I2
I1
VDS1 M1 M2 VDS 2
VDS
VDS1 VDS 2
The slope of the MOS-output characteristic in saturation mode

is not flat because of the channel length modulation.
This causes a current mismatch, which is more relevant in
MOS, compared to the similar „early-effect“ of bipolar devices

Mismatch of MOS Current Mirror (Simulation)
This channel-modulation
or „early voltage“ caused
mismatch can be
improved by using longer
channels.
The term „early volage“ is only

defined for bipolar transistors
but often used as nickname to
decribes the slope of MOS
output characterstics, caused by
channel modulation effect.

Cascode Current Mirror
Cascoding (or stacking) of two

devices enables equal drain-
I1 I2 source voltages for the mirror-
transistors M1, M2
M3 M4 To simplify layout, M3, M4 can be

in the same p-well as M1, M2.
Advantage:
VDS 1 M1 M2 VDS 2 Improved matching accuracy,
recommended to use as a
standard circuit for MOS if possible
with available supply voltage.
Disadvantage:
Higher operation voltage required
P-channel implementation
check bulk connections in

schematic to allow the layout of
I1 I2 all transitors in one common well
(body effect to be considered)

Possibilities to generate the cascode-gate voltage
If the supply at the mirror input is too low for a cascode „MOS-Diode“
you have to generate this voltage in a different way
I1 I2
I1 I2
Vcasc.
Vcasc.
M1 M2 M1 M2
circuit to generate the

cascode voltage
Cascode Current Mirror – Reduce min. Vout
A lower cascode voltage (Vc) allows

operation with lower Vout voltages
Ic Iin Iout than standard cascode configuration.
Value of Vc ist scaled by size (w/l) of
Vc M4 (1/1) M5 in respect to M4. For equal
currents Ic = Iout the ratio M4 to M5
should be 4 : 1 or larger.
M5
if M4 is not in a separate well than the
(1/4) body effect has to be taken in
M1 M2 account, ratio >4 required
Accuracy:
Vds(1) is not exact Vds(2), this cause
a slight mismatch.

Matching Improved Cascode Current Mirror with Reduced Vout(min)
Ic Iin Iout Adding M3 forces Vds1 = Vds2 to

guarantee best current matching of
Vc Iin to Iout
M5 M3 M4 (1/1)
(1/4)
M1 M2

Cascode Current Mirror - Generating Vcasc.with Resistor
Voltage drop at resistor Vr should be:

Iin
Vcasc Vr >= Von
Iout required Vcasc = Vth + Von
Vr Von is the „effective gate
voltage“: how much more than
threshold-voltage is needed for a
M3 M4 (1/1) given drain current:
Vgs = Vth + Von
M1 M2 Id
it‘s a kind of „selfbiasing“:

more current results in more voltage Vgs
but according to chip area resistors are not Vth Von
preferred components in MOS integrated circuit
Comparing MOS – Current Mirrors
improved cascode, accurate at lower voltage
simple mirror,“early effect“
cascode mirror, very precise
cascode w/ reduced. vout,

constant offset,
normal cascode, deviation at low voltage

SMART Cascode Topologies
Vgs2 Vgs2 > Vgs1
mpne2 mpne2
higher threshold
( p-channel)
Vgs1
mpne mpne lower threshold

( p-channel)
I in I out I in I out
The availability of MOS-transistors with different threshold

voltage in SMART technology (S-Smart, SMART 5)
enables cascode mirrors with can operate with
lower supply voltage
Source: M.Ladurner, design symposium 2004

SMART Cascode Using Depletion Devices
I out
I in I out
mnnd2 mnnd2 lower threshold

( n-channel)
Vgs(depl) can be ~ 0
mnne2 mnne2
mnnd higher threshold
( n-channel)
Current mirror with Cascoded depletion transistor

depletion as cascode current source
Source: M.Ladurner,
Note: Depletion transistors are NOT available in SPT-Process design symposium 2004

High Voltage Current Mirror
Solution 1:
Use high-voltage devices 10 uA 20 uA 50 uA
udw better than udd (SPT4)
mnh (long channel) better udw
1z 2z 5z
than dmos (SPT5)
dmos: current scaling by
number of cells
Solution 2: 10 uA 20 uA 50 uA Protection Z-diode

Low-voltage transistors recommended against
for accuracy, fast voltage spikes
(e.g. ESD)
High voltage as cascode
mn
Current scaling by size
w =10u w=20u w=50u
of low-voltage devices.

Example of Cascode Curent Mirrors (S1055/SPT5)
l(M11) = 4 x l(M7)
Vc(p)
Generation of
Vcasc with one
long-channel
device Vc(n) 10u 5u
current scaling
l(M5) = 4 x l(M2)
with multiplication
factor „m“ for best
Vcasc matching
w=2.6u l=4u m=2 w=2.6u l=4u m=1

Example of Cascode Mirror Bias (S1138/SPT5)
Iin
series connected transistors (no cascode)

cascode mirror larger w for
same l for better matching
w = 6.5u x 2 or 13 u (layout reasons) cascode device
exact same w would „theoretically“ be better w=13 x 3 (m=3)
Regulated Current Mirror
If an application requires to mirror high currents with high
accuracy
e.g. “IASG” circuit in airbag ASIC’s S916, S922, S936, ...
10 mA 1 mA
this solution will not work with pnps I1 I2

(current value, accuracy,chip-area)
10 x R par.
Iin Iout
Practical solution can use very simple opamp

Iout I1, I2 should to be low compared to Iin, Iout
Iin
Good accuracy if I1, I2 are scaled like Iin, Iout
Measuring with poly-resistors and feedback loop

Regulated Current Mirror
Vbat Realization in block IASG of S 916 (SPT75)
Accuracy given by
matched poly-resistors
Exact ratio 1:10
possible by use of only
7 resistors
(2 par, 5 ser)
I1
Compensation of
comparator
I2
input current I1:
I-in
Bias
equivalent current I2
is added to the output
I-out
Bias Concept
“Current banks“ with MOS mirrors
VDD
PLB
Resistor or any
kind of
currentsource
50 uA 10 uA 20 uA
10 uA
50 uA
NLB
w=50u w=10u w=50u w=10u w=20u
This bias-lines „NLB, PLB“ (for low voltage MOS) and following the same principle
„NHB, PHB“ for high voltage current mirrors can be used all over the chip to
generate than a local current by simple adding a transistor.
Take care that the GND and VDD line do not have significant voltage drops!
H.Zitta – Smart Power Analog 3.1 – Bias Concepts 147

Bipolar Bias Current Bank
(p-bias)
clamping
circuits circuit
(n-bias)
open collector:
transistor in saturation
The common base line has to be supplied with enough base current
Important for bipolar bias concepts: an open output is not allowed, it
would disturb all other stages due to its saturation effect!

Central Biasing
VDD
PLB
NLB
Advantage:
simple, each block uses “NLB”, “PLB” voltages to
generate local the required currents for biasing
comparators, pull-up and pull-down currents,
charging current for delays, oscillators and so on.
Disadvantage:
sensitive to voltage drops on VDD and GND lines
could cause problems on larger chip
Sensitive to capacitive coupling into the bias line
(long line large capacitance large error current)
sensitive to global mismatch
Local Biasing for Larger Chips
Transfer
Transferof
ofcurrents
currentsalong
alongthe
thechip
chip
avoids
avoidsproblems
problemsofofvoltage
voltagedrop
drop
Capacitive coupling only into
sub-nodes (smaller C)
Only sensitive to local mismatch
Cost: Additional power drain

I1
I2
I3
Functional subblocks
of a larger chip
Main Bias Circucit

How to Build a Current Source?
Series connected
Using a resistor l MOS-”diodes”
e.g. p-well with long channels
(high ohmic, l not accurate
very low accuracy)
or high ohmic poly
l
or jfet
for startup-circuits
if available: depletion-transistor I1 I2 I1 I2
(Smart Technology)
not accurate
H.Zitta – Smart Power Analog 3.1 – Current Sources 151

Simple Voltage Regulator for Internal Supply
use simple a resistor

for startup
S 904 B (SPT75)

Temperature Compensated Current Source
use Vbe to compensate TK of (diffusion)-resistor
use rd: + 4.1.10-3/K

usebipolar
bipolarVbe
Vbetotocompensate
compensatethe the
pos.
pos.temp.coeff.
temp.coeff.ofof(diffusion)-resistor
(diffusion)-resistor
rm: + 1.10-3/K
Vbe - 2mV/K
I
Vref1
T
Vbe Function principle:
Compensation of neg. TK of Vbe
Vref2
with pos. TK of Resistors
Rbody (rd) With a good mix of diffused(body,basis) and
VR polysilicon resistors the temp. compensation
could be set to a variation of < 5% over full
Rpoly (rm) temp.range
The absolute value in any way
depends on resistor tolerance ( < 30 % )
Slope of resulting TK can be adjusted with value of Vref2 For absolute accuracy an adjustment
Vref1,Vref2 = temp.constant (from bandgap reference) (e.g. zener-zapping) is recommended
CMOS Low-Current Current-Source
M3 M4 ID M1
1:1 M2
I1 I2 I1 = I 2
M1 n:1 M2
Vgs1
start-up R1 M1 > M2 Vth VR
VR1 Vgs2 Vgs1
circuit
Vgs2
I = I1 = I2 forced by mirror M3/M4 Vgs 2 − Vgs 1

Vgs1 < Vgs2 because size (M1) > size (M2) I =
Delta of (Vgs2-Vgs1) = voltage drop at R1 R1
Without
Withoutstart-up
start-upcircuit
circuitthis
thiscurrent-source
current-sourcecould
couldtheoretically
theoreticallystop
stopatatcurrent
current==0.0.
Any
Anypositive
positivevoltage
voltageramp
rampwillwillstart
startthe
thecircuit,
circuit,aanegative
negativeramp
rampcould
couldstop!
stop!
Application of MOS-Current Source in Supply S904 A
Although there is no start-up circuit, in this application no problem was reported

(in any way we changed in the redesign B the current source by a simple resistor)

Cross-Coupled Current Source
VS U BE 1 + U BE 4 + U R 2 = U BE 2 + U BE 3
I1 I I I
V T ln + V T ln 2 + I 2 R = V T ln 2 + V T ln 1
M2 mI S Do you like
nI S IS IS
 
− ln some
R1 M1 I I I I
I 2 R = V T  ln 2 2
+ ln 1
− ln 1

 IS nI I mI 
nImaths?
S S S
I1  I I mI 
I 2 R = V T  ln 2 ⋅ S + ln 1 ⋅ S
 = V T ln( n + m )
I2  I S I 2 I S I 1 
IREF
Vt ⋅ ln( n ⋅ m )
I2 = = I REF
U BE 1 Q1 m:1 Q2 U BE 2 R2
The effect of cross-coupling is that the current I1
I1 I2 (defined by resistor R1 and Vs) has no influence
to the resulting current I2.
R1 could be an inaccurate devices e.g. p-well
Q3 1:n Q4 U BE 4 resistor or junction-fet
U BE 3 R2 defines the accurate reference-current
R2 U R2 ( Iref always depends on a resistor accuracy)
often
oftenused
usedininSPT4-projects:
SPT4-projects: Easy
Easytemp.compensation
temp.compensation
with diffusion resistor (with pos. tc)
with diffusion resistor (with pos. tc)
Current Source Using Vref & R
„diode up – diode down“

realization
Vref
Vref
I=
R70
from S1172 / SPT5

Current Source Using Vref & R
Vref
I= I out
R Iout
Vref
Vref
proposed
proposedsolution
solutionforfor R
accurate R
accuratebiasing,
biasing,
ififRRwith
withlow
lowtctcisisavailable
available
High
Highprecision:
precision:
use
useexternal
externalRR(needs
(needsaapin)
pin) principle simple MOS realization
Example of Iref/Bias Circuit (S1078/SPT5)
1.2 V
bias distribution to the 8 channels
Bias current generation

is based on reference
rpm voltage VR1_2 (from
bandgap) and poly
rph resistors.
Mixing of medium- and
high-ohmic poly resistor
for best temperature
compensation.

Application of Current Mirros: Delay Circuit (1)
10 : 1
td
10uA
I1=1uA (Vth)
C1=10p
delay time defined by charging current I1, C1 and Inverter threshold Vth
H.Zitta – Smart Power Analog 3.1 – Delay Circuits 160
Delay Circuit (1) - Simulation
out Q = C •V = I • t
V
Vth t =C•
I
VC
C = 10pF
V = 3.4V
I = 1uA
-> t = 34us
t = 35 us
How to achieve longer delay times: 1) smaller current: not recommended to go too low
because of leakage currents,
2) larger C -> needs more chip area
Delay Circuit (2)
longer delay-time with same cap & current
2nd terminal of capacitor not at GND but at switched inverter output

Delay Circuit (2) - Simulation
Vc Voltage swing at C:
charging to (3.5V + 5V)
out
inverter
VC2 threshold
VC1-VC2
switching
voltage VC1
at cap second terminal of cap
Vc
t =C• = 85µs
I
t = 84 us

Delay-Circuit
using „switch 2nd terminal of cap“ principle
This node is switched
This node is charged
Threshold of smitt-trigger
is higher than
threshold of inverter
Source: S1271/ toff_dly

Delay-Circuit: 70us with 4pF, 0.5uA
0,5µA
4pF
Vc (3,5 + 5)V
t =C• = 4 pF • = 68µs delay_70us / S1969
I 0,5µA
Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.2 – Voltage Reference 166
What Characteristic Can be Used to Generate a Reference Voltage?
Bipolar MOS
Vbe
Vgs
Base-emitter-voltage Vbe: Gate-source-voltage Vgs:
depends on temperature, but is not Depends strong on process variation
sensitive to process variation.
Bipolar device is the key MOS device based voltage

component for accurate reference circuits will not
voltage reference circuits achieve high accuracy

Characteristic of Bipolar Transistor Ic = f (Vbe)
 VVtBE  k ⋅T
IC 
= IS ⋅e − 1  Vt = ≈ 26 mV [ 25° C ]
q
 
IC log(IC)
linear scale logarithmic scale
1 mA 1 mA
100 µA
10 µA
1 µA
100 µA IS
0,2 0,4 0,6 0,8 0,2 0,4 0,6 0,8 VBE [V]
VBE [V]
VBE Bipolar Transistor: VBE = f (T)
1,2
1,0 Temperature behaviour ca. - 2mV/K

0,8
0,6 IC=100µA
0,4
IC=10µA
0,2
0K 300 K 400 K T
-273 C
-40 C 27 C 150 175C
Normal operating range for integrated circuits in
automotive applications
extended temp.range

 VVtBE 
Bipolar Transistor: IC = f (VBE) IC = I S ⋅  e − 1 
 
 IC 
V BE = ln   ⋅ Vt
IC  IS 
 I 
1 mA ∆ V BE = ln  C 1  ⋅ Vt
100 µA Ic1  IC 2 
10 µA Ic2
k ⋅T
1 µA
Vt = ≈ 26 mV [ 25° C ]
∆VBE q
k = 1,38 ⋅ 10 −23 J / K
q = 1,602 ⋅ 10 −19 As
T [°C] T [K] VT [mV]

IS -40 233 20,1
25 298 25,7
0,2 0,4 0,6 0,8 VBE [V] 100 373 32,1
150 423 36,4
200 473 40,7

Temperature-Compensation of Vbe Voltage
Vbe
Vref = const.
T Vbe
∆ Vbe
∆ Vbe -40 C 25 C 150 C

T
The negative temperature dependence of Vbe can be compensated by the

positive temperature dependence of delta-Vbe
Temperature-Constant Reference Voltage
“Bandgap-Reference”
+Vdd
Vbe
Q3 Q4
T
Q5
I1 I2 C1 ∆ Vbe
R3
VREF T
VBE1
Q1 Q2
n:1 VREF
VBE2
1,2
VR1
R1
VREF
R4 UBE2
0,6
VR2
R2
UR2
T
-40 C 25 C 125 C
topology: Brokaw cell, 1974
Calculation of Bandgap Reference Circuit
Assumption: I1 =I2, this is done by the current mirror Q3,Q4.
Q1 ,Q2 have different emitter areas, (AE), with AE(Q1) > AE(Q2) .
Ratio n is choosen as integer.
If the collector-currents are equal, the base-emitter-voltages (UBE) of Q1, Q2 are different.
AE ( Q1) k
∆ V BE = Vt ⋅ ln (n ) n=
AE ( Q 2 )
Vt =
q
⋅T Example:
n=10
V R 1 = ∆ V BE = I 1 ⋅ R 1 ∆ U B E = 6 0 m V [ 2 5C ]
R2
V R 2 = ( I1 + I 2 ) ⋅ R 2 = 2 ⋅ I1 ⋅ R 2 = 2 ⋅ ⋅ ∆ V BE R2/R1 = 5
R1 VR2 = 600 mV
VBE2=600 mV
V REF = V BE 2 + V R 2 = 1, 20 ... 1, 25V for optimal temp .comp . VREF = 1,2 V
Voltage drop at R1 equals delta-Vbe and has the same positiv tc (temp.coefficient) as Vt. So also the
voltage VR2 has the same tc, the absolute value of VR2 is choosen to a value similar to VBE .
This leads to a compensation of the negative tc of VBE over full temperature range. The resulting
temperature error is of 2nd order and is in practice lower than 1%. The best temperature
compensation will be achieved if the voltage Vref is adjusted to 1.2 - 1.25 V. The absolute value of this
reference voltage is better than +/- 5% assuming all practical fabrication tolerances.

Bandgap
Reference
Circuit
Application:
As reference for
temperature sensor
vref / S0946 (SPT4)

Bipolar „Gummel-Poon“ Plot of Ic,Ib
log (Ic,Ib)
Ic
Max. useable current Ib
for bandgap-reference
IC
as long as current follows β =
IB
the exponential law
Vbe

Startup-Problem of Bandgap-Reference Circuit
+Vdd
Q3 I2 I1
Q4
Q5
I1 I2
I1 I2 C1 Vref
R3
VBG
VREF
Q1
n:1 Q2 Current Mirror Q3/Q4 forces I1=I1,
this defines the operating point.
R1 But there exists a second stable
R4
operating point: I1=I2=0
R2 A startup-circuit is required

Adjustment of Bandgap Reference Voltage
Vref If you adjust to higher voltage,

R2 higher pos tc of delta-Vbe will be dominant
Vref
R2 lower
If you adjust to lower voltage,
R1 neg. tc of Vbe will be dominant
T
R2
- 40°C - 25°C 150°C
Adjusting the Vref by changing the value of the resistor ratio R1/R2 changes not only the output
voltage but also the temperature behaviour.
There exists one point with minimal temperature depedence (in practice < 1%)
For bipolar technologies this optimal voltage is around 1,25V (using diffusion resistors with pos. tc)
or around 1,2 V (using low tc polysilicon resistors)
Adjustment can be done during wafer measurement, using „zener-zapping“ or laser trimming.
Adjustment (2) with Help of Switched Currrent Mirrors
M3 M4 M5 M1 M2
1:m
Vref
+ 1%
+ 2%
n:1
- 3% R1
R2
For BicMOS Technologies (like SPT) a current mirror of MOS devices simplifies the adjustment
strategie. The effective ratio for Delta-VBE calculation is now ( n * m ). The ratio m can easiliy be
changed by switching additional transistors in parallel.
Take care to avoid MOS offset by correct sizing (large devices) and layout of the MOS mirror.

Adjustment (3): How Many Bits Needed for Given Accuracy ?
1. approach: binary weighted steps
3 bit : +1%, +2%, +4% -> 0 to +7% (8 steps)

4 bit : +1%, +2%, +4%, +8% -> 0 to +15% (16 steps)
2. approach: +/- steps, „quasi“ binary

+1%, +2%, -3 % -> allows -3 % to +3 % ( 7 steps)
+1%, +2%, +4%, -7 % -> allows -7 % to +7 % (15 steps)
Advantage: set to middle without adjustment
Accuracy after adjustment is +/- ½ step-size:

e.g. 1% smallest step -> +/- 0,5% adjustment possible

Undervoltage Detection Circuit
based on the bandgap reference principle
Vin
Vref UV UV
Vbg Vin
By opening the feeback loop of the bandgap reference circuit, similar circuit can be used
for accurate switching at a given voltage threshold, e.g. for undervoltage detection
Using
Usingbipolar
bipolarbandgap-principle
bandgap-principleforforundervoltage
undervoltagedetection
detectionisisvery
veryrecommended:
recommended:
autonomous
autonomouscircuit,
circuit,simple
simpleto
toachieve
achieveaccuracy
accuracy
based on the
Undervoltage Detection Circuit bandgap reference principle
uvdet / S0955
(SPT4)
Accuracy of Voltage Dividers (Diffusion Resistors)
a) b)
R2
V2/V1 k=
( R1 + R2 )
R1 a
V1
k
R2
b
V2
V1
well connection
a) all resistors in one well – not suited for precision resistor divider
b) each resistor in separate well – better accuracy
Remark: this problem does not exist for polysilicon resistors
Diffusion Resistor Voltage Divider - Layout
(+) V1 (-)
a)
all resistors in one well: R1 R2
R2 sees a higher voltage in
p-resistor p-resistor
respect to the n-well -> tends to
be highohmic compared to R1, p p
n- well
caused by the backgate effect.
b)
each transistor
p-resistor p-resistor
in separate wells:
better for accurate matching p p p
n- well n- well
disadvantage:
sensitive to leakage or parasitic currents
from well to substrat because well connection is more
high-ohmic (via resistor)
S1969
vdd5_uv_detect
very accurate, because based on the bandgap reference principle (SPT5)
Hysterese
Undervoltage_Low
S1172
uv_lockout
only key-devices (npn) are bipolar, other MOS -> saves chip-area (SPT5)
start up
Bandgap Reference in SMART 5
switch-off the startup
4:1
Source: L8208/BTS5590/SPOC/Cornerswitch
CMOS Compatible Bandgap Reference
If in a CMOS process no real npn is available, use the „substrat-npn“, which always is
available in a p-well CMOS technology, as bipolar reference.
e.g. in the Smart technology this substrat-npn exists.
The collector is fixed to + Vbat (=substrat in that technologies), so you cannot use the npn
as an amplifier. There is only free access to base and emitter, which is enough to use the
emitter-scaling for the delta-Vbe principle.
The amplifier has be done in MOS which will cause more offset as a pure bipolar solution.
p-Kanal n-Kanal npn

S G D S G D E B +Vbat = Substrat
B
C
p-
p+ B
n+
n Substrat E
CMOS p-well process

e.g. logic part of Smart C

Bandgap Reference with all npn-Collectors Connected to VDD
+Vdd = Substrat (for p-well CMOS)
Vref
MOS Opamp
1) This is a possible solution to realise a bandgap reference in a CMOS technology.
Take care of opamp offset
2) This circuit is robust against leakage currents and other parasitic currents at the bipolar
collectors. So it can also be used with bipolars in a BCD process to improve
robustness.
=> therefore also current bandgap-concepts for SPT use this topology

Bandgap Reference Example for Smart-Sipmos
startup-circuit
Can we do a bandgap reference circuit

in a poor MOS process?
(e.g. old Smart processes, used for profet designs)
20 years anniversary
of this circuit
Yes, we can!
This example comes from a telecom supply circuit which used the „Smart-Sipmos“ Technology
(the first name of our vertical Smart Technologies as it was fabricated in the Munich-Freimann Wafer Fab)
source:
In that MOS technology (n-substrat) the substrat npn was used for the bandgap reference. M170/vref (1988)

Lateral Parasitic npn - „Reverse Current Problem“
G S
C B E D
P P
P N+ P
N-Epi N+
N
P
N+
N+
P
P-Substrat
Lateral Substrat npn (Substrat Querstrom)

If an epi-well is biased with a negative voltage below substrat potential than the formation of lateral npn
transitors is evident. All epi wells in the neighborhood will acts as collector of this parastic npn.
In consequence currents into the substrat are drawn from al epi wells which could strongly influence function
of the circuit (parameter shift or functional fail) and additional current consumption.
This is our main parasitic to fight against in lowside-switch applications with

junction isolated BCD-type processes, called the „Reverse Current Problem“!
Countermeasures are external (schottky) diodes (expensive for customer), special epi doping (expensive for
wafer-fab) and special know how in layout (guard rings) and circuit design.

Different names, but same problem:
Reverse- , Inverse-Current, „Querstrom“
I-normal I-reverse
„I-quer“
Sub
Current through the DMOS Reverse-Diode acts as base current of a

lateral npn parasitic which have more collectors: each epi well on the chip
could be a collector, although it is far away!
Parasitic current flows across the die -> „Querstrom“ „across-current“
In SMART process (n-subtrat) the problem is called „inverse current“

Bandgap Reference in a n-well CMOS Technology (1)
p-ch. n-ch.
S G D S G D
p B
Vref
n-well p-
p Substrat
1:n MOS Opamp
parasitic pnp can be used as
bipolar diode
Also
Also„CMOS“
„CMOS“bandgap
bandgapcircuits
circuitsuse
useaabipolar
bipolardevice
deviceas
askey
keydevice
devicefor
foraa
bandgap
bandgapreference.
reference.

Bandgap Reference in a n-well CMOS Technology (2)
+Vdd
1:m
start-up
Vref p-ch. n-ch.
R2 S G D S G D
p B
R1
1:n n-well p-
p Substrat
VR1 = ∆VBE = Vt ⋅ ln(n) parasitic pnp can be used as

R2 bipolar diode
Vref = VR1 ⋅ m ⋅ + VBE
R1
Bandgap - Reference (3) Doubled Vbe for Higher Accuracy
VCC
Vref 2,4 V ( 2 * Vbg)

1:n
1:n
This
Thiscircuit
circuitisisrobust
robustagainst
againstthe
the„reverse
„reversecurrent
currentproblem“
problem“because
becausethetheCCofofnpn
npn(epi-well)
(epi-well)isisdirectly
directly
connected
connectedtotosupply.
supply.Any
Anyparasitic
parasiticcurrents
currentsfrom
fromwell
welltotosubstrat
substratdo
donot
notdisturb
disturbthe
thebandgap
bandgapvoltage,
voltage,
only
onlyincrease
increasethe thepower
powersupply
supplycurrent.
current.
Bandgap – Reference - Example SPT5 (S1077)

Undervoltage Detection Based on Bandgap with npn-C at VDD
(to be reverse current robust)
Source: S1085 (SPT6)

Bandgap – Reference
a only npn-based circuit („Widlar“)
+Vcc U REF = U R 1 + U BE ( Q 1 ) = U R 2 + U BE ( Q 3 )
Assumption : R1 = R 2 , I 1 = I 2 ⇒ U R 1 = U R 2
U: R 3 = ∆ U BE ( Q 1,Q 2 ) = Vt ⋅ ln( n )
R2
U R2 = U R3 ⋅
UREF R3
R2
R2 R1 U REF = ⋅ Vt ⋅ ln( n ) + U BE ( Q 1)
R3
Q3
If R2 > R1 than the resulting different collector-
currents have to be taken into account by the
Q2 Q1 factor R2/R1:
n:1
R3 R2 R
U REF = ⋅ Vt ⋅ ln( n ⋅ 2 ) + U BE ( Q 1)
R3 R1

Bandgap – Reference
example of the „Widlar“ circuit
Vbg
1:1
1 : 10
advantage:
needs no startup-circuit
1:1
but for accuracy 1 : 10
use of brokaw cell
recommended
Source: Widlar, IEEE Journal of solid-state circuits, Feb. 1971 Source: S1714 (DOPL)

Low Voltage Bandgap Reference
Adding diode voltage (Vf1) with neg. tc and delta-vbe (dVf) with pos. tc is here not
done with stacking one over the other, so operating voltages < 1,2V are possible.
Source: Banba et.al: A CMOS Bandgap Reference with Sub-1-V-Operation
IEEE Journal of Solid State Circuits, May 1999

Smart 5 – Bandgap Reference Based on „Low Voltage“ Concept
Reason to use this concept was not the low voltage capability, but the way easy to generate the
reference voltages for temperature sensors (incl. delta-T-temp-sensor) with the output stage
Source: L8211/B_91_Bandgap
Internal Opamp of Smart 5 – Bandgap Reference
folded cascode
output stage
In Smart 5 also isolated „real“ bipolars are available –

they are used in the input stage for low offset Source:
L8211/B_911_Opamp
Simulation of Bandgap Reference Circuits
„A bandgap reference is the ultimate test of accuracy for

device models. For example, it is very difficult to measure
a VBE over temperature accurately enough on a wafer so
that it will predict the behaviour of a bandgap reference.“
from Camenzind, „Designing Analog Chips“
We made the same experience e.g. for SPT5, after

measuring of the bandgap reference over temperature the
models of the npn-transistor had to be adapted.

Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.3 – Comparators, Opamps 203
Bipolar or MOS ? – That is the Question
bip MOS
Accuracy + -
Offset + -
Noise + -
Process deviation + -
Chip area - +
Voltage capability - +
Robust at high currents - +
Current consumption - +
Revers-current sensitivity - +

What Accuracy can be Achieved?
1 3 10 30 mV
Offset BIP
MOS
Reference- BIP: Bandgap-Reference +/- 3 % without adjust

voltage MOS: no absolute accuracy possible!
Reference- There exists no absolute reference current in an IC!

current You can never achieve more accuracy as that of a resistor!
TC
worst case for resistor accuracy value 25C ->125C
P-well > 50 % > + 50%
Basis (body) (SPT4) +/- 30 % > + 40%
Poly (SPT4 or rpm-SPT5) +/- 20% + 10% or lower
Alu +/- 20% + 38%

P- or N-Input for Comparators?
Choose topologie according to input voltage range

min ca. 0 V pnp, p-channel input
VCC
min < 0 (-0.x) V darlington pnp, p-channel
min > 0,7V bzw. > Vth npn, n-channel
max ca. VCC npn, n-channel Vin
max. > VCC + 0.x V darlington npn, ..

GND, 0V
VCC
VIN
P-Darl.
PNP, P
= Ube or Vth NPN, N
N -Darl.

Comparator, Opamp, OTA ?
Comparator
The general circuit which is based on a diffential-pair input to compare voltages.
Output stage can be digital.
Opamp, Operational Amplifer
If you use a comparator in a feedback loop, you need a well known frequency
response/open loop gain characteristic
Design of opamps is a wide field to give lessons ...
OTA , Operational Transconductance Amplifier

If you take it very seriously, you should say „OTA“ to a simple MOS amplifier
because it do not have a high voltage gain,
but a high transconductance = output current/input voltage
MOS-opamp = OTA + output buffer

Comparator, Op-amp, OTA ?
Comparator Op-amp OTA

operational operational trans-
amplifier conductance amplifier
Vin Iout
Vin Vin
Vout Vout
no feedback: for feedback loop: input voltage is translated

high voltage gain, no check frequency response to output current:
special frequency response for stability: internal or
required for stability if no external frequency comp. Iout = Gm ⋅Vin
feedback loop components (C,R) required.
Vout = A ⋅ Vin output must be able to drive

ohmic loads

Basic use of Op-amps
R
+ R
_
-
closed loop gain =1:
most critical acc. stability! +
Noninverting Buffer
Noninverting Buffer
Inverting Buffer
Inverting Buffer
R2
+
R1
_
-
Noninverting Amplifier
Noninverting Amplifier
Inverting Amplifier
Inverting Amplifier
Comparator with N-device as Input
OUT OUT
IN IP IN IP
NLB
Bipolar: npn-input MOS: n-channel input

Simple 1-Stage CMOS - OTA
I OUT
Transconductance g m =
(VIN 1 − VIN 2 )
M3 M4
Iout OUT Curent mirror M3/M4 transfers
I1 I2 differential input to single output
IN M1 M2 IP
Vin2 CL
Vin1 Ibias
M1,M2: choose large w for high gain; large area ( w ⋅ l ) for low random offset
M3,M4: choose large l for high gain and low systematic offset

gm – Compare Bipolar / MOS
Bipolar: gm increase linear with current
V BE Bip MOS
I C = I S ⋅e Vt Id
d Ic IC
gm = =
d Vbe Vt
MOS: gm increase with square root of current

and size w/l of device
w
Id = k ⋅ ⋅ (Vgs − Vth) 2
l
d Id w
gm = =k⋅ ⋅ 2 ⋅ (Vgs − Vth)
d Vgs l Vgs
w
gm = 2 ⋅ k ⋅ ⋅ Id
l

2-Stage MOS – Comparator
1st stage 2nd stage
M3 M4
M6
Ibias I2 I3
M1 M2
OUT
IN IP
I4
M8 (NB)
I1
M7
M5
Adding a second stage increases gain and allows full swing at output
For use as comparator: no compensation C required

2-Stage MOS – OTA „Miller OTA“
M3 M4
node1 M6
node3
Ibias I2 I3
OUT
CC
IN M1 M2 IP node2
I4
M8 I1 CL RL
(NB)
M7
M5
For using the 2-stage OTA in a feedback loop add a compensation CC

Bode Diagram of Miller OTA
voltage gain Av
1 without Cc
10.000 = 80 dB 1 node1 3 poles created by
internal capacitances at
1000 = 60 dB nodes A, B, C
2 node2
100 = 40 dB 2 with Cc
set dominat pole to obtain
slope 20 dB/decade phase-margin
10 = 20 dB
node3
1 = 0 dB f (MHz)
100 1k 10k 100k 1M 10M
phase F
1
0°
2 for stability phase margin

-90 °
(180°-f ) should be > 60°
-180 °
-270 °
AC-Simulation of a 2-Stage Miller OTA
without Cc
Cc = 100 fF
Cc = 1 pF
Cc = 2.5 pF
Cc = 5 pF
higher Cc
55°
improves the
phase margin
-10°
ϕm > 45° required

> 60° recommended

Rs C=1pF
adding a resistor in series

to the millercapacitor
increases the phase
margin, with small
influence in amplitude
behaviour.
ϕ=97,5°
ϕ=80,4°
ϕ=56,4°
ϕ=36,2°
increasing R

After AC-analysis: Check Stability with Transient Analysis
C =1 / 2.5 / 10 / 100pF
with C = 100 fF
+
Noninverting Buffer
without miller-C

w/l Scaling for 2-Stage MOS - Comparator
( w / l )1 = ( w / l ) 2
( w / l )3 = ( w / l ) 4
M3 M4
at switching point
M6
(VIP=VIN):
Ibias I2 I3
OUT I1
IN M1 M2 IP
I2 = I3 =
2
I4
to avoid systematical
M8 I1
(NB) offset choose:
M7
M5
( w / l )6 ( w / l )7
= 2⋅
(w / l ) 4 (w / l )5
For MOS comparators/opamps this rule helps to avoid systematic offset,

caused by the limited gain of first stage

How to Avoid/to Minimize Offset of a Comparator
Random offset:
Use large devices (area, not only w)
Use operating point with sufficient (Vgs-Vth), better strong than weak inversion
Use same size devices for matching, do not match small with large devices
Same orientation
Far away from heating sources (if possible) or on isotherms (line of same temp.)
Symmetric wiring (poly, alu)
Avoid other wiring with high voltages over opamp layout 1 : 2
Use dummy devices to improve matching
Try a centroid layout for the devices to be matched: dummies

both transistors of a differential pair are
doubled and connected pairwise in parallel
this helps to average out global errors
Systematic offset:
Use symmetry insofar as posible
Most offset is caused by first stages, but do not forget second stage
Random Offset – Monte Carlo Simulation
M3 M4
4/4 4/4
32/4
Ibias I2 I3
IN M1 M2 IP
40/4 40/4
I4
M8 (NB)
I1
5/4
M5 20/4
5/4
for MOS comparators you have to accept a

offset in the xx mV range, offset simulation:
use MC-simulation to get a better feeling standard deviation σ = 2mV, 3σ = 6mV
(simulation done with SPT5-modells) good centered, no systematic offset
Improve the Offset with Larger Devices
W1, W2 = 100u
σ = 1,14 mV, 3σ = 3,42 mV
W1, W2 = 200u
σ = 0,88 mV, 3σ = 2,64 mV
Offset
Offsetimproves
improvesapprox.
approx.with
withthe
the
square-root
square-rootofofthe
thearea
area
MOS - Comparator with Push-Pull Current Output
Rule for no systematic offset:

M9 M3 M4 M6
( w / l ) 6 ( w / l )7 ( w / l )9
50µA = ⋅
5µA 5µA ( w / l ) 4 ( w / l )10 ( w / l )3
10µA OUT
IN M1 M2 IP
Ibias 50µA
10µA
M10 M7
M8 (NLB)
M5
The symmetrical design is a method to achieve low systematic offset

take care of current mirror accuracy: further improving by use of cascode mirrors
According voltage gain it is a „single-stage“ amplifier

(lower gain, good for stability)

MOS - Comparator (OTA) with Cascode Output
M9 M3 M4 M6
VB1 M12
IN M1 M2 IP
OUT
Ibias VB2 M14
M10 M7
(NLB)
M8 M5
VB1,VB2:
Cascode output to increase the open-loop gain Bias voltages for cascode
Disadvantage: Limited voltage swing at output

MOS - OTA: Folded Cascode
M9 M3 M4
I3 I4 I3 = I4 ≥ I5
I1 I2 VB1 M12
OUT
IN M1 M2 IP
VB2 M14 Cout
Ibias
I5
M6 M7
M8 M5
static condition: I3 = I5 = 2 * I2 -> I6 = I2 , I7 = I1

Advantage against normal cascode output (page before): extended output swing
Single gain stage, no internal compensation capacitance required
Capacitive load at output is the dominant pole
Folded cascode OTA – frequency response
larger Cout
increases the
Coutá phase margin
no internal
compensation-C
required
91,3°
118°
172°

Folded Cascode Example (1) (SPT4)
w2=4.4u
Vcasc
w1=22u
Source: S959 / bmc3 (SPT4) w2 < w1 to generate Vcasc (thumb rule w1/w2 >= 4)
Folded Cascode Example (2) with Bipolar Input S1969 / diagcursink_amp1
(SPT5)
switches to set definite (not floating) and symmetric voltage conditions

in standby (off) condition -> otherwise drift (offset) could appear over lifetime
Folded Cascode Example (3) (SMART 5)
bipolar input
for low offset
Depletion Trans. as bias current source

(only available in SMART) Source: L8211 (SMART 5)
H.Zitta – Smart Power Analog – Comparators & Opamps
3.3 – Comparators, Opamps 229
Bipolar - Comparator
OUT
IN IP
I4
I1
NLB
Using
Usingbipolar
bipolarasasactice
actice
components
componentsand and
MOS
MOSfor
forthe
thecurrent
currentsources
sourcesisis
aagood
goodmix
mixfor
forbicmos
bicmosopamps
opamps
and
andcomparators.
comparators.

Open Loop Gain - Bip vs. MOS
gain increasing gain

bias current
f f
Bipolar:
Bipolar: MOS:
MOS:
more
morebias
biascurrent
current->
->more
moregain
gain more
morebias
biascurrent
current->->less
lessdc
dc-gain
-gain
but
butmore
moregain
gainatathigh
highfrequency
frequency
Note: very simplified bode-plot, only first pole shown
Detailed AC-analysis of opamps is not part of this course, there are a lot of literature and
textbooks available to go in more detail.
Comparator with P-Devices as Input
PLB
OUT OUT
IN IP IN IP
bipolar: pnp-input MOS: p-channel input
Use
UseP-Input
P-Inputcomparators
comparatorsfor
forinput
inputvoltages
voltagesnear
nearGND
GND(neg.
(neg.supply
supplyvoltage)
voltage)
Pnp-Input Comparator: Input Voltage Range
Vcc
Voltage > 0,5

input range
min / max 1/ (Vcc–0,5)
OUT
0.7
IN IP
0,3 / Vcc-1,2 0,3
0.7

Darlington Inputs
PLB
OUT
OUT
IN IP IN IP
pnp - Darlington P-channel - levelshift
For
Forinput
inputvoltage
voltagerange
rangeincluding
includingGND
GNDuse
useP-darlington
P-darlingtoninput
input
Pnp Darlington Comparator
Application: current measurement
icomp / S0955 (SPT4)

P-Input MOS Comparator
Application: logic input buffer with special input specification range
ibufd / S0955 (SPT4)

Npn -Input Comparator
Application: open load voltage measurement
opld / S0955 (SPT4)

Emitter / Source Follower
Used as buffer.
No voltage gain (=1),
but can deliver Vin
current into a load.
Does not invert the phase, Vout
compared to gain stage
AC: Vout = Vin
DC: Vout = Vin - Vbe
signal polarity:
emitter follower gain stage

not inverting inverting

Opamp as Buffer
In
Out
C Out
(+) (-)
Vin = Vout -> closed loop gain = 1 In
I4
AAclosed
closedloop
loopgain
gainof
of11(0(0db)
db) I1
isisknown
knownas asmost
mostcritical
criticalfor
for Bias
stability
stabilityconsiderations
considerations
avoid
avoidtoo
toohigh
highopen
openloop
loopgain!
gain! simple solution: one gain-stage opamp
For a buffer-circuit with closed loop gain =1 an amplifier with only one gain
stage and an output buffer with no additional gain (source follower) is a good
choice to simplify frequency response requirement for stability.
Anyway check with AC simulation if a compensation C is required.

MOS Opamp with Buffered Output (Source Follower)
large (w*l) for

low offset
2-stage
2-stagemiller
millerOTA
OTA++no-gain-buffer
no-gain-buffer bg_buf / S1222 (SPT5)
npn-Input Opamp as Buffer
(voltage follower)
in DOPL technology highohmic

poly-resistors are available
Low gain (only one gain-

stage),
Vin gives the chance that no
frequency compensation is
required for stability.
Vout
Check anyway allways
stability with AC analysis!
Source: S1174 (DOPL)

npn-Input Opamp as Buffer (voltage follower)
current limit
Wilson mirror for
higher accuracy
Application:
buffer to supply
internal bandgap-
voltage to an
external pin.
Degeneration
resistors to lower ESD protection
gain (stability)
Source:
S1041 bgbuf
(SPT 4)
Push-Pull Output Stage
Iout
(-) Iqu Out
(+)
I2
similar
similartotoaa
I1 traditionell
traditionellaudio
audio
Bias
class
classA/B
A/Bamplifier
amplifier
This output is able to source and to sink currents with help of

a npn and a pnp emitter-follower.
The output stage has no voltage gain (gain =1) so over all this is an one-stage amplifier.
Possible Iout is higher than the qiescent current Iqu -> class B mode
If Iout max Iqu -> class A mode.
Stabilization and temp.compensation of Iqu with help of the diodes
Opamp with Push-Pull Output (1) example SPT4
Application:
Error amplifier in a linear
voltage regulator
R,C for frequency

compensation

Opamp with Push-Pull Output (2) example SPT5
opreg5 S1289
(SPT5)
N-input MOS Comp with Hysteresis
Application: logic input buffer ebuf / S0940
Against the rules here the current

mirror transistors M4/M5 has not
the same size! This causes an
offset and this offset is used to
define a hysteresis.
M7 is used as a switch to connect
in parallel M6 to M5 if Vout is low.
Vin Vout
Offset
Vref
Vref Vin
Nbias Hysteresis
Resulting offset is larger if gain of comp. is

low, therefore w of M1, M2 are small
npn-input, otherwise MOS comp.
Application: voltage measurement
Bipolar input for low offset

Unwanted
Unwantedeffect
effectofofbipolar
bipolar
MOS for smaller area devices
devicesisissaturation-
saturation-
behaviour:
behaviour:
Saturation
Saturationofof T2
T2will
will
increase
increaseinput
inputcurrent
currentIP.IP.
bmk1 / S0940
Bulk Parasitics npn-Saturation
P-zones inside the epi can form the emitter of a parasitic pnp
with epi = base and p-substrat =collector.
In normal operation condition of the npn the epi (C of npn) is always higher than the p-zones
inside. But if the bipolar npn goes into saturation, collector voltage drops to a lower level than
base(npn) voltage (VC < VB). Now the parasitic pnp starts conducting.
This effect is well known as the saturation problem for the bipolar transistor, current gain
decreases because the base current now feeds the parasitic.
C B E
N-sinker
N-Epi P N+
N
P
P Ib
N+
P
P-Substrat
NPN-transistor with parasitic substrat PNP

Countermeasure against Bipolar Saturation Parasitic
1) Layout 2) Circuit design
This parasitic effect can not be avoided For circuit design it is recommended to avoid
complete, but the gain of parasitic pnp can be saturation of bipolar components.
reduced by applying a closed n-sinker ring In analog circuits it can be e.g. done by
round the base. applying a clamp-voltage via a diode to the
collector.
N-sinker ring
C B E
P
N-Epi P N+
N P Vclamp
N+ Q1
P Vce
P-Substrat
Clamping circuit to avoid

saturation (Vce < Vbe) of Q1
Bip/MOS Comparator with Hysteresis
with clamp voltage (vr3) to avoid bipolar saturation
Adds current in
Q3 clamps Vc of Q2 one path to
not to go lower than Vb
obtain a
hysteresis
vref 1,25V
bmk3 / S0940
Calculation of Hysteresis of Bipolar Comp.
If size of M1 not equals size of M2, currents I1,

M2 I2 will not be equal. This causes an offset which
can be calculated with the Delta-Vbe equation
for bipolar:
M1  I1 
∆ V BE = ln   ⋅ Vt
 I2 
1:n
Switching on and off this offset depending of the
output voltage results in a hysteresis.
Hysteresis will be temperature dependent according
I2 Vt behaviour but very accurate compared to
I1 Out comparators with MOS input stage.
IN IP
30,0
25,0
20,0
Delta Vbe
example 15,0
for n=2: 10,0
5,0
0,0
-50 0 50 100 150
Temp (C)

High Voltage Comparator
built in offset, low voltage output, with hysteresis
high voltage supply
Ibias
built in offset Vo = •R
2
hysteresis
low voltage supply
IT10
Bias Current IT10 generated with

resistor of same type as R1
Comparator with Emitter-Input
if Q1, Q2 are same size:

no offset,
switching point at Vin = 0
OUT if Q1, Q2 have different size:

switching point can be calculated
with Delta-Vbe formula:
Q1 Q2  size Q 1 
V IN = ln   ⋅ Vt
IP  size 
 Q2 
V IN
IN Note:
Input current is equal to collector currents.
npn- emitter-input To take into account for accuracy.
For input-range near ground e.g. current measurement

Pnp Emitter / P-MOS Source – Input Comparator
IN
Vbat
IP
IN
M1 M2
IP Q1 Q2
Ibias
OUT
OUT
(NLB)
For input-range near Vbat e.g. current measurement for high side switches
Different size of Q1, Q2 or M1, M2 can be used to design the wanted offset
(bipolar gives higher accuracy)
Current Comparator
VCC
A current mirror (bip or MOS)

can simply be used to compare
two currents
I1 I2
OUT You can call it a
„current amplifier“ or a
„current comparator“
Q1 Q2 where the input signals are not
voltages, but currents.
I1 > I2: OUT = High

I1 < I2: OUT = Low

High Voltage Input - Current Comparator
To sense high voltages with low voltage devices
IP IN IP IN
VCC VCC
R1 R2
R1 R2
OUT OUT
Only resistors have to withstand the high input voltage (no problem
with poly resistors), active devices can be low voltage devices.
MOS-circuit:
MOS-circuit:take
takecare
careto
toadd
addz-diodes
z-diodesfor
for
overvoltage
overvoltageclamping
clampinge.g.
e.g.against
againstESD
ESDevents
events
Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.4 – Diagnostic & Protection 257
Protection and Diagnostic of Smart Power Switches
Overcurrent
Overvoltage
on Overtemperature
Open Load
feedback- measure
loop
switch - off
latch
reset
status logic
This is really the „Smart“ part of our Smart Power devices

3.4.1 Temperature Sensors
3.4.2 Current Measurement
3.4.3 Overvoltage Protection
3.4.4 Openload Detection
H.Zitta – Smart Power Analog 3.4.1 – Temperature Sensors 259

Temperature Sensors
function principle comment
I-leakage very simple

only possible for high
1) I-leak using leakage current as
temperatures (>150°C)
temperature information
very recommended
Vbe
2) using Base-Emitter voltage accurate, real „physics“,
not too sensitive to
Vbe of bipolar transistor
fabrication process
other parameters not recommended
any other parameter which fabrication tolerance of used

3) changes with temp. parameter causes inaccuracy
e.g. Vth, R, Isat, ...

Temperature Sensor (1)
Using the leakage current as temperature signal
V+ ICB
ICB
R1 T
150 °C
VTMP VTMP
I1
T
The base-emitter of a bipolar npn ist connected to a resistor

(or current source).
With shorted B-E normally you will expect no current through the
npn, but at high temperature the leakage current (Icb) will switch on
the npn:
This can be used as „high-temperature“ information
Leakage Current Based Temperature Sensor
n The leakage current is very low at junction temperatures

< 150°C
n For higher temperatures it increases exponentially, V+

doubling approx. for each 10K of temperature ICB
n Therefore the leakage current is a good indicator to

detect an overtemperature in the range > 150°C in R1 VTMP
integrated smart power circuits
n In a MOS technology the always available parasitic
I1
substrat npn can be used as bipolar device
n The temperature threshold is only in a given range
adjustable by the values of R1 and I1, the exact
temperature is not predictable (in comparison to direct
Vbe measurement)

How to Find a Bipolar Device in a CMOS Process
Substrat-
P-channel N-channel npn +Vbat = Substrat
S G D S G D E B C
B
B
p- E
p+
n+ CMOS p-well process
n Substrat
e.g. logic part of Smart-Techn.
C
n In any CMOS process the well can be used as base of an substrat
bipolar-device
n For n-substrat (as used in selfisolated vertical Smart Power

technology) this is a npn transistor. For p-substrat it would be a pnp.
n This substrat-bipolar is very usefull in circuit design for temperatur

sensors and bandgap-reference circuits, which need bipolar devices.
Temperature Sensor Circuit (2)
Comparing of the bipolar VBE voltage with a stable reference
IC=I1+I2
I2 IC=I1
I1 UBE
Vconst. M1 M2
VREF
(Bandgap)
VTMP T
R1 IC VTMP
Vref R2 Q1 M3
The diode-voltage Vbe of a bipolar device depends linear on temperature, Hysteresis

-2mV/K, and is therefore very well suited as a temperature sensor. The
temperature threshold can be precise set with help of a stable reference
voltage e.g. from a bandgap reference. Changing the collector current IC
by means of switch M1 adds a temperature hysteresis to the circuit.
Bipolar
Bipolarcharacteristic
characteristicofofapprox.
approx.-2mV/K
-2mV/KofofVbe
Vbeisisvery
veryreliable
reliabletotobe
beused
usedas
astemperature
temperaturesensor
sensor
Vbe-Temperature Sensor: Threshold Calculation
With known characteristic of npn, the temperature threshold can easy be

estimated as follows:
Assume: Vbe = 0.65V @ Ic=10uA, room-temp.(300K or 25..27°C)
Target: Temp-threshold should be 175°C
There exist 2 operation currents: 10uA or 20 uA (hysteresis-circuit)
Calculate for 20 uA:
20 µ A = •
k
= 26 mV @ 27°C/300K
∆ Vbe = ln( n ) ⋅ Vt n = =2 Vt T
10 µ A q
= 39 mV@ 177°C/450K
∆Vbe = 18 mV @ 300K or 27 mV @ 450K
For Vbe = f(T) use -2mV/K as an estimation: Vbe(175°C) = Vbe(25°C)

Vbe (175 °C ) = Vbe ( 25 °C ) − 0 . 002 ⋅ (175 − 25 ) = 0 . 65 − 0 . 3 = 0 .35 V
This is true for Ic=10µA for Ic=20uA : Vbe=0.35V + 0.027V = 0.377V
Now set the reference-voltage VT with help of R1, R2 to 0.377 V to achieve a
temperature sensor threshold of 175°C.
Lower threshold (hysteresis) will than be 27/2 = 13.5K lower = approx.160 °C
Circuit Example of Vbe-Temperature Sensor with Hysteresis
+ 5V supply
bias
10µA 10µA
I-bias =10µA
Vbg
Bandgap
Reference R1 10 or 20 µA
This
Thiswaswasaastandard
standardcircuit
circuitfor
formany
many
R2 SPT4 designs.
SPT4 designs.
But
Butititisisnot
notrecommended
recommendedfor forfuture
future
usage
usage because of the „reversecurrent“
because of the „reverse current“
Take care in layout-design to use separate GND-connection for sensitivity (coll. = epi well)
sensitivity (coll. = epi well)
temp-sensor to avoid inaccuracy caused by voltage-drops
More Temperature Sensors, Using Same Reference
Vbg IB1
Bandgap- Channel 1
Reference
If there are more bipolars connected to the IB2

same reference voltage, activating of one Channel 2
bipolar, caused by local overtemperature, could
need more base current because of the
saturation effect of the bipolar.
Therefore it is recommended to use a buffer

which can provide more current than the
bandgap output.
IBn
Channel n

Lowside Switch with Vertical Smart Technology
+VS
If a low-side switch is realised
in a vertical Smart Tecnology Rload
than the drain of the DMOS =
Output= n-substrat. n - Substrat
If switched on, Vdrain is low
(close to GND voltage). C
Drain=OUT
Im that condition the substrat B
Substrat moves
npn has no suply voltage and E
down during
cannot be used as switching
temperature sensor. driver
GND 0V
another device has to be used as temp-sensor

Temperatursensor-Circuit (3)
Using the temperature dependence of MOS characteristics
V1 V2
IREF V1
V2
TMP
V1
T
w/l small M21 TMP

w/l large
z.B. 10/42 M1
z.B. 170/10
high M22 low
current density current density
T
If in a MOS technology the substrat-npn cannot be used because the substrat is pulled down against
ground-level in the ON-state of the power-switch („Hitfet“ Low-Side-Switch in SMART technology), this
concept uses the different behaviour of MOS characteristics below and above the „temperatur-stable-
point“ for temperature measuring.
This
Thismethod
methodisismore
moresensible
sensibleto
tofabrication
fabricationtolerances
tolerancescompared
comparedto
toVbe
Vbemeasuring
measuring
Temperature Sensor for very high temperatures
with leakage current compensation
leakage curent
compensation of C-Sub
and C-B leakage allows
C-B leakage operation up to to 300°C!
used for hot-spot

measurement inside a
DMOS which is used to
fire an Airbag.
C-sub
leakage
T1 is the temp. Sensor
T31 is a leakage sensor
source: S936/tsensd (SPT4)
Bipolar Transistor
Sensitivity to Leakage- or Parasitic Currents
C B E
n+
p
p+ p+ C
n-
n+ B
Leakage currents E Sub

p-substrat
The collector of an npn-device is Rootcause of this leakage current
sensitive according to leakage could be:
currents to substrat. This is a risc for - High temperatures
the functionality of analog circuits, - Reverse current at a DMOS
which use bipolar transistors (instead
of MOS).

Temperature Sensor with npn-Collector at VCC
For reverse current applications
VCC
Vref
OT
Epi well (C of npn) is often affected by

parasitics (reverse current, EMC, ...) Hysteresis
Solution:
Solution:
Temp-sensor
Temp-sensorwith
withnpn-C
npn-Cat
atsupply
supplyline,
line,
emitter
emitteras
astemperature
temperatureinformation
information

Very good for reverse current, disadvantage: Offset of MOS-Comparator!
source: S1077/tsens (SPT5)

Buffering the npn with sourcefollower, supplied by Vbat
High current from C to VBat

VBat substrat (reverse current
condition) does not
increase 5V current
Ref_5V
consumption
Vref Isub
OT
Hysteresis
source: S1071 (SPT5)

Temperature Sensor Based on Cross-Coupled Current Source
needs no additional voltage reference
VS
UR2
M1 1:k M2
R1 M3
I1 M4
I2
T
VTMP
I3
Q1 Q2 UR3
M5
UBE(Q5)
Q4 Q5 T
Q3 1:n
U R3 VTMP
R2 R3
U R2
E m itterfläche ( Q 4 ) w / l( M 2)
n=
E m itterflä che ( Q 3 )
k =
w / l ( M 1)
T
ln( n ) ⋅ Vt R3
I2 = I3 = k ⋅ I2 U R 3 = I 3 ⋅ R3 U R3 = ln( n ) ⋅ Vt ⋅ k ⋅
R2 R2
Positioning of Temperature Sensor in Layout
C
E A center –hot spot *)
Power-DMOS B inside, but not center
C outside, at long edge
D outside, at short edge
D B A not recommended – to cool!
E outside, for general
chiptemperature
Temperature
tmax(hot-spot) *) because the sensor needs a „hole“

inside the DMOS it will not see the full
hot spot temperature but a little bit less.
Use thermal simulation to define the

each sensor-position will see temperature threshold of the sensor
another temperature for same to ensure protection in case of short
overload condition! circuit with max. power dissipation.

Thermal Simulation
Ch 3 Ch 6 Ch 2
To decide size
Treiber Treiber Treiber
of power-DMOS
(if not only
Logik R-on related)
and best position
of temperature
Treiber Treiber Treiber
sensors
Ch 4 Ch 5 Ch 1

Verifying of the
Thermal Model by
Infrared Thermografy
Modelling of thermal behaviour of chip and
package. This example is a power package
with a heat slug included inside the package. 4
Chip is soldered to heatslug, heatslug is K/W
soldered to PCB. Thermografie (30W , 147°C)

Tjunction FEM (4.5W , 141°C)
2
heatslug
Tcase 0
-2 -1 0 1 mm 2

Differential Temperature Sensor
Tempsens for Tempsens for For improved overload protection there
leadframe temp. DMOS core temp. could be introduced a differential
temperature measurement in addition to
the absolute temperature monitoring.
This can improve the number of short-
circuits events a device could withstand.
Controlling the max. temperature
Vbe1 Vbe2 difference on a chip with two sensors can
help to increase the short-circuit lifetime.
OT The delta-temp. value is set by
applying different currents in the
bipolar transistors.
1
∆T = * ⋅VT ⋅ ln(n)
2
I1 1:n I2
with n=10, Vt=37mV(@150°) ->
∆T = 43K
example from L8200B11 (Testchip, Smart5), A.Zanardi *) acc. to tc of Vbe approx. -2mV/K
Absolute & Differential Temperature Sensor
Vs For more flexible setting of the

delta-temp value here a
V1 bandgap reference circuit is
used
V2
Bandgap Vref
V1 defines delta-temp. value
Reference (approx. 2mV / K)
compared to the solution of the page
before the value is const. over temp.
V2 defines absolute temperature

absolute delta
temp. temp.
In L8211 the comparators
use bipolar inputs (thanks
to SMART 5 possibilities)
concept from L8211B (Smart5), L.Petruzzi to minimize the offset

H.Zitta – Smart Power Analog 3.4.2 – Current Measurement 281

Current Measurement with Shunt-Resistor
ILAST
To measure a current you
must transfer first the current
into a voltage -> resistor
V1
ILAST
VREF
V1 IOVL
+
- IOVL
R1 VREF
Requires a reference voltage

Current Measurement with Shunt-Resistor
Comparator uses Delta-VBE principle
ILOAD
I1 I2
VR1
ILOAD
IOVL VS
Q1 Q2
n:1 VIOVL
R1 VR1
Calculation of threshold VS:

I
V S = Vt ⋅ ln( n⋅ 2 )
I1
n = ratio of emitter areas Q1/Q2 z.B. I1=I2 , n=2 VS = 18 mV bei 25C
R1 as aluminum-resistor results in a good first order temperature compensation of Vt (TKAL= 3,8 10-3 )

Improved temperature compensation
for current measurement
Delta Vbe: TK = 3,1 .. 3,3 10-3

Alu-Res: TK = 3,8 10-3
I1 I2
ILOAD
IOVL Temp-Error for 100K:
1,38/1,32 = 1,045 (4,5%)
Q1 Q2
n:1 -40C .. +150C
UDVbe for this temp-range approx. 10 %
This could be improved by use of the
R1 alu VR1 R2 poly VR2 poly-resistor R2
V R1 = VDeltaVbe + VR2
n = ratio of emitter areas Q1/Q2

Current Measurement with Sense-Transistor
Shunt-resistance in series to sense-cell
ILOAD
I1 I2
ISENS
M1 z:1 IOVL
M2
Q1 Q2
n:1
I LOAD
R1 VR1 V R1 = ⋅ R1
z
The layout of the powerdevice (DMOS) in general consist of many cells (> 1000). One or few cells are
used as sense cells, the current ratio between main (M1) and sense DMOS (M2) is defined by the ratio z.
The shunt resistor R1 must therefore not be dimensioned for the full load current and, as additional
advantage, the shunt resistor does not generate a voltage drop in series to the power DMOS.

Sense-cell with Shunt-Res., Reference-Current with Reference-Resistor
ILOAD
M5
M3 M4
ISENS IR1 IR2
z:1 M2 IOVL
M1
Q1 Q2 IREF
1:1
R1 VR1 R2 VR2
I 
V R1 =  LOAD + I R 1  ⋅ R1 VR 2 = I R 2 ⋅ R2 Q1,Q2 are input stages of a
 z  comparator and do not use
R2
with IR1 << Isens and IR1=IR2=IREF I OVL = I REF ⋅ z ⋅ the delta VBE principle!
the threshold can be calculated: R1

Current Measurement
Temp. compensation of alu-resistor with body-diffusion + poly res. (SPT4)
ILOAD
IBias IBias IREF
ISENS
Adjusted
z:1 M2 IOVL
M1 reference current
(zener zapping
Q1 Q2 at wafer level)
1:1
Advantage for layout:
Rpoly Rd Rd bipolar can be far from
Ralu alu-resistor
Rbody All resistors at same
temperature is easier to
manage in layout as the
combination bip + alu-
Diffusion resistor (rd) usually have a positive tc
resistor
which can compensate alu-metal resistor
Current Measurement
Compensation of inaccuracy, caused by Vds(M2) < Vds(M1)
ILOAD
If the different drain-source
voltages of M1, M2 cannot
be neglected, adding M3 in
IREF parallel to R3 can help to
z:1 M2 improve accuracy.
M1
M3
R2 R3
R2 : Ron(M2) = Ron(M3) : R3 (Harris: HIP6050)

without Shunt-Resistor
ILOAD
ILOAD IREF
VP IOVL
VP
M1 z:1 VN VN
IOVL
M2
VP = RdsOn ( M 1) ⋅ I LOAD
VP = RdsOn ( M 2 ) ⋅ I REF
R d s O n ( M 2 ) = z ⋅ R d s O n ( M 1)
Here the voltage drop at the power-transistor itself is used as current measuring device.
This allows the measurement of high currents (overload) and very low currents (open load
detection), depending on the choosen value of the reference current.
Current Measurement for Low Currents
e.g. normal operation 2A, open load detection 2 mA
Feedback loop with

ILOAD IREF K1 VDS K2 increases VDS
IOpenLoad at low currents
M1 M2
VREF
VDS z:1 ILoad
K2
2 mA 2A
Normal Ron behaviour

VREF without use of K2
In that given example the voltage drop at the DMOS VDS is too low in comparison with the offset
voltage of a comparator, e.g. Ron = 0,3 Ohm, nominal: 2A * 0,3 Ohm = 0.6V, open load: 2mA*0,3
Ohm = 0.6 mV! Solution: Increase of Ron by regulating the gate voltage in a feedback-loop which
controls that VDS is never smaller then a given value Vref ( e.g. 50 mV).
Current Sens-Output in a Highside Application
+ Vbat
With sens-cells (M2) a given ratio of the
D load current can be mirrored to the pin IS
Gate
(current sens) as current feedback signal.
M1
To obtain the same source voltage at the
M2 sense-DMOS as of the power-DMOS the
z:1
S gate voltage of an additional Transistor
M3 in series to the sens DMOS M2 is
S-sense controlled by a regulation-loop.
With an external resistor Rsens this
current Is can be transformed to an
M3
analog voltage, which is proportional to
ILoad Is
the load current.
OUT IS
The accuracy depends on the matching
A/D ratio M1/M2 and requires a low offset
µC comparator, especially if measuring low
RLOAD Rsens currents.
For SMART Technology (Highside Switch) the Sens Ratio of DMOS cells
is more accurate as for SPT, here the ratio of few cells to a large DMOS is
not well defined. In SPT the sens-ratio will differ between Ron and
saturation mode of DMOS.
Sens-Ratio „KILIS“
k = ILoad / ISens -> kILIS Example from data sheet BTS 5234
at low currents the KILIS

accuracy is worse because of
the offset of opamp, which is
significant compared to the
voltage drop at the DMOS.
At low temperature (-40°C)
DMOS-Ron is lowest -> more
error.
KILIS accuracy depends also
on threshold voltage
matching and on bonding.

Matching Error of Updrain-DMOS Structures (SPT)
G drain-connections
D S Drain
source-
cells
p+ p+
n-sinker burried layer

Due to the „updrain concept“ the inner cells have higher ny
resistance as outer cells: cells are not equal acc. Rdson.
This gives limited accuracy by using small DMOS
transistors as sens-cells e.g. for current measurement
The sens-ratio will also differ between Ron and nx
saturation mode of DMOS!
Current Sens-Output (Current-Feedback)
in a Lowside Application
Vbat
Vdd = 5V
RLOAD Rsens VRSens In principle the same concept as

OUT CFB for highside could be used.
VCFB But for voltage drop Vcfb limits
the available outpt voltage Vrsens
M3 to Vrsens = Vdd – Vcfb.
For lower currents this will be no

D
z:1 D-sense problem (Vds2 = low) but for
M1
higher currents it‘s better to use
M2
another concept (see next page).
VDS2
.

Accurate Current Feedback (for Low-Side SPT )
adjustment to correct external

resistor µC
the error of
ILOAD A/D
sens-ratio z
(layout dependend) CFB
Ratio:
IFB
I Load R
M1 z:1 M2 = z⋅ 2
I FB R1
R1 VR
R2
For precison and linearity from low to high currents choose voltage drop VR not to small
Use bipolar comparator for low offset.
Current Feedback - Lowside
adjustment with zener zapping
bipolar comparator with

transistors for adjustment have to be crosscoupled input stage S 977 (ATIC 39)
outside of the the regulation loop
S1073 (TLE 6214)
H.Zitta – Smart Power Analog 3.4.3 – Overvoltage Protection 297

Overvoltage Protection Concepts
Switching off an inductance generates an overvoltage: protection needed.
Vs Vs Vs
R+L R+L R+L

IOUT IOUT
Vz
on->off
External (power)z-diode External or internal free- Internal z-diode from drain to

from drain to GND wheeling diode gate switches on the DMOS
Switch off delay could in case of overvoltage
be a disadvantage High power dissipation
at the DMOS
Overvoltage Protection - Switching of Inductive Loads (1)
ton Vs
VIN
R+L
IOUT Imax
IOUT
Vz
VZ
IN
VOUT VS
tclamp
To avoid an overvoltage
destruction the DMOS is
switched on by use of z-diodes
Current during turn-on:
form drain to source.
 − 
t
VS L Caution: now all magnetic
I = I max ⋅  1 − e τ  Imax = τ =
  R R energy has to be dissipated by
the DMOS chip area.
Switching of Inductive Loads – Calculation of Power Dissipation
L ⋅ I m ax 2
Magnetic energy: Em =
2
Clamping voltage: VZ = VL + VB
L+ RL VL VL = L •
di
Voltage at inductance:
IOUT
dt
di I
VB Current slope: = max
dt t clamp
L
Time to demagnetise: t clamp = • I max
VZ (V Z − V B )
Electrical power dissipation: Eel = ∫ I out ⋅Vz ⋅ dt
L ⋅ I max
2
VZ
Electric energy: E el = •
2 VZ − VB
= Power dissipation in DMOS during clamping
simplified, neglecting ohmic power losses at RL and losses due to eddy currents

Switching Off an Inductive Load
Dependence on Battery Voltage – Simulation
t0 t12 t24
tAZ
12/24 Ω
VIN
10 mH
12/24V
VB=24V
IOUT 50V
VB=12V
VB=24V
VOUT
VB=12V
Simulation done with same inductance and current (same magnetic energy), but different VB.
For higher VB the switch off time is longer -> this generates more power dissipation

Inductive Clamping Circuits
Vs Vs
Vclamp = Vz + Vd + Vth
Vz
Vz
Clamp detect
Vclamp
Vd
OFF
R1 Vth Vth
Adjust clamping voltage by number of Adding bipolar diodes for temperature

z-diodes, for 60V process e.g. Vz = 50V compensation.
R1 to define minimum current in z-diodes Clamp detect signal, e.g. for slew rate control

Inductive Clamping Circuit - Referred to GND
first diode reverse

to avoid epi-well at Here the clamping voltage is
output measured in respect to GND.
This gives more accuracy, no

dependency on the DMOS threshold
voltage.
Temperature compensation of the

z-diodes (positive tc) with a Vbe
multiplier (negative tc)
R1
bipolar temp. comp
test pad to deactivate R2 V = (R1+R2)/R1 * VBE
clamping (test mode)
e.g. S977/ATIC39 SPT4

Clamping – must work also with VDD = 0V or open
Vs
n check clamping with all VDD values
and impedances
n check, that driver does not short
the clamping function
Gate Driver
consider low voltage VDD
or short or open on „Gate stress“
VDD Test pad
insert resistor not insert resistor to allow higher

to short clamping gate voltage for test purposes
Clamping with Slew Rate Controlled Soft Clipping
Clamping voltage defined by

bandgap ref, not with z-diodes
+ > 85V
Vref
Reference
Power
Voltage DMOS
+ > 70V
OFF S955 (Spt4-90)

Ref-voltage and comparators have to be supplied via Drain to guarantee
clamping function in case of loosing or missing supply voltage
Clamping: Voltage Defined with Bandgap Circuit
Vout
I1
V3z Normal operation: Vout < V3z, no
current flow I1.
If voltage Vout increases due to
inductive clamping (Vout > V3z), the
R1
Vs-bg bandgap circuit is supplied (Vs-bg)
and M1 switches on the resistor
divider R1,R2. Now the bandgap
M1 functionality regulates Vout to the
value Vclamp:
Gate-Drive R + R2
V Clamp = Vbg • 1
Vbg R2
With a good matching of R1,R2-ratio
R2 this circuit could give better accuracy
and temperature compensation of
the clamping voltage compared to
a only z-diodes referred circuit.
Bandgap-based Clamping Circuit
Usable for Low and Highside Configuration
drain Clamping voltage is defined by bandgap-
voltage (1,25 V) and resistor divider plus
Vz
3 z-diodes.
R1 + R2
Vds(clamp) = 1.25V ⋅ + 3 ⋅Vz
R1
Vz
In a highside config. the source voltage will
go below ground during clamping:
P-type diffused resistors (or poly-res, if
available) can be used below ground, so the
circuit is also working in a high-side switch in
VBG R1 BCD technologies.
For required operating also in case of

missing supply voltage the circuit is supplied
Vz from the drain-source voltage only.
Remaining 3 z-diodes in series prevent
R2 leakage current at normal operating up to
source Vbat = 18V.

Clamping Circuit
For Highside Switch
in SPT Technology
Because Source goes below GND,

Z-diodes cannot be used
Clamping voltage is defined by

bandgap-voltage (1,25 V) and
resistor divider
P-type diffused resistors can be
VBG used below ground
For required operating also in case

of missing supply voltage the circuit
is supplied from drain-source
voltage only.
Remaining 3 z-diodes in series
prevent leakage current at normal
operating up to Vbat = 18V.
Note: Leakage current measurement of

DMOS with higher voltages is therefore
not possible.
Source: S 999/TLE 6288 (SPT4)

High Voltage Protection of Logic Input
HV n-channel
IN A high-voltage transistor in
+5V source-follower
M1 OUT configuration can protect a
High voltage
(logic) input against high
protected output
voltages.
For low input voltages M1

VOUT is fully on and vout = vin.
For higher input voltages
vout is clamped to max. vin
5V-Vth minus threshold voltage.
VIN

Circuit Example: High Voltage Protection of Logic Input
INPUT
Normal operation at
logic levels (0 – 5V)
but overvoltage up
to 40V can occur
Requirement e.g. from
Bosch for powertrain
applic.(EGAS-H-Bridge,
Multichannel Low´
SideTLE6244, LSPS) source:
S1271 / I_Pu-40V (SPT5)
Reverse Polarity of Battery Supply
normal
If the battery is reverse reverse polarity
polarity
connected (reverse
polarity) then it is not Rload - +
possible to switch of the
DMOS, because of the
always existing intrinsic +
source-drain diode. -
Current limit is only done

by the external load and
cannot be controlled by a
circuitry.

Measures against Reverse Polarity Condition (1)
reverse reverse
polarity polarity
Rload
Rload - -
S
M2
+ ON D +
M1
S
Internal 2 DMOS in „back to back“ configuration

External reverse polarity M2 is used as a diode and switched with the
protection diode same gate-voltage as M1 to reduce the voltage
drop in ON-condition.
Needs 4 times more chip area to get the same Ron!
Measures against Reverse Polarity Condition (2)
reverse
polarity
Rload -
switch on, if
VDrain < GND D
+
In case of very low-ohmic loads, the power dissipation during

reverse current (Vdiode * Iload) could destroy the device.
To avoid this, a circuit which switches on the DMOS during
reverse current is added, if Ron*Iload < Vdiode, then the
power dissipation is reduced.

n Diagnostic & Protection Circuits
– Temperature Sensors
– Current Measurement
– Overvoltage Protection
– Openload Detection
H.Zitta – Smart Power Analog 3.4.4 – Openload Detection 314

Open Load Diagnostic (at OFF)
+ Vbat To detect an open load condition the output

voltage is measured at off-state. A pull
Vref RL down current (or resistor) is used to pull
Open 3V RL
open,
down the output in case of an open load
Load Iout broken (broken wire). This pull down device always
OUT is seen like a “leakage” current during off-
Ipd state. Therefore a switch to disable this
e.g. 100 uA off DMOS current (e.g. in reset-mode) should be
foreseen to enable real leakage
measurement of power DMOS.
Open-Load In application this “leakage” current is

accepted, normal loads are not effected,
Iout but it could be that e.g. LEDs are visible
ligthing also with low currents in the 100µA
VOUT
range.
3V Vbat

Open Load Diagnostic (at OFF) - Calculation
The threshold of the open load detection depends on the
choosen pull-down current (Ipd) , the comparator threshold
voltage (Vref) and the supply battery voltage (Vbat).
+ Vbat
Open load detection level calculation:
VRL = VBAT − VREF = RL ⋅ I PD
Vref RL VBAT − VREF
3V RL =
Open open, I PD
Load broken
OUT with Vref=3V, Ipd=100µA
Ipd
e.g. 100 uA off DMOS Vbat = 6V -> RL = 30 kOhm
Vbat =16V -> RL = 130 kOhm
RL < 30 kΩ will never be detected als open load
RL > 130 kΩ will always be detected as open load
Range of commonly used pull-down currents: 50µA to 1 mA

If the application drives LEDs, this diagnosis current could be a
problem (LED may glow in off condition)

Short to GND Diagnostic (at OFF)
+ Vbat The open load detection in any

I-pull up way will also detect a short to
RL GND (or switch bypass).
Vref
2V Iout
Short to GND To differ between this two
OUT
conditions, the direction of the
Short to current can be used:
GND For open load the internal pull
Short to GND down current flows into the pin,
for short to GND the current
flow is out from the pin.
VOUT
2V Vbat
Iout

Open Load / Short to GND Detection Circuit
VDD
Diag 4 :2 :1
off
Open
0 uA 0 uA Load-Q
0 uA LOW
H
Normal Condition
H
DMOS = OFF
LOW
no failure Short
to GND-Q
100 uA
5 uA 50 uA
Bias
OFF

VDD
Diag 4 :2 :1
off
Open
50 uA 25 uA Load-Q
100 uA HIGH
L
H
Open Load LOW
Short
to GND-Q
100 uA
5 uA 50 uA
Bias
OFF

VDD
Diag 4 :2 :1
off
Open
> 100 uA > 50 uA Load-Q
> 200 uA HIGH
L
L
Short to GND
HIGH
Short
to GND-Q
100 uA
5 uA 50 uA
Bias
OFF
> 100 uA

Advanced Open Load / Short to GND Diagnostic Circuit
I1
Open
Load
Iout
DMOS
OFF
Short I2
to GND
Switch between internal pull-down Iout
and pull-up depends on output level:
Uout > 2,5 V -> pull-down I2 for Open Load det. 2V 3V Vout
Uout < 2,5 V -> pull-up I1 for Short to GND det.
Advanced Open Load / Short to GND Diagnostic Circuit

Blockdiagram of a Lowside Switch with Diagnostic Functions
Smart Two Channel Low-Side Switch TLE 5224 (S904) or TLE 6215 (S1069)
(SPT75) (SPT4)
VS
Thermal overload
ENA Open Load
IN1 LOGIC Overload
ST1 RPD
OUT1
Open Load
IN2 LOGIC Overload
ST2 RPD OUT2
GND
INTERFACE SMART-PART POWER-PART

TLE 5224: Realization of Diagnostic Functions
VS VS
Bandgap- Iref2 Iref2

Reference 50 uA 1 mA
Rref RL
Temperature-
Overtemperatur Sensor
Overcurrent
Status
1:z Pull-down
Open load current, resistor
Open load if ON VS 20k
R1 1kOhm 0,2 Ohm

Senscells DMOS
Open load voltage
Open load if OFF R2
Blockdiagram of 1 channel
Blockdiagram of One Channel of TLE 6220
4-fold Lowside switch (S946/SPT4)
PRG RESET VS FAULT

GND VS
normal function VBB

IN1 SCB / overload
open load
IN2 as Ch. 1 LOGIC short to ground
IN3 as Ch. 1
Output Stage OUT1
IN4 as Ch. 1
8 1 4
SCLK 8 4
Output Control
SI Serial Interface
SPI Buffer OUT4
CS
SO
GND

Digital Output of Diagnostic via SPI
Serial Peripheral Interface Bus
Diagnostic Serial OUT (SO) example TLE 6220/30/40:
7 6 5 4 3 2 1 0
2 bits per channel diagnostic
Ch.4 Ch.3 Ch.2 Ch.1 output:
HH Normal function Current overload and

HL Overload, Shorted Load or Overtemperature temperature overload use
LH Open Load
LL Shorted to Ground the same bit
Diagnostic Serial Data Out SO

MSB LSB
example TLE 6214: 7 6 5 4 3 2 1 0
2 bits per channel C h .2 C h .1

IC Overtem -
plus overtemperature flag to Channel Overtem -
perature Flag perature Flag
differ between current or HH Normal function

temperature overload HL Overload , Shorted Load or Overtemperature
LH Open Load (off), Under Current (on)
LL Short to GND

Example of an „all on one sheet“ design Hitfet BSP 75 (S934)
1 channel lowside, 500 mOhm, 1 A

Technology: SPT75 (1st design), now SPT4-90

ESD & Overvoltage
protection
hysteresis
test-pad for wafertest

of temp-sensor
Details of
temperature
S934 circuit sensor
(1)
define temp threshold
with resistor-ratio and
Delta-VBE
z-diodes for
inductive
clamping
Details of
S934 circuit test pad for gate-
(2) oxid stress-test
on wafer
resistor for slew-

rate control
current limit (switch on/off
time) and to
V t ⋅ ln( 3) protect circuits
I LIM = from gate-stress
Ralu
voltage
26 mV ⋅ 1 .01
= = 1, 4 A
21 mOhm

Layout S0934 / BSP75 Techn. SPT75
temp.sensor
DMOS 0,5 Ohm
current measurement
Metal-resistor for
OUT GND
IN
Drain Source
Gate

Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.5 – Driver Circuits 332
Switching Behaviour of a MOS Transistor
on off
Vdd Vs
I II III
Vgs
I1 RL
Vth
Cdg
Id
on
90%
off
Cgs Vds Vds
Vgs
10%
I2 td tf td tr
Ron . IL
t on t off
Resulting waveforms if
charging and discharging of
the gate with a constant Id
current

Gatecharge Plot
to understand switching behaviour of DMOS
ID Example from datasheet Qg

Infineon IPD14N06S2-80
IG
OptiMOS N-channel Qgs Qgd
80 mΩ / 55 V
VGS
The characteristic of the gate-voltage over time in case of

driving with constant current is presented as Vgs vs Qgate
(gatecharge) in data sheets of power MOS transistors.
This allows easy to calculate the required charge/discharge
currents to obtain a given switching time.
Gatecharge is, in contrast to other parameters, not
dependent from temperature.
Simulation Gatecharge – DMOS 5850 cells (from S1077, SPT5)
Drain voltage
Ron = 0.9 Ohm(25C)
+ 20 uA Qgate =
45 us * 20 uA =
Gate current 0,9 nC
- 20 uA
(for Vgmax=5V)
45 us
Gate voltage
switch ON switch OFF

How to Switch on/off a Gate-charge/discharge Current
Vdd
Vdd Vs
Vs
Igate-on RL RL
Power Power
DMOS DMOS
I gate-off
I gate-off Low = OFF
a) series switches b) parallel switch to current mirror

Simple Driver Circuit for Low-Side Switch
Gate charge and discharge with constant current
Vdd Vs
M1 M6
M2 M11 RL
M10
Ibias Igate-on
M7 Power
DMOS
M8 M9 Igate-off
IN
M4 M5
M3

Low Side Switch
Improved discharge circuit for switch off
Vs
Vdd
RL
M1
M2
Ibias
Power
DMOS
fast M12
normal
discharge fast
discharge
IN
M11
M4 M5
M3
2 discharge pathes: 1) low discharge current with M5 for slew rate control
2) higher discharge current (M11), controlled by switch M12
for reduce switch-off delay time
Circuit Example: Detail of „Soft Edge“ Switch-off Circuit
2 discharge paths
slow fast
using M14 (small

DMOS) in a „MOS
diode“ connection to
enable soft discharge
without
the fast discharge current is automatically with fast disch.
Iload
reduced by the decreasing gate voltage,
this smoothes the output voltage avoid an edge
– good for EMC
t
Optimizing of Switch-Off Current Shape to Avoid EMC-Radiation
Switching off with a “soft edge” will improve EMI behaviour
IN IN
Lower slewrate
ID = 2A
ID = 2A
VDS Soft
edge
VDS

EMC Measurement: Radiation Caused by Periodic Switching
IN
ID = 2A
fast Abstrahlungsmessung
Last 7 Ohm + 2m Kabel
100
VDS 90
80
70
dB
60
fast, worser EMC
Competitor
50
40
IN
30
slow 20
ID = 2A
10 TLE
slow,6240 GP
improved
0
100,E+3 1,E+6 10,E+6 100,E+6
Frequenz [Hz]
VDS

Low Side Driver
Complete circuit including current limit and inductice clamping
5000 cells
44 mOhm
44 mΩ
Specification:
ton, toff typ. 5 us, Ron typ. 0.3 Ohm (25C), current limit typ. 4.5 A, Vclamp typ. 50V S947 / SPT4
How to Prevent Switching-On in Case of Missing Vs ?
VBatt
VS
a positive voltage slope could switch

on the output due to the Cds
capacitance
In most applications it is not allowed, that a DMOS

can be avtivated (switched on) without supply voltage of the
driver circuit
Use Reverse Diode of P-channel Driver
to Discharge the DMOS-Gate
VBatt
VS
a positive voltage slope could switch

on the output due to the Cds
capacitance
Reverse diode of p-channel could help

to discharge, if VS = 0
but: does not work if VS > 1V or
highohmic (not connected)

Active Discharge Circuit (1)
VBatt
VS
This solution needs to

have access to VBatt.
active circuit to discharge gate if

VS =0 and Vbatt >0

VBatt
VS
If Vbatt is not available

on a pin, this could be a
solution.
disadvantage: always some current

consumption through R1 at shut off
(like a leakage current) – has to be
mentioned in specification

VBatt
VS
This circuit uses a pnp (or a p-
channel with low threshold) as
self-conducting device to
discharge the gate without
needing access to VBatt.
vs-ok
Rb disadvantage: additional
load at gate (Rb + diode)

Level Shift: Low to High Voltage
Vbat
+ 12V ... +40 V mp66
mph66
mn66
Vbat – 5V
+5V
VCC
mp00
ON
mn00
GND
High Voltage Level Shifter
Vs +50V
H ... Hochvolttransistor
Vdd +5V H H
Ibias
OUT
H 50V
5V IN
0V H
0V

High Voltage Level Shifter
Vs +50V
M4 M5
H H
Vdd +5V
H ... High Voltage Transistor
M7
Ibias H
I1
I2
OUT
IN 50V
5V
0V M3 M1 M2 H
M6 0V
Improvement: M7 as high-voltage cascode allows M2 to be low voltage (Mirror M1/M2)

Low Voltage Level Shift 3V –> 5V (for logic)
latching the information in a

flip-flop ->
no quiescent current needed
(like CMOS logic)
cell: Lev3sh5
S1071 E-Gas
SPT5

Low Voltage Level Shift 3V –> 5V (for logic)
with additional resistors for defined output signal in case of missing 3V supply
cell:
S1289 3to5_PU
(SPT5)

High Voltage Level Shift
MOS-Diode for gate-source

voltage protection against
high voltage
(could also be z-diode)
high voltage level shifter needs

always some quiescent current
here limited by current source
from book:
Balan, High voltage devices and circuits in
standard CMOS technologies

High Voltage Level Shift
without quiescient current from charge pump
Vcp
Vcp / Vbat
Vbat
Clamping against Vbat avoid
static current from Vcp
0 / 5V

High Side Driver – Vertical SMART Technology
Vcp > Vbat
DMOS-Drain
Vbat = Substrat = Substrat
switch on by zenerdiodes
activating the for inductive
charge pump clamping
Vchp
ON
Levelshifter necessary
to transfer GND
related signals to Vbat DMOS
Source
= Output
Depletion transistors switch off fast switch on
used as current source: slew-rate switch off slew-rate

High Side Driver (from L8205 / BTS 5234 SMART5)
ON
Vbat
=Drain
Gate
Source
= OUT
H.Zitta – Smart Power Analog 3.5 – Driver Circuits 356 356

Levelshift Vbat
form GND related High side driver
input to Vbat
detail (1)
Charge pump
ON
switching on
Charging the gate
with constant
current =
slew rate control
Charge pump Gate

Oscillator
limit gate voltage

with 8V Z-diode
limit charge pump

voltage with Z-
diode to OUT + 6V

High side driver detail (2) switching off
clamping: GND
Z-diodes limit
the voltage for
switch off subtrat=Vbat
inductive loads
p-channel controls
transition from fast to
slow discharge
1)
R & Z-diode to
fast discharge protect devices
current for during gate-stress
faster switch off test
2) slow additional
discharge switch-off
current for slew devices for
rate control improved EMC-
behavior

High Side Driver – Switching a Resistive Load
IN (ON) (OFF)
Iload
controlled slewrate
start with faster discharge
Vout to reduce delay

High Side Driver – Switching an Inductive Load
IN (ON) (OFF)
Vout
GND
negative voltage
caused by
switching off
inductive load

CMOS Logic in a N-Substrate Vertical Smart Prozess
Supply voltage dependence caused by Body effect of p-channels
+ 6 to 16 V + VBAT
VBAT P-channel N-channel
S G D S G D
B
+ 5V
VDD
p-
p+
n+
n- Epi / Substrat
IN OUT
If in a n-substrate HV-MOS or SMART
process the p-channels are directly in
the substrate (without additional well),
Vth of this p-channels is dependent on
the substrate voltage, which is usually
Vbat.
Inverter Threshold and Delay-time
Supply voltage dependence caused by Body effect of p-channels
VThresh (of logic-inverter)

+ 6 to 16 V 2,5
2,0
+ 5V
1,5
1,0
0,5
0,0
6 8 10 12 14 16 VBAT
e.g. in S-Smart projects logic

gates shows this behaviour.
In SMART 5 logic p-channels

are in separate wells to avoid time
this supply-voltage dependence.
High-Side/Low-Side Driver (SPT5)
normal z-diodes for

lowside clamping
3 pol z-diodes for

below GND clamping
in highside mode
mn66 with epi-well connected at highest voltage VCP concept of S1078 - simplified
SPT Technology: Component Selection for Highside Operation
with Negative Voltage Clamping Requirement
Diffusion PMOS NMOS NPN DMOS

Resistor C B E
SGD S GD D S G
V+ B B
p p- n+
p
p+
p+ p-n+p+
n+ n- Epi p+ n- p+ p+
n
n+ n+
p Substrat
GND (-) Epi well cannot be operated with a voltage negative to GND.
Therefore all components which use the epi-well cannot be used
in circuits for negative clamping, which will go below ground. V+
C=epi-well
Only devices which use p-diffusion inside the n-epi can be used:
p-diffusion resistor, N-MOS (but not DMOS),
below
B-E of npn as z-diode (epi-well to be connect at high voltage), = GND
no bipolar diode in forward, no npn, no pnp
Polysilicon-resistors (if available) 3-pol z-diode
HS/LS Driver as Lowside
tran-simulation with inductive load 1mH + 12 Ohm
ON
I-load
Drain Lowside:
Inductive clamping to + 55V

HS/LS Driver as Highside
tran-simulation with inductive load 1mH + 12 Ohm
ON
Source
Highside:
Inductive clamping to - 20V
I-load

Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.6 – Chargepumps & Oscillators 367
High Side Switch: What Power Device Should be Used?
N-channel P-channel
+Vbat
Drain Vgs Source

Vg
Vgs Source Drain
Vs
Load Load
N-channel needs a control P-channel needs no voltage

voltage Vgs, Vg = Vs + Vgs >Vbat for control.
Because Vs is close to Vbat, But: Ron of p-channel is approx.
(Switch on) a factor 2 worser than of a
Vg must be higher than Vbat. n-channel for same chip area.
Mostly a N-channel is used as power device
High Side Switch Needs a Charge Pump
Power DMOS is always a N-channel device.
For inserting the DMOS as switch into the

+Vbat positive supply line („high side switch“), the
drain is connected to Vbat (plus). A more
positive gate-voltage (higher than Vbat) is
therefore necessary to drive the DMOS to
Vbat
obtain a low-ohmic Rds-on.
The usual way to generate this voltage is a
capacitive voltage multiplier called „charge
pump“. In smart power circuits this charge
pump can be integrated on the same chip
with the power DMOS.

Principle Circuit of a One-Stage Charge Pump
VS VCP
VCP
C1
Oscillator C2
VCP (max) = 2 ⋅ (Vs − Vd )
turn-on time to charge C2:
Ton ≥ 2 ⋅ (C 2 / C1) ⋅ T
1
T= for faster switching time increase C1 and/or frequency
f

One-Stage Charge Pump – Start-up Simulation
Vs=5V
f = 4MHz
C1 = 10 pF
C2 = 40 pF
2 3
VS VCP
VCP
C1
Oscillator C2
1

Principle Circuit of a Two-Stage Charge Pump
VS1
VCP
VS VS2
C1 C2
Oscillator C3
clk1 out1 out2
clk2
Output of first stage (out1) could also be

used as inverted clock (clk2)
Adding more stages will increase the voltage to

Vcp(max) <= (stages -1) * (Vs –Vd)
Waveforms
for better efficiency non overlapping

clocks are prefered, but many simple
charge-pumps use only inverters to define
the inverting clock-phases
Source: Gebhardt Melcher Course TT05 Charge-Pump design

V – I Output Characteristic of a Charge Pump
C1,C2
Output voltage
20 pF
10 pF
5 pF
Vin = 5 V
f = 4 MHz
Output current
Output C = 10pf,
this causes high
ripple. In reality
the C-gate of the
DMOS will help
to decrase the
ripple.
Simulation of a 2-stage chargepump: Startup is without load, at t=10us an increasing load current
up to 100uA is added. A chargepump is a „weak“ voltage source, any output current decreases
the output voltage and inceases the high frequency ripple. Use higher C-values for more current.
Improving the Charge Pump Current Capability by Higher Frequency
fosz
Output voltage
8 MHz
4 MHz
2 MHz
Vin = 5 V
C1,C2 = 10 pF
Output current
Increasing the frequency allows more current without increasing capacitors (=chipsize!)
Also the start-up will be faster.
What Frequency Should the Charge Pump Use?
A charge pump is always a rootcause for EMC emission, so

choosing the right frequency has to be considered.
It is a trade-off between efficiency, application (slow or fast
switching) and EMC behaviour.
For a given current and output voltage fclk * C = const.
n choose low frequency for low EMC emission
n choose high frequency for low chip area, high output current
for EMC it is very critical if harmonics are seen in the FM-radio
band (87.5 – 108 MHz)
More-phase charge-pumps can have lower emission:
if they are very symmetrical (circuit and layout), some
harmonics are suppressed

Examples for Charge Pump EMC Emission
BTS 640, Profet High Side Switch TLE 7209, Motor-Bridge (Highside & Lowside)
High side switch, weak charge pump H-Bridge, strong charge pump at
(low switching speed), low frequency very high frequency (60 MHz),
(1.3 MHz) 4-phase concept.
Low emisson in the AM (0.6-1.5 MHz) No harmonics in the FM-radio
and FM (88-100 MHz) radio bands band.
source: internal EMC-reports from http://app4.muc.infineon.com/EMC-Center/

Improving the Charge Pump Output Voltage by Use of
Switched MOS-Transistors Instead of Diodes
M3 M4 with MOS-switches
Vin Vout
M1 M2
with diodes
Vcc
VC1
Osc.
Replacing the diodes with MOS-switches can help to

get more voltage.
Reverse diodes of M1 and M2 are used as diodes, by
switching on the Rds-on reduces the voltage drop.
The configuration M1 to M4 is a flip-flop which is
triggered by the signal VC1 (up or down)

Charge Pump in SMART Technology
If no bipolar diodes are available, a n-channel „MOS-diode“ can be used.
Substrate npn can be used as first diode, the other substrat npns support precharging of caps.
(substrate)
B S G D VBatt
VCP
p-well
n-epi/substrat
Osc.
Example: 2-stage VCP = 3 ⋅ (Vs − Vd )

Ring Oscillator Circuit for Charge Pump Driving
With an odd (ungerade) number of

inverters it will always oscillate .
Frequency depends on internal delay of
logic inverters – strong technology
dependend
Frequency can be choosen by size of inverters.
Use more stages or add additional C to lower the
frequency, if required.
Very simple, often used in Highside Switches

Charge Pump
3-stage with ring-oscillator
VS VCP
Simple concept which combines ring-oscillator and driver stages

Usefull for low-power chargepumps

Simple RC – Oscillator with Logic Inverters
R
Frequency is defined
by R and C and does
not depend on the
delay time of the
C
inverters.
T = 1/f = 2...3 RC
Use a low-tc resistor

(e.g. polyres.) for more
constant frequency

Frequency Dependence on Vdd, Temperature
Compare Ring-Oscillator vs Simple RC - Oscillator
frequency-deviation
%
40 % s
30 30
Ring
20 20
10 10
RC Temp [°C]
0 0
-40 -20 0 20 40 60 80 100 120 140 160 4 4,5 5 5,5 6 6,5 7
-10 -10
Vdd [V]
-20 -20
RC
-30 -30
Ring
-40 -40
-50 -50
f = funct (Temp) f = funct (Vdd)
typical simulation results for a 4 MHz Osc. in a 0.5u BCD Techn.

Circuit Example: Charge Pump with RC Oscillator
For EMC behaviour the customer asked for frequencies always

> 1.6 MHz (above AM radio-band), a RC oscillator was choosen
to have better frequency stability as the ring-oscillator.
Frequency set to typ. 4 MHz.
Source:
With
Withan
anRC
RCoscillator
oscillatoryou
youhave
havebetter
bettercontrol
controlover
overfrequency
frequency S940/chargepump
Charge Pump: Detail of Driver Stage
To avoid to much cross-

1 2 3 current in path 3 , there
is a resistor R7 included
in path 2. During
transition of path2 the
gate of M11, M12 are
not activated at the
same time.
Otherwise transient
current in the large
devices M11,M12 would
be high, this would give
more EMC problems.

Oscillators: Accuracy Considerations
Principle of an RC oscillator is always the charging/discharging of a

capacitor with a defined current
capacitor: tolerance of oxid-thickness (e.g. +/- 10 %)

has no temperature coefficient
current: defined by voltage and resistor

voltage: bandgap reference, e.g. +/- 3..5 % (without adj.)
resistor: no good absolute reference available
best: poly resistors, (e.g. +/- 20 %), low tc
worse: diffusion resistors, high tc
comparator: overshoot give additional error,
more critical for higher frequencies
-> adjustment required for frequ. spec. better +/-30%

-> choose lower frequency for better accuracy
Ring Oscillator with Improved Frequency Stability
Bias p
Bias n
Inserting biased transistors as current sources

defines the charging/discharging time -> more constant frequency
Frequency-Adjustable Ring Oscillator
Uses
Useswell
wellcontrolled
controlled(adjustable)
(adjustable)bias
biascurrents
currents
to
todefine
definethe
thefrequency
frequency cell: ringOscReg/ S1289 (SPT5)
Bias Current Adjustment for Ring-Oscillator

Voltage Regulator for Highside Charge Pump
If outut voltage is
higher than V1
(two zenerdiodes
V1
+ bip. diode) the
input voltage is
reduced by a
feedback loop
Using
Usingaavoltage
voltageregulator
regulatorfor
forcharge
chargepump
pumpsupply
supply
Source: S940/chpmp can
canhelp
helpto
toimprove
improveEMC
EMCbehaviour
behaviour
10
Chargepump for a Low Side Switch 8
VCP
5
for VCC = 5V to improve RDS(on) of Power-DMOS 2
0
2 2,5 3 3,5 4 4,5 5 5,5 6
voltage is regulated to 9V max. (SPT4, 55nm Gox) VCC
For
Foraalow
lowside
sideswitch
switchaacharge
chargepump
pumpimproves
improves
Rds-on
Rds-onatatlow
lowsupply
supplyvoltages
voltages
Source: S955/chgpmp
More Phase Chargepump (Concept Feldtkeller)
1 3 2
3
Vbat VCP 4
2 4
4-phase concept for higher output current

3 1
with lower EMC radiation
4 2
1 2 3 4
Oscillator and driver

Synchronisation of Ring-Oscillators for More-Phase Charge Pumps
4 synchronised oscillators
2 synchronised oscillators
all concepts from M.Feldtkeller, presented at SPT-Workshop 1998

High Efficient 2-Stage 4-Phase Charge Pump
C-Pump / S1071 E-Gas / SPT5

One Driverstage for 4-Phase Charge Pump
C_1xPump / S1071
RC - Oscillators
Vcc
R1
Vref2
Vref2
Vref1
R2
C1 Vref1
overshoot causes frequency

error -> high frequ. needs fast Principle (traditionell concept of „555“ oscillator)
comparator
Good concept if R,C, are outside the chip.
For „all components inside“ you can replace R1, R2 by current
sources; Vref1,Vref2 by bandgap reference circuit.
Oscillator
General purpose triangle osc. ( e.g. 64 kHz)
I2
charge
I1 Vref1/2
discharge
Required current sources: comparator

I1: temperature constant current to charge/discharge capacitor
I2: current with tc of resistor to generate temp-comp. threshold voltages Vref1,2 Source: S940 (SPT4)
RC – Oscillator with 2 Caps
Vdd
Vref
Ibias
Osc
Advantage: both comparators have same input

voltage range, more symmetry
Disadvantage: needs 2 caps (chip area)

RC – Oscillator with 2 Caps example from S1083(SPT5)

Simple Oscillator with Divider (1)
Application: clock for digital delays
Oscillator 16 kHz -> Frequency divider 8:1 -> 2 kHz
Use
Useofofdigital
digitalfrequency
frequencydivider
dividerallows
allowshigher
higherosc-
osc-
frequency->
frequency->smaller
smallercaps
caps-> ->smaller
smallerchiparea
chiparea
(trade
(tradeoff
offanalog
analogvs.vs.digital
digitalarea)
area)
Source: S939 (SPT 75)

RC-Oszillator with Schmitt-Trigger
VC
CLK
VC

RC-Oszillator with Schmitt-Trigger, Internal Circuit
No reference current and reference voltage

needed to define thresholds ->
lower accuracy but low power consumption
Well suited e.g. as a clock for digital delays. Source: S1264 (SPT5)
Zapping Circuit (SPT4)
„zapping“
during wafer test
e.g.
100 mA testpads
To achieve accuracy for voltage reference, reference currents, oscillator frequency and so on an
adjustment chip by chip is necessary. A zenerdiode can be used as „fusing“ structure. This
„zapping“ diode will be overloaded by a high current (some 100 mAmps) during wafer test and is
seen afterwards as a short. So the output ZOUT of the zapping circuit is LOW (not zapped) or
HIGH (zapped)
For SPT5 this method of zapping is not possible -> replaced by laser fuses
Tungsten plugs in the SPT5 metallisation do not allow the aluminum „spiking“ which
gives the low-ohmic connection of overloaded zener diodes. Source: .../zap

Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 3.7 – Linear Voltage Regulators 404
Linear Voltage Regulators
IOUT
VIN
VOUT
Power dissipation: PV = (VIN − VOUT ) ⋅ I L

Block Diagram of a Linear Voltage Regulator
power device
VIN VOUT
current temp.
limit sensor
internal prestab.voltage
voltage +
reference driver
-
op-amp
To improve the power-supply-rejection the internal circuits could be supplied by the regulated
output voltage itself. In that case: check startup-condition – a first startup bias-current has to be
generated from the input voltage anyway

Possible Power Devices for Linear Voltage Regulators
VIN VOUT
npn (VIN − VOUT ) ≥ VBE
VBE
pnp low drop: (VIN − VOUT ) < VBE possible

VBE
(VIN − VOUT ) ≥ Vth

> Vth n-channel for low-drop: charge pump required
VTH
p-channel larger chip size as n-ch. device

Voltage Capability of Different Power Devices
bipolar
VIN VOUT DOPL SPT4 SPT5
npn 40(60)V (40 V) 20V
pnp 60 V 50 V (40V)
DMOS
60 V 60V
n-channel
High-voltage 60 V 60V
p-channel

Characteristics of Voltage Regulators
absolute accuracy +/- 5% (without adjustment possible)

+/- 1 .. 2% requires adjustment
with zener-zapping or laser-fuses
temperature behaviour vout = f(temp)
line regulation vout = f(Vin)
load regulation vout = f(Iout)
power supply rejection (dynamic), important for EMC, ISO-pulses
start-up behaviour for Vin increasing from 0V

temp behaviour line regulation (static) load regulation (static)
power supply rejection(dynamic) load-step response startup-behaviour

Voltage Regulator with NPN
VIN for higher currents bipolar darlington required

Disadvantage: min. (Vin - Vout) > 1,5 V
Vout
npn
npnregulators
regulatorsneeds
needsenough
enoughinput
inputvoltage
voltage
Voltage Regulator with PNP
VIN Vout
usage
usageofofpnp
pnpisisthe
the
„classical“
„classical“low
lowdrop
drop
regulator
regulator
for pnp regulators min.(Vin – Vout) can be lower ( = Vce-sat)

„low-drop“ regulator
Very succesful used in DOPL (bipolar techn., very cheap compared to SPT)
Simple Prestabilization, using Z-diode as Reference
simplest solution
w/o feedback loop with very simple feedback loop
Circuit example (concept) of voltage regulator with npn as output device
e.g. for internal prestabilisation
npn: take care of

voltage capability

Voltage regulator with DMOS and Charge Pump
use
useof
of charge
chargepump
pump
enables
enableslow
lowdrop
drop
regulator
regulatorwith
withDMOS
DMOS
this concept is used in:

S912 (SPT 75)
S1041 (SPT 4)
S1289 (SPT 5)
S1222 (SPT 5)

5V Regulator for Internal Supply
DMOS as
pass element
needs Vref
from bandgap:
check startup! Source: S 1289 (SCON)
Bias Current Generation (for internal voltage reg.)
6v ..40V
VZ − VGS ( DMOS )
I=
R2
Vz
reverse current
compensation
Source: S 1289 (SCON)

Opamp for Internal Voltage Regulator
Miller opamp
with C+R compensation
Source: S 1289 (SCON)

Contents
0. Introduction

4. Parasitics
5. Literature
H.Zitta – Smart Power Analog 4 – Parasitics 419
Parasitics
Due to the kind of isolation (p-n-junctions but not oxid-isolated) there are
many possibilities to get unwanted parasitic components in case of
overvoltage spikes, substrate currents or some bad layout conditions in
combination with higher voltages.
Especially in automotive environment there are some voltage conditions
on the car battery line which need “robust” designs, to avoid a
malfunction, caused by parasitic effects.
For a junction isolation process two kinds of parasitics can occur:

• Surface Parasitics
• Bulk Parasitics

Surface Parasitics
parasitic P-channel P-channel

thickoxid-transistor transistor
metal line at
negative potential
gate-oxid
thick-oxid
P P
P
N-
All wiring metal lines of an integrated circuit can theirself act as a gate of a parasitic
MOS transistor. High voltage operation could activate this parasitic transistor.
This need special attention at layout design for high voltage circuits.

Countermeasures Against Surface Parasitics
1) Insert a channel stopper 2) Insert a field plate
P P P P
P P
N- N-
N+ Channel Stopper Field-plate at positive voltage
The higher doping concentration of the The second method is to use an electrostatic
channel stopper prevents the activation of shield with a field-plate. This can be done with
a parasitic MOS channel. the polysilicon layer below the metal layer.
It is the prefered method, because it needs not
so much space in layout compared with the
channel stopper diffusion.

Bulk Parasitics: npn-saturation
P-zones inside the epi can form the emitter of a parasitic pnp
with epi = base and p-substrat =collector.
In normal operation condition of the npn the epi (C of npn) is always higher than the p-zones
inside. But if the bipolar npn goes into saturation, collector voltage drops to a lower level than
base(npn) voltage (VC < VB). Now the parasitic pnp starts conducting.
This effect is well known as the saturation problem for the bipolar transistor, current gain
decreases because the base current now feeds the parasitic.
C B E
N-sinker
N-Epi P N+
N
P
P Ib
N+
P
P-Substrat
NPN-transistor with parasitic substrat PNP

Countermeasure Against Bipolar Saturation Parasitic
1) Layout 2) Circuit design
This parasitic effect can not be avoided For circuit design it is recommended to avoid
complete, but the gain of parasitic pnp can be saturation of bipolar components.
reduced by applying a closed n-sinker ring In analog circuits it can be e.g. done by
round the base. applying a clamp-voltage via a diode to the
collector.
N-sinker ring
C B E
P
N-Epi P N+
N P Vclamp
N+ Q1
P Vce
P-Substrat
Clamping circuit to avoid

saturation (Vce < Vbe) of Q1
Bulk Parasitics: Diffusion Resistor (SPT 4)
A diffusion resistor, e.g. rd in SPT4, could open a parasitic pnp to substrat,

if forward biased.
Take care to operate the resistor in right polarity to avoid this parasitic.
(p) (n) (n) (p)
P E
P P
N-Epi N sub
if the forward-diode operation

P cannot be avoided, then use
P-Substrat
resistor layout with closed
n-sinker ring to decrease the
substrat current

Parasitic Substrat Current:
Darlington amplification for series connected (stacked) devices
The forward biased diodes of stacked diffusion resistors, as well as forward

biased z-diodes in series connection, can lead to very high substrate currents due
to a multi PNP darlington configuration of that parasitic PNPs.
Improvement could be an additional diode which short-cuts all the series
parasitic-diodes
R3
QP3 Prevention
QP3 Prevention
DBP
R2 DBP
QP2
QP2
R1
QP1
QP1
(from: H.Rothleitner, Parasitics)

Bulk-Parasitics of DMOS (1)
G S/B
D D
N
P
P N+ P
N-Epi N
N+
S/B
P-Substrat P
Parasitic substrat pnp is
actice if DMOS-reverse-diode
is forward biased (VD < VS)
Parasitic substrat pnp
a pnp parasitic can be found (E=source/bulk, B=drain, C=substrat).
This pnp is activated when the DMOS is reverse biased (Vsource > Vdrain)
To improve the behaviour a collector sinker ring is recommended.
Large DMOS devices have general closed n-sinker ring included in layout library.
In comparison with the problems of npn saturation this parasitic does not disturb functionality.
Only the amount of current into the substrat has to be calculated (few %).
If you use a DMOS as high-voltage diode you always have to accept this substrat current, if it is
not acceptable than use a bipolar „low leakage diode“ instead.
Bulk-Parasitics of DMOS (2)
G S
C B E D
P P
P N+ P
N-Epi N+
N
P
N+
N+
P
P-Substrat
Lateral Substrat npn (Substrat Querstrom)

If an epi-well is biased with a negative voltage below substrat potential than the formation of lateral npn
transitors is evident. All epi wells in the neighborhood will acts as collector of this parastic npn.
In consequence currents into the subtrat are drawn from al epi wells which could strongly influence function of
the circuit (parameter shift or functional fail) and additional current consumption.
This is our main parasitic to fight against in lowside-switch applications with

junction isolated BCD-type processes, called the „Reverse Current Problem“!
Countermeasures are external (schottky) diodes (expensive for customer), special epi doping (expensive for
wafer-fab) and special know how in layout (guard rings) and circuit design.

Different names, but same problem:
„Reverse“- , „Inverse“-Current, „Querstrom“
I-normal I-reverse
„I-quer“
Sub
Current through the DMOS Reverse-Diode acts as base current of a

lateral npn parasitic which have more collectors: each epi well on the chip
could be a collector, although it is far away!
Parasitic current flows across the die -> „Querstrom“

Why does reverse current occure in an applikation?
• Disturbance on power supply line (defined by ISO testpulses)

e.g. Testpulse 1 (-100V / 2ms)
Testpulse 2 (+ 100V / 200 ms), Tespulse 3a, 3b (+/- 100V Bursts)
• Loss of Vbat in case of inductive loads ->

Magnetic energy will discharge via other DMOS channels
(problem of multichannel low.side switches)
• Use of the DMOS reverse-diode as freewheling diode (H-Bridge)
• Shift of GND level due to voltage losses in GND lines

up to 1V (1,5V) sometimes requested by customers

Negative Voltage Transients can cause Reverse Current
200ms 500ms
V
V 50µs
<100µ
100ns
12V
t 112V
10%
90%
VBAT
90% 10%
-100V 12V
1µs 200ms t
2ms
5s
Load
0V Test Pulse 2
Automotive Test Pulse 1
(ISO-puls)
Reverse Current
through DMOS
GND = 0 V

Loss of Vbat in Case of Inductive Loads
VBAT When opening the

switch (e.g main ignition
S1
I1 key of a car) current is
searching for another
path and will go through
L1 L2
reverse diode of other
DMOS. DMOS2 are
then in reverse current
ON OFF condition, Drain < GND.
DMOS 1 DMOS 2
Multichannel-Lowside-Switch

Motor H-Bridge
In case of motor drive the reverse current is not a fault, but a normal operation condition
during any change (reversing) of the rotation direction. The internal reverse-diodes of the
DMOS are used as freewheeling diodes and no external diodes are foreseen.
ON -> OFF OFF
Freewheeling via
OFF revers-diodes ON -> OFF

Failure Modes Caused by Reverse Current
Ø increased current consumption

Ø parameter deviation
Ø functional fail
Ø open load diag. disturbed by neighbour channel
Ø unwanted switch on/switch off – worst case: latched
Ø latch up
Ø increased logic-input pull down currents -> disturbance of µC-port
Ø disturb of current limit or temp-sens circuit – worst case: destruction

Countermeasures against reverse-current problem
q Application: external circuitry to avoid negative drain-voltage
e.g. schottky-diodes, buffering capacitors, diodes to avoid reverse polarity
It‘s clear, that external components are not preferred by customer!
q Integrated circuit:
§ Circuit Design
avoid components/circuits which are sensitive to reverse current
§ Technologie
use special epi doping e.g. SPT4-90RC (used for ATIC21 (6 inch),
this special technology was not transfered to 8 inch
-> help of technology no more avaible for reverse current problem!
use lateral DMOS isolated from epi (not available in SPT)
§ Layout Design
distance of analog circuits to DMOS (not always possible)
guard rings
Reverse Current Measures - Circuit Design
• Connect all epi wells in a way (low-ohmic), that current pulled from the
parasitic does not disturb the circuit function, only increase current
consumption.
• Do not use components have epi-well a sone node (DMOS, npn, pnp)
(not really a practicable recommendation)
• Buffering of epi-well connections (emitter-follower, buffer-amps)
• Increase bias current in case of reverse-current
• Switch on DMOS in case of reverse-current (works if Ron*I < Vdiode)
• Compensate reverse-current by dummy-components, like leakage
compensation (depend on layout)

Reverse current: Where are the epi-well connections ?
A good Smart Power Designer have to know, where are the epi-wells at any device!
• Drain of DMOS
• Collector of npn
• Base of pnp
• Well of diffused resistors (SPT4)
• Kathode of Z-Diode
• Anode of Diode
• Well of capacitor (SPT4)
• Bulk of p-channel MOS
• Epi-well of n-channel MOS
• ESD struktures with n-epi at pad

SPT5/6: Which node is connected to n-Epi-Well?
Devices with critical n-Epi-nodes are highlighted in red:
cst
clp
chh
zd5f zd5sub zd5s

zd6f ze5sub zd6s
Tree-Pole-Z-Dio
Collector Base Drain Cathode Anode Bulk Epi-W e ll

NPN PNP DMOS DRP DLL PMOS NMOS

SPT5/6: Which node is connected to n-Epi-Well?
Devices with critical n-Epi-nodes are highlighted in red:
Esd snapping Esd no snapping esd_ser
esd_anti

What Components are Insensitive to the Reverse-Current Problem?
• low voltage CMOS (digital)

• low voltage MOS analog, take care to bulk-connection
Using
Usingmore
moreanalog
analogMOS
MOSinstead
insteadofofbipolar
bipolaris
isan
anadvantage
advantagefor
forreverse
reversecurrent,
current,
but
butbe
becareful
carefulnot
notto
tounderestimate
underestimateMOS
MOSoffset!
offset!
• poly-resistors the
theavaibility
avaibilityofofpoly
polyresistors
resistorsare
arethe
thegood
goodnews
newsfor
foranalog
analogdesign
design
• SPT5: poly-poly caps, poly-metal caps
SPT4: cap with well at GND or VCC
• Z-diode 3-pol type with epi-well (C) free to connect
• SPT5: revers-current-prove npn (not yet a libray comp.)
• ESD: only some structures: be careful

How to do Lowohmic Epi-well Connections?
example: diffusion resistors
VDD VDD VDD
from
VDD
accurate res-divider, all epi-wells at VDD, epi-wells buffered:

but sensitive against res-divider will not be higher accuracy
parasitic currents so accurate and robustness

Circuit example:
Buffering of Wells of Diffusion Resistors
SPT4 – 90V
ATIC21/S0955
cell 7.56 resclamp

example: bipolar temp-sensor
VDD VDD VDD VDD
ü
ü epi=grounded
temp-sensor with npn pnp-diode as temp sensor

example: MOS comp with p-input (bulk!)
VDD VDD VDD
Vh
bulk-connection of p-MOS solution 1) solution 2)

is an epi well! connect bulk to VDD buffering of
therefore also MOS amplifier could disadvantage: bulk-epi-well
have reverse current problem body effect, more offset

P-MOS Comparator: Low Ohmic Buffering of Well-Voltage
S0969 / lvmoscomp3
Reverse Current Measures - Layout Design
• Guardring around power-DMOS (active guardring)

• Shielding of sensitive analog circuits with passive guardrings or
by use of large epi-wells (e.g. parts of logic circuits)
• All other components which are connect with the drain of power-DMOS
should be inside the guard ring
• Place sensitive analog (bipolar) circuits as far as possible away from
DMOS
• Attention: substrat contacts can be counterproductive in combination
with some guard ring concepts

Layout: Impact of Distance and Shielding by Logic Block
Example: 8-fold lowside switch S945 without reverse current measures

disturbance of bipolar bandgap reference
DMOS DMOS
ce
en
inf dium
flu Strong influence
e
nc
in
DMOS to DMOS
me
lue
low
(seen at open load detection

DMOS SPI - Logic DMOS behaviour)
VREF
DMOS DMOS
DMOS DMOS

Reverse Current Problem: Disturbance of Logic Input Current
okay
100
0
0 2 4 6 8 #9
10
-100
-200
INON [µA]
-300
-400
disturbed by reverse current Reverse current at power
-500 DMOS could sink current
-600 out of logic input ->
S0955 B1 #4
-700 problems wit µC port

S0955 B1 #9
IRev [A] could be the consequence
2.5. inputs pullup current (0<Vin<0.9Vcc) #4

IIN -100 -20 µA
Example out of
datasheet ATIC21: 2.6 ∆Iin during reverse output-current IIN 50 µA
(Ioutp = -10A on one output)

S0968: Efficiency DMOS-DMOS, Reverse current at channel 1
5,00E-03
4,50E-03
SPT4-60V 4,00E-03
Standard-process
3,50E-03
Nachbar-Kanäle
Neighbour-channels ch2
I pull down [A]
3,00E-03 ch3
ch4
2,50E-03 ch5
ch6
2,00E-03
ch7
1,50E-03 ch8
1,00E-03
other-channels
andere Kanäle
5,00E-04
0,00E+00
-1 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0
Irev Ch1[A]

Layout S968 with Reverse-current measuring points
Ch7 Ch6
Ch8 Ch5
1 2 3 4 5 7 8 9 10 11
6
Ch1 Ch4
Ch2 Ch3
Infuence ofEinfluß
S0968: ReversedesCurrent as a Function
Reverstromes of Distance (SPT4)
auf Teststrukturen
distance
Abstand [um]
1,00E-03
0 200 400 600 800 1000 1200 1400 1600 1800
1,00E-04
1,00E-05 Edge of DMOS

Iwanne [A]
1,00E-06
1,00E-07
1,00E-08
1,00E-09
measured on a „real“ chip layout of S968 (SPT4)
Reverse Current Sensitive Points in a
Standard Bandgap Reference Circuit (Brokaw Cell)
red circles indicate

substrate junctions
this points are highly

effected by reverse
current and thermal
leakage currents

Standard Bandgap Reference:
Circuit Performance and Current Consumption at High Temp.
1,28 90
Vref 80
1,275
Ivcc
70
1,27 60
Ivcc[mA]
50
Vref[V]
1,265
40
1,26 30
20
1,255
10
1,25 0
0 50 100 150 200 250 300
T[°C]
Leakage
Leakagecurrents
currentsdisturb
disturbfunctionality
functionalityover
over200°C
200°C
Robust Bandgap Reference Circuit
green circles:
all nodes
associated with
n-epi wells are
supplied from low
impedance such
as the voltage
supplies.
This
Thisreverse-current
reverse-current
robust
robustbandgap
bandgap
reference
reference- -concept
concept
isisnow
nowused
usedas asaa
standard
standard(reuse)
(reuse)inin
SPT5
SPT5projects
projects

Robust Bandgap Reference – Measuring Results
21
2,427
Vref[V] Ivcc[mA]
2,422
2,417 16
2,412
Ivcc[mA]
Vref[V]
2,407
11
2,402
2,397
6
2,392
2,387
2,382 1
0 50 100 150 200 250 300
result of testchip SPT5 T[°C]

by W. Horn
AACD 2004 Accurate
Accurateouput
ouputvoltage
voltageup
upto
to300°C
300°C !!
Using PNP‘s Under Reverse Current Conditions
B C E
For a pnp the n-epi-well is the base

and therefore the sensitive point
p+ p p+
n-well
p-substrat
Vbe
B C E
Diode connected pnp with grounded base

would cause no problems and is therefore
a usefull device for temperature-sensor
cross section and layout of a or bandgap reference circuits to withstand
junction isolated lateral pnp reverse current problems

PNP‘s Differential-stages @ Reverse Current
VCC
standard pnp-inp diff-stage: pnp comparator with emitter-input

not recommended because of can be used, if base-current is
reverse current sensitivity supplied from a low-ohmic buffer

Collector
Reverse- Collector
ofofnpns
npnsare
are
current-prove connected
connected
totoVCC
VCC
Bandgap-
Reference
to avoid MOS-
comparator offset
problems this
solution uses
pnp-emiter input
comparator
Base
Baseofofpnp
pnp
MOS offset was found
to be significant high: isisbuffered
buffered
SPT4 with 55nm GOX
gives more offset
compared to SPT5
with 15 nm Gateoxid.
from S967 (SPT4)

Measurement Results: Substrate Current Injection
Direct Current Injection into Bandgap Reference Circuit
0,03
0,028 new
0,026
standard
0,024
0,022
0,02
0,018
dVref[V]
0,016
0,014
0,012
0,01
0,008
0,006
0,004
0,002
0
0,1 1,0 10,0 100,0 1000,0
Isub[uA]
(S967-SPT4 robust bandgap reference)

Reverse Current Problem: Shielding with Guardrings
DMOS analog circuits
As a layout
measure
guardring
guardrings can try
to avoid or to
minimise the
effect of the
reverse current
parasitic
substrat

Guardring Concepts: Situation without Guardring
DMOS
CMOS Bipolar vertical “updrain"
PMOS NMOS npn-transistor power transistor
SG D S G D C B E D S G
B B
n+
p- p
p+ n+
p- p+
p+ n+ p+ n- p+ p+
n- Epi
n+ n+
Minority Carriers
(Electrons)
p Substrate
GND(0 V)
Guardring Concepts: 1) Grounded n-Guardring
GND
C BE 0V D S G
n+
Sensitive Analog
p n+
p- p+
p+ n- p+ p+ p+
Logic
DMOS
n+ n+ n+
p Substrate
n+ guard
GND(0 V)
This guard ring gives an improvement by shielding sensitive components with

grounded n-stripes around the DMOS. The effectiveness increases with the area of
the guard ring, but this costs chip area!
Existing n-wells e.g. the wells of a logic block can be used as additional shielding
without spending additional chip area.

2) Floating p-n Guardring (‚Feldtkeller‘)
C BE D S G
n+
Sensitive Analog
p n+
p- p+
p+ n- p+ p+ p+ p+
Logic
DMOS
n+
n+ n+ n+
Q2
p Substrate Q1
I2
p+
GND(0 V)
Activating of 1st parasitic Q1 will lower the local substrat potential which formes the
base for Q2. Vbe (Q2) decreases and this lowers the parasitic current I2.
This concept is more effective than the grounded n-guard ring.

3) Improved Floating p-n Guardring
GND
C BE D S G
GND
n+
Sensitive Analog
p n+
p- p+ n+
p+ n- p+ p+ p+
Logic
DMOS
n+
n+ n+ n+
Q2
p Substrate Q1
p+
p+
GND(0 V)
First parasitic Q1 is on chip edge (far from analog circuits) p-contact is grounded to
increase Q1 current. Drain of Q1 is a floating n-stripe and is connected with a p-stripe at
the other side of DMOS, where the analog parts are. This lowers there local substrat
potential and thereafter reduces parasitic Q2 current.
This is the most effective guard ring concept.
Take care that no grounded substrat-contacts at chip edge disturb this concept – check
the sealring layout, maybe you have to change it.
Inverse Current Problem in SMART Technology
n SPT/BCD: voltage below GND (=below Subtrat) -> „Reverse Current“
n SMART: voltage above Vbat (=above substrat) -> „Inverse Current“
DMOS p-channel substrat-npn

Drain = Vbat G S S D E B
p- n+p+
Normal Inverse n- Epi
Current Current
n+ Substrat
Vsource>Vbat
+ Vbatt Drain = Substrat
Source
Reverse-diode of DMOS (bulk to drain) is B-E-diode of pnp parasitics

This can disturb functionality of devices which use p-impl. (p-channel, npn)
Especially in monolithic multichannel Profets this can cause problems
Layout dependent parasitics: guard rings (SMART5)
ß Guardring • Inverse current flows through the

output DMOS of the channel A
• An adjacent pmos belonging to
Output channel B is placed closed to the
DMOS B DMOS
• Its terminals are p-doped regions
à collector of the pnp
• The guard ring (p-doped region
shorted to gnd) collects the
Output injected current and reduces the
pmos
DMOS A efficiency of the DMOS-pmos
parasitic
• Guard rings help, but they are
100uA
GND = 0V big and sometimes they can‘t be
VBB = 12V
used
3A 12V
10V Source: Luca Petruzzi: Inverse current in SMART technology

OUT = 12.7 V
12V presented at Designer Meeting Vi
Parasitics Thyristors (Latch-Up)
The activating of parasitic thyristors is the rootcause of „Latch-Up“, unwanted but well known in all
CMOS processes.
Important is the current-gain of the parasitic npn and pnp which form finally the thyristor.
For CMOS circuits it is critical, if spurious voltages higher VDD or lower GND occur. In that case the
MOS revers-diodes (drain-bulk) go into forward mode and form the base-emitter of parasitic bipolars.
Therefore output circuit connected to pads are most critical and need a special layout:
Sufficient well connections, seperate wells for n and p-channel devices.
Bad experience: Latch-up can also be triggered by reverse-current parasitic! Vcc
P-Kanal N-Kanal P
S G D D G S N
B B
P P N N
P-
N-
P
N
GND
Triggering of Latch-Up Thyristor
Latch up is triggered by a VDD (+ 5 V)

positive or negative spike which
exceeds the supply voltage
range: P1 P2
Vpad > Vdd triggers P2, VDD
Vpad < GND triggers N2,
as a consequence the thyristor Pad
GND
formed by P1+N1 stays
conductive also if the triggerpuls
is removed.
P-Kanal N-Kanal
S G D D G S N1
B B N2
P P N N
GND
P- 0V
N-
Latch up can only occur if
bulk connections are weak
(to less, to highohmic)

Latch-up: Worse Layout (S0967 A1)
Epi-well same for N and P-channel device

Bulk-contact PMOS
Bulk-contact NMOS only few contacts
Latch-up: Improved Layout (S0967 A2)
sufficient source-bulk contact stripes
H.Zitta – Smart Power Analog

separated epi-wells for n / p-channel 470
Literature
Murari et. al. (eds.) , Smart Power ICs, Technologies and Applications, Springer Verlag, 1995, ISBN: 3-540-60332-8
Stengl/Tihanyi, Leistungs-MOS-FET-Praxis, Pflaum Verlag München, ISBN: 3790506192
Th.Szepesi, Smart Power IC’s für DC-DC Converter, from Course in Lusanne
R. Plassche et. al. (eds.), Analog Circuit Design, Low-Power, Integrated Filters and Smart Power,
Kluwer Academic Publishers,1995, ISBN: 0-7923-9513-1
R. Plassche et. al. (eds.), Analog Circuit Design, Sensor Electronis, Integrated High-Voltage Electronics,
Low-Power ADC’s, ISBN: 1-4020-2786-9
BicMOS und Smart Power, GME-Fachbericht, Bad Nauheim, 1990
K. Hoffmann, System Integration, Vom Transistor zur großintegrierten Schaltung,

Verlag Oldenburg, ISBN: 3-486-27224-1
Widmann, Moder, Friedrich, Technologie hochintegrierter Schaltungen, 1996, Springer Verlag, ISBN: 3540593578
Ballan, Declerq, High Voltage Devices and Circuits in Standard CMOS Technologies,
Kluwer Academic Publisher, ISBN 079238234X
Camenzind, Designing Analog Chips free download: www.designinganalogchips.com
H.Zitta – Smart Power Analog 5 – Literature 471

Intern Infineon Courses in Design-Center Villach:
“Technical Training”
TT03 Dieter Draxelmayr Basics of Analog Circuit Design
TT05 Gebhard Melcher Charge Pump Design

TT12 Hubert Rothleitner Devices for SMART-Power: HV-BCD (Bipolar-CMOS-DMOS)
TT13 Hubert Rothleitner Devices for SMART-Power: HV_Smart (HV-CMOS)
TT26 Heinz Zitta Smart Power Analog ( This course )
TT27 Mario Motz Analysis and Specific Simulation Methods of Stability
TT16 Gebhard Melcher Matching and Crosstalk
TT11 Bernhard Schaffer Design of Linear Voltage Regulators
TT35 Kucher / Bernardon Switched Mode Power Supply
TT43 Alberto Gola Bulk Parasitic Effects in Smart Power Technologies
TT40 Dirk Hammerschmidt Automotive EMC Requirements and Measures
TT11 Bernhard Schaffer Design of Linear Voltage Regulators
TT27 Mario Motz Compensation and Offset Reduction Techniques
for more details see Intranet:
http://eu-intranet.infineon.com/Austria/de/functions/hr/weiterbildung/Qualifizierungsangebot/Technical/index.htm
H.Zitta – Smart Power Analog 5 - Literature (last page) 472

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TT 26 Smart Power Analog

3.5 Driver Circuits Lowside, Highside

3.6 Chargepumps & Oscillators

H.Zitta – Smart Power Analog 0 - Introduction 3

H.Zitta – Smart Power Analog 0 - Introduction 4

Target is always, that :

H.Zitta – Smart Power Analog 0 - Introduction 5

n A good design uses well-known characteristics of the

A good device will not be altered during testing, so it is really not

H.Zitta – Smart Power Analog 0 - Introduction 6

try to have a margin of

faktor 2 to spec limit

−6σ −3σ µ +3σ +6σ

3.5 Driver Circuits Lowside, Highside

3.6 Chargepumps & Oscillators

n Junction Isolation p-isolation

H.Zitta – Smart Power Analog 1 - Technologies 10

+Vdd device 1 device 2

It is the simplest solution and is used in any MOS process. Isolation of

H.Zitta – Smart Power Analog 1 - Technologies 11

Gnd (-) device 1 device 2

This isolation is really done with an insulator (oxid).

+ VDD p-channel n-channel

Gate G Bulk Correct

H.Zitta – Smart Power Analog 1 - Technologies 15

Introduce drain extension as a better solution:

H.Zitta – Smart Power Analog 1 - Technologies 17

The vertical DMOS is born!

Drain Drain = Substrat +

Lateral High-Voltage MOS Vertical Trench DMOS

H.Zitta – Smart Power Analog 1 - Technologies 22

P-MOS N-MOS HV-P-MOS HV-N-MOS NPN PNP trench DMOS

H.Zitta – Smart Power Analog 1 - Technologies 24

Isolation sinker buried layer

H.Zitta – Smart Power Analog 1 - Technologies 25

at GND level (-) Isolation sinker buried layer

Isolation is done with two

H.Zitta – Smart Power Analog 1 - Technologies 27

CMOS BIPOLAR Vertical Vertical BCD

Substrat-npn (X) (X)

High-Side Low-Side Half-

Self-Isolation only 1 channel

Smart Power Switches Smart Power System ICs

Vertical Smart Technology Chip on chip

H.Zitta – Smart Power Analog 1 - Technologies 31

H.Zitta – Smart Power Analog 1 - Technologies 32

H.Zitta – Smart Power Analog 1 - Technologies 33

S 946 / TLE 6220 4 x 400 mOhm / 3A / 60V

LS: Source = GND

On-chip Integration of both Highside and Lowside Power-DMOS is only possible in

Disadvantage: Rds-on is higher compared to vertical Smart-technology at same chipsize

H.Zitta – Smart Power Analog 1 - Technologies 36

H.Zitta – Smart Power Analog 1 - Technologies 37

Chip on Chip Monolithic

H.Zitta – Smart Power Analog 1 - Technologies 38

Chip on Chip solution Monolithic device

Smart control chip is glued

H.Zitta – Smart Power Analog 1 - Technologies 39

High Current Profet

H.Zitta – Smart Power Analog 1 - Technologies 40

Features: Top Chip OUT GND

• PT- IGBT Process