Assignment-I

EE370 2nd Sem. 2010-2011, IITR

Jan. 14, 2011

1. (a) In the following combinational circuit (Figure 1),

Figure 1: Combinational circuit diagram for Q-1(a)

i. Derive the Boolean expression for T1 through T4 . Evaluate the

outputs F1 and F2 as a function of four inputs.
ii. List the Truth Table with 16 binary coordinates of four input
variables. Then list the binary values for T1 through T4 and
outputs F1 and F2 in the table.
iii. Plot the Boolean output functions obtained in part(ii) on K-map
and show that the simplified Boolean expressions are equivalent
to ones obtained in part(i).
(b) Design a combinational circuit with three inputs x,y and z and three
outputs A,B and C when binary input is 0,1,2 and 3, the binary
output is two greater than input. When the binary input is 4,5,6 or
7, the binary output is two less than input.
(c) A majority circuit is a combinational circuit whose output is equal
0 0
to 1, if the input variable has more than 1 s than 0 s. The output is
0 otherwise.
i. Design a three input majority circuit by finding the circuits Truth
Table, Boolean equation and a logic diagram.
ii. How many 2-input-NAND Gates are needed.
2. An ABCD-to-seven segment decoder is a combinational circuit that con-
verts a decimal digit in BCD to an appropriate code for the selection

1
 of segments in an indicator used to display the decimal digit in a fa-
miliar form. The seven outputs of the decoder (a,b,c,d,e,f,g) select the
corresponding segments in the display as shown in the Figure 2(a). The
numeric display chosen to represent the decimal digit is shown in Figure
2(b). Using a Truth Table and K-maps, design the BCD-to-seven segment
decoder using minimum number of gates. The six invalid combinations
should result in a blank display.

Figure 2: The seven output segments of decoder w.r.t. each of the 10 decimal
numbers 0-9 in Q-2

3. (a) Design a four bit combinational circuit 2’s complementer (the output
generates the 2’s complement of the input binary number). Show
that it can be constructed with Ex-OR gates. What will the output
functions for the five bit 2’s complementer.
(b) Using four half adders,
i. Design a four bit combinational circuit incrementer (a circuit
that adds 1 to a four bit binary number).
ii. Design a four bit combinational circuit decrementer (a circuit
that subtracts 1 from a four bit binary number).
(c) i. Derive the two level Boolean expression for the output carry C4 ,
shown in Figure 3 of lookahead carry generator (CLG).
ii. Find the total propagation delay for CLG in Figure 3 if Ex-OR
gate has 10ns delay and AND/OR gate has 5ns delay.
4. (a) Define the carry propagate and carry generate as,
Pi = Ai + Bi
Gi = Ai .Bi respectively.
Show that the output carry and output sum of the full adder be-
comes,
Ci+1 = (Ci0 .G0i + Pi )0
Si = (Pi .G0i ) ⊕ Ci .
The logic diagram of the first stage of four bit parallel adder as im-
plemented in IC type 74283 is shown in Figure 4. Identify the Pi0 and
G0i terminals and show that circuit implemented as full adder.
(b) Show that output carry in full adder circuit can be expressed in
AND-OR-INVERT form as Ci+1 = Gi + Pi .Ci ≡ (G0i .Pi + G0i .Ci0 ).

2
 Figure 3: The block diagram of Lookahead Carry Generator in Q-3(c).

Figure 4: The logic diagram of IC 74283 in Q-4(a).

5. (a) Design a combinational circuit that generates the 9s complement and

10s complement of a BCD digit.
(b) Constructs a BCD Adder-Subtracter circuit by showing only block
diagrams.
(c) A binary multiplier multiplies two unsigned four bit numbers. Using
AND gates and binary adders design the circuit.
(d) Draw the logic diagram of two-to-four line decoder using (I) NAND
gates only, (II) NOR gates only. Include an ENABLE input. Suggest
the circuit change in part (I) that produces an high outputs.
6. (a) Construct a 5-to-32-line decoder with four 3-to-8-line decoder with
enable and 2-to-4-line decoder using block diagram of components.
(b) Using decoder and external gates, design the combinational circuit
defined by following three Boolean functions:
F1 = (y 0 + x)z; F2 = (y 0 z 0 + xy 0 + yz 0 ) ; F3 = (x0 + y)z
(c) Implement the following Boolean functions with a multiplexer
P
i. F (A, B, C, D) = (0, 2, , 5, 7, 11, 14)
Q
ii. F (A, B, C, D) = (3, 8, 12, 15)