Medalist i3070 In-circuit Test System

Boundary-Scan Testing

5
Testing Advanced I/O Devices
Overview of IEEE Standard 1149.6 5-2
Test Development 5-4
Testing and Debugging 5-6
Test Diagnostics and Repair 5-8

This chapter describes the IEEE Standard 1149.6- 2003 for Boundary Scan
Testing of Advanced Digital Networks1.

1. The information in this chapter is derived and/or reprinted from IEEE std. 1149.6-2003, IEEE
Standard for Boundary Scan Testing of Advanced Digital Networks. Copyright 2003 by the
Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or
liability resulting from the placement and use in this publication. Information is reprinted with the
permission of the IEEE.

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5 Testing Advanced I/O Devices

Overview of IEEE Standard 1149.6

IEEE Standard 1149.6

IEEE Std 1149.6 defines extensions to IEEE Std 1149.1 to standardize the
Boundary- Scan structures and methods required to ensure simple, robust,
and minimally intrusive Boundary- Scan testing of advanced digital
networks. Such networks are not adequately addressed by existing
standards, especially for those networks that are AC- coupled, differential,
or both. Testing enabled by this standard will operate in parallel with
IEEE Std 1149.1 testing of conventional digital networks and in
conjunction with IEEE Std 1149.4 testing of conventional analog networks.
This standard also specifies software and Boundary- Scan Description
Language (BSDL) extensions to IEEE Std 1149.1, which are required to
support new I/O test structures.
Figure 5- 1 shows an example of a basic IEEE Std 1149.6- compliant device
with basic differential AC signal path with load termination and receiver
common- mode generation using a bias network.

Figure 5-1 Example IEEE Std 1149.6-compliant device

C U RL VBias C U

TX RX

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 Testing Advanced I/O Devices 5

IEEE Standard 1149.6 Advanced I/O Device Test

On the Medalist i3070, IEEE Std 1149.6 Boundary Scan interconnect
testing can consist of combinations of device types, as shown in the
following figures.

Figure 5-2 1149.6-compliant devices with AC coupling

Figure 5-3 1149.6- and 1149.1-compliant devices with DC coupling

Boundary-Scan Testing 5-3

5 Testing Advanced I/O Devices

Test Development
Medalist i3070 software release 07.10 and above supports IEEE Std 1149.6
interconnect testing. The IEEE Std 1149.6 interconnect tests will
automatically be generated if the boundary scan chain consists of
1149.6- compliant devices.
Boundary scan test generation is described in Generating Tests for
Boundary- Scan Chains on page 4- 41. For IEEE Std 1149.6 test
development, minimal changes are required:
• enable Keywords
• BSDL Extensions to IEEE Std 1149.1

enable Keywords
The enable statements define the type of boundary- scan interconnect tests
the Medalist i3070 software will generate. They include two new enable
keywords.

1149.1 interconnect tests (e.g. digital/u5_u6, DC only)

• enable advanced boundary scan
With the existing enable advanced boundary scan statement in the
board configuration file, there is no change in the generated
interconnect tests from previous releases of the software.
• enable advanced boundary scan differential
The new differential keyword will work with an existing advanced
boundary scan license to enable testing of differential DC on a 1149.1
device.
When tests are generated with the enable advanced boundary scan
differential statement, the negative legs are included and reported on
DC- coupled differential structures.

1149.6 interconnect tests (e.g. digital/u5_u6_aio, AC and DC)

• enable 1149.6 boundary scan
The 1149.6 interconnect test is an addition to the existing 1149.1
boundary scan interconnect test (for information, see Interconnect Tests
on page 1- 25).
This new test for AC and DC structures requires a 1149.6 boundary
scan license and the addition of the new enable 1149.6 boundary
scan statement in the board configuration file.

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 Testing Advanced I/O Devices 5

BSDL Extensions to IEEE Std 1149.1

It is imperative to have accurate and compliant BSDL for the 1149.6 tests
to be generated correctly.
There are two new instructions, EXTEST_PULSE and EXTEST_TRAIN, and
new boundary register cells also need to be identified.
For details, refer to IEEE Standard 1149.6- 2003.

Example 5-1 Example BSDL taken from National part SCAN90004

use STD_1149_1_2001.all;
use STD_1149_6_2003.all;

attribute COMPONENT_CONFORMANCE of Scan90004 : entity is

"STD_1149_1_2001";

attribute PIN_MAP of Scan90004 : entity is PHYSICAL_PIN_MAP;

.
.
.
attribute INSTRUCTION_OPCODE of Scan90004 : entity is
"EXTEST (000000010010),"& --012
"EXTEST_PULSE (000000010110),"& --016
"EXTEST_TRAIN (000000011110),"& --01E
"BYPASS (111111111111),"& --FFF
"IDCODE (000000000001),"& --001
"PRELOAD (000000010000),"& --010
"SAMPLE (000000010000),"& --010
"HIGHZ (000000100000),"& --020
"CLAMP (000001100000)"& --060
.
.
.
attribute REGISTER_ACCESS of Scan90004 : entity is
"BOUNDARY (EXTEST, EXTEST_TRAIN, EXTEST_PULSE, SAMPLE,
PRELOAD)," &
"DEVICE_ID (IDCODE)," &
"BYPASS (CLAMP, HIGHZ, BYPASS)" ;
.
.
.
attribute AIO_COMPONENT_CONFORMANCE of Scan90004 : entity is
"STD_1149_6_2003";

attribute AIO_Pin_Behavior of Scan90004 : entity is

"IN3p, IN2p, IN1p, IN0p : LP_time=10.0e-9 HP_time=1.0e-6;"&
"OUT0p : AC_Select=12;"&
"OUT1p : AC_Select=11;"&
"OUT2p : AC_Select=10;"&
"OUT3p : AC_Select=9";

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5 Testing Advanced I/O Devices

Testing and Debugging

IEEE Std 1149.6 testing on the Medalist i3070 is the same as the testing
for IEEE Std 1149.1 devices.
Debugging 1149.6 tests is also similar. Debugging Boundary- Scan Tests on
page 4- 97 describes the debug process and Boundary- Scan Debug on
page 8- 8 provides more details on the debug software.
During debugging, if a hysteretic memory match is encountered, the results
will be highlighted in the Boundary- Scan Debug window (Figure 5- 4).

What is Hysteretic Memory Match?

• During execution of 1149.6 tests, 1149.6 chips have memory that is
pre- loaded with a unique signature called a hysteretic signature.
• If there is no open on the net, this memory will be overwritten by edge
transitions.
• If there is an open on the net, the memory will never be overwritten.
The receiver memory will still contain the hysteretic signature,
indicating a highly probable open. This condition is indicated by
magenta text in the Boundary- Scan Debug window (Figure 5- 4).

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 Testing Advanced I/O Devices 5

Figure 5-4 Boundary-Scan Debug

Boundary-Scan Testing 5-7

5 Testing Advanced I/O Devices

Test Diagnostics and Repair

The Medalist i3070 1149.6 Boundary- Scan test will detect defects that are
both differential and AC coupled. However, many potential defects may
result in ambiguous diagnoses. For example, a short across differential
legs, or a stuck at ground, can lead to some diagnoses that essentially say
“check everything” in the differential pathway.
Consider the classic AC differential channel in Figure 5- 5.

Figure 5-5 Debugging 1149.6 tests

The failure tickets may not lead to the exact defect location. To pinpoint
the exact location, technicians are used to checking more and different
places, just to be sure, based on experience.
To complicate matters, many boards will have BGA chips where pins
cannot be readily viewed. In the days of DC connectivity, the technician
basically has to flip a coin to decide which IC may need to be reworked
during repair. This leads to many good ICs being repaired, which is
expensive.
Now there is a better alternative. In the example in Figure 5- 5, note there
is access to only six points: the GND and VCC nodes, and the two
terminals of the two capacitors that are surface- mounted. If the Medalist
i3070 failure ticket points to this defect, troubleshoot as explained below,
using visual inspection and a ohm- meter.
Table 5- 1 lists defects and what can be determined with simple inspection
or impedance measurements based on those six access points. Note that
the impedance measures of import are:
• zero ohms (short)
• open (infinite) ohms
• neither (for example, 50 ohms)

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As shown in Table 5- 1, defects will cause short or open measurements
while other non- zero/open readings indicate passing cases.
Table 5-1 Defects table
Potential Defect
No defect
No defect
No defect
No defect
No defect
Open on capacitors
Short, NodeA-NodeB
Short, NodeC-NodeD
Open, U4.12 or U4.13
Open, U7.17 or U7.18
Short, GND-NodeA
Short, VCC-NodeA
Short, GND-NodeB
Short, VCC-NodeB
Short, GND-NodeC
Short, VCC-NodeC
Short, GND-NodeD
Short, VCC-NodeD
Short, NodeA-NodeC
Short, NodeB-NodeD
Short, NodeA-NodeD
Short, NodeB-NodeC
NOTE
Boundary-Scan Testing
Testing Advanced I/O Devices 5
Measurement Verification Repair Action
> 0 ohms, C1.1 to C2.1 None
> 0 ohms, C1.2 to C2.2 None
> 0 ohms, GND to C1.1, C1.2, C2.1 and C2.2 None
> 0 ohms, VCC to C1.1, C1.2, C2.1 and C2.2 None
> 0 ohms, C1.1 to C1.2, C2.1 to C2.2, None
C1.1 to C2.2, C2.1 to C1.2
Visual inspection Touch up capacitors
0 ohms, C1.1 to C2.1 Fix U4 connection
0 ohms, C1.2 to C2.2 Fix U7 connection
Open, C1.1 to C2.1 Fix U4 connection
Open, C1.2 to C2.2 Fix U7 connection
0 ohms, GND to C1.1 Fix U4 connection
0 ohms, VCC to C1.1 Fix U4 connection
0 ohms, GND to C2.1 Fix U4 connection
0 ohms, VCC to C2.1 Fix U4 connection
0 ohms, GND to C1.2 Fix U7 connection
0 ohms, VCC to C1.2 Fix U7 connection
0 ohms, GND to C2.2 Fix U7 connection
0 ohms, VCC to C2.2 Fix U7 connection
0 ohms, C1.1 to C1.2 Replace shorted cap
0 ohms, C2.1 to C2.2 Replace shorted cap
0 ohms, C1.1 to C2.2 Touch up capacitors
0 ohms, C2.1 to C1.2 Touch up capacitors
If measuring ohms from either VCC or Ground shows an unstable and
increasing ohms reading, then there may be a short to the opposite
(GND or VCC) node charging the GND/VCC bypassing and no short on
the contacted node (VCC or GND).
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5 Testing Advanced I/O Devices

Table 5- 2 shows a step- by- step repair process that isolates defects to the
correct IC or capacitor. This process is enabled by the AC coupling and
represents a new breakthrough in diagnostic clarity.

Table 5-2 Step-by-step repair process

Step Test Action

1 Inspect C1 and C2 terminals;
a Missing capacitor Add new capacitor
b Tombstone capacitor Remove, add new capacitor
c Lack of solder Touch up solder
2 Measure ohms across C1, C2
a Observe ~0 ohms Remove, add new capacitor
3 Measure ohms from GND to:
a C1.1, ~0 ohms U4.12 shorted to GND, fix U4
b C1.2, ~0 ohms U7.17 shorted to GND, fix U7
c C2.1, ~0 ohms U4.13 shorted to GND, fix U4
d C2.2, ~0 ohms U7.18 shorted to GND, fix U7
4 Measure ohms from VCC to:
a C1.1, ~0 ohms U4.12 shorted to VCC, fix U4
b C1.2, ~0 ohms U7.17 shorted to VCC, fix U7
c C2.1, ~0 ohms U4.13 shorted to VCC, fix U4
d C2.2, ~0 ohms U7.18 shorted to VCC, fix U7
5 Measure ohms from C1.1 to C2.1
a ~0 ohms U4.12 shorted to U4.13, fix U4
b Open U4.12 or U4.13 open, fix U4
6 Measure ohms from C1.2 to C2.2
a ~0 ohms U7.17 shorted to U7.18, fix U7
b Open U4.17 or U4.18 open, fix U7
7 Measure ohms from C1.1 to C2.2
a ~0 ohms Touch up solder
8 Measure ohms from C2.1 to C1.2
a ~0 ohms Touch up solder

5-10 Boundary-Scan Testing