Mapua University

School of EECE
3rd Quarter SY 2019-2020

ADVANCED LOGIC CIRCUITS AND SWITCHING THEORY

LABORATORY

COE118L/E02

1024x8 RAM

By

Bertoldo, Sherine
Mendoza, Bernard Benedict
Santosildes, John Isaac
Villasencio, Julienne Marie

Sir Meo Vincent Caya

Professor
 Acknowledgement

We would like to express our gratitude to our friends and families for
their guidance and support for us on our journey as a student.

We also thank our dear professors, especially Sir Meo Vincent Caya, for
imparting to us their knowledge about the course and guiding us all
throughout given the circumstances nowadays.
SCHEMATIC DIAGRAM

Figure 1: SR Latch

Figure 2: Binary Cell

Figure 3: 4X8 RAM

Figure 4: 32X8 RAM

Figure 5: 256x8 RAM

Figure 6: 1024x8 RAM

 SIMULATION

The RAM simulation contains the following:

 8 bits of input and output
 Read/Write port
 Enable port
 10 bits of Address lines

Here are the inputs used to run the simulation (Using Isim Simulator)
 Discussion

RAM is one of the most important component on digital devices and personal
computers. Without RAM, devices will not be able to multitask, and it will have a
slow performance. A slow performance decreases productivity.

RAM is a volatile memory. It means that it is capable of storing information

when it is powered. The data stored in RAM is only temporary. The reason why
computers or cellphones run a bit slower after restarting is because the RAM is in a
reset mode and all the data stored are cleared. The larger the capacity of RAM, the
more data will be stored which allows multiple tasks to be performed fastly.

The RAM designed in this project is implemented on the 14.7 version of Xilinx
ISE Design Suite which is a very handy tool for logic designs. It allows you to see
the output of the design accurately.

The RAM we designed is a 1024x8 RAM. The RAM has 2 k words and n bits per
word. In our case, our RAM has 210 words and 8 bits per word. A RAM has k address
lines. Therefore, our RAM has 10 address lines which is shown in the schematic. As
for the input and output, we have 8 bits of input and output because each word
length is 8 bits. To select which address is accessed, a RAM is paired with a
decoder.

In designing a RAM, an SR Latch is first constructed. The SR Latch is then

converted to a block then the 1 bit of a cell is constructed. A large memory ram is
constructed by cascading other RAM blocks. We started at 4x8 RAM, then created a
32x8 RAM by combining 8 blocks of 4x8 RAM. Afterwards, a 256x8 RAM is created
by combining 8 blocks of 32x8 RAM. Finally, 4 blocks of 256x8 RAM will create the
required RAM in this project which is 1024x8 RAM.
 Conclusion

By implementing all we have learned from the lecture and laboratory of

Advaced Logic Circuits and Switching Theory, we are able to construct a 1024x8
RAM. RAM is a volatile memory of the computer which temporarily stores data. To
design a RAM, the starting point is an SR Latch. Then, a binary cell, which
represents a bit of data, was created. The RAM memories were combined to form
large storage of RAM. A RAM consists of input and output, address lines, enable and
a read/write operation. The read/write operation functions depends on the input of
the user. If logic ‘0’ is the input of the user, it will signify a read operation, else if
logic ‘1’ is the input, a write operation is performed. The enable port of the RAM
activates the whole circuit, allowing the circuit to be functionable.