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A Remote Synthesised VFO for the HW9 by Stewart Rolfe / GWØETF

This project provided an opportunity to put to good use a long held interest in Programmable Interface
Controllers (PICs) and an urge to play with the new Direct Digital Synthesiser chips which had just started
appearing in the amateur radio press in such articles as G3XJP’s excellent Pic’n Mix in RadCom1. The
following describes an exercise in self education first and foremost, but one which has been applied in
practice to cure some basic problems in an otherwise fine QRP transceiver. Though aimed at one specific
radio it is hoped that the description will be of more general interest and could be easily adapted to other
situations. Most of the technical content is a compilation of previously published ideas and articles with a
small amount of original material mainly connected with the need to adapt to the specific case of the HW9.
All material used is fully acknowledged, and reference to the original sources will provide a fuller description
of what is included here.

The project involves the replacement of the analogue VFO in this classic Heathkit QRP transceiver with
an external unit utilizing modern digital techniques. The end result is highly stable and accurate signal
generation, along with features such as band edge selection and variable tuning rate only available through
microprocessor control. The use of the remote VFO does however affect the radio’s innate portability and so
the design philosophy from the outset included the ability to return the HW9 to it’s original state by a
minimum of work with a small soldering iron and a screwdriver, which should be easily accomplished in 30
to 45 minutes.

Fig 1 is a block diagram of the signal generation in the HW9; it is a single conversion superhet with an
IF of 8.813 MHz. As can be seen the VFO operates at 5.7493 to 5.9993 MHz on all bands and feeds a mixer
chain involving band-switched crystal oscillators (the HFO) to produce the required injection frequency on
each of 9 amateur bands. The unit described simply takes the place of the original VFO, the remaining band
switching circuitry being retained to avoid the need for wide frequency coverage and in keeping with the
design criterion already mentioned. This does however mean that the accuracy of the remote VFO is limited
by the slight variations from the nominal values in the frequencies of the band-switched crystal oscillators and
‘software trimming’, described later, is used to compensate for this.

28.83 MHz
20 m 5.7493 MHz
5.9993 MHz

MIXER 2 14.00 –14.25 MHz

8.8307 MHz

Detector AF

Fig 1.Transmit signal flow in the HW9. Band switch set for 20m and receive path differences in dashed lines.

The remote VFO consists of 2 distinct sections, namely the Phase Locked Loop which
generates the signal itself, and a software controlled Direct Digital Synthesis board that ‘tunes’ and
otherwise controls the PLL to a high degree of accuracy. It is possible, and indeed was tried initially, to
use the output of the DDS directly as the signal source for the VFO. However, DDS outputs are by their
nature sampled waveforms and so contain well-defined spurii as described elsewhere3. This is a major
drawback to DDS techniques and can severely degrade the performance of an HF VFO such as this;
however the use of a PLL ‘clean up’ loop can overcome this problem and has been adopted here.

The Phase Locked Loop

Figure 2 describes the remote VFO in block diagram form, and Figure 3 is the circuit diagram
of the PLL board. It is a standard Phase Locked Loop using the DDS as the controlling signal source.
The VCO (TR2) feeds the NE602 loop mixer (IC1) as well as providing the actual VFO output; a 10
MHz crystal oscillator (TR2J) feeds the other mixer port and the filtered difference frequency is fed to
one input of the 4046 phase frequency detector (IC2). The output of the 4046 is dependant upon the
phase/frequency relationship between this input and that of the DDS feeding the other input and when
both are identical the signal fed to the VCO via the loop filter (IC3) will be a constant DC voltage
(ideally!) – the loop is then said to be ‘in lock’. This DC voltage applied to the varicap tuning diode of
the VCO will control it’s frequency; varying the DDS frequency will change the value of this voltage
and will in turn change the VCO frequency in sympathy so keeping the VCO locked to the DDS.


VCO Loop Phase
5.8493 MHz Detector 4.0007 MHz
To Mixer To
5.9993 MHz 4.1507 MHz

VFO Oscillator
Output 10 MHz

Fig 2.Block diagram of the remote VFO. The DDS is the box in heavy line on the right and the rest is the
Phase Locked Loop circuitry.

The PLL board is based on the discontinued PLL10 kit from Hands Electronics which is
in turn based on a design for an amateur band synthesizer by G3ROO and GM4ZNX appearing
originally in the December 1993 issue of RadCom; it is also featured in recent editions of the
ARRL Handbook with some minor modifications. (Unfortunately Hands Electronics has closed for
good and so the PLL will have to be built from scratch; the above references and the parts list in
Appendix 1 will hopefully be of use to anyone wishing to construct this unit). Intended originally as
a 10 band VFO together with a separate board to house the crystal oscillators means that 9 of the 10
VCO positions are unused; one of these can therefore be populated with the crystal oscillator (TR2J
etc), the crystal occupying the intended coil position. Part of the board housing the redundant VCO
positions was then cut away to ease fitting into the box and this necessitated the fitting of a couple
of wire links to replace broken tracks. L3 is wound on a surplus Toko KANK3335R transformer –
the existing windings are replaced by 20 turns (5 per bay) and connected between pins 1 and 3.
When resonated by two BB204 diodes in parallel (D5), the VCO can be adjusted to cover the range

5.85 – 6.0 MHz with the aid of the core of L3; the resulting tuning sensitivity of about 30KHz per
volt gives an approximate range of 150KHz for a tuning voltage swing of 5.25 – 9 which is
convenient for CW coverage on all the bands covered by the HW9.



IC1 - NE602 D5 – 2 x BB204 in parallel X1 – 10MHz
IC2 – 74HCT4046 TR1 – BC183L L3 - See Text
IC3 – TL072 TR2,2J – J310 RLY – Miniature DPDT
IC4,5 – 78L05 T1 – 6 T bifilar on FT43-61 core
T2 - 8 T bifilar on FT37-43 core

Fig. 3 The Phase Locked Loop board. It is based on the now discontinued Hands PLL10 kit with
the addition of an output stage (2N3866 etc) and a lock indicator (IC6). A full component
listing is included as Appendix 1.

Phase Locked Loop theory is a subject in it’s own right2 and any design involving a PLL
requires care if problems are to be avoided. Using a kit such as here is a good start but if one
intends to stray from the original design values of frequency coverage, tuning rate and component
selection, it is essential to redesign the loop filter to prevent instability occurring in the PLL. The
crucial role of the loop filter in a PLL is described in the ARRL Handbook and the recalculation of
filter component values is also fully described in an excellent article by WA6NUT published in
QEX4 in which he describes a very similar project to this and which includes some excellent
background information on PLL theory. Rick refers to a small DOS computer program written by
KD9JQ that will ease the calculation of loop filter component values and which is available for
download over the internet5. Using this tool a VCO tuning sensitivity of 30 KHz/V, loop bandwidth
of 5 KHz and a nominal reference frequency (the DDS) of 4.25 MHz results in value changes to the
following loop filter components:

R10 – 2K2 (470K), R12 – 940R (820R), R13 – 8K2 (10K), C36 – 1nF (10nF)
(Original kit values in brackets)

All other PLL board components are unchanged with the exception of D5 and L3 as already
described. The output from the board at C30 feeds an output stage (a J310/2N3866) which supplies
7V P-P to the 1st mixer of the HW9 via a 50 ohm miniature coax patch lead between the VFO and
the radio. Also added on to the basic PLL kit is a lock indicator, IC6 which provides a necessary
visual indication of PLL lock. The three resistors placed between 12V and ground supply a voltage
‘window’ of about 3.3 - 10.2 volts as the reference levels to the dual comparator IC6. If the PLL
should ever fall out of lock the tuning voltage supplied to the VCO will collapse to either rail
voltage, normally 12V; the operating frequency will then no longer be under normal control and it
is clearly imperative to have some sort of warning if this happens. The tuning voltage is also fed to
the comparator input and in this case causes the comparator outputs to flip high and activate the
relay thereby switching the bicolour LED to the Red direction. When the tuning voltage input to the
comparator is within the window, indicating locked condition, the output is low and the
unenergised relay then switches the LED to Green. Conveniently the PLL will take a couple of
seconds to find lock at switch on resulting in the LED being momentarily red initially and assuring
us that the system is working.

The DDS Unit

The Direct Digital Synthesiser is at the heart of the VFO. The functional unit is a
miniature surface mount chip, the Analog Devices AD98513 which digitally synthesizes a sine
wave from information stored in on chip ROM; frequency is determined by the value of a digital
number input from a microprocessor and with suitable clocking speeds can be any value from DC
to 90 MHz. No heterodyning is required to produce these high frequencies hence the use of the term
‘Direct’. The DDS controls the tuning and imparts upon the free running analogue VCO all the
advantages of digital synthesis such as extreme stability and accuracy, band edge selection, variable
tuning rates and general flexibility of frequency selection. Many excellent articles have appeared
recently about DDS so please refer to these for a fuller explanation as only a brief outline will be
presented here. Particularly recommended is the Pic ‘n Mix series by G3XJP which appeared in
RadCom from January to June 1999.

Anyone reading the above article will notice that the project uses the DDS alone to
produce the VFO signal and dispenses with the PLL; this approach is found in many similar designs
published in magazines and on the web. So why bother with the complication of the PLL? The
reason, touched on in the article by G3XJP, is the fact that DDS also produces certain well defined
unwanted signals or spurii which depending on the application can significantly degrade
performance. Digital Synthesis is a sampling technique whose theory dictates that certain non
harmonically related spurious signals are unavoidable and are in fact entirely predictable as to level
and frequency. Elliptical low pass filtering is always used in DDS but can’t be completely effective;
DDS alone was tried first in this project but the level of spurs, probably exacerbated by the mixing
techniques in the HW9 was unacceptable. The use of the PLL removes the bulk of the spurii to a
level at least as good as with the native analogue VFO.

Fig 4 shows the circuit of the AD9851 DDS chip with it’s associated output filter and
Fig 5 is that of the PIC which controls the operation of the DDS; the 555 timer is the keying break
in timer and is mounted separately on a small piece of veroboard. The AD9851 is a tiny 28 pin
surface mount device whose manipulation and soldering can provide a considerable challenge to the
average amateur. I was tempted by the availability of a high quality professional DDS development
board designed by G4JNT6 and marketed by HF Instruments who can be contacted on their web site

20 MHz
20 MHz

Fig 4 The DDS unit which is based on the G4JNT development board. The elliptical output filter has a 3dB
cut-off frequency of 6MHz and 200 ohm output impedance. The x6 multiplier in the AD9851 is turned
on (via the software) giving an actual clock frequency of 120 MHz.

(Alps EC16B)

Fig 5 The Controlling Circuitry based around a Microchip 16F628 PIC. The 555 Timer is associated with
TX/RX change-over timing. The LCD is based on the Hitachi HD44780U chip and here is a 2 line
by 16 character type, the LM052L.

This can be supplied with the chip already soldered in position leaving the user the responsibility of
populating the rest of the board including the PIC. Fig 6 shows the board – the DDS chip is seen
toward the bottom left with the pads for the 18 pin DIL PIC above and connections for the 8 PIC
I/O ports top right. It is a multilayer board for surface mount components but the low population
density presents little difficulty in soldering these in position. The board is small (45 x 55mm) and
was seated on top of a larger piece of doubled sided copper clad board using short lengths of wire
passing through the ground plane holes and corresponding holes in the copper board before being
soldered to it’s underside. Before fixing, the copper clad board was etched to enable peripheral
components to be mounted conveniently and then interconnected with the DDS board by short
lengths of wire. The clock oscillator module was mounted thus as well as
the output amplifier (originally this was fed directly from the DDS as
mentioned earlier).

Control of the whole unit is effected through the PIC by virtue

of software embedded (aka ‘burned’) into flash memory on the chip. This
code has to be written ofcourse and for a reasonably complex project such
as this can be a significant undertaking. Thankfully there was no need to
write the software from scratch as there are several programs already
available for similar tasks to this. The most suitable discovered for this
Fig 6 The G4JNT board particular purpose was a package written by Steven Jones
(stevejones@picknowl.com.au)for a DDS kit produced in Australia by
Minikits (http://www.minikits.com.au/) and which has been made available free for use by radio
amateurs; this software, called DD_SYNTH.v1.40, appears to have been influenced by the efforts
of some US hams and VK5EME of Minikits and who are suitably acknowledged in Steven’s listing
and reproduced in mine. It is designed to be general purpose software easily adaptable to a variety
of VFO applications from VHF to HF, with or without repeater offsets etc and much of my
programming effort was spent in removing unwanted code which reduced its size considerably.
Some extra sections of code then had to be written and incorporated into the main body; most of
this revolved around the requirement of displaying the correct frequency on the LCD dependant on
the position of the band switch of the HW9. Because the DDS frequency range is the same
whatever the band, a means had to be found to apply a display offset according to band selection so
that the correct frequency is displayed; this also provided an opportunity to adjust the VFO
operating frequency on each band to account for different relative band edges, for example to move
to 18.068MHz instead of a default of 18.000MHz. All this necessitated an interface linked to the
band switch in addition to the software – the interface is described in Fig 7 and is based on a
MC14532 8-bit priority encoder. The 8 inputs are connected to the band switch, and the 9V which
appears on the relevant band switch position in order to activate the associated HFO and filters is
also applied to one of the 8 inputs to the encoder. This then appears as a 3 bit binary coded number
at the output which is fed to the PIC where the software will translate this information into band
data and thus calculate the correct offset to display on the LCD.

Fig 7. The Band Display Interface. The resistor network converts a 9V on the band switch to 5 V at the input to the
encoder which then translate this active high input to a 3 bit binary address at the output. It is mounted on a
piece of veroboard which sits on top of the BFO screening enclosure inside the top cover of the HW9.

The code is written in Microchips’ own assembly language using their free and excellent
MPLAB Windows programming interface (downloadable from their website7 – but be warned, it is
about 26Mb in size..!). This will ultimately produce a binary file ready for burning into the PIC and
for that some hardware (and associated software) is needed to transfer the file from the computer to
PIC. This is in fact surprisingly simple and can be home brewed easily; I use a system developed by
David Tait for the 16F84 but it works fine with the 16F628 too. It is called TOPIC and originally
the software was DOS only (TOPIC03) though there is now a Windows version (FPP09). David
Tait no longer maintains a web site for these files but conveniently they are available from the
Minikits site in the kits8 section as they also supply a kit based on TOPIC.

One problem encountered while adapting the Minikit software to the G4JNT
development board was that the PIC ports used for communicating with the DDS chip were
different. Rather than undergoing the onerous task of rewriting the code to adjust for this, it was
considered far easier to rewire the PIC socket to effectively divert the three data pins of the DDS to
the ‘correct’ PIC ports as allocated in the Minikits software and details of this are given in
Appendix 2.

Linking VFO and HW9

In it’s present form 2 interconnecting cables are required, the signal injection and
data/control lines which also include the 12 volt supply to power the VFO from the radio. Because
of the wish to avoid permanent changes to the original radio a duplicate rear panel was constructed
from double sided copper clad board and drilled using the original as a template. Two additional
holes were then drilled, one for a BNC socket (RF) and one for a DIN socket (7-way for the data).
The data socket at the VFO is a 9 pin ‘D’ type socket and surplus CAT5 twisted pair computer
networking cable is used for making up a suitable lead. 50 ohm miniature coax is used for the signal
injection cable and BNC sockets/plugs are used at each end. The LO signal is injected at C196 in
the HW9 immediately prior to the filter stage, the ‘upstream’ connection of the capacitor having
been lifted from the circuit board and the VFO of the HW9 disabled by removing R129 (47R) and
R138 (100R) which carry power to the oscillator and buffer stages (see Fig.8).

Fig 8. The HW9 VFO. R129 and R138 are removed to disable Q102 (the vfo) and Q105 (buffer). C196 is lifted
from the board at it’s Q105 end and connected to a miniature coaxial lead connecting the BNC socket
on the rear panel. This carries the external VFO RF injection signal.

Setting Up, Software Trimming

Initial setting up involves just the PLL as the DDS is set up initially from the program code.
A suitable trimming tool for adjusting the VCO inductor L3 will be required along with a high
impedance digital voltmeter for monitoring the PLL tuning control voltage. (This voltage is a good
indicator of the ‘health’ of the PLL loop and two jack plugs have been provided on the rear panel to
give convenient access for a voltmeter or oscilloscope). On initial startup with the HW9 on, for
example, the 20m band position, the display will show 14.000000 MHz and the PLL may or may
not be in lock depending on the inductance of L3. If not in lock the LED shows red and the tuning
control voltage will be at or near rail, probably 12V; and ofcourse the VCO frequency will be
unpredictable. In this case adjust the core of L3 until the PLL locks indicated by the LED turning
green and the tuning voltage dropping away from rail; the operating frequency will also now be
14.0MHz ± HFO innaccuracies. The idea now is to continue adjusting the voltage so as to give
coverage between the frequency extremes (eg 14.00 – 14.15 MHz) on the linear portion of the
BB204 varicaps’ voltage/capacitance transfer ratio; aim for c.9V at 14.00MHz and check that this
reduces to about 5 – 5.25V at 14.15MHz. It is advisable to allow a few minutes after switch on for
the VCO to stabilise before adjusting the tuning voltage as the voltage will slowly change to offset
any drift, thereby keeping the actual frequency perfectly stable. Notice that while in lock, only
changing the DDS will cause the operating frequency to vary; adjusting L3 will only result in the
tuning voltage changing, in effect compensating for the change in inductance by altering the
capacitance of the BB204 varicaps by a corresponding amount – the frequency stays rock solid at
the value dictated by the DDS frequency.

There are 2 settings accessible during normal operation from the set up screens; these are
entered from the main display by pressing the CAL button for 1 second – a second, brief push
returns to the main screen and stores any new entered data for future use. The first screen sets the
range for RIT adjustment and applies to all bands; the second, (actually appears first for
convenience) is an offset frequency setting and is band specific. Earlier it was pointed out that the
extreme accuracy of the DDS is potentially compromised here due to the way the frequency mixer
chain is implemented in the HW9. Allocated to each band is a high freqency crystal oscillator
(HFO) which subtractively mixes with the VFO to generate the LO signal (Fig 1.). In practice,
whilst the HFOs are highly stable it seems impossible to persuade them to operate exactly on their
nominal frequencies thus giving rise to slight discrepancies in operating frequency versus displayed
frequency. The answer is to provide a method of supplying an offset for each band which can be
applied to the DDS whilst not affecting the displayed frequency on the LCD; this is done in
software and illustrates nicely the flexibility of the digital approach. So for each band in turn,
transmit low level RF into a dummy load while monitoring the frequency accurately on either a
frequeny counter or reliable general coverage receiver. Note the discrepancy and then enter the
‘Offset Freq’ set up screen. Enter this frequency, either positive or negative depending on whether
the discrepancy is high or low and exit the screen; the value is stored in EEPROM and will be used
everytime this band is selected. Check again and make any final adjustments; obviously this can be
carried out at will though once done it rarely seems to require repeating.

On Air, Shortcomings and Future Developments

This VFO enhances the operation of the HW9 considerably. Absolute stability from switch
on, reliable and accurate frequency readout and excellent reports on transmit tone have all made the
effort worthwhile. There are still occasional birdies as there were with the original analogue VFO
(presumably linked with the signal mixing techniques in the HW9) as well as some very low level
internally generated spurii which are definitely caused by the DDS system. However these are so
low as to be hardly noticeable on a normally active band and do not affect operating enjoyment or
transmitted signal quality.

One problem directly attributable to the DDS system is the relatively slow TX/RX
switching caused by the timings inherent in the PIC code. This causes chirp at the start of each
element wben the TX and RX frequencies are different, that is when RIT is in operation. To
overcome this, the QSK of the HW9 is replaced by semi break in controlled by the 555 timer IC as
shown in Fig 5. This allows a variable time delay for RX return (adjustable from rear panel) and
means that only the first element of a ‘phrase’ is chirped when RIT is in use; whether this is an
inconvenience or not depends on one’s operating habits ofcourse.

A project such as this is probably never finished in the strict sense of the word and already
thoughts have turned to improvements and additions. The 16F628 PIC has 128 bytes of EEPROM
but there is a pin for pin upgrade now manufactured which has 256 bytes and which would enable
‘band stacking registers’ to be incorporated giving ‘last frequency’ memory to be invoked for each
band. This chip, the 16F648A is not yet available in this country unless imported from the USA in
multiples of 100…! In the meantime the possibility of adding code to provide serial data transfer
for automatic computer logkeeping is being considered.


1. ‘Pic “n” Mix Digital Injection System’ P.J.Rhodes G3XJP, RadCom Jan – June 1999
2. http://www.minicircuits.com/appnote/vco15-10.pdf
3. AD9851 Data Sheet – http://www.analog.com/
4. ‘A PLL Spur Eliminator for DDS VFOs’ by Rick Peterson WA6NUT – QEX July 2000
(Available as reprint from ARRL)
5. PLL3 V2 from http://mywebpages.comcast.net/kd9jq/hamradio/PLL3.html
6. ‘Direct Digital Synthesis for Radio Projects’: A.Talbot G4JNT, RadCom Nov 2000
7. MPLAB and lots more at http://www.microchip.com/- also for PIC device data sheets etc
8. http://www.minikits.com.au/kits4.html. Both TOPIC03 and FPP09 archives contain full
construction details for PIC programmers as well as the software.

Appendix 1:-

Component list for the adapted Hands PLL10 board (Fig. 3)

R1,4,5,7 100R C1,2,8,9,12,13,14,16, 10N

R2 3K3 18,23,23J,30,34
R3,13 8K2 C3,4,10,11,15 100N
R6 1K8 C5,7 22P
R8 1K5 C17 1N5
R9,11 10K C6,21,21J,22,22J 68P
R10 2K2 C19,19J,24,36 1N
R12 940R C25,27,28 4.7µ
R14,15 1K
R16 10K IC1 NE602
R17,17J 100K IC2 74HC4046AN
R18,18J 100K IC3 TL072
R19,19J 100R IC4,5 78L05
VR1,2,3 4K7 TR2,TR2,J J310
TR1 BC183L
T1 6T bifilar on FT43-61 core D1 – D4 IN9184
T2 8T bifilar on FT37-43 core D5 2 X BB204
X1 10MHz crystal

Appendix 2 :-

The original software allocates the I/O ports of the PIC to the pins of the DDS chip
differently to the G4JNT board used here. Rather than the onerous task of rewriting the code, it was
decided to physically redirect the ports by jumpering the board with hook up wire. This is detailed

1. Solder an 18 pin DIL socket to the TX

G4JNT board using the surface pads.

2. Whilst fixing the socket, connect 3 Grnd

wires between the pins as illustrated :-

• 1 > 11 (WCLK to RB5)

• 18 > 6 (FQUD to RB0)
• 17 > 13 (DATA to RB7)
(redirected AD9851 pin to PIC pin in

3. Take a second 18 pin DIL socket and

bend out pins 1,2,17 and 18.
4. Plug this second socket into the first. Encoder
Ensure the bent out pins do not 18 17

contact the corresponding ‘inserts’ in PIC16F628

the lower DIL socket. 1 2

5. Connect wires from these pins to the
relevant pull up resistors as indicated
opposite. See also photos for further

6. Plug PIC into upper DIL socket.