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VLSI
VLSI (Very Large Scale Integration) is an efficient way to get reliability, less volume, low
weight and less power consumption for designing hardware, now a days due to use of VLSI,
millions of gates can be formed on a single programmable chip. As time progresses
complexity of digital system is increasing and sophisticated design tools are being
introduced in to hardware design process. Hardware description language such as VHDL and
VERILOG are used to describe hardware for this purpose.
The Background
With tremendous pressures on developing low cast mass production designs with ease in
upgradability, the future definitely belongs to IC Designing. With increasing number of
companies getting in to core of VLSI designing excellent job opportunities are opening up.
As the technology keep scaling to sub 45nm, design complexity is increasing, at the same
time reducing design time due to increasing pressure to meet time to market. First time
silicon success has become a very distinct competitive advantage in current scenario
To meet this growing demand our courses has been designed by BrainSupport
team to meet present and future needs of the industry. The course is carefully
planned to meet the need of corporate within unique learning contexts and
environments. To be in par with industrial requirements trainers who will conduct
the course have more than 10 years of industrial experience in FPGA/ ASIC
design.
1. Lecture : 3 hrs
2. Lab : 4 hrs
Important Dates:
Course Structure
1. Digital and advanced digital Design:
Duration 3 Weeks
(a) Fundamentals of Digital Design
(b) Combinational Logic Design
(c) Sequential Logic Design
(d) State Machines
(e) ALU Design
(f) Processor Logic Design
2. System Architecture
Duration 2 Weeks
(a) Memories
3. HDL (VHDL/Verilog)
Duration 4 Weeks
(a) HDL Basic Concepts
(b) Concurrent Statements
(c) Sequential Statements
(d) Design Using HDL
(e) Test Cases and Test vectors
(f) Synthesis and Optimization
(g) Efficient Coding using HDL
(h) Constraining Design and optimization
(i) State Machines using HDL
(j) Multiple clock Domains and Design
5. ASIC Design
Duration 6 Weeks
(a) Introduction to ASIC
(b) ASIC design Flow
(c) ASIC Synthesis
(d) ASIC EDA Tools and Flow
(e) Design and optimization constraints
(f) Area, Power and Speed minimization techniques
(g) HDL efficient coding and analysis
(h) Pipelining, resource sharing and register balancing
(i) Netlist generation and SDF files
(j) State machine optimization
9. Physical Design
Duration 8 Weeks
(a) Backend Design flow
(b) Technology files and library formats
(c) Floor planning
(d) Power planning
(e) Placement of Standard cells and macros\
(f) Clock Tree Synthesis
(g) Global and detailed routing
(h) Parasitic extraction and back annotation
(i) STA
(j) GDS II
11. PROJECT
Duration 12 Weeks
(a) RISC processor design at 65 nm
(b) ORCA Processor implementation
(c) Logical, Physical Design and timing closure at 65, 40 nm.
Design Flow
Eligibility criteria
Mentors are ME/M.Tech in electronics from IITs and other leading institutions with strong
fundamentals in chip design and working experience on ASIC/FPGA designs. All the Mentors
have more than 10 years of Industrial experience.
Software/Hardware tools
EDA Tools
1. MODELSIM SE
4. Altera Quartus II
Contact Information