D.Y.

PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE-44

DEPARTMENT OF
Class: - S.E. (SEM-II )
Subject: Digital Electronics & Logic Design
Marks: 50 MCQ-UNIT IV Time: 1 Hour Date:_______
Instructions:1) All questions are compulsory. 2) Use of Calculator is allowed. 3) Mark the correct answer as
(√ ).
1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with
an input clock frequency of 20.48 MHz.
a. 10.24 kHz b. 5 kHz c. 30.24 kHz d. 15 kHz
2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
a. The logic level at the D input is transferred to Q on NGT of CLK.
b. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
c. The Q output is ALWAYS identical to the D input when CLK = PGT.
d. The Q output is ALWAYS identical to the D input.
3. Propagation delay time, tPLH, is measured from the ________.
a. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
b. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
c. preset input to the LOW-to-HIGH transition of the output
d. clear input to the HIGH-to-LOW transition of the output
4. How many flip-flops are in the 7475 IC?
a. 1 b. 4 c. 2 d. 8
5. How many flip-flops are required to produce a divide-by-128 device?
a. 1 b. 4 c. 6 d. 7
6. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
________.
a. parity error checking b. ones catching c. digital discrimination d. digital
filtering
7. What is another name for a one-shot?
a. Monostable b. Multivibrator c. Bistable d. Astable
8. On a master-slave flip-flop, when is the master enabled?
a. when the gate is LOW b. when the gate is HIGH c. both of the above d. None of
these
9. One example of the use of an S-R flip-flop is as a(n):
a. Racer b. astable oscillator c. binary storage register d. transition pulse
generator
10. What is the difference between the 7476 and the 74LS76?
a. the 7476 is master-slave, the 74LS76 is master-slave
b. the 7476 is edge-triggered, the 74LS76 is edge-triggered
c. the 7476 is edge-triggered, the 74LS76 is master-slave
d. the 7476 is master-slave, the 74LS76 is edge-triggered
11. Which of the following is correct for a gated D flip-flop?
a. The output toggles if one of the inputs is held HIGH. b. Only one of the inputs can be HIGH at a
time.
c. The output complement follows the input when enabled.
d. Q output follows the input D when the enable is HIGH.
12. With regard to a D latch, ________.
a. the Q output follows the D input when EN is LOW b. the Q output is opposite the D input when
EN is LOW
c.the Q output follows the D input when EN is HIGH d.the Q output is HIGH regardless of EN's
input state
13. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
a. It can't be done. b. Invert the Q outputs. C. Invert the S-R
 inputs. D. None
14. When is a flip-flop said to be transparent?
a. when the Q output is opposite the input b. when the Q output follows the input
c. when you can see through the IC packaging d. None of these
 15. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below.
Determine if the circuit is functioning properly, and if not, what might be wrong.

a. The circuit is functioning properly.

b. b. Q2 is incorrect; the flip-flop is probably bad.
c.The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
d. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
16. A 555 operating as a monostable multivibrator has an R 1 of 1 M . Determine C1 for a pulse width of 2 s.
a. 1.8 F b. 18 F c. 18 pF d. 18 nF

17. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is
read during the entire time the clock pulse is at a LOW level.

A. True b. False

18. Which of the following is correct for a D latch?

a. The output toggles if one of the inputs is held HIGH.
b. Q output follows the input D when the enable is HIGH.
c. Only one of the inputs can be HIGH at a time.
d. The output complement follows the input when enabled.

19. A J-K flip-flop is in a "no change" condition when ________.

a. J = 1, K = 1 b. J = 1, K = 0 c. J = 0, K = 1 d. J = 0, K = 0
20. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
a. clock is LOW b. slave is transferring c. flip-flop is reset d. clock is HIGH
21. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a. If both inputs are HIGH, the output will toggle.
b. The output will follow the input on the leading edge of the clock.
c. When both inputs are LOW, an invalid state exists.
d. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock.
22. What does the triangle on the clock input of a J-K flip-flop mean?
a. level enabled b. edge-triggered
23. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
a. constantly LOW b. constantly HIGH c. a 20 kHz square wave d. a 10
kHz square wave
24. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________
state(s) at the ________.

a. opposite, active clock edge b. inverted, positive clock edge

b. c. quiescent, negative clock edge d. reset, synchronous clock edge

25. What is the hold condition of a flip-flop?

a. both S and R inputs activated b. no active S or R input
c. only S is active d. only R is active
26. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0,
the latch will be ________.
a. SET b. RESET c. clear d. invalid
27. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will
cause it to change states?
a. CLK = NGT, D = 0 b. CLK = PGT, D = 0 c. CLOCK NGT, D = 1 d. CLOCK
PGT, D = 1
28. The symbols on this flip-flop device indicate ________.

a. triggering takes place on the negative-going edge of the CLK pulse

b. triggering takes place on the positive-going edge of the CLK pulse
c. triggering can take place anytime during the HIGH level of the CLK waveform
d. triggering can take place anytime during the LOW level of the CLK waveform
29. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
 a. active-HIGH b. active-LOW
30. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
a. edge-detection circuit. b. NOR latch. c. NAND latch. d. pulse-steering circuit.
31. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates
a count of how many input clock pulses?
a. 16 b. 8 c. 4 d. 2
32. What is the significance of the J and K terminals on the J-K flip-flop?
a. There is no known significance in their designations.
b. The J represents "jump," which is how the Q output reacts whenever the clock goes high
and the J input is
also HIGH.
c. The letters were chosen in honor of Jack Kilby, the inventory of the integrated
circuit.
d. All of the other letters of the alphabet are already in use.
33. Why are the S and R inputs of a gated flip-flop said to be synchronous?
a. They must occur with the gate. b. They occur independent of the gate.
34. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
a. True b. False
35. Which of the following is not generally associated with flip-flops?
a. Hold time b. Propagation delay time c. Interval time d. Set up time
36. Edge-triggered flip-flops must have:
a. very fast response times b. at least two inputs to handle rising and falling edges
c. positive edge-detection circuits d. negative edge-detection circuits
37. What is one disadvantage of an S-R flip-flop?
a. It has no enable input. B. It has an invalid state. C. It has no clock input. D. It has
only a single output.
38. To completely load and then unload an 8-bit register requires how many clock pulses?
a. 2 b. 4 c. 8 d. 16
39. Edge-triggered flip-flops must have:
a. very fast response times. b. at least two inputs to handle rising and falling edges.
c. a pulse transition detector. d. active-LOW inputs and complemented
outputs.
40. A positive edge-triggered D flip-flop will store a 1 when ________.
a. the D input is HIGH and the clock transitions from HIGH to LOW
b. the D input is HIGH and the clock transitions from LOW to HIGH
c. the D input is HIGH and the clock is LOW
d. the D input is HIGH and the clock is HIGH
41. If an input is activated by a signal transition, it is ________.
a. edge-triggered b. toggle triggered c. clock triggered d. noise triggered
42. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
a. True b. False
43. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input
clock pulses, the binary count is ________.
a. 00 b. 11 c. 01 d. 10
44. The output of a gated S-R flip-flop changes only if the:
a. flip-flop is set b. control input data has changed c. flip-flop is reset d.
input data has no change
45. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what
could be causing the problem?
 a. The output is always low; the circuit is defective.
b. The Q output should be the complement of the output; the S and R terminals are
reversed.
c. The Q should be following the R input; the R input is defective.
d. There is nothing wrong with the circuit.
46. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
a. An invalid state will exist. b. No change will occur in the output.
c. The output will toggle. d. The output will reset.
47. For an S-R flip-flop to be set or reset, the respective input must be:
a. installed with steering diodes b. in parallel with a limiting resistor c. LOW
d. HIGH
48. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
a. No change will occur in the output. b. An invalid state will exist.
c. The output will toggle. d. The output will reset.
49. How many flip-flops are required to produce a divide-by-128 device?
a. 1 b. 4 c. 6 d. 7
50. On a master-slave flip-flop, the master enabled __
a. when the gate is LOW b. when the gate is HIGH c. both of the above d. none of
above