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1 1
Compal Confidential
.ru
m
2 2
ru
AMD APU Ontario-FT1 + FCH Hudson-M1 + GPU Roberson XT
Fo
3
er 2010-11-10 3
REV:1.0
yb
C
4 4
CIT RD Only
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 1 of 48
A B C D E
A B C D E
For PAWGD
1 1
.ru
page 11
page 5,6,7
VRAM 64*16 x4 PCI-E GPP GEN2
DDR3*4 x4 UMI Gen. 1
page 18 ~ 24 2.5GT/s per lane
2Channel Speaker
page 27
m
2
Audio Codec Internal MIC 2
page 27
Hudson M1 AZALIA CX20671
ru
page 27
BGA 605-Ball Audio Jacks
23mm x 23mm Stereo
HeadPhone Output
4 * x1 PCI-E 2.0 14*USB2.0
Microphone Input
CMOS Camera page 10
Fo
WLAN &WiMax page 13,14,15,16,17 6*SATA serial BlueTooth CONN page 34
page 30
3
page 25,26
SPI ROM
page 15
er EC
ENE KB930
WLAN/WiMAX
Card Reader
3
page 31
yb
PCI Express USB(WiMAX) Realtek RTS5139
SD/MMC/MS/MS Pro/XD
Mini card Slot 1 PCI-E(WLAN)
WLAN/WiMAX page 30
Int.KBD
page 32
ESATA HDD AND USB CONN
C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 2 of 48
A B C D E
A B C D E
APU
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF GPU
+APU_CORE_NB 1.0V switched power rail ON OFF OFF Port1 NC PCIE2 PCIE x4 SATA2 eSATA
1 1
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF
USB2.0 PCIE3 SATA3 NC
+1.0VS 1.0V switched power rail for NB VDDC & VGA ON OFF OFF Port0 Left USB1 PCIE0 LAN SATA4 NC
+1.1VS 1.1VS switched power rail ON OFF OFF
Port1 USB Camera PCIE1 WLAN SATA5 NC
FCH
+1.8VS 1.8V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON* Port2 Left(Combo) PCIE2 NC
+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF
Port3 Left USB2 PCIE3 NC
+3VS 3.3V switched power rail ON OFF OFF
.ru
+5VALW 5V always on power rail ON ON ON* Port4 Right USB
+5VS 5V switched power rail ON OFF OFF
Port5 BT
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON Port6 CardReader
+1.1VALW 1.1V always on power rail ON ON ON*
Port7 Mini-PCIE
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
m
Port8 NC
ru
Smart Battery 0001-011xb 15H EMC1412-2 (dGPU) 1111-100xb F8H
Port11 NC
- PX3@ : PX3.0 only
EMC1403-2(DDR,WLAN) 1001-101xb 9AH Port12 NC - BACO@ : Baco only
SB-TSI 1001-100xb 98H
Port13 NC GIGA@ : AR8151
8152@ : AR8152
Fo
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
CMOS@ : USB camera
HDMI@ : HDMI function
Device Address HEX nonHDMI@ : w/o HDMI function
APU SIC/SID (FCH_SMB3)
ESATA@: eSATA function
H_THERMTRIP# (FCH_ALERT#)
BT@ : BT function
ME@ : ME components
X76@, H1G@, H512@, S1G@, S512@ : VRAM
3
SM Bus Controller 1
Device Address
(FCH_SMB0)
HEX
er 45@ : 45 Level
HWM@ : hardware monitor function
nonHWM@: w/o hardware monitor function
3
yb
DDR DIMM1 (FCH_SMB0) 1001-000xb 90
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
WLAN (FCH_SMB0)
C
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 3 of 48
A B C D E
5 4 3 2 1
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
.ru
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VGS) VDDC/VDDCI 1.12V OFF OFF 12.9A C
m
VDDC/VDDCI(1.12V)
ru
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
Fo
PE_GPIO1
REFCLK PX_mode
B +3.3VALW MOS
+3.3VGS B
Straps Reset 1
Straps Valid
er +1.0V Regulator
2
+1.0VGS
+1.5V SI4800
3
+1.5VGS
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1
U22B
+1.8VS C508 1 0.1U_0402_16V7K HDMI_TX2P_C R398 1 2 150_0402_1%
DISPLAYPORT 1
(11) HDMI_TX2P 2 A8 TDP1_TXP0 DP_ZVSS H3
C509 1 0.1U_0402_16V7K HDMI_TX2N_C
DP MISC
(11) HDMI_TX2N 2 B8 TDP1_TXN0
G2 APU_ENBKL (10)
C510 1 0.1U_0402_16V7K HDMI_TX1P_C DP_BLON
(11) HDMI_TX1P 2 B9 H2 APU_ENVDD (10)
R404 300_0402_5% APU_DBREQ# C511 1 0.1U_0402_16V7K HDMI_TX1N_C TDP1_TXP1 DP_DIGON
2 1 (11) HDMI_TX1N 2 A9
TDP1_TXN1 DP_VARY_BL
H1 APU_BLPWM (10)
D R399 1K_0402_5% APU_SVC D
1 2
R400 1 2 1K_0402_5% APU_SVD C512 1 2 0.1U_0402_16V7K HDMI_TX0P_C D10
LDT_RST# (11) HDMI_TX0P HDMI_TX0N_C TDP1_TXP2 HDMI_CLK
R405 2 1 300_0402_5% C513 1 2 0.1U_0402_16V7K C10 B2
(11) HDMI_TX0N TDP1_TXN2 TDP1_AUXP HDMI_CLK (11)
R401 2 1 300_0402_5% APU_PWRGD C2 HDMI_DATA
TEST_25_L HDMI_CLKP_C TDP1_AUXN HDMI_DATA (11)
R402 1 2 510_0402_1% C514 1 2 0.1U_0402_16V7K A10
(11) HDMI_CLKP TDP1_TXP3
R403 1 2 1K_0402_5% TEST36 C515 1 2 0.1U_0402_16V7K HDMI_CLKN_C B10 C1
(11) HDMI_CLKN TDP1_TXN3 TDP1_HPD HDMI_DET (11)
B5 A3 EDID_CLK
(10) LVDS_A2 LTDP0_TXP0 LTDP0_AUXP EDID_CLK (10)
EDID_DATA
DISPLAYPORT 0
(10) LVDS_A2# A5 B3 EDID_DATA (10)
LTDP0_TXN0 LTDP0_AUXN
D6 D3 R406 1 2 100K_0402_5%
(10) LVDS_A1 LTDP0_TXP1 LTDP0_HPD
(10) LVDS_A1# C6 LTDP0_TXN1
DAC_RED C12 DAC_RED (12)
A6 D13 R407 1 2 150_0402_1%
+3VS (10) LVDS_A0 LTDP0_TXP2 DAC_REDB
B6 A12
.ru
(10) LVDS_A0# LTDP0_TXN2 DAC_GREEN DAC_GRN (12)
B12 R408 1 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
HDMI_DATA (10) LVDS_ACLK LTDP0_TXP3 DAC_BLUE DAC_BLU (12)
R811 1 2 10K_0402_5% C8 B13 R409 1 2 150_0402_1%
(10) LVDS_ACLK# LTDP0_TXN3 DAC_BLUEB
R812 1 2 10K_0402_5% HDMI_CLK V2 E1
(13) APU_CLK CLKIN_H DAC_HSYNC CRT_HSYNC (12)
(13) APU_CLK# V1 CLKIN_L DAC_VSYNC E2 CRT_VSYNC (12)
R410 1 2 1K_0402_5% APU_PROCHOT#
CLK
(13) DISP_CLK D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK (12)
R411 1 2 1K_0402_5% APU_ALERT#_R D1 D4
(13) DISP_CLK# DISP_CLKIN_L DAC_SDA CRT_DDC_DATA (12)
R412 1 2 1K_0402_5% APU_SIC J1 D12 R413 1 2 499_0402_1%
(44) APU_SVC SVC DAC_ZVSS
(44) APU_SVD J2 SVD
SER
R414 1 2 1K_0402_5% APU_SID R1 PAD T66
m
APU_SIC TEST4 AMD check list update
P3 SIC TEST5 R2 PAD T67
APU_SID P4 R6 20101110
SID TEST6
TEST14 T5 PAD T68
T3 E4 TEST15 R415 1 @ 2 1K_0402_5%
C (13) LDT_RST# RESET_L TEST15 C
(13) APU_PWRGD T4 K4 PAD T69
CTRL
PWROK TEST16
TEST17 L1 PAD T95
APU_PROCHOT# U1 L2 TEST18 R416 1 2 1K_0402_5%
APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19 R417 1
M2 2 1K_0402_5%
TEST
THERMTRIP_L TEST19
(13) FCH_PROCHOT#
R807 1 @ 2 0_0402_5% APU_PROCHOT# (15) APU_ALERT#_FCH
R418 1 @ 2 0_0402_5% APU_ALERT#_R T2 K1 TEST25_H R419 1 2 510_0402_1%
ALERT_L TEST25_H
ru
R873 1 2 0_0402_5% K2 TEST_25_L
(31) APU_ALERT#_EC APU_TDI TEST25_L TEST28_H
R808 1 2 0_0402_5% N2 L5 PAD T71
(31) EC_PROCHOT# TDI TEST28_H
Connection to EC, FCH input need to pull-down APU_TDO N1 M5 TEST28_L PAD T72
APU_TCK TDO TEST28_L TEST31
P1 M21 PAD T73
TCK TEST31
JTAG
APU_TMS P2 J18 TEST33_H C516 1 2 0.1U_0402_16V4Z R420 1 2 51_0402_1%
APU_TRST# TMS TEST33_H TEST33_L C517 1
T93PAD M4 J19 2 0.1U_0402_16V4Z R421 1 2 51_0402_1%
APU_DBRDY TRST_L TEST33_L Delete Test point for layout limitation
T94PAD M3 U15
Close to APU APU_DBREQ# DBRDY TEST34_H 20100818
M1 T15
DBREQ_L TEST34_L TEST35 R422 1
H4 2 1K_0402_5%
TEST35 TEST36 nonHDMI@
(44) APU_VDDNB_RUN_FB_H F4 N5
VDDCR_NB_SENSE TEST36
Fo
G1 R5 TEST37 PAD T76 R958 1 2 1K_0402_5%
(44) APU_VDD0_RUN_FB_H VDDCR_CPU_SENSE TEST37 +1.8VS
T77PAD F3 HDMI@
VDDIO_MEM_S_SENSE
Pull-high to enable HDMI function
(44) APU_VDD0_RUN_FB_L F1 20100812
VSS_SENSE
K3
TEST38
B4 T1 ALLOW_STOP# (13)
RSVD_1 DMAACTIVE_L
W11
RSVD_2 R423 1
V5 2 1K_0402_5% +1.8VS
RSVD_3
+3VS ONTARIO-2M161000-1.6G_BGA413
1
R424
10K_0402_5%
er
2
B R425 B
2
1K_0402_5%
2
B
AMD Debug
1
Q79
E
yb
MMBT3904_NL_SOT23-3 +1.8VS
1 2
R427 @ 0_0402_5% APU_TCK R843 2 1 1K_0402_5%
1K_0402_5%
If FCH internal pull-up disabled, level-shifter could be deleted. 2 APU_TMS R844 2 1 1K_0402_5%
need to pop for HDT debug
Need BIOS to disable internal pull-up!!
R842
@ APU_TDO
+3VS
2N7002DW-T/R7 0_0402_5%
1
C
R428
Typ 1.6V R848 2 @ 1 10K_0402_5% APU_DBRDY
10K_0402_5% Max 2.0V R849 2 @ 1 10K_0402_5% APU_DBREQ# R850 1 @ 2 300_0402_5%
@
If Q80 or R429, R432 implemented,
2
1 2
R431 0_0402_5%
5
@
APU_SIC 4 3 EC_SMB_CK 1
R432
@ 2
0_0402_5%
FCH_SIC
FCH_SIC (14) T0 FCH
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
Q80B EC_SMB_CK2
1 2 EC_SMB_CK2 (19,29,31) TO EC FT1 CTRL/DP/CRT
2N7002DW-T/R7_SOT363-6 R433 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
R434 0_0402_5% Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 5 of 48
5 4 3 2 1
A B C D E
U22E
DDR_A_MA0 R17 B14 DDR_A_D0
DDR_A_MA1 M_ADD0 M_DATA0 DDR_A_D1
H19 A15
DDR_A_MA2 M_ADD1 M_DATA1 DDR_A_D2
J17 A17
DDR_A_MA3 M_ADD2 M_DATA2 DDR_A_D3 DDR_A_D[0..63]
H18 D18 DDR_A_D[0..63] (8,9)
DDR_A_MA4 M_ADD3 M_DATA3 DDR_A_D4
H17 A14
DDR_A_MA5 M_ADD4 M_DATA4 DDR_A_D5 DDR_A_MA[0..15]
G17 C14 DDR_A_MA[0..15] (8,9)
DDR_A_MA6 M_ADD5 M_DATA5 DDR_A_D6
H15 C16
DDR_A_MA7 M_ADD6 M_DATA6 DDR_A_D7 DDR_A_DM[0..7]
G18 D16 DDR_A_DM[0..7] (8,9)
4 DDR_A_MA8 M_ADD7 M_DATA7 4
F19
DDR_A_MA9 M_ADD8 DDR_A_D8
E19 C18
DDR_A_MA10 M_ADD9 M_DATA8 DDR_A_D9
T19 A19
DDR_A_MA11 M_ADD10 M_DATA9 DDR_A_D10
F17 B21
DDR_A_MA12 M_ADD11 M_DATA10 DDR_A_D11
E18 D20
DDR_A_MA13 M_ADD12 M_DATA11 DDR_A_D12
W17 A18
DDR_A_MA14 M_ADD13 M_DATA12 DDR_A_D13
E16 B18
DDR_A_MA15 M_ADD14 M_DATA13 DDR_A_D14
G15 A21
M_ADD15 M_DATA14
.ru
DDR_A_DM3 M_DM2 M_DATA21 DDR_A_D22
H22 F20
DDR_A_DM4 M_DM3 M_DATA22 DDR_A_D23
P23 F21
DDR_A_DM5 M_DM4 M_DATA23
V23
DDR_A_DM6 M_DM5 DDR_A_D24
AB20 H21
DDR_A_DM7 M_DM6 M_DATA24 DDR_A_D25
AA16 H23
M_DM7 M_DATA25 DDR_A_D26 U22A
K22
DDR_A_DQS0 M_DATA26 DDR_A_D27 PCIE_CRX_GTX_P0
(8,9) DDR_A_DQS0 A16 K21 (18) PCIE_CRX_GTX_P0 AA6 AB6 PCIE_CTX_C_GRX_P0 C518 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0 (18)
M_DQS_H0 M_DATA27 P_GPP_RXP0 P_GPP_TXP0
(8,9) DDR_A_DQS#0
DDR_A_DQS#0 B16 G23 DDR_A_D28 (18) PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N0 Y6 AC6 PCIE_CTX_C_GRX_N0 C519 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N0 (18)
DDR_A_DQS1 M_DQS_L0 M_DATA28 DDR_A_D29 P_GPP_RXN0 P_GPP_TXN0
(8,9) DDR_A_DQS1 B20 H20
DDR_A_DQS#1 M_DQS_H1 M_DATA29 DDR_A_D30 PCIE_CRX_GTX_P1
(8,9) DDR_A_DQS#1 A20 K20 (18) PCIE_CRX_GTX_P1 AB4 AB3 PCIE_CTX_C_GRX_P1 C520 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1 (18)
PCIE I/F
M_DQS_L1 M_DATA30 P_GPP_RXP1 P_GPP_TXP1
(8,9) DDR_A_DQS2
DDR_A_DQS2 E23 K23 DDR_A_D31 (18) PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 AC4 AC3 PCIE_CTX_C_GRX_N1 C521 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N1 (18)
DDR_A_DQS#2 M_DQS_H2 M_DATA31 P_GPP_RXN1 P_GPP_TXN1
(8,9) DDR_A_DQS#2 E22
M_DQS_L2 PCIE_CTX_C_GRX_P2 C522 1
(8,9) DDR_A_DQS3
DDR_A_DQS3 J22 N23 DDR_A_D32 (18) PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P2 AA1 Y1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2 (18)
M_DQS_H3 M_DATA32 P_GPP_RXP2 P_GPP_TXP2 PCIE_CTX_C_GRX_N2 C523 1
DDR_A_DQS#3 DDR_A_D33 PCIE_CRX_GTX_N2 2 0.1U_0402_16V7K
m
(8,9) DDR_A_DQS#3 J23 P21 (18) PCIE_CRX_GTX_N2 AA2 Y2 PCIE_CTX_GRX_N2 (18)
DDR_A_DQS4 M_DQS_L3 M_DATA33 DDR_A_D34 P_GPP_RXN2 P_GPP_TXN2
(8,9) DDR_A_DQS4 R22 T20
M_DQS_H4 M_DATA34 PCIE_CTX_C_GRX_P3 C524 1
(8,9) DDR_A_DQS#4
DDR_A_DQS#4 P22 T23 DDR_A_D35 (18) PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P3 Y4 V3 2 0.1U_0402_16V7K PCIE_CTX_GRX_P3 (18)
3 DDR_A_DQS5 M_DQS_L4 M_DATA35 DDR_A_D36 PCIE_CRX_GTX_N3 P_GPP_RXP3 P_GPP_TXP3 PCIE_CTX_C_GRX_N3 C525 1 3
(8,9) DDR_A_DQS5 W22 M20 (18) PCIE_CRX_GTX_N3 Y3 V4 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3 (18)
DDR_A_DQS#5 M_DQS_H5 M_DATA36 DDR_A_D37 P_GPP_RXN3 P_GPP_TXN3
(8,9) DDR_A_DQS#5 V22 P20
DDR_A_DQS6 M_DQS_L5 M_DATA37 DDR_A_D38 P_ZVDD_10 R436 1 1.27K_0402_1%
(8,9) DDR_A_DQS6 AC20 R23 +1.0VS 1 2 Y14 AA14 P_ZVSS 2
DDR_A_DQS#6 M_DQS_H6 M_DATA38 DDR_A_D39 R435 2K_0402_1% P_ZVDD_10 P_ZVSS
(8,9) DDR_A_DQS#6 AC21 T22
DDR_A_DQS7 M_DQS_L6 M_DATA39
(8,9) DDR_A_DQS7 AB16
M_DQS_H7
Less than 1"
DDR_A_DQS#7 AC16 V20 DDR_A_D40 Less than 1"
(8,9) DDR_A_DQS#7 M_DQS_L7 M_DATA40
V21 DDR_A_D41 (13) UMI_RX0P AA12 AB12 UMI_TX0P_C C526 1 2 0.1U_0402_16V7K
M_DATA41 P_UMI_RXP0 P_UMI_TXP0 UMI_TX0P (13)
ru
DDR_A_CLK0 M17 Y23 DDR_A_D42 (13) UMI_RX0N Y12 AC12 UMI_TX0N_C C527 1 2 0.1U_0402_16V7K
(8) DDR_A_CLK0 M_CLK_H0 M_DATA42 P_UMI_RXN0 P_UMI_TXN0 UMI_TX0N (13)
DDR_A_CLK#0 M16 Y22 DDR_A_D43
(8) DDR_A_CLK#0 M_CLK_L0 M_DATA43
DDR_A_CLK1 M19 T21 DDR_A_D44 (13) UMI_RX1P AA10 AC11 UMI_TX1P_C C528 1 2 0.1U_0402_16V7K
(8) DDR_A_CLK1 M_CLK_H1 M_DATA44 P_UMI_RXP1 P_UMI_TXP1 UMI_TX1P (13)
DDR_A_CLK#1 M18 U23 DDR_A_D45 Y10 AB11 UMI_TX1N_C C529 1 2 0.1U_0402_16V7K
UMI I/F
(8) DDR_A_CLK#1 M_CLK_L1 M_DATA45 (13) UMI_RX1N P_UMI_RXN1 P_UMI_TXN1 UMI_TX1N (13)
DDR_B_CLK2 N18 W23 DDR_A_D46
(9) DDR_B_CLK2 M_CLK_H2 M_DATA46
DDR_B_CLK#2 N19 Y21 DDR_A_D47 (13) UMI_RX2P AB10 AA8 UMI_TX2P_C C530 1 2 0.1U_0402_16V7K
(9) DDR_B_CLK#2 M_CLK_L2 M_DATA47 P_UMI_RXP2 P_UMI_TXP2 UMI_TX2P (13)
DDR_B_CLK3 L18 (13) UMI_RX2N AC10 Y8 UMI_TX2N_C C531 1 2 0.1U_0402_16V7K
(9) DDR_B_CLK3 M_CLK_H3 P_UMI_RXN2 P_UMI_TXN2 UMI_TX2N (13)
DDR_B_CLK#3 L17 Y20 DDR_A_D48
(9) DDR_B_CLK#3 M_CLK_L3 M_DATA48
AB22 DDR_A_D49 (13) UMI_RX3P AC7 AB8 UMI_TX3P_C C532 1 2 0.1U_0402_16V7K
M_DATA49 P_UMI_RXP3 P_UMI_TXP3 UMI_TX3P (13)
DDR_RST# L23 AC19 DDR_A_D50 (13) UMI_RX3N AB7 AC8 UMI_TX3N_C C533 1 2 0.1U_0402_16V7K
(8,9) DDR_RST# M_RESET_L M_DATA50 P_UMI_RXN3 P_UMI_TXN3 UMI_TX3N (13)
Fo
DDR_EVENT# N17 AA18 DDR_A_D51
(8,9) DDR_EVENT# M_EVENT_L M_DATA51
AA23 DDR_A_D52 ONTARIO-2M161000-1.6G_BGA413
M_DATA52 DDR_A_D53
AA20
DDR_CKE0 M_DATA53 DDR_A_D54
(8,9) DDR_CKE0 F15 AB19
DDR_CKE1 M_CKE0 M_DATA54 DDR_A_D55
(8,9) DDR_CKE1 E15 Y18
M_CKE1 M_DATA55
AC17 DDR_A_D56
M_DATA56 DDR_A_D57
Y16
DDR_A_ODT0 M_DATA57 DDR_A_D58
(8) DDR_A_ODT0 W19 AB14
DDR_A_ODT1 M0_ODT0 M_DATA58 DDR_A_D59
(8) DDR_A_ODT1 V15 AC14
DDR_B_ODT0 M0_ODT1 M_DATA59 DDR_A_D60
(9) DDR_B_ODT0 U19 AC18
DDR_B_ODT1 M1_ODT0 M_DATA60 DDR_A_D61
(9) DDR_B_ODT1 W15 AB18
M1_ODT1 M_DATA61 DDR_A_D62
AB15
DDR_CS0_DIMMA# M_DATA62 DDR_A_D63
(8) DDR_CS0_DIMMA# T17 AC15
2 (8)
(9)
(9)
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
(8,9) DDR_A_RAS#
(8,9) DDR_A_CAS#
(8,9) DDR_A_WE#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
W16
U17
V16
U18
V19
V17
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1
M_RAS_L
M_CAS_L
M_WE_L
ONTARIO-2M161000-1.6G_BGA413
M_ZVDDIO_MEM_S
M_DATA63
M_VREF
M23
M22
er +MEM_VREF
R437 2 1
39.2_0402_1%
+1.5V
2
yb
+1.5V
C
2
+1.5V R438
1K_0402_1%
R444 1 2 DDR_EVENT#
1
1K_0402_5% +MEM_VREF
2
1 1
R439 C534 C535
1 1K_0402_1% 1
1000P_0402_50V7K 0.1U_0402_16V4Z
2 2
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT1 DDRIII/UMI/PCIE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 6 of 48
A B C D E
5 4 3 2 1
+APU_CORE
+1.8VS
TSense/PLL/DP/PCIE/IO
E5 U8 FBMA-L11-201209-221LMA30T_0805 A7 N13
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
0.1U_0402_16V7K
VDDCR_CPU_1 VDD_18_1 VSS_1 VSS_50
1 1 1 1 1 1 1 E6 W8 1 1 1 1 1 1 1 B7 N20
VDDCR_CPU_2 VDD_18_2 VSS_2 VSS_51
C539
C536
C541
C542
C543
C544
C540
C545
C537
C546
C538
C547
C548
C549
F5 U6 B11 N22
D VDDCR_CPU_3 VDD_18_3 Change from SM010014520 to SD002000080 VSS_3 VSS_52 D
F7 U9 B17 P10
VDDCR_CPU_4 VDD_18_4 20100816 VSS_4 VSS_53
G6 W6 B22 P14
2 2 2 2 2 2 2 VDDCR_CPU_5 VDD_18_5 2 2 2 2 2 2 2 VSS_5 VSS_54
G8 T7 C4 R4
VDDCR_CPU_6 VDD_18_6 VSS_6 VSS_55
H5 V7 D5 R7
VDDCR_CPU_7 VDD_18_7 VSS_7 VSS_56
CPU CORE
H7 D7 R20
VDDCR_CPU_8 VSS_8 VSS_57
J6 D9 T6
VDDCR_CPU_9 VSS_9 VSS_58
J8 D11 T9
VDDCR_CPU_10 VSS_10 VSS_59
L7 D14 T11
VDDCR_CPU_11 VSS_11 VSS_60
M6 B15 T13
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
180P_0402_50V8J
VDDCR_CPU_12 Change from SM010014520 to SD002000080 VSS_12 VSS_61
1 1 1 1 1 1 M8 D17 U4
VDDCR_CPU_13 20100816 VSS_13 VSS_62
C550
C551
C552
C553
C554
C555
N7 D19 U5
VDDCR_CPU_14 +1.8VS VSS_14 VSS_63
R8 E7 U7
VDDCR_CPU_15 VSS_15 VSS_64
GND
0.15A E9 U12
2 2 2 2 2 2 +APU_CORE_NB L30 VSS_16 VSS_65
10A E12
VSS_17 VSS_66
U20
DAC
E8 W9 +VDD_18_DAC 2 1 E20 U22
VDDCR_NB_1 VDD_18_DAC VSS_18 VSS_67
E11 F8 V8
10U_0603_6.3V6M
180P_0402_50V8J
VDDCR_NB_2 FBMA-L11-201209-221LMA30T_0805 VSS_19 VSS_68
E13 1 1 1 F11 V9
1U_0402_6.3V6K
VDDCR_NB_3 VSS_20 VSS_69
.ru
C556
C557
C558
F9 +1.0VS has been raised to +1.05VS for F13 V11
VDDCR_NB_4 VSS_21 VSS_70
F12 AMD design guide 45339_R1.02 update 20101004 G4 V13
VDDCR_NB_5 VSS_22 VSS_71
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
C560
C561
C562
C563
K11
VDDCR_NB_10
0.2A G20
VSS_27 VSS_76
W7
K13 L31 G22 W12
VDDCR_NB_11 VSS_28 VSS_77
DIS PLL
L10 U11 +VDDL_10 2 1 H6 W20
2 2 2 2 2 VDDCR_NB_12 VDDPL_10 VSS_29 VSS_78
L12 H11 Y5
1U_0402_6.3V6K
180P_0402_50V8J
10U_0603_6.3V6M
0.1U_0402_16V7K
VDDCR_NB_13 FBMA-L11-201209-221LMA30T_0805 VSS_30 VSS_79
L14 1 1 1 1 H13 Y7
VDDCR_NB_14 VSS_31 VSS_80
C564
C565
C566
C567
M11 J4 Y9
VDDCR_NB_15 VSS_32 VSS_81
M12 J5 Y11
VDDCR_NB_16 VSS_33 VSS_82
M13 J7 Y13
VDDCR_NB_17 2 2 2 2 VSS_34 VSS_83
N10 J20 Y15
VDDCR_NB_18 VSS_35 VSS_84
m
N12 K10 Y17
+APU_CORE_NB VDDCR_NB_19 L32 VSS_36 VSS_85
N14
VDDCR_NB_20
5.5A K14
VSS_37 VSS_86
Y19
PCIE/IO/DDR3 Phy
P11 +VDD_10 2 1 L4 AA4
VDDCR_NB_21 VSS_38 VSS_87
P13 U13 L6 AA22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
0.1U_0402_16V7K
0.1U_0402_16V7K
VDDCR_NB_22 VDD_10_1 FBMA-L11-201209-221LMA30T_0805 VSS_39 VSS_88
W13 1 1 1 1 1 1 1 L8 AB2
+1.5V VDD_10_2 VSS_40 VSS_89
C568
C569
C570
C571
C572
C573
C574
C 2A V12 L11 AB5 C
VDD_10_3 Change from SM010014520 to SD002000080 VSS_41 VSS_90
G16 T12 L13 AB9
VDDIO_MEM_S_1 VDD_10_4 20100816 VSS_42 VSS_91
G19 L20 AB13
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C576
C577
C578
C579
J16 M7 AB21
VDDIO_MEM_S_4 VSS_45 VSS_94
DDR3
L16 N4 AC5
VDDIO_MEM_S_5 VSS_46 VSS_95
ru
L19 N6 AC9
2 2 2 2 2 VDDIO_MEM_S_6 VSS_47 VSS_96
N16 N8 AC13
VDDIO_MEM_S_7 VSS_48 VSS_97
R16 N11 A11
DP Phy/IO
VDDIO_MEM_S_8 VSS_49 VSSBG_DAC
R19
VDDIO_MEM_S_9
0.5A
W18 +3VS
VDDIO_MEM_S_10 ONTARIO-2M161000-1.6G_BGA413
U16 A4
VDDIO_MEM_S_11 VDD_33
1U_0402_6.3V6K
0.1U_0402_16V7K
1 1
C580
C581
ONTARIO-2M161000-1.6G_BGA413
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
180P_0402_50V8J
1 1 1 1 1 1 1 2 2
C582
C583
C584
C585
C586
C587
C588
Fo
2 2 2 2 2 2 2
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1
C589
C590
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 2 2
C591
C592
C593
C594
2 2 2 2
er
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
C595
C596
C597
C598
B B
POWER +1.0VS
2 2 2 2
yb
220U_B2_2.5VM_R35
1
10U_0603_6.3V6M
1
+
C620
C621
@ 1 1 1 1 1
180P_0402_50V8J
180P_0402_50V8J
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2 2
C599
C600
C601
C602
C603
2 2 2 2 2
C
+APU_CORE POWER
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
1
+ + +
C605
C606
C607
C616
+1.5V
@
2 2 2 2
+1.5V
POWER +1.8VS
POWER
Near CPU Socket
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
unpop for PVT 20101004 1 1 1 1 1 1 1 1
+APU_CORE_NB
C608
C609
C610
C611
C612
C613
C614
C615
A A
330U_6.3V_M
1
10U_0603_6.3V6M
330U_2.5V_M
1 1
22U_0805_6.3V6M
330U_D2_2.5VY_R9M
+ 2 2 2 2 2 2 2 2
C624
C625
1 1
10U_0603_6.3V6M
+
C622
C623
1
+
C618
C619
@
@ 2 2
2 2
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P07-FT1 PWR/VSS
Size Document Number Rev
(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)*1=(SF000002000) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
20100813
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 7 of 48
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
JDIMM1 ME@
+VREF_DQ 1 VREF_DQ VSS 2
3 4 DDR_A_D4 +1.5V +1.5V
VSS DQ4
1000P_0402_50V7K
DDR_A_D[0..63]
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 DDR_A_D[0..63] (6,9)
1 1 7 DQ1 VSS 8
2
C626
C627
9 10 DDR_A_MA[0..15]
VSS DQS0# DDR_A_DQS#0 (6,9) DDR_A_MA[0..15] (6,9)
DDR_A_DM0 11 12 R440 R441
DM0 DQS0 DDR_A_DQS0 (6,9) DDR_A_DM[0..7]
13 14 DDR_A_DM[0..7] (6,9) 1K_0402_1% 1K_0402_1%
2 2 DDR_A_D2 VSS VSS DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
1
DQ3 DQ7
19 20 +VREF_DQ +VREF_CA
D DDR_A_D8 VSS VSS DDR_A_D12 D
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
2
25 26
VSS VSS DDR_A_DM1 R442 R443
(6,9) DDR_A_DQS#1 27 28
DQS1# DM1 1K_0402_1% 1K_0402_1%
(6,9) DDR_A_DQS1 29 30 DDR_RST# (6,9)
DQS1 RESET#
31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34
1
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41
43
DQ17 DQ21
42
44
Combine to one?
VSS VSS DDR_A_DM2
(6,9) DDR_A_DQS#2 45 DQS2# DM2 46
(6,9) DDR_A_DQS2 47 DQS2 VSS 48
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 52
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DDR_A_D19 DQ18 DQ23
53 DQ19 VSS 54
55 56 DDR_A_D28
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
DQ25 VSS
61 VSS DQS3# 62 DDR_A_DQS#3 (6,9)
DDR_A_DM3 63 64
DM3 DQS3 DDR_A_DQS3 (6,9)
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72
73 74 +1.5V
(6,9) DDR_CKE0 DDR_CKE1 (6,9)
m
CKE0 CKE1
75 VDD VDD 76
C DDR_A_MA15 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
77 NC A15 78
79 80 DDR_A_MA14 2 2 2 2 2 2 2 2 2 2 2 2
(6,9) DDR_A_BS2 BA2 A14
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11 C628 C629 C630 C631 C632 C633 C634 C635 C636 C637 C638 C639
DDR_A_MA9 A12/BC# A11 DDR_A_MA7 @ @ @ @ @ @
85 A9 A7 86
1 1 1 1 1 1 1 1 1 1 1 1
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
ru
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
VDD VDD
101 102 DDR_A_CLK1 (6)
(6) DDR_A_CLK0 CK0 CK1
103 104 DDR_A_CLK#1 (6)
(6) DDR_A_CLK#0 CK0# CK1#
105 106
DDR_A_MA10 VDD VDD
107 108 DDR_A_BS1 (6,9)
A10/AP BA1
(6,9) DDR_A_BS0 109 110 DDR_A_RAS# (6,9)
BA0 RAS#
111 112
VDD VDD
Fo
113 114 DDR_CS0_DIMMA# (6)
(6,9) DDR_A_WE# WE# S0#
(6,9) DDR_A_CAS# 115
117
CAS# ODT0
116
118
DDR_A_ODT0 (6) CRB 0.1u X1 4.7u X1 CRB 100U X2
DDR_A_MA13 VDD VDD
119 120 DDR_A_ODT1 (6)
A13 ODT1 +1.5V
121 122
(6) DDR_CS1_DIMMA# S1# NC +0.75VS
123 124
VDD VDD
125 126 +VREF_CA
TEST VREF_CA
127 128
VSS VSS
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
220U_6.3V_M
0.1U_0402_16V4Z
DDR_A_D33 131 132 DDR_A_D37 1 2 2 1 1
DQ33 DQ37
C645
C640
C641
C642
133 134 1
VSS VSS
C644
C643
135 136 DDR_A_DM4 +
B (6,9) DDR_A_DQS#4 DQS4# DM4 B
137 138 @
(6,9) DDR_A_DQS4 DQS4 VSS DDR_A_D38 2 1 1 2
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
139
141
143
145
147
149
151
153
155
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
140
142
144
146
148
150
152
154
156
er
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5 (6,9)
DDR_A_DQS5 (6,9)
2
20100729
C647
+1.5V +1.5V
JDIMM2 ME@
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
VSS2 DQ4
1000P_0402_50V7K
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
1 1 7 DQ1 VSS3 8
9 VSS4 DQS#0 10 DDR_A_DQS#0 (6,8)
C648 C649 DDR_A_DM0 11 12 DDR_A_D[0..63]
DM0 DQS0 DDR_A_DQS0 (6,8) DDR_A_D[0..63] (6,8)
13 14
2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6 DDR_A_MA[0..15]
15 16 DDR_A_MA[0..15] (6,8)
D DDR_A_D3 DQ2 DQ6 DDR_A_D7 D
17 18
DQ3 DQ7 DDR_A_DM[0..7]
19 20 DDR_A_DM[0..7] (6,8)
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
VSS9 VSS10 DDR_A_DM1
(6,8) DDR_A_DQS#1 27 28
DQS#1 DM1
(6,8) DDR_A_DQS1 29 30 DDR_RST# (6,8)
DQS1 RESET#
31 32
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS15 VSS16 44
45 46 DDR_A_DM2
.ru
(6,8) DDR_A_DQS#2 DQS#2 DM2
(6,8) DDR_A_DQS2 47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 VSS22 DQS#3 62 DDR_A_DQS#3 (6,8)
DDR_A_DM3 63 64
DM3 DQS3 DDR_A_DQS3 (6,8) +1.5V
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
69 DQ27 DQ31 70
71 72 2 2 2 2 2 2 2 2 2 2 2 2
m
VSS25 VSS26
C650 C651 C652 C653 C654 C655 C656 C657 C658 C659 C660 C661
@ @ @ @ @ 0.1U_0402_16V4Z
73 74 1 1 1 1 1 1 1 1 1 1 1 1
C (6,8) DDR_CKE0 CKE0 CKE1 DDR_CKE1 (6,8) @ C
75 76 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78
79 80 DDR_A_MA14
(6,8) DDR_A_BS2 BA2 A14
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
ru
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91
93
A5 A4
92
94
CRB 0.1u X1 4,7uX1
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0 +0.75VS
99 100
VDD9 VDD10
101 102 DDR_B_CLK3 (6)
(6) DDR_B_CLK2 CK0 CK1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
103 104 DDR_B_CLK#3 (6)
(6) DDR_B_CLK#2 CK0# CK1#
Fo
105 106 2 2 1
DDR_A_MA10 VDD11 VDD12
107 108 DDR_A_BS1 (6,8)
A10/AP BA1
C662
C663
C664
(6,8) DDR_A_BS0 109 110 DDR_A_RAS# (6,8)
BA0 RAS#
111 112
VDD13 VDD14 @ 1 1 2
113 114 DDR_CS0_DIMMB# (6)
(6,8) DDR_A_WE# WE# S0#
(6,8) DDR_A_CAS# 115 116 DDR_B_ODT0 (6)
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16
119 120 DDR_B_ODT1 (6)
A13 ODT1
121 122
(6) DDR_CS1_DIMMB# S1# NC2
123 124
VDD17 VDD18
125 126 +VREF_CA
NCTEST VREF_CA
127
VSS27 VSS28
128 Place near JDIMM2
1000P_0402_50V7K
0.1U_0402_16V4Z
B
(6,8) DDR_A_DQS#4
(6,8) DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
131
133
135
137
139
141
143
145
147
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
132
134
136
138
140
142
144
146
148
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
er 1
2
C665
2
C666
B
0.1U_0402_16V4Z
R962
CRB only one 4.7k 10K_0402_5%
DDR3 SO-DIMM B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
1
Reverse Type
For DRAM strap pin reservation
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3 SODIMM-II Socket
20100817 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1
+3VS
1
D R458 R459 D
W=60mils
150_0603_1% 100K_0402_5%
Change footprint
(5) EDID_CLK EDID_CLK 20100812 1 Change footprint
(5) EDID_DATA EDID_DATA C669 20100812
2
1
3
D R462 220K_0402_5% 4.7U_0603_6.3V6K
LVDS_A0 Q81 2 1 2 2
(5) LVDS_A0 LVDS_A0# 2
2N7002H_SOT23-3 G
(5) LVDS_A0#
S
3
LVDS_A1 Q82
(5) LVDS_A1 LVDS_A1# Change footprint 1 AP2301GN-HF_SOT23-3
1
(5) LVDS_A1#
1
20100812 C670
LVDS_A2 W=60mils
OUT
(5) LVDS_A2 LVDS_A2# 0.1U_0402_16V4Z
(5) LVDS_A2# 2 +LCDVDD +LCDVDD_CONN
.ru
LVDS_ACLK L33
(5) LVDS_ACLK (5) APU_ENVDD 2 IN
LVDS_ACLK# 1 2
GND
(5) LVDS_ACLK#
Q83 FBMA-L11-201209-221LMA30T_0805
1
DTC124EKAT146_SC59-3 1 1
3
C671 C672
R473 @ 4.7U_0603_6.3V6K
100K_0402_5% 0.1U_0402_16V4Z
2 2
2
Change footprint
20100812
(5) APU_BLPWM 1 @ 2
R491 0_0402_5%
m
1 2 INVTPWM
(31) INVT_PWM
R490 0_0402_5%
2
ru
R480
+LEDVDD B+ 100K_0402_1%
1 R479 2 0_0805_5%
1
1 1
C673
680P_0402_50V7K C674
@ 4.7U_0805_25V6-K
2 2
+3VS
Fo
JLVDS1 +3VS_CMOS
2
2 1 1
1
4 USB20_N1 CMOS @
4 3 3 USB20_P1
USB20_N1 (14)
R483
6
+LCDVDD_CONN 6 5 5 USB20_P1 (14)
10K_0402_5%
(60 MIL) 8
8 7 7
10 LVDS_A0#
10 9 9 LVDS_A0
12
11 11
2
12
14
13 13
+3VS 1 2
CE_EN 14 LVDS_A1# R484 0_0402_5%
16
(31) CE_EN INVTPWM 16 15 15 LVDS_A1
18
@
1
DISPOFF# 18 17 17
20
680P_0402_50V7K 20 19 19 LVDS_A2# DISPOFF#
22
AMD check list update 22 21 21 LVDS_A2 (31) BKOFF# 1 2
C675
2 20101110
24
26
28
24
26
28
23 23
25 25
27 27
er LVDS_ACLK#
RB751V_SOD323
D4 @
1
+5VS 30 LVDS_ACLK
B 30 29 29 R485 B
32 31 10K_0402_5%
GNDGND
1
2
2K_0402_5% 2K_0402_5% ME@
yb
2
EDID_CLK
EDID_DATA
CMOS Camera
Q84 AP2301GN-HF_SOT23-3
1
Change footprint
470P_0402_50V7K
470P_0402_50V7K
C
2
R489 0.1U_0402_16V4Z
CMOS1 C680 0_0603_5% 2 CMOS@
1 @ 1 @ +5VALW R488 CMOS@ 100K_0402_5% 1 2 1 2 CMOS@
2
C677 C679
2
R880 +3VS_CMOS
0.1U_0402_16V4Z
1
20100728 R938 150K_0402_5%
2 2 0_0402_5% CMOS@ 1
OUT
CMOS@
@
For EMI 20100728 C681
1
2 10U_0805_10V4Z
(31) CMOS_OFF# IN 2 CMOS@
GND
Q85
A DTC124EKAT146_SC59-3 A
3
CMOS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1
+5VS +5VS
(5) HDMI_CLKP R513 1 HDMI@ 2 0_0402_5% HDMI_CLK+_CONN
R514 1 HDMI@ 2 0_0402_5% HDMI_CLK-_CONN 3 3
(5) HDMI_CLKN
R515 1 HDMI@ 2 0_0402_5% HDMI_TX0+_CONN
(5) HDMI_TX0P
R516 1 HDMI@ 2 0_0402_5% HDMI_TX0-_CONN 1 HDMIDAT_R 1 HDMICLK_R
(5) HDMI_TX0N
(5) HDMI_TX1P R517 1 HDMI@ 2 0_0402_5% HDMI_TX1+_CONN
(5) HDMI_TX1N R518 1 HDMI@ 2 0_0402_5% HDMI_TX1-_CONN 2 @ 2 @
R519 1 HDMI@ 2 0_0402_5% HDMI_TX2+_CONN D5 D6
(5) HDMI_TX2P
R520 1 HDMI@ 2 0_0402_5% HDMI_TX2-_CONN BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
(5) HDMI_TX2N
D D
+3VS
@ L34
HDMI_CLKP 1 2 HDMI_CLK+_CONN Change footprint
1 2 HDMI_CLK+_CONN 20100812
1 2
.ru 2
R500 HDMI@ 499_0402_1%
HDMI_CLKN 4 3 HDMI_CLK-_CONN HDMI_CLK-_CONN 1 2
4 3 R501 HDMI@ 499_0402_1% HDMICLK_R
(5) HDMI_CLK 1 6
WCM-2012-900T_4P HDMI_TX0+_CONN 1 2
R502 HDMI@ 499_0402_1% 2N7002KDWH_SOT363-6
@ L35 HDMI_TX0-_CONN 1 2 Q86A
HDMI_TX0P 1 2 HDMI_TX0+_CONN R503 HDMI@ 499_0402_1% HDMI@
1 2 HDMI_TX1+_CONN 1 2
R505 HDMI@ 499_0402_1%
5
HDMI_TX0N 4 3 HDMI_TX0-_CONN HDMI_TX1-_CONN 1 2
4 3 R506 HDMI@ 499_0402_1%
WCM-2012-900T_4P HDMI_TX2+_CONN 1 2 4 3 HDMIDAT_R
(5) HDMI_DATA
R508 HDMI@ 499_0402_1%
m
@ L36 HDMI_TX2-_CONN 1 2 2N7002KDWH_SOT363-6
HDMI_TX1P 1 2 HDMI_TX1+_CONN R509 HDMI@ 499_0402_1% Q86B
1 2 HDMI@
1
C HDMI_TX1N HDMI_TX1-_CONN D 0_0402_5% C
4 4 3 3
+5VS 2 Q87 1 @ 2
WCM-2012-900T_4P G 2N7002H_SOT23-3 R815
1
S HDMI@
3
@ L37 @ 1 @ 2 0_0402_5%
ru
HDMI_TX2P 1 2 HDMI_TX2+_CONN R512 R816
1 2 100K_0402_5%
NEAR CONNECT
2
HDMI_TX2N 4 3 HDMI_TX2-_CONN
4 3
WCM-2012-900T_4P
@ R521
Fo
0_0805_5%
D7
Add fuse for safety requirement
20100923 +5VS_HDMI_F 1 2 +5VS
RB491D_SC59-3
2
HDMI@ HDMI@
F2
1.1A_6V_SMD1812P110TF
1
+5VS_HDMI
er 1 C690
0.1U_0402_16V4Z
2
HDMI@
B HDMI@ HDMI@ B
R522 R523 2
R524 2K_0402_5% 2K_0402_5%
1 2
1
+5VS
0_0402_5% AMD check list update
20101110
yb
HDMI@ 3
+3VS 1 HDMI_HPD JHDMI1
HDMI_HPD 19
@ HP_DET
2 18
D8 +5V
17
BAT54S-7-F_SOT23-3 HDMIDAT_R DDC/CEC_GND
16
SDA
1
C R525 HDMICLK_R 15
@ Q88 HDMI_HPD SCL
2 1 2 14
Reserved
MMBT3904_NL_SOT23-3 B 150K_0402_5% 13
E @ HDMI_CLK-_CONN CEC
12 20
3
CK- G1
2
(5) HDMI_DET 11 21
CK_shield G2
C
@ @ HDMI_CLK+_CONN 10 22
CK+ G3
1
HDMI_TX1+_CONN D1_shield
4
HDMI_TX2-_CONN D1+
3
D2-
2
HDMI_TX2+_CONN D2_shield
1
D2+
SUYIN_100042GR019M23DZL
ME@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 11 of 48
5 4 3 2 1
A B C D E
FCM1608CF-121T03 0603
1 DAC_RED 1 2 RED 1
(5) DAC_RED
L38
FCM1608CF-121T03 0603
DAC_GRN 1 2 GREEN
(5) DAC_GRN
L39
FCM1608CF-121T03 0603
DAC_BLU 1 2 BLUE
(5) DAC_BLU
L40
1
1 1 1 1 1 1
R531 R532 R533 C692 C693 C694 C697 C695 C696 +5VS +5VS +5VS
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J
2 2 2 2 2 2
3 3 3
2
.ru
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J 1 BLUE 1 GREEN 1 RED
CLOSE TO CONN
2 2 2 BAT54S-7-F_SOT23-3
@ @ @
D9 D10 D11
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
+CRT_VCC
R537
+5VS +5VS
1 2
m
1
1K_0402_5% 3 3
C699
0.1U_0402_16V4Z 1 JVGA_HS 1 JVGA_VS
2 2 2
5
2 2
@ @
OE#
P
ru
G
@
C700
10P_0402_50V8J
+CRT_VCC 2
R543
1 2
1
Fo
C701 1K_0402_5%
0.1U_0402_16V4Z
2
5
1
OE#
P
2 4 CRT_VSYNC_1 1 2 JVGA_VS
(5) CRT_VSYNC A Y L42
G
@ C702 +CRT_VCC
10P_0402_50V8J +5VS
3
+3VS +3VS +CRT_VCC
er 2
2
D14
RB491D_SC59-3
1 1
F1
2
1.1A_6V_SMD1812P110TF
W=40mils
1
2
C691
0.1U_0402_16V4Z
3
1
yb
R546 R547 R548 R549
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
JCRT1
2
6
Change footprint 11
5
20100812 RED 1
7
(5) CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN CRT_DDC_DAT_CONN 12
GREEN 2
C
2N7002KDW H_SOT363-6 8 G 16
Q89B JVGA_HS 13 17
BLUE G
3
9
2
JVGA_VS 14
4
(5) CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN 10
CRT_DDC_CLK_CONN 15
2N7002KDW H_SOT363-6 1 1 5
Q89A @ @ 1
C703 C704 C698 CONTE_80431-5K1-152
100P_0402_50V8J 68P_0402_50V8K
2 2 100P_0402_50V8J
4 2 ME@ 4
1 @ 2
R964 0_0402_5%
1 @ 2
R965 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 12 of 48
A B C D E
A B C D E
@ +3VALW
C705
Watchdog timer on NB_PWRGD
2 1 enable for pull-up
update for PX function T78 disable for pull-down
+3VS
5
0.1U_0402_16V4Z @ U25
20100811
10K_0402_5%
SB_ARST#_GATE 2 PAD 20100527 @
P
B 150P_0402_50V8J
Y 4 PX_RST# (18)
R554
PLT_RST# 1 C706 1 2 U26E
A
G
P1 W2 PAD T96
PCIE_RST_L PCICLK0
1
PCI CLKS
PLT_RST# R557 2 1 33_0402_5% A_RST# L1 W1
2
A_RST_L PCICLK1/GPO36 PCI_CLK2 PCI_CLK1 (17)
R555 W3
100K_0402_5% NC7SZ08P5X_NL_SC70-5 C707 0.1U_0402_16V7K UMI_RX0P_C PCICLK2/GPO37
(6) UMI_RX0P 1 2 AD26 W4 PCI_CLK3 (17)
UMI_TX0P PCICLK3/GPO38
10K_0402_5%
C708 1 2 0.1U_0402_16V7K UMI_RX0N_C AD27 Y1
(6) UMI_RX0N UMI_RX1P_C UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 (17)
C709 1 2 0.1U_0402_16V7K AC28
2
R558
1 PX@ 2 C710 1 2 0.1U_0402_16V7K UMI_RX1N_C AC29 V2
1 (6) UMI_RX1N UMI_RX2P_C UMI_TX1N PCIRST_L 1
R559 0_0603_5% C711 1 2 0.1U_0402_16V7K AB29 PAD T92
(6) UMI_RX2P UMI_RX2N_C UMI_TX2P
C712 1 2 0.1U_0402_16V7K AB28
2
PLT_RST# (26,30,31) (6) UMI_RX2N UMI_RX3P_C UMI_TX2N
C713 1 2 0.1U_0402_16V7K AB26 AA1
(6) UMI_RX3P UMI_TX3P AD0/GPIO0
update for PX function C714 1 2 0.1U_0402_16V7K UMI_RX3N_C AB27 AA4
(6) UMI_RX3N UMI_TX3N AD1/GPIO1
.ru
R561 2K_0402_1% PCIE_CALRP AD12/GPIO12
+PCIE_VDDAN 2 1 AD28 PCIE_CALRN AD13/GPIO13 AD1
AD2 PE_GPIO0 R918 1 PX@ 2 100K_0402_5%
C715 0.1U_0402_16V7K PCIE_FTX_DRX_P0 AD14/GPIO14
LAN (26) PCIE_FTX_C_DRX_P0
C716
1
1
2
2 0.1U_0402_16V7K PCIE_FTX_DRX_N0
AA28
AA29
GPP_TX0P AD15/GPIO15 AC6
AE2
(26) PCIE_FTX_C_DRX_N0 PCIE_FTX_DRX_P1 GPP_TX0N AD16/GPIO16 20101012
WLAN C717 1 2 0.1U_0402_16V7K Y29 AE1
(30) PCIE_FTX_C_DRX_P1 PCIE_FTX_DRX_N1 GPP_TX1P AD17/GPIO17
C718 1 2 0.1U_0402_16V7K Y28 AF8
(30) PCIE_FTX_C_DRX_N1 GPP_TX1N AD18/GPIO18
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 GPP_TX3P AD21/GPIO21 AG1 PE_GPIO0 (18) Close to SB
W29 GPP_TX3N AD22/GPIO22 AF2
AD23/GPIO23 AE9 PCI_AD23 (17)
AA22 AD9 @ R562 20M_0402_5%
@R562
(26) PCIE_FRX_DTX_P0 GPP_RX0P AD24/GPIO24 PCI_AD24 (17)
PCI I/F
(26) PCIE_FRX_DTX_N0 Y21 AC11 PCI_AD25 (17) 1 2
m
GPP_RX0N AD25/GPIO25
(30) PCIE_FRX_DTX_P1 AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 (17)
AA24 AF4 Change from 22P to 18P for RTC correction
(30) PCIE_FRX_DTX_N1 GPP_RX1N AD27/GPIO27 PCI_AD27 (17) 20101012
W23 AF3 C719
GPP_RX2P AD28/GPIO28 RTC_32KHO
V24 GPP_RX2N AD29/GPIO29 AH2 1 2
2 2
W24 GPP_RX3P AD30/GPIO30 AG2 Y4
W25 AH3 18P_0402_50V8J
GPP_RX3N AD31/GPIO31
1
CBE0_L AA8 4 OSC NC 3
AD5 R563
CBE1_L 20M_0603_5%
CBE2_L AD8 1 OSC NC 2
ru
CBE3_L AA10
AE8 32.768KHZ_12.5PF_9H03200413
2
FRAME_L C720
AB9
DEVSEL_L RTC_32KHI
close to FCH within 1" M23
PCIE_RCLKP/NB_LNK_CLKP IRDY_L
AJ3 1 2
P23 AE7
PCIE_RCLKN/NB_LNK_CLKN TRDY_L 18P_0402_50V8J
AC5
R564 1 DISP_CLK_R PAR
(5) DISP_CLK 2 0_0402_5% U29 AF5
R565 1 DISP_CLK#_R NB_DISP_CLKP STOP_L
(5) DISP_CLK# 2 0_0402_5% U28
NB_DISP_CLKN PERR_L
AE6
AE4
SERR_L
T26 AE11
NB_HT_CLKP REQ0_L +1.8VS +3VS
Fo
T27 AH5
NB_HT_CLKN REQ1_L/GPIO40
AH4
REQ2_L/CLK_REQ8_L/GPIO41
1
R566 1 2 0_0402_5% APU_CLK_R V21 AC12
(5) APU_CLK CPU_HT_CLKP REQ3_L/CLK_REQ5_L/GPIO42
R567 1 2 0_0402_5% APU_CLK#_R T21 AD12 R568
(5) APU_CLK# CPU_HT_CLKN GNT0_L
AJ5 10K_0402_5%
R569 1 CLK_PCIE_VGA_R GNT1_L/GPO44
(18) CLK_PCIE_VGA 2 0_0402_5% V23
SLT_GFX_CLKP GNT2_L/GPO45
AH6 PE_GPIO1 (20,21,43)
2
G
R570 1 2 0_0402_5% CLK_PCIE_VGA#_R T23 AB12
2
(18) CLK_PCIE_VGA# SLT_GFX_CLKN GNT3_L/CLK_REQ7_L/GPIO46
AB11
R571 1 CLK_PCIE_LAN_R CLKRUN_L APU_PWRGD
(26) CLK_PCIE_LAN 2 0_0402_5% L29 AD7 3 1 H_PWRGD_L (44)
CLK_PCIE_LAN#_R GPP_CLK0P LOCK_L
D
R572 1 2 0_0402_5%
LAN (26) CLK_PCIE_LAN# L28
GPP_CLK0N
CLOCK GENERATOR
AJ6 SB_ARST#_GATE
R573 1 CLK_PCIE_WLAN_R INTE_L/GPIO32
(30) CLK_PCIE_WLAN 2 0_0402_5% N29 AG6 FDV301N_NL_SOT23-3
R574 1 CLK_PCIE_WLAN#_R GPP_CLK1P INTF_L/GPIO33 For PX function reserved
WLAN (30) CLK_PCIE_WLAN# 2 0_0402_5% N28
GPP_CLK1N INTG_L/GPIO34
AG4 Q90
3
er M29
M28
T25
V25
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
INTH_L/GPIO35
LPCCLK0
AJ4
H24
R853 1
R575 1
CLK_PCI_DB_R (17)
2 0_0402_5%
2 22_0402_5%
LPCCLK0 (17)
LPC_CLK0_EC (31)
1
2
@
C1011
100P_0402_50V8J 3
LPC
H25 R854 1 @ 2 0_0402_5%
LPCCLK1 CLK_PCI_DB (30)
L24 J27 LPC_AD0 (30,31)
GPP_CLK4P LAD0 Reserve for EMI for PVT build
L23 J26 LPC_AD1 (30,31)
GPP_CLK4N LAD1 20101005
H29 LPC_AD2 (30,31)
LAD2
yb
P25 H28 LPC_AD3 (30,31)
GPP_CLK5P LAD3
M25 G28 LPC_FRAME# (30,31)
GPP_CLK5N LFRAME_L
J25
LDRQ0_L
P29 AA18
GPP_CLK6P LDRQ1_L/CLK_REQ6_L/GPIO49
P28 AB19 SERIRQ (31)
GPP_CLK6N SERIRQ/GPIO48
N26
GPP_CLK7P
N27
GPP_CLK7N
G21 ALLOW_STOP# (5)
ALLOW_LDTSTP/DMA_ACTIVE_L
CPU
T29 H21 FCH_PROCHOT# (5)
GPP_CLK8P PROCHOT_L
T28 K19 APU_PWRGD (5)
GPP_CLK8N LDT_PG
G22
LDT_STP_L
C
C721 D2
RTCCLK SUSCLK (31)
22P_0402_50V8J 1M_0603_5% B2 +RTCBATT
Y5 R576 25M_CLK_X2 INTRUDER_ALERT_L W=20mils
L27 B1 1 2
C722 25M_X2 VDDBT_RTC_G R577 510_0402_5%
2
1U_0402_6.3V4Z
22P_0402_50V8J 21807-A11-HUDSON-M1_FCBGA605 1
1
1 2
25MHZ_20PF_7A25000012 C723 CLRP1 @
4 SHORT PADS 4
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 13 of 48
A B C D E
A B C D E
+3VALW
1 2 USB_OC2# 1 2 USB_OC7#
R870 10K_0402_5% R929 10K_0402_5% U26A
1 2 USB_OC1# 1 @ 2 EC_LID_OUT#
USB MISC
R871 10K_0402_5% R930 10K_0402_5%
1 2 USB_OC0# 1 2 USB_OC5# J2 A10
(31) PCI_PME# PCI_PME_L/GEVENT4_L USBCLK/14M_25M_48M_OSC
ACPI/WAKE UP EVENTS
R872 10K_0402_5% R931 10K_0402_5% K1 R578
FCH_SIC ODD_DA#_FCH (46) Kill_SW# RI_L/GEVENT22_L USB_RCOMP 1
1 2 1 2 D3 G19 2
R603 10K_0402_5% R932 10K_0402_5% 20100810 SPI_CS3_L/GBE_STAT1/GEVENT21_L USB_RCOMP 11.8K_0402_1%
(31) SLP_S3# F1 SLP_S3_L
1 2 FCH_SID 1 2 ODD_DETECT# H1
(31) SLP_S5# SLP_S5_L
R604 10K_0402_5% R933 10K_0402_5% F2 10mils and <1"
FCH_PCIE_WAKE# (31) PBTN_OUT# FCH_PWRGD H5 PWR_BTN_L
1 2
PWR_GOOD
USB 1.1
R605 10K_0402_5% G6 J10
1 +3VS SUS_STAT_L USB_FSD1P/GPIO186 1
T82PAD B3 H11
TEST0 USB_FSD1N
T83PAD C4
TEST1/TMS
T84PAD F6 H9
TEST2 USB_FSD0P/GPIO185
(31) GATEA20 AD21 J8
LAN_CLKREQ# GA20IN/GEVENT0_L USB_FSD0N
1 2 (31) KB_RST# AE21
R817 10K_0402_5% KBRST_L/GEVENT1_L
(31) EC_SCI# K2 B12
WLAN_CLKREQ# LPC_PME_L/GEVENT3_L USB_HSD13P
1 2 (31) EC_SMI# J29 A12
R818 10K_0402_5% LPC_SMI_L/GEVENT23_L USB_HSD13N
H2
NB_PWRGD R579 1 @ GEVENT5_L
1 2 +3VALW 2 10K_0402_5% J1
SYS_RESET_L/GEVENT19_L USB_HSD12P
F11
R597 4.7K_0402_5% (26,30) FCH_PCIE_WAKE# H6 E11
FCH_SMCLK0 WAKE_L/GEVENT8_L USB_HSD12N
1 2 F3
R598 2.2K_0402_5%
(5) H_THERMTRIP# J6
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L USB_HSD11P E14 Root
1 2 FCH_SMDAT0 NB_PWRGD AC19 E12
R599 2.2K_0402_5% NB_PWRGD USB_HSD11N
G1 J12
.ru
(31) EC_RSMRST# RSMRST_L USB_HSD10P
USB_HSD10N J14
AD19 CLK_REQ4_L/SATA_IS0_L/GPIO64
20100802 AA16 A13
CLK_REQ3_L/SATA_IS1_L/GPIO63 USB_HSD9P
(33) SATA_DET# AB21 SMARTVOLT1/SATA_IS2_L/GPIO50 USB_HSD9N B13
R580 2 @ 1 0_0402_5% AC18
(26) LAN_CLKREQ# CLK_REQ0_L/SATA_IS3_L/GPIO60
AF20 SATA_IS4_L/FANOUT3/GPIO55 USB_HSD8P D13
R581 2 1 0_0402_5% AE19 C13
SATA_IS5_L/FANIN3/GPIO59 USB_HSD8N
(28) FCH_SPKR AF19 SPKR_GPIO66
GPIO
USB 2.0
AD22 G12
+3VS @ (8,9,30) FCH_SMCLK0
(8,9,30) FCH_SMDAT0 AE22
SCL0_GPIO43
SDA0_GPIO47
USB_HSD7P
USB_HSD7N G14
USB20_P7 (30)
USB20_N7 (30)
WLAN Root
C724 0.1U_0402_16V7K FCH_SMCLK1 F5
FCH_SMDAT1 SCL1_GPIO227
1 2 F4 G16
AH21
SDA1_GPIO228 USB_HSD6P
G18
USB20_P6 (34)
USB20_N6 (34)
CR
m
CLK_REQ2_L/FANIN4_GPIO62 USB_HSD6N
5
2 2
1 2 D5 GBE_LED0/GPIO183 USB_HSD4P B14 USB20_P4 (34)
@ @ NC7SZ08P5X_NL_SC70-5 D7 A14
RP
3
ru
C1009 @ 0_0402_5%
100P_0402_50V8J J16
USB_HSD2P USB20_P2 (33)
Reserve for EMI for PVT build 2 USB_OC7# H3
BLINK/USB_OC7_L/GEVENT18_L USB_HSD2N
J18 USB20_N2 (33) COMBO Root
USB OC
20101005 D1
Reserve for EMI for PVT build (31) EC_LID_OUT# USB_OC5# USB_OC6_L/IR_TX1/GEVENT6_L
E4 B17
20101005
(46) ODD_DA#_FCH D4
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_HSD1P
USB_HSD1N
A17
USB20_P1 (10)
USB20_N1 (10)
CMOS
(46) ODD_DETECT# E8
@ PEG_CLKREQ#_R USB_OC3_L/AC_PRES/TDO/GEVENT15_L
1 2 F7 A16
R823 10K_0402_5%
(34) USB_OC2#
(33) USB_OC1# E7
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_HSD0P
USB_HSD0N
B16
USB20_P0 (33)
USB20_N0 (33)
LP1
1 2 FCH_SMCLK1 F8
(33) USB_OC0# USB_OC0_L/TRST_L/GEVENT12_L
Fo
R587 10K_0402_5%
1 2 FCH_SMDAT1
R588 10K_0402_5%
HD AUDIO
1 2 EC_RSMRST# R583 1 2 33_0402_5% HDA_BITCLK M3 D25 GPIO193 R584 2 1 10K_0402_5%
(28) HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK SCL2/GPIO193 GPIO194
R606 2.2K_0402_5% R585 1 2 33_0402_5% N1 F23 R586 2 1 10K_0402_5%
HDA_BITCLK (28) HDA_SDOUT_AUDIO HDA_SDIN0 AZ_SDOUT SDA2/GPIO194
1 @ 2 L2 B26
(28) HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 FCH_SIC (5)
R607 10K_0402_5% M2 E26
AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 FCH_SID (5)
1 @ 2 HDA_SDIN0 M1 F25
R608 10K_0402_5% AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
M4 E22
HDA_SDOUT AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
1 2 (28) HDA_SYNC_AUDIO
R589 1 2 33_0402_5% HDA_SYNC N2 F22 EC_PWM2
AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
R609 10K_0402_5%
(28) HDA_RST_AUDIO#
R590 1 2 33_0402_5% HDA_RST# P2 E21 EC_PWM3 Internal Pull-Up available
AZ_RST_L EC_PWM3/EC_TIMER3/GPIO200
Pull-down for enable high performance mode
20100527 (required for M1) G24
KSI_0/GPIO201
R5911
R5921 er 2 10K_0402_5%
2 10K_0402_5%
T1
T4
GBE_COL
GBE_CRS
KSI_1/GPIO202
KSI_2/GPIO203
G25
E28 +3VALW
EMBEDDED CTRL
L6 E29
R593 GBE_MDCK KSI_3/GPIO204
+3VALW 1 2 10K_0402_5% L5 D29
3 GBE_MDIO KSI_4/GPIO205 3
T9 D28
GBE_RXCLK KSI_5/GPIO206
2
10K_0402_5%
10K_0402_5%
+3VALW +3VALW +3VALW
GBE LAN
U1 C29
GBE_RXD3 KSI_6/GPIO207
U3 C28
GBE_RXD2 KSI_7/GPIO208
R594
R595
T2
GBE_RXD1
U2 B28
GBE_RXD0 KSO_0/GPIO209
1
PX@ 1
2 BACO@ 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
nonHDMI@
T5 A27 @ @
1
GBE_RXCTL/RXDV KSO_1/GPIO210
yb
R596 1 2 10K_0402_5% V5 B27
GBE_RXERR KSO_2/GPIO211
R912
R911
R910
P5 D26
GBE_TXCLK KSO_3/GPIO212 EC_PWM3
M5 A26
GBE_TXD3 KSO_4/GPIO213 EC_PWM2
P9 C26
2
GBE_TXD2 KSO_5/GPIO214
T7 A24
GBE_TXD1 KSO_6/GPIO215
P7 B25
GBE_TXD0 KSO_7/GPIO216
2.2K_0402_5%
2.2K_0402_5%
GPIO189 R913 M7 A25
GBE_TXCTL/TXEN KSO_8/GPIO217
1
GPIO190 P4 D24
GBE_PHY_PD KSO_9/GPIO218
R601
R602
GPIO191 M9 B24
R600 GBE_PHY_RST_L KSO_10/GPIO219
1 2 10K_0402_5% V7 C24
GBE_PHY_INTR KSO_11/GPIO220 @
B23
KSO_12/GPIO221
2 HDMI@ 1
2 UMA@ 1
2 UMA@ 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
C
R914
R913
F21 C22
SPI_CS2_L/GBE_STAT2/GPIO166 KSO_15/GPIO224
SD028000080 G29
FC_RST_L/GPO160 KSO_16/GPIO225
A22
B22
PX3@ GPIO189 KSO_17/GPIO226
D27
GPIO190 PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
GPIO191 F29
PS2M_DAT/GPIO191
EC_PWM3 EC_PWM2 ROM TYPE
E27
PS2M_CLK/GPIO192
BOARD For BRD Config.
Config. GPIO189 GPIO190 GPIO191 Function 21807-A11-HUDSON-M1_FCBGA605 x 0 SPI ROM *
0 0 0 UMA x x Reserved
4 4
1 0 0 DIS 0 0 Reserved
0 x LPC ROM
0 1 0 PX3
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 0 PX4 Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH HDA/USB/ACPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
x x 1 w/o HDMI Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 14 of 48
A B C D E
A B C D E
1 1
.ru
U26B
C726 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AH9 AH28
(29) SATA_ITX_DRX_P0 SATA_ITX_C_DRX_N0 AJ9 SATA_TX0P FC_CLK
C727 1 2 0.01U_0402_16V7K AG28
(29) SATA_ITX_DRX_N0 SATA_TX0N FC_FBCLKOUT
HDD FC_FBCLKIN AF26
(29) SATA_DTX_C_IRX_N0 AJ8 SATA_RX0N
(29) SATA_DTX_C_IRX_P0 AH8 SATA_RX0P FC_OE_L/GPIOD145 AF28
FC_AVD_L/GPIOD146 AG29
C728 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1 AH10 AG26
(46) SATA_ITX_DRX_P1 SATA_ITX_C_DRX_N1 AJ10 SATA_TX1P FC_WE_L/GPIOD148
C729 1 2 0.01U_0402_16V7K AF27
(46) SATA_ITX_DRX_N1 SATA_TX1N FC_CE1_L/GPIOD149
ODD FC_CE2_L/GPIOD150 AE29
(46) SATA_DTX_C_IRX_N1 AG10 SATA_RX1N FC_INT1/GPIOD144 AF29
(46) SATA_DTX_C_IRX_P1 AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
GPIOD
ESATA@
m
C730 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P2 AG12 AJ27
(33) SATA_ITX_DRX_P2 SATA_ITX_C_DRX_N2 AF12 SATA_TX2P FC_ADQ0/GPIOD128
C731 1 2 0.01U_0402_16V7K AJ26
(33) SATA_ITX_DRX_N2 SATA_TX2N FC_ADQ1/GPIOD129
eSATA FC_ADQ2/GPIOD130 AH25
(33) SATA_DTX_C_IRX_N2 ESATA@ AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
SERIAL ATA
2 2
(33) SATA_DTX_C_IRX_P2 AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
ru
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23
AF23
FC_ADQ11/GPIOD139
AG17 AJ24
SATA_TX4P FC_ADQ12/GPIOD140
AF17 AJ25
SATA_TX4N FC_ADQ13/GPIOD141
AG25
FC_ADQ14/GPIOD142
AJ17 AH26
SATA_RX4N FC_ADQ15/GPIOD143
AH17
SATA_RX4P
AJ18
SATA_TX5P
HW MONITOR
Fo
AH18 W5
SATA_TX5N FANOUT0/GPIO52
W6 ODD_EN (29)
FANOUT1/GPIO53
AH19 Y9 BT_OFF# (33)
SATA_RX5N FANOUT2/GPIO54
AJ19
SATA_RX5P
10 mils and < 1" FANIN0/GPIO56
W7
V9 WL_OFF# (30)
R610 SATA_CALRP FANIN1/GPIO57
1 2 1K_0402_1% AB14
SATA_CALRP FANIN2/GPIO58
W8
+1.1VS R611 1 2 931_0402_1% SATA_CALRN AA14
SATA_CALRN TEMPIN0 R612 2 10K_0402_5%
B6 1
TEMPIN0/GPIO171 TEMPIN1 R613 2 10K_0402_5%
A6 1
TEMPIN1/GPIO172 TEMPIN2 R614 2 10K_0402_5%
(46) HDD_LED# AD11 A5 1
SATA_ACT_L/GPIO67 TEMPIN2/GPIO173 R615 2 10K_0402_5%
B5 1
R616 1 TEMPIN3/TALERT_L/GPIO174
+3VS 2 10K_0402_5% TEMP_COMM
C7
APU_ALERT#_FCH (5)
1 2 25M_SATA_X1 AD16
SATA_X1
er VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
A3
B4
A4
GPIO175
GPIO176
GPIO177
R617
R618
R619
2
2
2
1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
3 GPIO178 3
@ C980 @ VIN3/GPIO178
C5 R620 2 1 10K_0402_5%
22P_0402_50V8J 1M_0603_5% A7 GPIO179 R621 2 1 10K_0402_5% VIN6/GBE_STAT3/GPIO181
Y7 R861 VIN4/GPIO179 GPIO180 R622 10K_0402_5%
B7 2 1 Enable integrated pull-down/up and leave unconnected
VIN5/GPIO180 GPIO181
@ C981 @ B8 R623 2 @ 1 10K_0402_5%
2
SPI_SO_R J5 G27
SPI_SI_R SPI_DI/GPIO164 NC1
E2 Y2
SPI_CLK_FCH_R SPI_DO/GPIO163 NC2
K4
SPI_SB_CS0#_R SPI_CLK/GPIO162
K9
GPIO161 SPI_CS1_L/GPIO165
T87 PAD G2
ROM_RST_L/GPIO161
21807-A11-HUDSON-M1_FCBGA605
+3VS
R625
33_0402_5%
@
R626 1 2 SPI_WP#
2
3.3K_0402_5%
4 R627 1 2 SPI_HOLD# +3VS C732 4
3.3K_0402_5% 22P_0402_50V8J
C733 @
1 2
R628
0_0402_5% U28 0.1U_0402_16V4Z
SPI_SB_CS0#_R 1 2 SPI_SB_CS0#1 8
SPI_SO_R SPI_SO_L CS# VCC SPI_HOLD# 0_0402_5% R631
1 2
SPI_WP#
2
3
SO
WP#
HOLD#
SCLK
7
6 SPI_CLK_FCH 1 2 SPI_CLK_FCH_R
Security Classification Compal Secret Data Compal Electronics, Inc.
33_0402_5% 4 5 SPI_SI 1 2 SPI_SI_R 2010/06/30 2012/06/30 Title
R629 GND SI Issued Date Deciphered Date
MX25L1605AM2C-12G_SO8 33_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-SATA/SPI
SA00003FO00 R630 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
SA00002KI00 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 15 of 48
A B C D E
A B C D E
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 +1.1VS +1.1VS
CORE S0
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 2 2 2 V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 1 1 1 1 1
PCI/GPIO I/O
C1006
C1007
C735
C736
C737
C738
C747
C739
C740
C748
Y19 VDDIO_33_PCIGP_3 VDDCR_11_3 N17
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13
AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17
2 2 1 1 1 2 2 2 2 2
330U_D2_2.5VY_R9M
AA2 VDDIO_33_PCIGP_6 VDDCR_11_6 V12
10U_0603_6.3V6M
AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 1
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 1
C741
C742
AA7 W18 Change from SM010014520 to SD002000080 +
VDDIO_33_PCIGP_9 VDDCR_11_9 20101012
AA9
VDDIO_33_PCIGP_10
GPIO I/F implemented: tied to +1.8V_S0 AF7
VDDIO_33_PCIGP_11
382.9mA L43
2 2
CLKGEN I/O
1 GPIO I/F not implemented: tied to +VDDAN_11_CLK 1
AA19 K28 2 1 +1.1VS
+1.8VS VDDIO_33_PCIGP_12 VDDAN_11_CLK_1
22U_0805_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
R632 +1.8V_S0 or 0 ohm to ground K29 1 1 1 1 1
VDDAN_11_CLK_2
C749
C750
C751
C752
C743
1 2 +VDDIO_18_FC J28 FBMA-L11-201209-221LMA30T_0805
VDDAN_11_CLK_3
0_0603_5% 0.16mA VDDAN_11_CLK_4
K26
1
0_0402_5%
FLASH I/O
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
2 2 2 J21
VDDAN_11_CLK_5 2 2 2 2 2
R633
C744
C745
C746
AF22 J20
VDDIO_18_FC_1 VDDAN_11_CLK_6
AE25 K21
VDDIO_18_FC_2 VDDAN_11_CLK_7
AF24 J22
@ 1 1 1 VDDIO_18_FC_3 VDDAN_11_CLK_8
AC22
2
VDDIO_18_FC_4
V1
VDDRF_GBE_S
22.5mA VDDIO_33_GBE_S M10
2.2U_0603_6.3V6K
L44
PCI EXPRESS
+3VS 2 1 +VDDPL33_PCIE AE28
.ru
FBMA-L11-160808-221LMT_2P VDDPL_33_PCIE
1
GBE LAN
C753
1115.6mA
Change from SM010014520 to SD002000080 U26 L7
20101012 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1
V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9
2
V26 VDDAN_11_PCIE_3
+1.1VS L45 +PCIE_VDDAN V27 VDDAN_11_PCIE_4
22U_0805_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
2 1 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6
1U_0402_6.3V6K
FBMA-L11-201209-221LMA30T_0805 V29 P8
VDDAN_11_PCIE_6 VDDIO_GBE_S_2
1 1 2 2 W22 VDDAN_11_PCIE_7
C754
C755
C756
C757
W26 VDDAN_11_PCIE_8
15.5mA
2 2 1 1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
m
SERIAL ATA
3.3V_S5 I/O
+VDDPL_33_SATA AD14 49.5mA
VDDPL_33_SATA
VDDIO_33_S_1 A21 +3VALW
+AVDD_SATA AJ20 D21 1 1
VDDAN_11_SATA_1 VDDIO_33_S_2
C758
C759
AF18 VDDAN_11_SATA_4 VDDIO_33_S_3 B21
2 1354.2mA 2
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10
2 2
AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9
AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6
AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8
ru 1U_0402_6.3V6K
1U_0402_6.3V6K
Change from SM010014520 to SD002000080
+1.1VALW
20101012 1 1
CORE S5
C760
C761
L46
VDDCR_11_S_1
F26 165.2mA
2 1 +AVDD_USB A18 G26
+3VALW VDDAN_33_USB_S_1 VDDCR_11_S_2
A19
VDDAN_33_USB_S_2
15.3mA
2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
USB I/O
10U_0603_6.3V6M
C762
C763
C764
C765
C766
0.1U_0402_16V7K
0.1U_0402_16V7K
B19 A11 L47
VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 +VDDCR_11_USB
B20 B11 2 1 +1.1VALW
VDDAN_33_USB_S_6 VDDCR_11_USB_S_2
Fo
C18 1 1 1 FBMA-L11-201209-221LMA30T_0805
2 2 2 2 2 VDDAN_33_USB_S_7
C767
C768
C769
C20
VDDAN_33_USB_S_8
46.5mA
D18 M21 +VDDPL33
VDDAN_33_USB_S_9 VDDPL_33_SYS
D19
VDDAN_33_USB_S_10
65.3mA 0_0805, no bead needed for this rail
2 2 2
PLL
D20 L22 +VDDPL11 2010/07/04
change from SM01000CB00 to SD013000080 VDDAN_33_USB_S_11 VDDPL_11_SYS_S
E19
VDDAN_33_USB_S_12
16.1mA
20101012 F19
VDDPL_33_USB_S +AVDD_USB
L48 11.4mA
0.1U_0402_16V7K
2.2U_0603_6.3V6K
2 1 +VDDAN_11_USB C11 D6
+1.1VALW VDDAN_11_USB_S_1 VDDAN_33_HWM_S +VDDAN33_HWM
D11 L49
FBMA-L11-160808-221LMT_2P VDDAN_11_USB_S_2 +VDDXL_33_S
1 2 L20 2 1 +3VS
VDDXL_33_S
C770
C771
2.2U_0603_6.3V6K
88.6mA 5mA 1
C772
21807-A11-HUDSON-M1_FCBGA605 FBMA-L11-160808-221LMT_2P
3
2 1 er 2
3
yb
Change from SM010014520 to SD002000080
20101012
+AVDD_SATA +VDDIO_AZ +3VALW
+VDDPL_33_SATA L50
22U_0805_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
L51 +1.1VS 2 1
1U_0402_6.3V6K
1U_0402_6.3V6K
+3VS 2 1 FBMA-L11-201209-221LMA30T_0805 1 2
FBMA-L11-160808-221LMT_2P 1 1 1 1 1 R634 0_0603_5%
C C773
C774
C778
C775
C776
1
C777 1 2 2.2U_0603_6.3V6K
2 2 2 2 2 C779
2.2U_0603_6.3V6K
2
HWM@
C780 1 2 2.2U_0603_6.3V6K
1 2
HWM@ C781
C782
4 4
L53
2 1
+VDDPL33
L55
+3VS 2 1
FBMA-L11-160808-221LMT_2P 0_0603_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
C783 1 2 2.2U_0603_6.3V6K SD013000080
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH PWR
nonHWM@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 16 of 48
A B C D E
5 4 3 2 1
U26D
Y14
Y16
VSSIO_SATA_1
VSSIO_SATA_2
VSS_1
VSS_2
AJ2
A28
REQUIRED STRAPS Check Internal PU/PD
AB16 VSSIO_SATA_3 VSS_3 A2
AC14 VSSIO_SATA_4 VSS_4 E5
AE12 VSSIO_SATA_5 VSS_5 D23 PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 CLK_PCI_DB
AE14 VSSIO_SATA_6 VSS_6 E25
AF9 VSSIO_SATA_7 VSS_7 E6
AF11 VSSIO_SATA_8 VSS_8 F24 PULL ALLOW PCIE USE Reserved internal EC Internal
AF13 N15 GEN2 DEBUG ENABLE CLKGEN
D
AF16
VSSIO_SATA_9 VSS_9
R13
HIGH D
VSSIO_SATA_10 VSS_10 STRAP Mode
AG8 VSSIO_SATA_11 VSS_11 R17
AH7 T10 DEFAULT
VSSIO_SATA_12 VSS_12 DEFAULT
AH11 VSSIO_SATA_13 VSS_13 P10
AH13 VSSIO_SATA_14 VSS_14 V11 IGNORE
AH16 VSSIO_SATA_15 VSS_15 U15 PULL FORCE PCIE DEBUG CLKGEN Mode internal EC External
AJ7 M18 GEN1 DISABLE CLKGEN
VSSIO_SATA_16 VSS_16 LOW STRAP
AJ11 VSSIO_SATA_17 VSS_17 V19 Internal Mode
AJ13 VSSIO_SATA_18 VSS_18 M11
AJ16 VSSIO_SATA_19 VSS_19 L12
GND
L18 DEFAULT DEFAULT DEFAULT
VSS_20
A9 VSSIO_USB_1 VSS_21 J7
B10 VSSIO_USB_2 VSS_22 P3
.ru
K11 VSSIO_USB_3 VSS_23 V4
B9 VSSIO_USB_4 VSS_24 AD6
D10 AD4 +3VS +3VS +3VS +3VALW +3VALW
VSSIO_USB_5 VSS_25
D12 VSSIO_USB_6 VSS_26 AB7
D14 VSSIO_USB_7 VSS_27 AC9
D17 VSSIO_USB_8 VSS_28 V8
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
E9 VSSIO_USB_9 VSS_29 W9
F9 VSSIO_USB_10 VSS_30 W10
R636
R637
R638
R639
R805
F12 VSSIO_USB_11 VSS_31 AJ28
F14 VSSIO_USB_12 VSS_32 B29
F16 U4 @ @ @
2
C VSSIO_USB_13 VSS_33 C
m
C9 VSSIO_USB_14 VSS_34 Y18
G11 VSSIO_USB_15 VSS_35 Y10
F18 VSSIO_USB_16 VSS_36 Y12
D9 VSSIO_USB_17 VSS_37 Y11
H12 VSSIO_USB_18 VSS_38 AA11 (13) PCI_CLK1
H14 VSSIO_USB_19 VSS_39 AA12 (13) PCI_CLK3
H16 VSSIO_USB_20 VSS_40 G4 (13) PCI_CLK4
H18 VSSIO_USB_21 VSS_41 J4 (13) LPCCLK0
ru
J11 VSSIO_USB_22 VSS_42 G8 (13) CLK_PCI_DB_R
J19 VSSIO_USB_23 VSS_43 G9
K12 VSSIO_USB_24 VSS_44 M12
K14 VSSIO_USB_25 VSS_45 AF25
K16 VSSIO_USB_26 VSS_46 H7
K18 VSSIO_USB_27 VSS_47 AH29
H19 VSSIO_USB_28 VSS_48 V10
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
VSS_49 P6
Fo
VSS_50 N4
R640
R641
R642
R643
R806
Y4 EFUSE VSS_51 L4
VSS_52 L8
D8 @ @
2
VSSAN_HWM
M19 VSSXL VSSPL_SYS M20
B B
P21 H23
P20
M22
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
H26
AA21
DEBUG STRAPS
M24
M26
P22
P24
P26
T20
T22
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
AA23
AB23
AD23
AA26
AC26
Y20
W21
er
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD27
USE internal
PLL generated
PCI_AD26
Disable I2C
PCI_AD23
Enable ROM Straps
Required Setting
(13)
(13)
PCI_AD27
PCI_AD26
T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20 PULL Disabled FC PLL ROM (13) PCI_AD25
PLL CLK
yb
V20 AE26
J23
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
L21
HIGH (13) PCI_AD24
VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 (13) PCI_AD23
K20 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
VSSIO_PCIECLK_27
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
21807-A11-HUDSON-M1_FCBGA605
R644
R645
R646
R647
R648
PULL BYPASS ILA FC PLL Getting Value
LOW PCI PLL AUTORUN bypassed from I2C EPROM Reserved
Enabled
2
C
@ @ @ @ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FCH-VSS/Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 17 of 48
5 4 3 2 1
5 4 3 2 1
TXOUT_U0P_DPF2P AL21
PCIE_CTX_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V7K 2 1 C276 PX@ PCIE_CRX_GTX_P2 AK20
PCIE_CTX_GRX_N2 PCIE_RX2P PCIE_TX2P TXOUT_U0N_DPF2N
AC31 PCIE_RX2N PCIE_TX2N AF26 PCIE_CRX_C_GTX_N2 0.1U_0402_10V7K 2 1 C277 PX@ PCIE_CRX_GTX_N2
TXOUT_U1P_DPF1P AH22
TXOUT_U1N_DPF1N AJ21
PCIE_CTX_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.1U_0402_10V7K 2 1 C278 PX@ PCIE_CRX_GTX_P3
PCIE_CTX_GRX_N3 PCIE_RX3P PCIE_TX3P
AB28 PCIE_RX3N PCIE_TX3N AD26 PCIE_CRX_C_GTX_N3 0.1U_0402_10V7K 2 1 C279 PX@ PCIE_CRX_GTX_N3
TXOUT_U2P_DPF0P AL23
TXOUT_U2N_DPF0N AK22
.ru
AB30 PCIE_RX4P PCIE_TX4P AC25 TXOUT_U3P AK24
AA31 PCIE_RX4N PCIE_TX4N AB25 TXOUT_U3N AJ23
m
W29 PCIE_RX7P PCIE_TX7P Y27 TXOUT_L1P_DPE1P AL17
V28 PCIE_RX7N PCIE_TX7N Y26 TXOUT_L1N_DPE1N AK16
TXOUT_L2P_DPE0P AH18
V30 PCIE_RX8P PCIE_TX8P W24 TXOUT_L2N_DPE0N AJ17
U31 PCIE_RX8N PCIE_TX8N W23
TXOUT_L3P AL19
ru
TXOUT_L3N AK18
U29 PCIE_RX9P PCIE_TX9P V27
T28 PCIE_RX9N PCIE_TX9N U26
LVDS
Fo
R29 PCIE_RX11P PCIE_TX11P T26
P28 PCIE_RX11N PCIE_TX11N T27
M30
L31
PCIE_RX14P
PCIE_RX14N
er
PCIE_TX14P
PCIE_TX14N
P24
P23 0.1U_0402_16V4Z
2
PX@
C1003
1
+3VGS
5
L29 M27 PX@ U48
PCIE_RX15P PCIE_TX15P
K30 N26 2
P
PCIE_RX15N PCIE_TX15N (13) PX_RST# B GPU_RST#
yb
Y 4
(13) PE_GPIO0 1 A
G
CLOCK
3
CLK_PCIE_VGA AK30
(13) CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32 NC7SZ08P5X_NL_SC70-5
(13) CLK_PCIE_VGA# PCIE_REFCLKN
20100728
R936 0_0402_5% CALIBRATION 1 @ 2
1 @ 2 Y22 1.27K_0402_1% 1 PX@ 2 R298 R956 0_0603_5%
(20,40,43) VGA_PWRGD PCIE_CALRP
C
2 R299 PX@
1 N10 PWRGOOD PCIE_CALRN AA22 2K_0402_5% 1 PX@ 2 R300 +1.0VGS update for PX function
A 10K_0402_5% A
20100811
GPU_RST# AL27 PERSTB
Security Classification Compal Secret Data Compal Electronics, Inc.
1
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1
1U_0402_6.3V4Z
0.1U_0402_10V6K
D DVDATA_6 TXCBM_DPB3N D
1 1 1 AB8
DVDATA_5
C304
C305
C306
AB7 AK6
DVDATA_4 TX3P_DPB2P RSVD GPIO8 RESERVED 0
AB4 AM5
DVDATA_3 TX3M_DPB2N
PX@
0.1U_0402_10V6K
1U_0402_6.3V4Z
TX0P_DPC2P
.ru
1 1 1 +DPC_VDD10 AA5 V2 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
DPC_VDD10#1 TX0M_DPC2N
C307
C308
C309
AA6
DPC_VDD10#2
Y4
TX1P_DPC1P
PX@
PX@
@
W5 RSVD H2SYNC 0
2 2 2 TX1M_DPC1N
U1 AA3
DPC_VSSR#1 TX2P_DPC0P RSVD GENERICC 0
W1 Y2
DPC_VSSR#2 TX2M_DPC0N
U3
DPC_VSSR#3 R305 1 PX@ AUD[1] AUD[0]
Y6 J8 2
DPC_VSSR#4 DPC_CALR 150_0402_1% AUD[1] HSYNC 11
AA1 0 0 No audio function
DPC_VSSR#5
0 1 Audio for DisplayPort and HDMI if dongle is detected
AUD[0] VSYNC 1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
+3VGS I2C
AMD RESERVED CONFIGURATION STRAPS
m
PX@ R306 1 2 4.7K_0402_5% VGA_SMB_CK2_R VGA_SMB_CK2_R R1 ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
PX@ R307 1 SCL
2 4.7K_0402_5% VGA_SMB_DA2_R VGA_SMB_DA2_R R3
SDA RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
PX@ R826 1 GENERAL PURPOSE I/O R
AM26 NOT CONFLICT DURING RESET If we meet some issue on bring up, we can check this item during reset.
C 2 10K_0402_5% VGA_ENBKL AK26 C
GPU_GPIO0 RB
U6
GPU_GPIO1 GPIO_0 GPIO21 H2SYNC GENERICC GPIO2 GPIO8
U10 AL25
GPU_GPIO2 GPIO_1 G +3VGS
T10 AJ25
GPIO_2 GB
U8
@ GPIO_3_SMBDATA
U7 AH24 For HDMI Audio strap
GPIO_4_SMBCLK B +AVDD +1.8VGS
ru
D3 1 2 GPU_GPIO5 T9 AG25
(31,38) ACIN
T8
GPIO_5_AC_BATT
GPIO_6
DAC1 BB
65mA PX@ L10 STRAPS +3VGS
RB751V_SOD323 VGA_ENBKL T7 AH26 R945 2 @ 1 10K_0402_5% 1 2
GPU_GPIO8 GPIO_7_BLON HSYNC R946 2 @ GPU_GPIO0
P10 AJ27 1 10K_0402_5% BLM15BD121SN1D_0402 R309 2 PX@ 1 10K_0402_5%
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
GPU_GPIO9 GPIO_8_ROMSO VSYNC GPU_GPIO1 R310
P4 1 1 1 2 PX@ 1 10K_0402_5%
GPIO_9_ROMSI GPU_GPIO2
C310
C311
C312
P2 R311 2 @ 1 10K_0402_5%
GPU_GPIO11 GPIO_10_ROMSCK R312 1 PX@
N6 AD22 2 499_0402_1% GPU_GPIO5 R308 2 @ 1 10K_0402_5%
GPIO_11 RSET
PX@
PX@
PX@
GPU_GPIO12 N5 20100728
GPU_GPIO13 GPIO_12 2 2 2 GPU_GPIO8 R313 @
N3 AG24 +AVDD 2 1 10K_0402_5%
GPIO_13 AVDD GPU_GPIO9 R314 @
Y9 AE22 2 1 10K_0402_5%
GPIO_14_HPD2 AVSSQ
(43) GPU_VID0 N1
T63 GPIO_15_PWRCNTL_0 GPU_GPIO11 R315
M4 AE23 +VDD1DI 2 PX@ 1 10K_0402_5%
Fo
THM_ALERT# GPIO_16_SSIN VDD1DI GPU_GPIO12 R316 @
R6 AD23 2 1 10K_0402_5%
GPIO_17_THERMAL_INT VSS1DI GPU_GPIO13 R317 @
W10 2 1 10K_0402_5%
R319 1 PX@ GPIO_18_HPD3 +VDD1DI +1.8VGS
2 10K_0402_5% M2
GPIO_19_CTF PX@ L11
(43) GPU_VID1 P8
GPIO_20_PWRCNTL_1 R2
AM12 110mA
P7 AK12 1 2
GPIO_21_BB_EN R2B BLM15BD121SN1D_0402
N8
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
GPIO_22_ROMCSB
(14) PEG_CLKREQ# N7 AL11 1 1 1
+3VGS GPIO_23_CLKREQB G2
C313
C314
C315
AJ11
GPIO24_TRSTB G2B
L6
JTAG_TRSTB
PX@
PX@
PX@
PX@ 1 R321 2 10K_0402_5% GPIO24_TRSTB GPIO25_TDI L5 AK10
PX@ R322 10K_0402_5% GPIO25_TDI GPIO26_TCK JTAG_TDI B2 2 2 2
1 2 L3 AL9
PX@ R323 10K_0402_5% GPIO27_TMS GPIO27_TMS JTAG_TCK B2B
1 2 L1
PX@ R324 10K_0402_5% GPIO26_TCK T64 GPIO28_TDO JTAG_TMS
1 2 K4
JTAG_TDO
R326 2 PX@ 1 10K_0402_5% TEST_EN K7 AH12
T65 TESTEN C +3VGS
AF24 AM10
TESTEN_LEGACY Y
AB13
W8
W9
GENERICA
GENERICB
er DAC2
COMP
H2SYNC
AJ9
AL13
AJ13
+VDD2DI
2mA PX@
1
L12
2
+1.8VGS
BLM15BD121SN1D_0402
Change footprint
20100812
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
2
B
R905 PX@ GENERICC V2SYNC B
W7 1 1 1
GENERICD
C316
C317
C318
1 2 AD10
4.7K_0402_5% GENERICE_HPD4 VGA_SMB_CK2_R
AD19 +VDD2DI 1 6 EC_SMB_CK2 (5,29,31)
VDD2DI
PX@
PX@
PX@
AC14 AC19
HPD1 VSS2DI 2 2 2 2N7002KDWH_SOT363-6
(20) PX_EN AB16
PX_EN
Q64A
+1.8VGS +DPLL_PVDD AE20 PX@
+A2VDD
yb
L14 PX@ A2VDD
75mA
2 1 0.60 V level, Please A2VDDQ
AE17 +A2VDDQ
5
BLM15BD121SN1D_0402
VREFG Divider ans
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
C324
C325
PX@
PX@
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 R2SET
2 PX@ 1 715_0402_1% 1 1 1 Q64B
C319
C320
C321
R331 249_0402_1% PX@
2 1
PX@
PX@
PX@
C322 0.1U_0402_10V6K DDC/AUX AE6
PX@ PLL/CLOCK DDC1CLK 2 2 2
AE5
DDC1DATA
+DPLL_PVDD AF14
+1.0VGS +DPLL_VDDC DPLL_PVDD
AE14 AD2
C
0.1U_0402_10V6K
1U_0402_6.3V4Z
C331
C332
PX@
PX@
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 XTALOUT AUX2N PX@
1 1 1 1
C326
C327
C328
PX@ 2 R332 1 0_0402_5% AC22 AD20
PX@ XO_IN DDCCLK_AUX3P
2 R333 1 0_0402_5% AB22 AC20 U9
XO_IN2 DDCDATA_AUX3N
PX@
PX@
PX@
1 8 VGA_SMB_CK2_R
2 2 2 VDD SCLK
AE16
DDCCLK_AUX5P GPU_THERMAL_D+ VGA_SMB_DA2_R
AD16 2 7
Chnge from SM010030010 to SD013000080 DDCDATA_AUX5N D+ SDATA
since EVT 20101012 AC1 PX@ 1 2 3 6
+1.8VGS +TSVDD GPU_THERMAL_D+ THERMAL DDC6CLK C333 D- ALERT#
T4 AC3
L17 PX@ GPU_THERMAL_D- DPLUS DDC6DATA 2200P_0402_50V7K THM_ALERT#
A 20mA T2
DMINUS GPU_THERMAL_D-
4
THERM# GND
5 A
2 1
BLM18AG121SN1D_0603 R334 2.61K_0402_5%
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
C335
C336
27MHZ_16PF_X5H027000FG1H PX@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
C337 C338 10K_0402_5%
18P_0402_50V8J 18P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 Main Generic/MSIC
PX@ PX@ SD028100280 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA6755P/7P 1.0
@ 20100722 for future ASIC MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 30, 2010 Sheet 19 of 48
5 4 3 2 1
5 4 3 2 1
1
10K_0402_5%
0.1U_0402_10V6K
(18,40,43) VGA_PWRGD
10K_0402_5%
C339 BACO@
BACO@
R340 R907
R338
BACO@
10K_0402_5% 10K_0402_5% 1
R339
@ BACO@
R906
2
PX_MODE_AND 1 2 2 VDDC_ON
0_0402_5% 2 1.0V_ON
2
@ C989
5
D
0.1U_0402_10V6K
1
Q68 1 D D
2 2
P
(19) PX_EN @ B
G 2N7002H_SOT23-3 4 2 Q66 2 Q67
BACO@ PX_MODE Y 2N7002H_SOT23-3 G 2N7002H_SOT23-3
.ru
S 1 G
3
NC7SZ08P5X_NL_SC70-5 A
G
S BACO@ S BACO@
3
PX_EN: High >>> BACO mode Change footprint BACO@ U10
3
Low >>> Normal Operation 20100812 update for BACO circuit Change footprint Change footprint
20100930 20100812 20100812
1
2 1 BACO@
C
@ C987 R903 C
m
0.1U_0402_10V6K 20K_0402_5%
1
P
RUNPWROK NC D29 BACO@
4
2
Y PE_GPIO1
A 2 2 1 PE_GPIO1 (13,21,43)
G
@ U46 1
update for BACO circuit SN74LVC1G07DCKR_SC70-5 RB751V_SOD323
3
20100930 C988
1 2 1U_0603_10V4Z Need to pop for BACO function
ru
R904 BACO@ 2 Should unpop for PX3.0
@ 20100728
0_0402_5%
+3VGS
@
C986 1 2 BOM structure update for BACO circuit
0.1U_0402_10V6K 20100928
5
Fo
Y 4 PX_MODE (21,43) 201009028
PX_MODE_AND 1
NC7SZ08P5X_NL_SC70-5 A
G
U44
3
BACO@
BACO@ BACO@
Q69 Q70
B 1 2 B
R888 BSS138_NL_SOT23-3 BSS138_NL_SOT23-3
0_0402_5% +1.0VGS +BIF_VDDC +VGA_CORE
D
@
S
3 1 1 3
er 1.0V_ON
BACO@
G
1 2 1 2
G
2
0.1U_0402_10V6K
R917 R342
BACO@ C343
BACO@ BACO@ 0_0402_5% 1 0_0402_5%
PX3@
Q71 Q72
BSS138_NL_SOT23-3 BSS138_NL_SOT23-3
+VGA_CORE 2
yb
S
S
3 1 1 3
VDDC_ON
G
2
2
Need to pop for BACO function
20100728 Should unpop for PX3.0
20100728
C
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 BACO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 20 of 48
5 4 3 2 1
5 4 3 2 1
1U_0603_10V4Z
10U_0805_10V4Z
PX@ U47
PX@
PX@
D For VGA power sequence 2MM J4 20100917 D
1
20100816 DMN3030LSS-13_SOP8L-8
1 1
1
R876 8 1
C982
C983
PX@ 3 1 470_0603_5% 7 2
1U_0603_10V4Z
1
10U_0805_10V4Z
PX@
PX@
R840 @ 6 3
1
51K_0402_5% Q65 2 2 C999 5 1 1
2
PX@ 10U_0805_10V4Z R877
2
2 PX@
C984
C985
PX@ AP2301GN-HF_SOT23-3 470_0603_5%
4
R857 @
1
Change footprint D 2 2
2
1
D 20K_0402_5% 20100812 +5VS
2
PE_GPIO1 2 Q121 1 G
G 2N7002H_SOT23-3 C351 S Q124
1
PX@ 0.1U_0603_25V7K 2N7002_SOT23 For VGA power sequence D @
S
.ru
3
PX@ @ R839 20100816 2 1 R879 2 PE_GPIO1#
Change footprint 2 20K_0402_5% G 0_0402_5%
20100812 @ PX@ PX@ For VGA PWR sequence S Q125
3
PE_GPIO1# 1 2 R856 20100928 2N7002_SOT23
Change footprint R878 0_0402_5% 1 2 @
20100812 39K_0402_5%
2
D
PE_GPIO1# 2 Q120 R944 1
G 2N7002H_SOT23-3 0_0402_5% C976
S PX@ @ 0.1U_0603_25V7K
3
PX@
1
Change footprint 2
m
20100812
20100728
C C
+1.5V +1.5VGS
J3
2 +1.8VS +1.8VGS
1 1
ru
2 @
@ JUMP_43X79 Change from SB00000GV00 to SB548000210 2 1
+1.5V TO +1.5VGS 20101125 +1.8VS TO +1.8VGS
Change footprint J5 Change from SB00000GV00 to SB548000210
2MM
20100812 20101125
PX@ U11 Change footprint
DMN3030LSS-13_SOP8L-8 PX@ U13 20100812
8 1 DMN3030LSS-13_SOP8L-8
1 7 2 1 1 8 1
Fo 1
6 3 C341 C342 1 7 2 1 1
1
C340 5 10U_0805_10V4Z 1U_0603_10V4Z R343 6 3
10U_0805_10V4Z PX@ PX@ 470_0603_5% C348 5 C349 C350
2 PX@ 2 2 @ 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R348
4
4
@
2
+VSB
20100728 +VSB
1
D For VGA power sequence
1
R344 2 1 R827 2 PX_MODE# 20100816
20K_0402_5% G 0_0402_5% R350 For VGA power sequence
1
Need to pop for BACO function PX@ Q73 @ 300K_0402_5% 20100816 D
S
Should be unpop for PX3.0
20100728 1
PX@
R345 2
er 3
2N7002_SOT23 1 R828
@
2 PE_GPIO1#
0_0402_5%
PX@ PX@
R352 G
2 1 R833 2 PE_GPIO1#
0_0402_5%
2
2
150K_0402_5% 1 @ 1 2 S Q76 @
3
1
2
B D R346 47K_0402_5% 2N7002_SOT23 B
1
1
PX_MODE# 1 R829 Q74 0_0402_5% C344 D R354 C352 @
2 2
0_0402_5% G 2N7002H_SOT23-3 @ 0.1U_0603_25V7K PE_GPIO1# 2 Q78 0_0402_5% 0.1U_0603_25V7K
BACO@ S PX@ 2 PX@ G 2N7002H_SOT23-3 @ PX@
3
S PX@ 2
1
PE_GPIO1# 1 R830 2 Change footprint
yb
0_0402_5% 20100812 Change footprint
PX3@ 20100812
C
+3VALW
Update design
20101001
1
+3VALW
PX@
1
R875
100K_0402_5% BACO@
R924
2
PE_GPIO1# 100K_0402_5%
Q123 PX_MODE#
1 2
1
DTC124EKAT146_SC59-3
PX@ D
OUT
A A
2 Q127
(20,43) PX_MODE
1
G 2N7002H_SOT23-3
2 BACO@ S BACO@
(13,20,43) PE_GPIO1
3
IN R925
GND
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
MBK1608121YZF_0603 1 1 1 1 1 1 MBK1608121YZF_0603
D D
C353
C354
C355
C357
C358
C359
U8G
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 DP E/F POWER DP A/B POWER 2 2 2
130mA
AG15 DPE_VDD18#1 DPA_VDD18#1 AE11
AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
+1.0VGS
total:240mA@LVDS +1.0VGS
L20 2
PX@
total:220mA@DP +DPEF_VDD10 110mA +DPAB_VDD10
total:220mA PX@ L21
1 AG20 DPE_VDD10#1 DPA_VDD10#1 AF6 1 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
MBK1608121YZF_0603 1 1 1 AG21 AF7 1 1 1 MBK1608121YZF_0603
DPE_VDD10#2 DPA_VDD10#2
C356
C360
C361
C362
C363
C364
.ru
PX@
PX@
PX@
PX@
PX@
PX@
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
2 2 2 AH14 AE3 2 2 2
DPE_VSSR#2 DPA_VSSR#2
AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5
m
+DPEF_VDD10 110mA +DPAB_VDD10
AF22 DPF_VDD10#1 DPB_VDD10#1 AF8
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9
ru
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8
PX@
Fo
R355 2 1 150_0402_1% AF17 AE10 R356 1 PX@ 2 150_0402_1%
DPEF_CALR DPAB_CALR
B B
+DPEF_VDD18 20mA 20mA +DPAB_VDD18
AG19 DPF_PVDD DPB_PVDD AG10
AF20 DPF_PVSS DPB_PVSS AG11
er 216-0774207-A11ROB_FCBGA631
PX@
yb
C
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 DP PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 22 of 48
5 4 3 2 1
5 4 3 2 1
+1.5VGS
2.3A(RMS)/2.8A(Peak)
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1
C365
C366
C369
C370
C371
C372
C373
C374
C389
C390
C391
C381
C392
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
2 2 2 2 2 2 2 2 2 2 2 2 2
change from SM010032020 to SD013000080
20101012
+PCIE_VDDR PX@ +1.8VGS
U8D
504mA 2 1 L22 U8E
MBK1608121YZF_0603
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
MEM I/O 1 1 1 1
D D
PCIE
C385
C387
C388
C380
H13 AB23 AA27 A3
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#1 GND#1
PX@
PX@
PX@
PX@
H16 AC23 AB24 A30
VDDR1#2 PCIE_VDDR#2 2 2 2 2 PCIE_VSS#2 GND#2
H19 AD24 AB32 AA13
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#3 GND#3
J10 AE24 AC24 AA16
VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4
J23 AE25 AC26 AB10
VDDR1#5 PCIE_VDDR#5 PCIE_VSS#5 GND#5
J24 AE26 AC27 AB15
VDDR1#6 PCIE_VDDR#6 PCIE_VSS#6 GND#6
J9 AF25 AD25 AB6
VDDR1#7 PCIE_VDDR#7 PCIE_VSS#7 GND#7
K10 AG26 AD32 AC9
VDDR1#8 PCIE_VDDR#8 PCIE_VSS#8 GND#8
K23 AE27 AD6
VDDR1#9 +1.0VGS PCIE_VSS#9 GND#9
K24 1920mA AF32 AD8
VDDR1#10 PCIE_VSS#10 GND#10
K9 L23 AG27 AE7
VDDR1#11 PCIE_VDDC#1 PCIE_VSS#11 GND#11
L11 L24 AH32 AG12
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
change from SM010009U00 to SD028000080 VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12
L12 L25 1 1 1 1 1 K28 AH10
+1.8VGS 20101012 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#13 GND#13
C398
C399
C383
C403
C384
L13 L26 K32 AH28
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#14 GND#14
L20 M22 L27 B10
+VDDC_CT VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
PX@
PX@
PX@
PX@
PX@
PX@ 110mA L21 N22 M32 B12
VDDR1#16 PCIE_VDDC#6 2 2 2 2 2 PCIE_VSS#16 GND#16
.ru
L23 1 2 L22 N23 N25 B14
BLM15BD121SN1D_0402 VDDR1#17 PCIE_VDDC#7 PCIE_VSS#17 GND#17
N24 N27 B16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C405
C408
PX@
PX@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 PCIE_VDDC#12 PCIE_VSS#22 GND#22
1 1 1 17mA AA20
VDD_CT#1
T32
PCIE_VSS#23 GND#23
B26
C409
C410
C411
AA21
AB20
VDD_CT#2
AA15
11.8A(RMS)/12.9A(Peak) U25
U27
PCIE_VSS#24 GND#24
B6
B8
VDD_CT#3 VDDC#1 PCIE_VSS#25 GND#25
PX@
PX@
PX@
AB21 CORE N15 V32 C1
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 VDD_CT#4 VDDC#2 PCIE_VSS#26 GND#26
PX@ C413
PX@ C414
PX@ C415
PX@ C416
PX@ C417
PX@ C418
PX@ C419
PX@ C420
PX@ C423
PX@ C424
PX@ C425
PX@ C426
N17 1 1 1 1 1 1 1 1 1 1 1 1 W25 C32
VDDC#3 PCIE_VSS#27 GND#27
R13 W26 E28
I/O VDDC#4 PCIE_VSS#28 GND#28
R16 W27 F10
VDDC#5 PCIE_VSS#29 GND#29
60mA AA17
VDDR3#1 VDDC#6
R18 Y25
PCIE_VSS#30 GND#30
F12
change from SM010009U00 to SD028000080 AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 F14
20101012 VDDR3#2 VDDC#7 PCIE_VSS#31 GND#31
m
AB17 T12 F16
VDDR3#3 VDDC#8 GND#32
AB18 T15 F18
PX@ VDDR3#4 VDDC#9 GND#33
T17 F2
L24 1 VDDC#10 GND#34
2 170mA V12
VDDR4#1 VDDC#11
T20
GND#35
F20
BLM15BD121SN1D_0402 Y12 U13 delete 5 capacitors for new CRB reference M6 F22
0.1U_0402_10V6K
1U_0402_6.3V4Z
POWER
1 1 VDDC#14
U18 New Ref circuit N12
GND#58 GND#38
F26
C429
C430
PX@
ru
U11 Y13 P6 G31
NC#4 VDDC#19 GND#63 GND#43
Y16 P9 G8
VDDC#20 GND#64 GND#44
Y18 R12 H14
VDDC#21 GND#65 GND#45
M11 R15 H17
PX@ VDDC#22 GND#66 GND#46
M12 R17 H2
L25 1 MEM CLK VDDC#23 GND#67 GND#47
2 R20 H20
BLM15BD121SN1D_0402 GND#68 GND#48
L17 T13 H6
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
C447
C449
1U_0402_6.3V4Z
1U_0402_6.3V4Z
GND#72 GND#52
PX@
PX@
PX@
1 1 T6 K2
2 2 2 PLL GND#73 GND#53
C451
C452
For Seymour, PCIE_PVDD is PCIE_VDDR. U15 K22
Fo
GND#74 GND#54
AM30 U17 K6
PCIE_PVDD GND#75 GND#55
PX@
PX@
R21 U20
BIF_VDDC#1 2 2 GND#76
U21 U9
+MPV18 BIF_VDDC#2 GND#77
75mA L8 NC_MPV18
V13
GND#78
V16
PX@ GND#79
V18
L26 1 +SPV18 GND#80
2 75mA H7 SPV18
Y10
GND#81
BLM15BD121SN1D_0402 ISOLATED Y15
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
C454
C455
PX@
PX@
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 VDDCI#5
M20 1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
VDDCI#6
C459
C460
C461
C466
1 1 1 M21 change from SM01000BZ00 to SD013000080
VDDCI#7
er
C456
C457
C458
N20 20100722
VDDCI#8
PX@
PX@
PX@
PX@
216-0774207-A11ROB_FCBGA631
2 2 2 2
PX@
PX@
PX@
2 2 2
B B
216-0774207-A11ROB_FCBGA631
+VGA_COREP
yb
330U_D2E_2.5VM_R9M
1
Source dist. 0.1u 1u 10u +
C1005
1.5VGS VDDR1 10 10 5 @ 2
VGA_core PCIE_VDDC 7 1
C
VDDC 25 6
VDDCI 6 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 23 of 48
5 4 3 2 1
5 4 3 2 1
U8C +1.8VGS
M_DA[63..0]
(25) M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 R357 1 X76@ 2 10K_0402_5% VRAM_ID0
M_MA[13..0] VRAM_ID0 (19)
M_DA0 K27 K17 M_MA0 R358 1 X76@ 2 10K_0402_5%
(25) M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1
M_DQM[7..0] DQA0_1/DQA_1 MAA0_1/MAA_1 VRAM_ID1 (19)
M_DA2 H30 H23 M_MA2 R360 1 X76@ 2 10K_0402_5%
(25) M_DQM[7..0] DQA0_2/DQA_2 MAA0_2/MAA_2
M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2
M_DQS[7..0] DQA0_3/DQA_3 MAA0_3/MAA_3 VRAM_ID2 (19)
M_DA4 G29 G24 M_MA4 R362 1 X76@ 2 10K_0402_5%
(25) M_DQS[7..0] DQA0_4/DQA_4 MAA0_4/MAA_4
MEMORY INTERFACE
M_DA5 F28 H24 M_MA5
M_DQS#[7..0] M_DA6 DQA0_5/DQA_5 MAA0_5/MAA_5 M_MA6
(25) M_DQS#[7..0] F32 DQA0_6/DQA_6 MAA0_6/MAA0_6 J19
D M_DA7 M_MA7 D
F30 DQA0_7/DQA_7 MAA0_7/MAA0_7 K19
M_DA8 C30 J14 M_MA8
DQA0_8/DQA_8 MAA1_0/MAA_8
M_DA9
M_DA10
F27 DQA0_9/DQA_9 MAA1_1/MAA_9 K14 M_MA9
M_MA10
Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
A28 DQA0_10/DQA_10 MAA1_2/MAA_10 J11
M_DA11 C28 J13 M_MA11
DQA0_11/DQA_11 MAA1_3/MAA_11
M_DA12 E27 DQA0_12/DQA_12 MAA1_4/MAA_12 H11 M_MA12
Hynix 512MB
M_DA13
M_DA14
G26 DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 G11 M_BA2
M_BA0
M_BA2 (25)
PN:SA000032460 1 0 0
D26 DQA0_14/DQA_14 MAA1_6/MAA_14/BA0 J16 M_BA0 (25)
M_DA15 F25 L15 M_BA1
DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 M_BA1 (25)
M_DA16 A25
M_DA17 DQA0_16/DQA_16 M_DQM0
C25 DQA0_17/DQA_17 WCKA0_0/DQMA_0 E32
M_DA18 E25 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 E30 M_DQM1
Hynix 1GB
M_DA19 D24 A21 M_DQM2
1 0 1
M_DA20 DQA0_19/DQA_19 WCKA0_1/DQMA_2 M_DQM3 PN:SA00003VS20
.ru
E23 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C21
M_DA21 F23 E13 M_DQM4
M_DA22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 M_DQM5
D22 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 D12
M_DA23 F21 E3 M_DQM6
DQA0_23/DQA_23 WCKA1_1/DQMA_6
M_DA24 E21 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 F4 M_DQM7
Samsung 512MB
M_DA25
M_DA26
D20 DQA0_25/DQA_25 M_DQS0 PN:SA000035700 0 1 0
F19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 H28
M_DA27 A19 C27 M_DQS1
M_DA28 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 M_DQS2
D18 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 A23
M_DA29 F17 E19 M_DQS3
DQA0_29/DQA_29 EDCA0_3/RDQSA_3
C
M_DA30 A17 DQA0_30/DQA_30 EDCA1_0/RDQSA_4 E15 M_DQS4
Samsung 1GB C
m
M_DA31 C17 D10 M_DQS5
+1.5VGS M_DA32 E17
DQA0_31/DQA_31
DQA1_0/DQA_32
EDCA1_1/RDQSA_5
EDCA1_2/RDQSA_6 D6 M_DQS6 PN:SA00003MQ20 0 1 1
+1.5VGS M_DA33 D16 G5 M_DQS7
M_DA34 DQA1_1/DQA_33 EDCA1_3/RDQSA_7
F15 DQA1_2/DQA_34
1
ru
PX@ M_DA39 C13 C15 M_DQS#4
2
Fo
M_DA47 D8 H26 M_CLK0
M_CLK0 (25)
2
(25) DRAM_RST# 1
R366 PX@
0_0402_5%
2 1
R369 PX@
2
51_0402_5%
DRAM_RST#_R
er M_DA58
M_DA59
M_DA60
G1
G3
J6
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
CSA0B_0
CSA0B_1
H22
J22
M_CS#0
M_CS#0 (25)
Hynix
H512@
X7624938L03
Samsung
S512@
X7624938L04
2
1 M_DA61 J1
R882 R371 C469 M_DA62 DQA1_29/DQA_61 M_CS#1
J3 DQA1_30/DQA_62 CSA1B_0 G13 M_CS#1 (25)
0_0402_5% 10K_0402_5% 120P_0402_50V8J M_DA63 J5 K13
@ PX@ PX@ DQA1_31/DQA_63 CSA1B_1
2 MVREFDA M_CKE0
K26 K20 M_CKE0 (25)
1
MAA1_8 G14
GDDR5 G20 M_MA13
DRAM_RST#_R MAA0_8
L10 DRAM_RST
@ C470
C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 MEM Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 24 of 48
5 4 3 2 1
5 4 3 2 1
M_DA[63..0]
(24) M_DA[63..0]
M_MA[13..0]
(24) M_MA[13..0]
M_DQM[7..0]
(24) M_DQM[7..0]
M_DQS[7..0]
(24) M_DQS[7..0]
M_DQS#[7..0]
(24) M_DQS#[7..0]
.ru
M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3
(24) M_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10 M_BA1 N9 D10
(24) M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
(24) M_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
(24) M_CLK0 J8 N10 J8 N10 (24) M_CLK1 J8 N10 J8 N10
M_CLK#0 K8 CK VDD M_CLK#0 CK VDD M_CLK#1 K8 CK VDD M_CLK#1 CK VDD
(24) M_CLK#0 R2 K8 R2 (24) M_CLK#1 R2 K8 R2
M_CKE0 K10 CK VDD M_CKE0 CK VDD M_CKE1 K10 CK VDD M_CKE1 CK VDD
(24) M_CKE0 R10 K10 R10 (24) M_CKE1 R10 K10 R10
CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
m
(24) M_CAS#0 C10 K4 C10 (24) M_CAS#1 C10 K4 C10
M_WE#0 CAS VDDQ M_WE#0 CAS VDDQ M_WE#1 CAS VDDQ M_WE#1 CAS VDDQ
(24) M_WE#0 L4 D3 L4 D3 (24) M_WE#1 L4 D3 L4 D3
WE VDDQ WE VDDQ WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ
F4 H3 F4 H3 F4 H3 F4 H3
M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ M_DQS5 DQSL VDDQ M_DQS7 DQSL VDDQ
C C8 H10 C8 H10 C8 H10 C8 H10 C
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
ru
G9 G9 G9 G9
M_DQS#2 VSS M_DQS#3 VSS M_DQS#4 VSS M_DQS#6 VSS
G4 J3 G4 J3 G4 J3 G4 J3
M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS M_DQS#5 DQSL VSS M_DQS#7 DQSL VSS
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
(24) DRAM_RST# T3 P10 P10 P10 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
PX@ J2 B2 PX@ J2 B2 PX@ J2 B2 PX@ J2 B2
Fo
R374 NC/ODT1 VSSQ R375 NC/ODT1 VSSQ R376 NC/ODT1 VSSQ R377 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J10 D2 J10 D2 J10 D2 J10 D2
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E3 E3 E3 E3
2
2
VSSQ VSSQ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
X76@ X76@ X76@ X76@
B
+1.5VGS +1.5VGS
er +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
B
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
1
1
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
R378
R379
R380
R381
R382
R383
R384
R385
2
2
yb
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
PX@ PX@ 1 PX@ PX@ 1 PX@ 1 PX@ 1 PX@ 1 PX@ 1 PX@ 1 PX@ 1
PX@ PX@ PX@ PX@ PX@ PX@
R386
C472
R387
C473
C474
C475
C476
C477
C478
C479
R388
R389
R390
R391
R392
R393
2 2 2 2 2 2 2 2
2
2
C
M_CLK1 1 PX@ 2
R395 56_0402_1%
+1.5VGS
+1.5VGS +1.5VGS
M_CLK#1 1 PX@ 2
R397 56_0402_1% 1 PX@ 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C507 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.01U_0402_16V7K
C488 C489 C490 C480 C491 C481 C492 C482 C483 C493 C494 C495 C496 C497 C498 C499 C500 C501 C484 C485 C486 C502 C503 C504 C505 C487
2 PX@ PX@ @ PX@ PX@ PX@ PX@ @ PX@ PX@ @ PX@ PX@ PX@ @ PX@ PX@ PX@ @ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M10U_0603_6.3V6M
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A M_CLK0 1 PX@ 2 A
R394 56_0402_1%
M_CLK#0 1 PX@ 2
R396 56_0402_1%
1 PX@
C506
0.01U_0402_16V7K VRAM P/N :
2
Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) Security Classification Compal Secret Data Compal Electronics, Inc.
Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
update VRAM PN 0619 update THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RobsonXT-S3 VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 25 of 48
5 4 3 2 1
5 4 3 2 1
+1.7_VDDCT
+1.7_LX
Power On strapping
+3VALW Pin Description Chip Default
+3V_LAN +1.7_VDDCT 1 2 +1.7_LX
1000P_0402_50V7K
10U_0805_10V4Z
L56 4.7UH_SIA4012-4R7M_20% H:Over Clock Enable
0.1U_0402_16V4Z
J6 LED0 H
1 1 2 2 1 1 1 Note: L:Over Clock Disable *
C784
C785
C786
Place Close to LAN chip H:SWR Switch mode regulator Select
JUMP_43X79 @ L56 DCR< 0.15 ohm
*
@
2 2 2
Rate current of L33 > 1A LED2 AR8151 Pin23=LED2.
D Atheros request can't disable LAN power Close to Pin40
D
--
AR8152, Pin23 is CLKREQ
.ru
U29 8152@
no overclocking
PD 5.1K
S IC AR8152-AL1E QFN 40P E-LAN CTRL R650
5.1K_0402_5%
1 2
U29 LED0,1,2 intel Pull UP
Place Close to Chip
m
C
(13) PCIE_FRX_DTX_N0 C7891 2 0.1U_0402_16V7K PCIE_FRX_DTX_N0_C 29 TX_N LED_0 38 ACTIVITY (27)
C
Atheros 39 R651
LED_1 LAN_LINK# (27)
(13) PCIE_FRX_DTX_P0 C7901 2 0.1U_0402_16V7K PCIE_FRX_DTX_P0_C 30 TX_P LED_2 23 1 8152@ 2 LAN_CLKREQ#
8151-AL1A 0_0402_5%
(13) PCIE_FTX_C_DRX_N0 36 RX_N
12 MDI0-
TRXN0 MDI0- (27)
35 11 MDI0+
(13) PCIE_FTX_C_DRX_P0 RX_P TRXP0 MDI0+ (27)
15 MDI1-
TRXN1 MDI1+ MDI1- (27)
ru
(13) CLK_PCIE_LAN# 32 REFCLK_N TRXP1 14 MDI1+ (27)
33 18 MDI2-
(13) CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- (27)
17 MDI2+
PLT_RST# TRXP2 MDI3- MDI2+ (27)
(13,30,31) PLT_RST# 2 PERST# TRXN3 21 MDI3- (27)
20 MDI3+
TRXP3 MDI3+ (27) +3V_LAN
R652 1 @ 2 0_0402_5% PCIE_WAKE# 3
(14,30) FCH_PCIE_WAKE# W AKE#
LAN_RBIAS 1 R654 2 2.37K_0402_1%
0.1U_0402_16V4Z
(31) LAN_WAKE# 25 SMCLK RBIAS 10
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
26 SMDATA +3V_LAN
Fo
28 TEST_RST VDD33 1
+1.7_LX
C791 & C792 Close pin1 < 200mil 1 1 1 1
C791
C792
C794
C795
+3VALW 27 @
TESTMODE C794 & 795 Close pin < 400mil
@ 40 +1.7_LX
LAN_CLKREQ# LAN_XTALO LX +1.7_VDDCT 2 2 2 2
1 R926 2 7 XTLO
10K_0402_5% LAN_XTALI 8
R657 XTLI +1.7_VDDCT
VDDCT 5
1 GIGA@ 2 CLKREQ_LAN#_R 1
(14) LAN_CLKREQ#
0_0402_5% 0.1U_0402_16V4Z 4 CLKREQ# +1.1_DVDDL C797 1
1 2 DVDDL 24 2 0.1U_0402_16V4Z C799
C796 8152@ 37 C798 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z
+1.1_AVDDL DVDDL_REG C800 1 2
B
13 AVDDL 2 0.1U_0402_16V4Z B
+1.1_AVDDL 19 AVDDL
31
34
AVDDL
AVDDL
er AVDDH
AVDDH
16
22 +2.7_AVDDH
Near Pin37
GIGA@
GIGA@
+1.1_AVDDL +2.7_AVDDH
0.1U_0402_16V4Z
6 AVDDL_REG AVDDH_REG 9
C810 GIGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1
41 GND
C801
C802
C803
C804
C805
C806
C807
C808
C809
AR8151-AL1A_QFN40_5X5
2 2 2 2 2 2 GIGA@ 2 2 2 2
LAN_XTALI
Place Close to LAN chip
yb
Near Near Near Near Near LAN_XTALO Near Near Near 49.9_0402_1%
Y6 MDI0+ R658 1 2 @ C811 1000P_0402_50V7K
Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 49.9_0402_1%
1 2
MDI0- R659 1 2 1 2 C812 0.1U_0402_16V4Z
27P_0402_50V8J
25MHZ_20PF_7A25000012 49.9_0402_1%
27P_0402_50V8J
C816
49.9_0402_1%
MDI1- R661 1 2 1 2 C814 0.1U_0402_16V4Z
49.9_0402_1%
2 2 MDI2+ R662 1 2 @ C817 1000P_0402_50V7K
GIGA@ 49.9_0402_1%
C
R916
+1.7_VDDCT 2 1
0_0603_5%
1
@ C996
1U_0402_6.3V4Z
2
Place Close to T88
D D
MDI1- T88
MDI1+ 1 16 MDO1+
(26) MDI1+ RD+ RX+
MDI1+ MDI1- 2 15 MDO1-
(26) MDI1- RD- RX-
D1 @ 3 14 MCT0 R666 2 1 75_0402_5%
CT CT
4 NC NC 13
TCLAMP3302N.TCT_SLP2626P10-10 5 12
NC NC MCT1 R667 1 75_0402_5%
10
6 CT CT 11 2
6
7
8
9
MDI0+ 7 10 MDO0+
(26) MDI0+ TD+ TX+
MDI0- 8 9 MDO0- 1 1
6
7
8
9
10
(26) MDI0- TD- TX-
11 @ @
.ru
GND C1013 C1012
350uH_NS0013LF 22U_1206_10V7K 22U_1206_10V7K
2 2
5
4
3
2
1
Reserve gas tube for EMI go rural solution
20101006
5
4
3
2
1
T97 GIGA@
m
5 NC NC 12
6 11 MCT3 R669 2 GIGA@ 1 75_0402_5%
MDI3+ CT CT MDO3+
(26) MDI3+ 7 TD+ TX+ 10
Reserve D1 for EMI go rural solution (26) MDI3-
MDI3- 8 9 MDO3- 1
C TD- TX- C822 C
20101006
350uH_NS0013LF 1000P_1206_2KV7K
2
ru
GIGA@
GIGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1
Fo
C990
C991
C992
C993
2 2 2 2
RJ45 Conn.
B
er @
C994
470P_0402_50V7K
1
2
+3V_LAN
MDO3-
MDO3+
MDO1-
11
6
Green LED-
Green LED+
PR4-
PR4+
SHLD2
SHLD1
16
15
B
PR2-
yb
MDO2- 5 PR3-
MDO2+ 4 PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1-
SHLD2 14
MDO0+ 1 PR1+
SHLD1 13
C
10 Yellow LED-
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 27 of 48
5 4 3 2 1
5 4 3 2 1
CX20671
High Definition Audio Codec SoC HDA_RST_AUDIO#
With Integrated Class-D Stereo
HDA_SYNC_AUDIO
EMI
Amplifier.
HDA_SDOUT_AUDIO
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO). 1 R672
0_0402_5%
2 HDA_BITCLK_AUDIO
C823
C824
C825
C826
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
2 2 2 2
D D
@ @ @ Cheange to pop for PVT for EMI solution
20101006
+3VS
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1
C827
C828
C829
+LDO_OUT_3.3V_R +LDO_OUT_3.3V
+3VS 2 1 +VAUX_3.3
0_0402_5% R673 2 2 2
1U_0603_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VALW 2 @ 1 1 1 1 1 AVDD_3.3 pinis output of
10U_0805_10V4Z
0.1U_0402_16V4Z
C832
C833
C834
C835
0_0402_5% R674 1 1 internal LDO. NOT connect
C830
C831
To support Wake-on-Jack or Wake-on-Ring, the CODEC
to external supply.
.ru
VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed. 2 2 2 2
Reserve for ESD *DSH page42 has more detail. 2 2 Layout Note:Path from +5VS to LPW R_5.0
RPW R_5.0 must be very low
resistance (<0.01 ohms) For 20671-21Z update
+3VS
20100928
+3VS 2 1
0_0402_5% R676 1 R963 2 0_0805_5%
1
1U_0603_10V4Z
0.1U_0402_16V4Z
R855 0_0402_5% R677 1 1 is removed during system re-start.
+ClassD_5VS
C836
C837
4.7K_0402_5% 1 R678 2 @ +5VS
10U_0805_10V4Z
0.1U_0402_16V4Z
1 1
C838
C839
0.1_1206_1%
10 mils
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
HDA_RST_AUDIO# 2 2
1 1 1 1
C840
C841
C842
C843
m
1
10U_0805_10V4Z
0.1U_0402_16V4Z
1
@ R959 2 2
10K_0402_5%
1 1
C844
C845
C977 0_0402_5%
100P_0402_50V8J R679 EMI reserved 2 2 2 2
2
2 20100816
0.1U_0402_16V4Z
2 2
18
29
27
28
26
C 1 C
3
7
2
C846
U31
FILT_1.8
VAUX_3.3
DVDD_3.3
FILT_1.65
AVDD_3.3
VDD_IO
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
12 2
LPWR_5.0
15
RPWR_5.0
ru
HDA_RST_AUDIO# 9 17
(14) HDA_RST_AUDIO# RESET# CLASS-D_REF R680 1 2 5.11K_0402_1% +VAUX_3.3
HDA_BITCLK_AUDIO 5 Sense resistors must be
(14) HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 36 R681 1 2 10K_0402_1% Port C
(14) HDA_SYNC_AUDIO SYNC SENSE_A MIC_JD (34) connected same power
R682 1 2 33_0402_5% 6 R683 1 2 39.2K_0402_1% PLUG_IN (34) Port A
(14) HDA_SDIN0 SDATA_IN that is used for VAUX_3.3
HDA_SDOUT_AUDIO 4
(14) HDA_SDOUT_AUDIO SDATA_OUT
35 MIC_INR Internal MIC
PORTB_R MIC_INL
34
PORTB_L
33 +MICBIASB
PC_BEEP B_BIAS R684 2.2K_0402_5%
EAPD active low 10
PC_BEEP +MICBIASC
R685 2.2K_0402_5%
0=power down ex AMP 32 +MICBIASC
Fo
C_BIAS
1=power up ex AMP PORTC_R
31 C847 1 2 2.2U_0603_6.3V4Z R686 100_0402_1%
EXT_MIC_R (34)
30 C848 1 2 2.2U_0603_6.3V4Z External MIC
PORTC_L EXT_MIC_L (34)
0_0402_5% 1 2 R688 38 R687 100_0402_1%
(31) EAPD GPIO0/EAPD#
(31) EC_MUTE# 2 1 37
0_0402_5% R689 GPIO1/SPK_MUTE# R690 15_0402_5%
23 1 2 HP_OUTR (34)
PORTA_R R691 15_0402_5%
PORTA_L
22 1 2 HP_OUTL (34) Headphone
40
DMIC_CLK
1
DMIC_1/2 NC
24 Changed from 5.1ohm to 15ohm
25 for "zi zi"noise.
NC
39
SPK_L2+ NC
11
SPK_L1- LEFT+
13
LEFT-
Internal SPEAKER AVEE
21
19
FLY_P
SPK_R2+
er16 20 1 2
10U_0805_10V4Z
0.1U_0402_16V4Z
SPK_R1- RIGHT+ FLY_N C852 1U_0603_10V4Z
14 1 1
RIGHT-
C853
C854
GND
B 2 2 B
CX20671-21Z_QFN40_6X6
41
1
yb
R695
4.7K_0402_5%
C849
1 2 change from SE070104Z80 to SD028000080 for EMI request
2
0.1U_0402_16V4Z 20101011 MIC1
1 C856 1 2 2.2U_0603_6.3V4Z MIC_INR
C850 2 GNDA
1 2 MIC_INL
0.1U_0402_16V4Z WM-64PCY_2P Delete redundant part base on
45@ vender's suggestion 20100810
R692
1 2
0_0402_5% Cheange to pop for PVT for EMI solution
R693 20101006
C
1 2
0_0402_5%
R696
1 2
0_0402_5%
Short GND and GNDA base on
vender's suggestion 20100810
wide 30MIL close to Codec
JSPK1
GND GNDA SPK_R1- L57 1 2 0_0603_5% SPK_R1-_CONN 1
SPK_R2+ L58 0_0603_5% SPK_R2+_CONN 1
1 2 2
SPK_L1- L59 0_0603_5% SPK_L1-_CONN 2
1 2 3
SPK_L2+ L60 0_0603_5% SPK_L2+_CONN 3
1 2 4
4
5
R953 @ 0_0402_5% GND1
6
PC Beep
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
GND2
A 2 1 1 1 1 1 A
C863
C861
C864
C865
ACES_88231-04001
EC Beep (31) BEEP# 2 1 L57 ~ L60 change to 0ohms base on ME@
vender's suggestion 20100810 2 2 2 2
D30 RB751V_SOD323
R934 L57 ~ L60 Change from SD013000080 to SM01000BZ00
ICH Beep (14) FCH_SPKR 2 1PC_BEEP1 1 2 1 2 PC_BEEP pop C863, C864, C865, C861
33_0402_5% C997 0.1U_0402_16V4Z
EMI solution 20100824
D31 RB751V_SOD323
1
@
20101007 R935
Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% 2010/06/30 2012/06/30 Title
Issued Date Deciphered Date
CX20671 Codec
2
Follow vender recommanded circuit THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
20100722 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 28 of 48
5 4 3 2 1
A B C D E F G H
Close U32
REMOTE1+ +3VS REMOTE1+
Close to DDR
1 SMSC thermal sensor 1 FAN1 Conn
1
@ C
1
C868
2200P_0402_50V7K +3VS placed near by VRAM R704
C867
100P_0402_50V8J
2
B
Q94
MMST3904-7-F_SOT323-3
2 REMOTE1- 2 E +5VS
10K_0402_5%
3
@ REMOTE1-
1 U32 JFAN1 1
2
1
1
(31) EC_TACH 2
REMOTE2+ 2
1 10 EC_SMB_CK2 (5,19,31) (31) EC_FAN_PWM 3
VDD SMCLK 3
1 4
@ REMOTE1+ 4
C869
2
DP1 SMDATA
9 EC_SMB_DA2 (5,19,31)
REMOTE2+
Under WLAN 2 5
6
G5
2 G6
2200P_0402_50V7K REMOTE1- 3 8 1 C872
DN1 ALERT#
1
2 REMOTE2- C871 @ C ACES_85205-04001
10U_0805_10V4Z
0.1U_0402_16V4Z REMOTE2+ C870 Q95 @ 1 ME@
4 7 2
1 DP2 THERM# 100P_0402_50V8J B MMST3904-7-F_SOT323-3
REMOTE2- 5 6 2 E
3
DN2 GND REMOTE2-
.ru
EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
Address 1001_101xb Trace width/space:10/10 mil
Trace length:<8"
Change from SA000029210 to SA000046C00 for main source
m
2 2
ru
SATA HDD Conn.
1
JHDD1
ODD Power Control
GND
Fo
SATA_ITX_DRX_P0 2
(15) SATA_ITX_DRX_P0 RX+
SATA_ITX_DRX_N0 3 @ J8
(15) SATA_ITX_DRX_N0 RX-
4 1 2
SATA_DTX_C_IRX_N0 C874 1 SATA_DTX_IRX_N0 GND 1 2
(15) SATA_DTX_C_IRX_N0 2 0.01U_0402_16V7K 5
TX-
SATA_DTX_C_IRX_P0 C873 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P0 6
(15) SATA_DTX_C_IRX_P0 TX+ JUMP_43X79 +5VS_ODD
7
GND +5VS Change footprint
20100812
3 1
1
1
8 Q96
3.3V AP2301GN-HF_SOT23-3 C883
+3VS 9
3.3V R707 0.1U_0402_16V4Z
10
2
3.3V 2
er 11
12
GND
10K_0402_5%
1
2
GND C884
13 0.01U_0402_16V7K
GND C885
14 1 2 1 2
5V
1
3 R859 10U_0805_10V4Z 3
+5VS 15
5V 100K_0402_5% 2
16
OUT
5V
17
GND
18
Reserved
19 (15) ODD_EN 2
+5VS +3VS GND IN
20 23
GND
12V GND
yb
21 24
12V GND Q97
22
12V DTC124EKAT146_SC59-3
1 1 1 1 1 1
3
@ @ SUYIN_127043FB022G278ZR
C877 C878 C879 C880 C881 C882 ME@
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/EMC1403/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 29 of 48
A B C D E F G H
A B C D E
1
1 1 1
Mini-Express Card(WLAN/WiMAX) 1 2 J10 @ @ @
1
1 2 C886 C887 C888
JUMP_43X79
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@
JUMP_43X79 2 2 2
2
@
JWLN1
2
1 1
(14,26) FCH_PCIE_WAKE# R708 1 2 0_0402_5% WLAN_WAKE# 1 2
R709 1 @ WAKE# 3.3V
(33) BT_ACTIVE 2 0_0402_5% 3 4
NC GND
5 6
WLAN_CLKREQ# NC 1.5V LPC_FRAME#_R
(14) WLAN_CLKREQ# 7 8
CLKREQ# NC LPC_AD3_R
9 10
GND NC LPC_AD2_R
(13) CLK_PCIE_WLAN# 11 12
REFCLK- NC LPC_AD1_R
(13) CLK_PCIE_WLAN 13 14
REFCLK+ NC LPC_AD0_R
15 16
PCI_RST#_R GND NC R885 1 @ 0_0402_5%
17 18 2 WL_OFF# (15)
CLK_PCI_DB NC GND R710 1 0_0402_5%
19 20 2 WL_OFF#_EC (31)
NC NC
21 22 PLT_RST# (13,26,31)
GND PERST# R711 1
(13) PCIE_FRX_DTX_N1 23 24 2 @ 0_0402_5% +3VALW
PERn0 +3.3Vaux R712 1 0_0402_5%
(13) PCIE_FRX_DTX_P1 25 26 2 +3VS
PERp0 GND
27 28
GND +1.5V R713 1
29 30 2 @ 0_0402_5% FCH_SMCLK0 (8,9,14)
GND SMB_CLK R714 1
(13) PCIE_FTX_C_DRX_N1 31 32 2 @ 0_0402_5% FCH_SMDAT0 (8,9,14)
PETn0 SMB_DATA
(13) PCIE_FTX_C_DRX_P1 33 34
PETp0 GND
.ru
35 36 USB20_N7 (14)
+3VS_WLAN GND USB_D-
37 38 USB20_P7 (14)
NC USB_D+
39 40
NC GND 0_0402_5% @
41 42 2 1 R715
NC LED_WWAN# 0_0402_5% @
43 44 2 1 R716 WLAN_LED# (46)
100_0402_1% NC LED_WLAN#
45 46
R717 NC LED_WPAN#
47 48
EC_TX_P80_DATA 1 NC +1.5V
(31,32) EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK 1 NC GND
(31,32) EC_RX_P80_CLK 2 51 52
R718 NC +3.3V
100_0402_1% 53 54
GND GND
TAITW_PFPET0-AFGLBG1ZZ4N0
2
m
debug card insert. 100K_0402_5%
1
2 2
ru
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R R720 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# (13,31)
LPC_AD3_R R721 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 (13,31)
LPC_AD2_R R722 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 (13,31)
LPC_AD1_R R723 1 @ 2 0_0402_5% LPC_AD1
LPC_AD1 (13,31)
Fo
LPC_AD0_R R724 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 (13,31)
PCI_RST#_R R725 1 @ 2 0_0402_5% PLT_RST#
CLK_PCI_DB CLK_PCI_DB (13)
3
er 3
yb
C
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 30 of 48
A B C D E
+3VALW
+EC_AVCC
1 1 1 1 1 1
0.1U_0402_16V4Z
C889
0.1U_0402_16V4Z
C890
0.1U_0402_16V4Z
C891
0.1U_0402_16V4Z
C892
1000P_0402_50V7K
C893
1000P_0402_50V7K
C894
L61 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C895 2 2 2 2 2 2
0.1U_0402_16V4Z C896
111
125
1000P_0402_50V7K
22
33
96
67
9
1 2 1 ECAGND 2 U33
L62 FBM-11-160808-601-T_0603
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
1 21 +5VS
(14) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
(14) KB_RST# 2 23 BEEP# (28)
KBRST#/GPIO01 BEEP#/PWM2/GPIO10 TP_CLK R731 1
(13) SERIRQ 3
SERIRQ# FANPWM1/GPIO12
26 2 4.7K_0402_5%
4 27 ACOFF
(13,30) LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (36,38) TP_DATA R732 1
(13,30) LPC_AD3 5
LAD3 2 4.7K_0402_5%
LPC_AD2 7 PWM Output
(13,30) LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
(13,30) LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (37)
LAD0 LPC & MISC
(13,30) LPC_AD0 10 64
BATT_OVP/AD1/GPIO39 BATT_TEMP
2 1 2 1 65 ADP_I (38) 1 2
@ C897 22P_0402_50V8J @ R729 10_0402_5% ADP_I/AD2/GPIO3A C899 100P_0402_50V8J
(13) LPC_CLK0_EC 12
PCICLK AD Input AD3/GPIO3B
66
PLT_RST# 13 75 BRDID ACIN 1 2
(13,26,30) PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42
1 2 37 76 C900 100P_0402_50V8J
+3VALW ECRST# SELIO2#/AD5/GPIO43
R730 47K_0402_5% EC_SCI# 20
(14) EC_SCI# SCI#/GPIO0E
2 (37) BATT_LEN# 38
CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68
C898 PWR function required 70
0.1U_0402_16V4Z 20101115 EN_DFAN1/DA1/GPIO3D IREF
1
DA Output IREF/DA2/GPIO3E 71 IREF (38)
KSI0 55 72 +3VALW 20100727
.ru
KSI1 KSI0/GPIO30 DA3/GPIO3F CHGVADJ (38)
56 KSI1/GPIO31
KSI2 57 EC_MUTE# R733 1 2 10K_0402_5% +5VALW
KSI3 KSI2/GPIO32
(46) KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# (28)
KSI4 59 84 USB_ON#
(46) KSI4 KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# (33,34) USB_ON#
60 85 R734 1 2 10K_0402_5%
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 CMOS_OFF# (10)
KSO[0..17] KSI7 62 87 TP_CLK
(46) KSO[0..17] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK (46)
39 88 +3VALW
KSI[0..7] KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (46)
(46) KSI[0..7]
40 KSO1/GPIO21 Ra
KSO2 41
KSO3 KSO2/GPIO22 BRDID R900 1 @
42 KSO3/GPIO23 SDICS#/GPXOA00 97 VGATE (14,44) 2 100K_0402_5%
KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 CE_EN (10)
+3VALW KSO5 R901 1 2 8.2K_0402_5%
44 KSO5/GPIO25 Int. K/B 99 APU_ALERT#_EC (5)
m
KSO6 SDIDO/GPXOA02 LID_SW#
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# (46)
KSO7 46 SPI Device Interface Rb
KSO7/GPIO27
R737 1 2 47K_0402_5% KSO1 KSO8 47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO (32)
R738 1 2 47K_0402_5% KSO2 KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SI
FWR#SPI_SI (32) ID BRD ID R900 R901 Vab
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK (32)
KSO12 51 128 FSEL#SPICS#
ENE UPDATE 08/10/21 KSO13 52
KSO12/GPIO2C
KSO13/GPIO2D
SPICS# FSEL#SPICS# (32)
0 R10 MP x 0 0V
KSO14 53 Reserve for EMI for PVT build
KSO14/GPIO2E
ru
KSO15 54 73 20101005
KSO16 KSO15/GPIO2F CIR_RX/GPIO40 EC_PROCHOT# (5)
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
KILL_SW#_EC (46) 1 R03 PVT 100K 8.2K 0.25V
KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# FSTCHG (38)
90 @ C1010
BATT_CHGI_LED#/GPIO52 CAPS_LED# CHARGE_LED0# (46)
CAPS_LED#/GPIO53
91 CAPS_LED# (34) 1 2 2 R02 DVT 100K 18K 0.5V
EC_SMB_CK1 77 GPIO 92
(37) EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PWR_LED# (34,46)
EC_SMB_DA1 78 93 CHARGE_LED1# 100P_0402_50V8J
(37) EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 CHARGE_LED1# (46)
EC_SMB_CK2 79 SM Bus 95 SYSON 3 R01 EVT 100K 33K 0.82V
(5,19,29) EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON (35,41,42)
(5,19,29) EC_SMB_DA2 80 121 VR_ON (44)
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN
127 ACIN (19,38)
AC_IN/GPIO59
Fo
+3VS
1
14 101 EC_LID_OUT#
(14) SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# (14)
15 102 @
(14) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (34,39)
16 103 D16 RB751V_SOD323 R739
LID_SW#/GPIO0A EC_SWI#/GPXO06 BATT_SEL_EC (38)
17 104 ICH_POK_EC 1 2 ICH_POK 10K_0402_5%
SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK (14)
18 GPO 105 BKOFF#
2
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# (10) EC_TACH
+3VS 19 GPIO 106 1 2 1 2 +3VS
INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_LED# (46)
25 107 R743 0_0402_5% R744 10K_0402_5%
(10) INVT_PWM EC_THERM#/GPIO11 GPXO10 WL_OFF#_EC (30)
(29) EC_TACH 28 108 BT_OFF#_EC (33) @
FAN_SPEED1/FANFB1/GPIO14 GPXO11
1
(46) ODD_DA# 29
EC_TX_P80_DATA FANFB2/GPIO15
(30,32) EC_TX_P80_DATA 30
EC_RX_P80_CLK EC_TX/GPIO16
R727
10K_0402_5%
@
(30,32) EC_RX_P80_CLK
(34) ON/OFF#
31
32
34
EC_RX/GPIO17
ON_OFF/GPIO18
er PM_SLP_S4#/GPXID1
ENBKL/GPXID2
110
112
114
ENBKL (10)
EAPD (28)
SUSP#
1
2
FRD#SPI_SO
yb
1 2
GND
GND
GND
GND
GND
69
ECAGND
2
1
1
C
2.2K_0402_5%
R752 EC_SMB_DA1
2.2K_0402_5% 1 2 EC_PME#
(26) LAN_WAKE# R741 0_0402_5%
@ 1 2
1 2 R742 @ 0_0402_5%
+3VS C978 15P_0402_50V8J
D
If Q8 or R429, R432 implemented, XCLKO 1 2 3 1
R747 & R748 need to be mounted FCH_RTCX2_OUT (13) (14) PCI_PME#
R922 0_0402_5%
1
32.768KHZ_12.5PF_9H03200413 @ @ Q98
@ @ @
G
3 NC
OSC 4 2N7002_SOT23
2
R747 R748 R860 +3VALW
2.2K_0402_5% 2.2K_0402_5% 2 1 20M_0603_5% changed 09.09.08
NC OSC
2
1
R960
D +3VALW 0_0402_5% D
20mils
2
1 1 1
1
@
C936 R758 C937 C1004
0.1U_0402_16V4Z 10K_0402_5% 10P_0402_50V8J 12P_0402_50V8J
2 2 2
2
U35
(31) FSEL#SPICS#
Change from SD028150A80 to SM01000DI00
FSEL#SPICS# 1 8 EMI solution after A phase 20100824 EMI requested after A test
(31) FRD#SPI_SO
FRD#SPI_SO R759 1 2 15_0402_5% SPI_SO 2
3
CS#
DO
VCC
HOLD# 7
6
HOLD#
SPI_CLK_R 1 R760 2 15_0402_5% SPI_CLK
EMI 20100817
WP# CLK SPI_CLK (31) R960 change to SD028330A80
4 5
.ru
GND DIO C1004 change to SE071220J80
MX25L2005CMI-12G SOP SPI_SI_EC 1 R761 2 15_0402_5% FW R#SPI_SI
FW R#SPI_SI (31)
20100826
m
C C
ru
1 1 1 1
EC DEBUG PORT
H_3P8
H1 H2 H3 H4
HOLEA HOLEA HOLEA HOLEA
Fo
JECDP1
+3VALW 1 1
EC_TX_P80_DATA 2
(30,31) EC_TX_P80_DATA
1
EC_RX_P80_CLK 2
(30,31) EC_RX_P80_CLK 3 3
4 4
ACES_85205-0400
ME@
H_3P3 H_3P0x4P5N H_6P0
H6
HOLEA H15 H16 H17
HOLEA HOLEA HOLEA
er
1
B B
H_2P8
H12 H11 H10 H14 H13 H8 H7
yb
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
H_5P5N H_3P0N
C
H9 H5
HOLEA HOLEA
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC SPI ROM/LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 32 of 48
5 4 3 2 1
A B C D E
+5VALW
L63 @
Left USB Conn.
+USB_VCCB USB20_P0 USB20_P0_C +USB_VCCB
U36
1 1 2 2 W=80mils JUSB1
1 GND OUT 8 1 VCC
2 7 USB20_N0 4 3 USB20_N0_C 1 2 R862 1 0_0402_5% USB20_N0_C 2
IN OUT 4 3 (14) USB20_N0 D-
C941 2 10.1U_0402_16V4Z 3 6 1 2 R863 1 0_0402_5% USB20_P0_C 3
IN OUT + (14) USB20_P0 D+
(31,34) USB_ON# USB_ON# 4 5 WCM-2012-900T_4P C939 4
EN OC# USB_OC0# (14) GND
220U_6.3V_M C940
2
PJDLC05_SOT23-3
1 APL3510BKI_SO8 1 L64 @ 470P_0402_50V7K 5 1
C942 USB20_P3 USB20_P3_C 2 2 D19 GND1
Low Active @ 1000P_0402_50V7K
1 1 2 2
@
6 GND2
7 GND3
8 GND4
2 USB20_N3 4 3 USB20_N3_C
4 3 ( 220U 6.3V M V LESR15M VL H5.9 )*1 SUYIN_020173GR004M58BZL
WCM-2012-900T_4P ME@
=(SF000001500)
L65 @
Left USB Conn.
1
USB20_P2 1 2 USB20_P2_C
1 2
+USB_VCCC
USB20_N2 USB20_N2_C
W=80mils JUSB2
4 3
.ru
4 3
1 VCC
WCM-2012-900T_4P 2 R865 1 0_0402_5% USB20_N3_C 2
+5VALW (14) USB20_N3 D-
1 (14) USB20_P3 2 R864 1 0_0402_5% USB20_P3_C 3 D+
4 GND
C943
2
PJDLC05_SOT23-3
USB20_N2_C 470P_0402_50V7K 5
+USB_VCCC 2 D20 GND1
6 GND2
U37 USB20_P2_C @ 7 GND3
1 GND OUT 8 8 GND4
2
PJDLC05_SOT23-3
2 IN OUT 7
C944 2 1 0.1U_0402_16V4Z 3 6 D21 SUYIN_020173GR004M58BZL
m
USB_ON# 4 IN OUT @ ME@
EN OC# 5 USB_OC1# (14)
APL3510BKI_SO8 1
ESATA and USB Conn.
1
2 Low Active C945 2
@ 1000P_0402_50V7K
+USB_VCCC
2
W=80mils
1
EMI request +USB_VCCC
ru
1
1
C947 + C946 JESAT1 ME@
220U_6.3V_M 470P_0402_50V7K 0_0402_5% 1 USB
VBUS
2 R866 1 USB20_N2_C 2
( 220U 6.3V M 6.3X4.2 )*1=(SF000002Y00)
2 (14)
2
(14)
USB20_N2
USB20_P2 2 R867 1 USB20_P2_C
0_0402_5%
3
4
D-
D+
USB
GND
A+ = RXP
Fo
5 GND
R768 1 ESATA@2 0_0402_5% SATA_ITX_DRX_P2_R 6
(15) SATA_ITX_DRX_P2
(15) SATA_ITX_DRX_N2
ESATA@
R769 1
ESATA@
2 0_0402_5% SATA_ITX_DRX_N2_R 7
8
A+
A-
ESATA
12
A- = RXN
0.01U_0402_16V7K 2 GND SHIELD
1 C948 SATA_DTX_C_IRX_N2_C R770 1 ESATA@2 0_0402_5% SATA_DTX_C_IRX_N2_R 9 13
(15) SATA_DTX_C_IRX_N2
(15) SATA_DTX_C_IRX_P2
0.01U_0402_16V7K 2 1 C949 SATA_DTX_C_IRX_P2_C R771 1
ESATA@
2 0_0402_5% SATA_DTX_C_IRX_P2_R 10
B-
B+
SHIELD
SHIELD 14 B- = TXN
11 15
ESATA@
R902 2 ESATA@1 10K_0402_5% ESATA@
GND SHIELD
FOX_3Q38111-RB1C3-7HC
B+ = TXP
+3VS
(14) SATA_DET# 1 R942 2 SATA_DET#_R
+5VALW 0_0402_5%
1
BT MODULE CONN er 2
C998 R943
1
2
20100728 100K_0402_5% +3VS
C950
@ 0.1U_0402_16V4Z
2
2 R941 1 1 R773 2 1 2
2
0_0402_5% 100K_0402_5%
yb
1
2
2 R884 1 2 IN 30mils U38
0_0402_5% Q99 3 1 7 6 C951 C952 R775 R776
GND
1
AP2301GN-HF_SOT23-3 C953 RX_0N VCC
C 2
BT@ SATA_DTX_C_IRX_P2_C 5 9
2 SATA_DTX_C_IRX_N2_C TX_1P D0
(46) BT_LED# 4 TX_1N D1 8
Q101 JBT1
1
2
DTC124EKAT146_SC59-3 1 3 15 SATA_ITX_DRX_P2_R
@ 1 GND TX_0P SATA_ITX_DRX_N2_R R777 R778
2 13 14
OUT
2 GND TX_0N
(14) USB20_P5 3 3 17 GND 0_0402_5% 0_0402_5%
(14) USB20_N5 4 18 12 SATA_DTX_C_IRX_N2_R @ @
BTON_LED 4 GND RX_1N SATA_DTX_C_IRX_P2_R
IN 2 5 7 19 11
1
BT_ACTIVE 5 G1 GND RX_1P
(30) BT_ACTIVE 6 8 21
GND
6 G2 PAD
ACES_87213-0600G SN75LVCP412RTJR_QFN20_4X4
4 ME@ @ 4
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BT/eSATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 33 of 48
A B C D E
ON/OFF switchSW 2 @
1 3
Power Button Power Button Board Conn. 8pin
2 4
SMT1-05_4P +3VALW
6
5
Card Reader/Audio Jack SB CONN
2
TOP Side J11
@ +5VALW
1 2 R779 Pin swap
100K_0402_5%
SHORT PADS JPW RB1 20100810
Bottom Side
1
D22 1 JCR1
ON/OFF# 1 HP_OUTL
2 ON/OFF# (31) (31) NUM_LED# 2 2 (28) HP_OUTL 1 1
(31) CAPS_LED# 3 HP_OUTR 2
3 (28) HP_OUTR 2
ON/OFFBTN# 1 (31,46) PW R_LED# 4 (28) PLUG_IN PLUG_IN 3
4 3
5 5 4 4
3 51_ON# NOVO_BTN# 6 EXT_MIC_L 5
51_ON# (36) 6 (28) EXT_MIC_L 5
ON/OFFBTN# 7 EXT_MIC_R 6
7 (28) EXT_MIC_R 6
CHN202UGP_SOT323-3 8 (28) MIC_JD MIC_JD 7
Change footprint 8 7
8 8
20100812 9 2 R908 1 0_0402_5% USB20_P6_C 9
GND +3VS (14) USB20_P6 9
NOVO_BTN# ON/OFFBTN# 10 2 R909 1 0_0402_5% USB20_N6_C 10
GND (14) USB20_N6 10
11 11
2
ACES_88058-080N 12 12
1
D D23 ME@ 13
.ru
EC_ON Q102 GND
(31,39) EC_ON 2 PJSOT24C 3P C/A SOT-23 14 GND
G 2N7002H_SOT23-3 @
S ACES_88058-120N
3
2
1
R780 20100812
10K_0402_5%
L67 @
USB20_P6 1 2 USB20_P6_C
1
1 2
USB20_N6 4 3 USB20_N6_C
EMI REQUEST 1ST = SCA00000E00 4 3
m
W CM-2012-900T_4P
2ST = SCA00000R00
EMI request
+3VALW
2
ru
R783
100K_0402_5% +5VALW
D25
1
NOVO# 2
(31) NOVO# +USB_VCCA
1 NOVO_BTN# U39
1 GND OUT 8 RIGHT USB PORT X1
51_ON# 3 C954 0.1U_0402_16V4Z 2 7
Fo
IN OUT
2 1 3 IN OUT 6
CHN202UGP_SOT323-3 (31,33) USB_ON# USB_ON# 4 5
Change footprint EN OC# USB_OC2# (14)
20100812 APL3510BKI_SO8
1
C957
@ 1000P_0402_50V7K
2
1 +USB_VCCA
W=80mils
1
JUSB3
1
1 2 R868 1 0_0402_5% USB20_N4_C 2
yb
(14) USB20_N4 2
C956 + 2 R869 1 0_0402_5% USB20_P4_C 3
(14) USB20_P4 3
220U_6.3V_M C955 4
470P_0402_50V7K 4
5 G5
2 2
6 G6
ACES_85205-04001
ME@
(220uF_6.3V_5.8L_ESR17m)*1=(SF000001500)
2
PJDLC05_SOT23-3
D27
@
C
L66 @
USB20_P4 1 2 USB20_P4_C
1
1 2
USB20_N4 4 3 USB20_N4_C
4 3
W CM-2012-900T_4P
EMI request
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Other IO/USB (right)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 34 of 48
A B C D E
Change from SB00000GV00 to SB548000210 Change from SB00000GV00 to SB548000210 Change footprint
20101125 20101125 20100812
+5VALW TO +5VS Change footprint +3VALW TO +3VS Change footprint +1.5V to +1.5VS
20100812 20100812 +1.5V Q126 +1.5VS
1
8 1 8 1 @
1 7 2 1 1 1 7 2 1 1 C958 AP2301GN-HF_SOT23-3 C959 C960
1
6 3 6 3 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R784
2
C961 C962 C963 C964 C965 C966 2 2 2 470_0603_5%
5 5
10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R785 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R786 @
2
1 2 2 2 2 2 2 1
470_0603_5% 470_0603_5%
4
@ @
1 2
1 2
1
+VSB +VSB +5VALW D
D D
2 SUSP
2 SUSP 2 SUSP G
1
G G S Q105
3
S Q103 S Q104 2N7002_SOT23
3
R787 2N7002_SOT23 R788 2N7002_SOT23 100K_0402_5% @
20K_0402_5% @ 47K_0402_5% @ R789
2
5VS_GATE2 R790 15VS_GATE_R 3VS_GATE 1 2 1.5VS_GATE
2
1 1 R792 1 1
1
1
D 10K_0402_5% D R791 D 75K_0402_5% @
SUSP 2 Q106 C967 SUSP 2 0_0402_5% C968 SUSP# 2 Q108 C969 C970
G 2N7002H_SOT23-3 0.1U_0603_25V7K G Q107 @ 0.1U_0603_25V7K G 2N7002H_SOT23-3 0.1U_0603_25V7K
.ru
S 2 S 2N7002H_SOT23-3 2 S 2 2
3
3
Change footprint 0.1U_0603_25V7K
20100812 Change footprint Change footprint
20100812 20100812
Change footprint
20100812
+1.1ALW to +1.1VS Change from SB00000GV00 to SB548000210
+1.1VALW U43 +1.1VS 20101125 +RTCBATT +5VALW
DMN3030LSS-13_SOP8L-8 +5VALW
8 1
1
1 7 2 1 1
1
@
m
2 6 3 2
C971 5 C972 C973 R798 R799 @
10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R801 100K_0402_5% 100K_0402_5% R800
2 2 2 470_0603_5% 100K_0402_5%
4
2
@ SUSP
(42) SUSP
2
2
SYSON#
1 Q114 Q115
1
+5VALW D DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
2 SUSP @
OUT
OUT
ru
G
1
S Q116
3
GND
GND
2
1.1VS_GATE
3
2
1
1
D R803
SUSP C975
Fo
2 0_0402_5%
G Q117 0.1U_0603_25V7K
S 2N7002H_SOT23-3 @ 2
3
Change footprint
20100812
3 3
yb
R793 R794 R797 R796
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @ @ @
1 2
1 2
1 2
1 2
D D D D
2 SUSP 2 SYSON# 2 SUSP 2 SUSP
G G G G
S Q109 S Q110 S Q113 S Q112
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 35 of 48
A B C D E
5 4 3 2 1
DC030006J00 VIN
Precharge detector
PF101 PL101 15.97V/14.84V FOR
4 APDIN
7A_24VDC_429007.WRML
1 2 APDIN1
SMB3025500YA_2P
1 2
ADAPTOR
4
3 3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
2
2
1
D D
1
1 PreCHG PQ102
TP0610K-T1-E3_SOT23-3
2
@ 4602-Q04C-09R 4P P2.5
PC101
PC102
PC103
PC104
PR102
JDCIN1 1K_1206_5% PD102
1 2 2 1 3 1
VIN
PR103 @ LL4148_LL34-2
1K_1206_5% @
1 2
100K_0402_1%
1
1
100K_0402_1%
PR104 @
PR105
PR106
1K_1206_5%
2
1 2
.ru
PR107 @
2
1K_1206_5%
@
1 2
VIN
@ @
@
100K_0402_1%
1
PD101
PR108
LL4148_LL34-2
1
PQ103
1
PD104 PD103 PDTC115EU_SOT323-3
1 2
LL4148_LL34-2 2 @
2 1 (31,38) ACOFF 1 2
m
BATT+
1
3 PQ104
PR101 PR109 (39) +5VALWP @ PDTC115EU_SOT323-3
68_1206_5% 68_1206_5% RB715F_SOT323-3 @
PQ101 VS 2
3
C TP0610K-T1-E3_SOT23-3 C
2 @
2
N1 3 1
0.22U_0603_25V7K
3
1
ru
1
PR110 PC106
PC105
100K_0402_5% 0.1U_0603_25V7K
B+
2
PR112
2
22K_0402_5% PR111
1 2 2.2M_0402_5%
(34) 51_ON#
2 1
VL
Fo
VS
499K_0402_1%
@
1
0.01U_0402_25V7K
PR113
1
1
PC107
PR114
100K_0402_1%
2
@
2
(37,39) MAINPWON
8
PD105 PU101A
2 LM393DG_SO8 3
P
@ +
1 1 O
205K_0402_1%
499K_0402_1%
0.01U_0402_25V7K
3 -
2
1
- + +RTCBATT
er
1
1000P_0402_50V7K
PR115
PR116
PC110
JRTC1 PR117 PR118 (38) ACON @ RB715F_SOT323-3 @
4
1
1
560_0603_5% 560_0603_5%
PC109
2 1 +RTCBATT 1 2 1 2 PC108
+CHGRTC
2
B 0.1U_0603_25V7K @ B
PRG++ 2
2
ML1220T13RE @
@ @
45@
2N7002W-T/R7_SOT323-3
yb
1 2 PR119 PR120
+3VLP (38) @ PACIN
1
34K_0402_1% D PQ105 47K_0402_5%
@
2 1 2 2 1
PD106 6251VREF G
1
RB751V-40_SOD323-2 S
3
PQ106
2
@ @ PDTC115EU_SOT323-3
PR121 @
2
@
66.5K_0402_1%
+5VALWP
1
C
3
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / Vin Detector /Pre-charge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 36 of 47
5 4 3 2 1
5 4 3 2 1
1
6
6
1
7 PC201 PC202
7
100_0402_1%
100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K VL
2
GND
9
GND
VL
PR201
PR202
TYCO_1775789-1
2
2
@
2
PC203 PR203 PR204
0.1U_0603_25V7K 10K_0402_1% 21.5K_0402_1% PR205
2
<BOM Structure> @ 100K_0402_1%
.ru 1
2
PU201
1
EC_SMB_CK1 (31) 1 VCC TMSNS1 8
2
2 GND RHYST1 7
PR206
EC_SMB_DA1 (31)
3 6 9.76K_0402_1%
OT1 TMSNS2
<BOM Structure>
@ 47K_0402_1%
1 2 +3VALW 4 5
1
OT2 RHYST2
2
PR207
1
PR208
6.49K_0402_1% G718TM1U_SOT23-8
<BOM Structure> PH201
100K_0402_1%_TSM0B104F4251RZ
m
1 2 A/D
1
BATT_TEMP (31)
PR209 <BOM Structure>
2
10K_0402_5%
MAINPWON (36,39)
<BOM Structure>
1
C C
PH202
@ 100K_0402_1%_TSM0B104F4251RZ
2
ru
VS
Fo
+3VALW +3VS
0.01U_0402_25V7K
1
PC204
VMB2
PR210 PR211
2
100K_0402_1% 10K_0402_1%
PR212 PR213 <BOM Structure> <BOM Structure>
2
649K_0402_1% 5.1M_0402_5%
1
1 2 BATT_OUT (38)
PQ202
PR214 PQ201 TP0610K-T1-E3_SOT23-3
8
10K_0402_1% 2N7002KW_SOT323-3
er
1
D
1 2 5
P
+
7 2 B+ 3 1 +VSBP
PR215 O G
6
-
G
2
100K_0402_1%
0.22U_0603_25V7K
B PU101B B
232K_0402_1% S
3
1
LM393DG_SO8
4
1
PR216
PC205
PQ204 PC206
1
D 2N7002KW_SOT323-3 0.1U_0603_25V7K
1
2
2
2
(31) BATT_LEN#
yb
2 1 G PR218
6251VREF VL
S 22K_0402_1%
3
PR217 1 2
10K_0402_1%
2
<BOM Structure>
PR219
100K_0402_1%
PR220
1
1
1K_0402_5% D PJ201
1 2 2 PQ203 @ JUMP_43X39
(39,40) SPOK
G 2N7002W-T/R7_SOT323-3 1 1
+VSBP 2 2 +VSB
C
1U_0402_6.3V6K S
3
1
PC207
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 37 of 47
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407A_SO8 SI4459A_SO8
10U_0805_25V6K
PR302
VIN 8
7
1
2
1
2
8
7 0.02_1206_1% CHG_B+ @
PL302
1
PC325
6 3 3 6
5 5 1 4 1 2 PQ303
AO4407A_SO8
10U_0805_25V6K
2
5600P_0402_25V7K
2 3 1 8
VIN
4
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
2 7
PC326
PC324
3 6
2200P_0402_50V7K
@
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
5
1 Structure>
1 Structure>
D D
2
47K_0402_5%
2
1
1
PC302
200K_0402_1%
PR303
0.1U_0603_25V7K
PC305
4
1
PR343
PC303
PC304
PC306
47K_0402_1% CSIN DISCHG_G
PC301
PR304
PQ304 @ CSIP
<BOM
<BOM
2
2
PDTA144EU @ PR305
1
PQ305B 47K_0402_1%
VIN PreCHG
2
2
2 2N7002KDW -2N_SOT363-6 1 2
3
PQ305A @ VIN
2ACOFF-1
191K_0402_1%
2
1
1
2 5 @ PR306 PR307
1DISCHG_G-1
BATT_OUT (37)
PR301
PQ306 191K_0402_1% 10K_0402_1%
1
2
PDTC115EU_SOT323-3 2N7002KDW -2N_SOT363-6 PD303
4
@ 1SS355_SOD323-2 PR308
1
.ru
BATT_ON 2 P2-1 PD301 200K_0402_1%
2
RB751V-40_SOD323-2 ACSETIN
1 1
1
1
PR309 PQ307
1
0_0402_5% 6251_VDD PR310 PDTC115EU_SOT323-3 PD304
3
2.2U_0603_6.3V6K
<BOM Structure>
1 (31) FSTCHG 10_1206_5% 1000P_0402_25V8J 2 1 2
2
6
2
PC308
2
1
150K_0402_1%
PR312
2200P_0402_50V7K
2
2
PR313
100K_0402_5%
PQ308A 10K_0402_1% PU301 PC309 PQ310
1
PC310
2 2N7002KDW -2N_SOT363-6 0.1U_0603_25V7K
12
1
D D
PR314
6251_DCIN 2N7002W -T/R7_SOT323-3
0.1U_0603_25V7K
1 VDD DCIN 24 2 1
1
BATT_OUT 2 PACIN
100K_0402_1%
2
m
1
1
PC311
G @ G
1
PR315
ACSETIN ACPRN @
BATT_ON
S 2 23 S
3
3
PQ309 ACSET ACPRN PR316
2N7002W-T/R7_SOT323-3
2
P2-2
5
6
7
8
C 6251_EN 6251_CSON CSON C
3 EN CSON 22 1 2
1
D
PQ311
PC312
AO4466L_SO8
3
PQ312
0.047U_0402_16V7K ACPRN 2
PR318 CELLS 4 21 6251_CSOP 1 2 CSOP G
2
47K_0402_1% PQ308B CELLS CSOP PR317 @ S
ru
3
PACIN 1 2 5 2N7002KDW -2N_SOT363-6 PC313 6800P_0402_25V7K 20_0402_5% 4
(36) PACIN
1 2 6251_ICOMP 5 20 6251_CSIN 2 1
ICOMP CSIN
2
PC314 PR319
4
3
2
1
VCOMP CSIP
1
5
6
7
8
Fo
1 2 2 (31) ADP_I 100_0402_1% 2 3
(31,36) ACOFF
1
PQ314
ACOFF-1 DH_CHG
AO4466L_SO8
4.7_1206_5%
8 VREF UGATE 17
2
PR325
PR324 PR326 PR327 PC317
10U_0805_25V6K
10U_0805_25V6K
1 2 6251VREF
10k_0402_5% PR342 154K_0402_1% PC316 0_0603_5% 0.1U_0603_25V7K
16251_SN
0_0402_5% 2
<BOM 1
Structure> 0.1U_0402_16V7K 6251_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
3
1
PC323
PC319
PR328 PD302
10U_0805_25V6K
4
1
21K_0402_1%
2N7002KW_SOT323-3
0.01U_0402_25V7K
1
1 2 6251_ACLIM 10 15 6251_VDDP
2
ACLIM VDDP
1
PC318
PQ315 6251VREF RB751V-40_SOD323-2
2
1
D
PC320
PR329 26251_VDD
680P_0603_50V7K
1
3
2
1
1
PC321
BATT_OUT 2 100K_0402_1% 6251_VADJ
11 14 DL_CHG
2
VADJ LGATE
1
G PR331 PR330
2
S 2.2K_0402_1% 4.7_0402_5%
3
er 12 13 PC322
2
GND PGND 4.7U_0805_6.3V6K
2
ISL6251AHAZ-T_QSOP24
B PR332 B
Connect to EC A/D Pin. 15.4K_0402_1%
1 2
(31) CHGVADJ
yb 1
<BOM Structure>
PR333
CHGVADJ=(Vcell-4)/0.10627 31.6K_0402_1%
6251_VDD 6251_VDD
Vcell CHGVADJ
2
4cell : VDD
2
6251_VDD
4V 0V DIS CP mode (65W*85%) PR334 PR335
4.2V 1.882V Vaclim=2.39*((2.2K//152K)/(2.2K//152K+21K//152K))=0.25136V PR337 3cell : GND @ 100K_0402_1% @ 100K_0402_1%
10K_0402_1%
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
1
1
where Vaclim=0.25136V, Iinput=2.76293A
C
PR338 CELLS
PR336 10K_0402_1%
3
PR328=21K 47K_0402_1%
CC=0.25A~3A PACIN PR339
2
1 2
PR331=2.2K 0_0402_5%
IREF=1.016*Icharge 2 5 2 1
1
2
IREF=0.254V~3.048V PDTC115EU_SOT323-3 @ 0_0402_5%
4
PR341 (31) BATT_SEL_EC
VCHLIM need over 95mV UMA CP mode (40W*85%) ACPRN 2
(39) ACPRN 14.3K_0402_1%
2
PR328=12.1K(SD034121280)
PR331=31.6K(SD034316280)
PR302=50mohm(SD00000CI10) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 38 of 47
5 4 3 2 1
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205 PJ402
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118
1U_0603_10V6K
D D
1
PJ403
PC402
+5VALW P 2 1 +5VALW
2
2 1
@ JUMP_43X118
PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2
.ru
PR403 PR404
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
Typ: 175mA
PJ401
B+ 2 1 +3VLP
2 1
ENTRIP2
ENTRIP1
@ JUMP_43X118 PR405 PR406
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
110K_0402_1% 121K_0402_1%
680P_0402_50V7K
0.1U_0603_25V7K
@
PC401
PC403
PC410
1 2 1 2
4.7U_0805_10V6K
1
1
PC404
PC405
PC406
PC422
PC407
PC408
PC409
m
2
5
6
7
8
PU401
2
2
PQ402
PC411
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
C C
25 P PAD
PQ401
2
4 AON7408L 4
7 24
ru
VO2 VO1 SPOK (37,40)
8 23 PR408 PC413
PR407 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K AO4406AL_SO8
1
2
3
3
2
1
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
0_0603_5% BOOT2 BOOT1
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% PC412 UG_3V 10
VFB=2.0V 21 UG_5V 4.7UH_PCMB104E-4R7MS_10A_20%
PL401 0.1U_0603_25V7K UGATE2 UGATE1 PL402
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
Fo
1
1
LG_3V LG_5V
4.7_1206_5%
4.7_1206_5%
12 LGATE2 LGATE1 19
5
6
7
8
PR409
PR410
SKIPSEL
PR411 @
VREG5
0_0402_5%
GND
VIN
NC
MAINPW ON 2 RT8205EGQW _W QFN24_4X4 PQ404
EN
1 1 1
2
2
4
PC414 + <BOM Structure> 4 <BOM Structure> PC416 +
13
14
15
16
17
18
1
1
PR412
680P_0603_50V7K
680P_0603_50V7K
150U_B2_6.3VM_R45M 499K_0402_1% AO4456_SO8 150U_B2_6.3VM_R45M
PC415
PC417
2 2
1 2
2
1
2
3
2
B+
3
2
1
PQ403
AON7702L er 100K_0402_1%
1U_0603_10V6K
PC418
1
VL
1
PR413
PC419
Typ: 175mA
4.7U_0805_10V6K
B B
2
ENTRIP1 ENTRIP2
2
2
RT8205_B+
6
1
PQ405B
yb
PQ405A 2N7002KDW -2N_SOT363-6
0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2VREF_8205
2
PC420
(36,37) MAINPWON
1
PR414
0_0402_5%
2 1
PR415
100K_0402_1%
C
2 1
VL
+5VALWP
Iocp=19.306A
1
2N7002W-T/R7_SOT323-3
PQ406 +3.3VALWP
PR416 PDTC115EU_SOT323-3
Iocp=5.81A
1
200K_0402_1% D
PQ407
2 1 2 1 2 2
ACPRN G VS
S PR417
40.2K_0402_1%
2.2U_0603_10V7K
3
A A
1
1
PR418
PC421
(2)SMPS2=375KHZ(+3VALWP)
3
2
(31,34) EC_ON
2
2 PQ408
PDTC115EU_SOT323-3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
3VALWP/5VALWP
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 39 of 47
5 4 3 2 1
5 4 3 2 1
PJ501
1.1VALW_B+ 2 1
2 1 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC502
PC501
5
6
7
8
2
D D
PR501
255K_0402_1% 4 PQ501
1 2
PR502 PR503
0_0402_5% 2.2_0603_5%
1 2 1 2 AO4466L_SO8
3
2
1
(37,39) SPOK
PJ502
1 BST_1.1V
PL501
15
14
PC504 +1.1VALWP 2 1 +1.1VALW
2 1
1
PC503 PU501 2.2UH_FMJ-0630T-2R2 HF_8A_20%
@.1U_0402_16V7K 1 2 1 2 @ JUMP_43X118
EN/DEM
BOOT
NC
+1.1VALWP
2
2 13 DH_1.1V 0.1U_0603_25V7K
.ru
TON UGATE
4.7_1206_5%
PR505 3 12 LX_1.1V
VOUT PHASE
5
6
7
8
PR504
100_0603_1% 1
220U_6.3V_M
+5VALW 1 2 4 11 1 2 +5VALW PQ502
VDD CS
PC505
PR506 + +1.1VALWP
2
5 10 15K_0402_1%
FB VDDP Iocp=7.21A
1
1
6 9 DL_1.1V 4 2
PGOOD LGATE
PGND
680P_0603_50V7K
PC506
GND
PC507
4.7U_0603_6.3V6K
2
2
PC508
RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K AO4712L_SO8
3
2
1
m
PR507
P_R
C C
1 2
1
PR508
ru
10K_0402_1%
2
Fo
PJ503
1.0V_B+ 2 1
2 1 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC509
PC510
5
6
7
8
2
PQ503
PR509
100K_0402_1%
1 2 PR510
(31,35,42,43) SUSP#
B
PR511
100K_0402_1%
1 2
255K_0402_1%
1 2 erPR512
0_0603_5%
1 2
4
AO4406AL_SO8
+1.0VSP 2
PJ504
2
@ JUMP_43X118
1
1 +1.0VS
B
3
2
1
(18,20,43) VGA_PWRGD
1
@
@ PR518
1
PL502
15
14
47K_0402_5% PC512
1
BOOT
NC
+1.0VSP
2
yb
2 13 DH_1.0V 0.1U_0603_25V7K Iocp=14.74A
TON UGATE
4.7_1206_5%
@ PR513
PR514 3 12 LX_1.0V
VOUT PHASE
5
6
7
8
100_0603_1% 1
220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS
PC513
PR515 +
2
5 10 10K_0402_1%
FB VDDP PQ504
1
1
6 9 DL_1.0V 4 2
PGOOD LGATE
PGND
680P_0603_50V7K
PC514
GND
@ PC515
4.7U_0603_6.3V6K
2
2
PC516
C
RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K
7
3
2
1
AO4456_SO8
PR516
3.74K_0402_1%
1 2
1
PR517
10K_0402_1%
A A
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VALWP/+1.0VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 40 of 47
5 4 3 2 1
5 4 3 2 1
PJ601
1.5_51117_B+ 2 1
2 1 B+
5
6
7
8
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC602
PC603
D PQ601 @ PC604
@PC604 D
680P_0402_50V7K
2
PR603
267K_0402_1% 4
PR601 1 2
0_0402_5%
(31,35,42) SYSON 1 2
AO4406AL_SO8
3
2
1
2
47K_0402_5%
PR604 PC605 PL601
PR605
2.2_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%
15
14
1
1
PU601 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP
PC601 @
EN/DEM
BOOT
NC
.1U_0402_16V7K
.ru
1
2
2 13 DH_1.5V
TON UGATE
1
3 12 LX_1.5V 1
VOUT PHASE
5
6
7
8
PQ602 PR606
4 VFB=0.75V 11 +5VALW 4.7_1206_5% + PC606
VDD CS 220U_B2_2.5VM_R15M
5 10
2
FB VDDP 2
6 9 DL_1.5V 4
PGOOD LGATE
PGND
PR607
GND
1
9.76K_0402_1%
100_0603_5% PC608
PR608
+5VALW 1 2 @ PC609
@PC609 PC607 680P_0603_50V7K
47P_0402_50V8J RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K
3
2
1
2
m
1 2 AO4456_SO8
1
2
PC610
4.7U_0603_6.3V6K
2
C C
<BOM Structure>
PR609
1 2
ru
10K_0402_1%
1
PR610
10K_0402_1%
2
Fo
PJ602 +1.5V
+1.5VP 2 1
2 1
@ JUMP_43X118
+1.5VP
Iocp=15.6A
B
er B
yb
C
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 41 of 47
5 4 3 2 1
5 4 3 2 1
+1.5V
D D
2
PJ701
2
JUMP_43X79
@
1
1
PU701
1
VIN VCNTL
6 +3VALW
PC701 2 5
GND NC
1
4.7U_0805_6.3V6K PJ702
1
3 7 PC702 +0.75VSP 2 1 +0.75VS
PR702 VREF NC 2 1
2
@ PR709
@PR709 1K_0402_1% 4 8 1U_0603_10V6K @ JUMP_43X118
.ru
0_0402_5% VOUT NC
1 2 9
2
(31,35,41) SYSON TP
PQ701
2N7002W-T/R7_SOT323-3 G2992F1U_SO8
0.1U_0402_16V7K
PR701
+0.75VSP
1
1
D
PC705
PC706
0_0402_5%
1K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
PC703
(35) SUSP 1 2 2
1
G
2
1
3 S PR703
@ PC704
2
1U_0402_6.3V6K
2
m
C C
ru
Fo
PU702 PL701
4
+5VALW 2
PJ703
1 10 2 LX_1.8V er 1UH_FMJ-0630T-1R0 HF_11A_20%
1 2 +1.8VSP 2
PJ704
1 +1.8VS
PG
2 1 PVIN LX +1.8VSP 2 1
68P_0402_50V8J
@ JUMP_43X118 9 3 @ JUMP_43X118
PVIN LX
1
1
680P_0603_50V7K 4.7_1206_5%
B B
1
1
PC708
PC707 8
SVIN
PR704
22U_0805_6.3VAM PR705
6 30K_0402_1%
2
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
1 2
EN
1
NC
NC
TP
PC710
PC711
yb
FB=0.6Volt
PC709
11
2
EN_1.8V
(31,35,40,43) SUSP# 1 2
2
PR706
0.1U_0402_10V7K
62K_0402_1%
2
PC712
SY8033BDBC_DFN10_3X3
1
PR707
1M_0402_5%
FB_1.8V
2
1
1
C
PR708
14.7K_0402_1%
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VP/1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 42 of 47
5 4 3 2 1
5 4 3 2 1
PD804
@ RB751V-40_SOD323-2
1 2
+3VS
PR823
100K_0402_1%
D (13,20,21) PE_GPIO1 2 1 D
2
PR803
PR802 205K_0402_1% PJ801
PD805 @ 1 2 @ 10K_0402_5% VGA_TON 1 2 VGA_IN 2 1 B+
RB751V-40_SOD323-2 2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ PR801 PD801 @ JUMP_43X79
5
100K_0402_1% 1SS355_SOD323-2
TPCA8065-H_SOP-ADV8-5
1
PC802
PC803
2 1 VGA_EN 1 2 +5VALW
(20,21) PX_MODE
PQ801
@ PR804
2
1 2 PC801 @ PR831 PR805
(31,35,40,42) SUSP# PC804
0.1U_0402_16V7K 47K_0402_5% 0_0603_5% 4
2
100K_0402_1% BST_VGA 1<BOM Structure>
2BST_VGA-1
1 2
1
0.1U_0603_25V7K
.ru
PL801
15
14
3
2
1
1
PU801 0.56UH +-20% PCMC104T-R88MN 20A
1 2
EN/DEM
NC
BOOT
+VGA_COREP
2 13 UG_VGA
TON UGATE
4.7_1206_5%
PR808 3 12 SW _VGA
VOUT PHASE
PR807
100_0603_1%
330U_6.3V_M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
TPCA8059-H_SOP-ADVANCE8-5
+5VALW 1 2 VGA_V5FILT 4 11 VGA_TRIP
1 2 +5VALW
VDD CS
1
+
PC805
PC807
PC808
PC809
PR806
1VGA_SNB
2
+3VS
PQ802
VGA_FB 5 10 9.1K_0402_1%
FB VDDP
1 2
2
LG_VGA 2
6 9 4
m
PGOOD LGATE
PGND
PC806
GND
4.7U_0603_6.3V6K PR824
680P_0603_50V7K
1
PC811
<BOM Structure> 100K_0402_1%
RT8209BGQW _W QFN14_3P5X3P5 PC810
3
2
1
2
C PR832 4.7U_0805_6.3V6K C
2
(18,20,40) VGA_PW RGD 1 2 <BOM Structure>
PC812
0_0402_5% @ 47P_0402_50V8J
1 2
ru
1 2
PR809
2K_0402_1%
1 2
+3VALW PR810
10K_0402_1%
PR811
30K_0402_1%
1
Fo
10K_0402_1%
1 2
PR812
GVID1-2 PJ802
6
PR813 2 1
10K_0402_1% +VGA_COREP 2 1 +VGA_CORE
2
2N7002KDW -2N_SOT363-6 PR814 PR815 GPU_VID0 GPU_VID1 Core Voltage Level PJ803
1
@ 10K_0402_5% 8.66K_0402_1% 2 1
PC813 2 1
2
10K_0402_1%
erGVID0-2
4
PR817 1 0 0.95V
1
10K_0402_1%
3K_0402_5%
PR818
+VGA_COREP
6
B 0 0 1.12 V Iocp=23.38A
B
2
+1.5VGS
2
2 1GVID0-1 2 PQ804A
PJ804
PR819 PC814 2N7002KDW -2N_SOT363-6 +5VALW
3
1
PQ804B 10K_0402_1% 0.022U_0402_16V7K 2 1
yb
+VGA_PCIEP +1.0VGS
1
1
@ 10K_0402_5% JUMP_43X79
2
+5VALW JUMP_43X79
2 1 5 @
(19) GPU_VID0
1
2
PR821 PC815 @
2
1
2
PR822 2
3K_0402_5% @ RB751V-40_SOD323-2
1
1 2
1
PR825 @ PC816
2
@ 0_0402_5% 4.7U_0805_6.3V6K
6
PR826 PU802
2
C
@ 40.2K_0402_1% 5
VCNTL
2
PE_GPIO1 VIN
(13,20,21) PE_GPIO1 1 2 7 POK
4 @ +VGA_PCIEP
VOUT
PR829 3
VOUT
1
@ 40.2K_0402_1%
22U_0805_6.3V6M
PC818
SUSP# 1 2 8 2
EN FB
1
GND
2
1
PC819
9 1.15K_0402_1%
PD803 PR827 VIN
2
1 2 @ 47K_0402_5% APL5912-KAC-TRL_SO8 VGA_PCIE 1.0V 1.1 V
2
1
2
@ RB751V-40_SOD323-2 @ PC817
1
@ 0.01U_0402_25V7K
A @ PR828 4.53K 3K A
PR828
4.53K_0402_1% @
@
2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 43 of 47
5 4 3 2 1
A B C D E
PL901
CPU_B+ HCB2012KF-121T50_0805
PC901 2 1 B+
33P_0402_50V8J
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 1 1 1
5
6
7
8
PC923
PC903
68U_25V_M_R0.36
68U_25V_M_R0.36
+ +
1
1
PC904
2 1 2 1
PC905
PR901 PC902 2 2
2
2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 PQ901
PR902 AO4466L_SO8
1 2_0603_5% 1
1 2 PC906 PL902
+5VS 1000P_0402_50V7K 3.3UH_PCMB104E-3R3MS_11A_20%
3
2
1
2 1 PHASE_NB 1 2 +APU_CORE_NB
PR903
5
6
7
8
1
PC907 PR904 2.2_0603_1%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PQ902 @PR905
2 1 4.7_1206_5% 1
2
@ PR907 PC908
10_0402_5% 0.22U_0603_25V7K + PC909
1 2
1 2 +APU_CORE_NB LGATE_NB 4 220U_D2_4VM
1 2 PR908 @ PC910
CPU_B+ 2
0_0402_5% 680P_0603_50V7K
PR906 2 1
2
APU_VDDNB_RUN_FB_H (5)
2_0603_5% PR909 AO4712L_SO8
.ru
3
2
1
+5VS +3VS 0_0402_5%
2 1 APU_VDD0_RUN_FB_L
PR911 1 @ PR9102
1
PC911 27.4K_0402_1% 10_0402_5% CPU_B+
0.1U_0603_25V7K 2 1 PHASE_NB
1
2
PR912 @ PR913 LGATE_NB
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0_0402_5% 105K_0402_1%
TPCA8065-H_SOP-ADV8-5
PHASE_NB
PQ903
2
2
1
1
PC912
PC913
PC914
UGATE_NB
@ PR915
m
PR914 10K_0402_1%
2
105K_0402_1% UGATE0 4
1
48
47
46
45
44
43
42
41
40
39
38
37
2
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
VIN
VCC
PR918 0.36UH_ETQP4LR36WFC_24A_20%
3
2
1
2.2_0603_1%
2
1 36 BOOT_NB BOOT0 1 2 1 2 1 4
(14,31) VGATE OFS/VFIXEN BOOT_NB +APU_CORE
1 2
(14) FCH_PWRGD
ru
@ PR917 100K_0402_5% 2 35 BOOT0 PC915 2 3
PGOOD BOOT0
5
1 2 0.22U_0603_25V7K
1
(13) H_PWRGD_L
PQ904
TPCA8059-H_SOP-ADVANCE8-5
PR919 100K_0402_5% ISL6265_PWROK 3 34 UGATE0
PWROK UGATE0
2
@ PR920
(5) APU_SVD 2 1 4 33 PHASE0 4.7_1206_5% PR922
(5) APU_SVC PR921 SVD PHASE0 9.31K_0402_1%
0_0402_5%2 1 5 32 4
1 2
(31) VR_ON PR923 SVC PGND0 +5VS
1
PR924 PR925 0_0402_5% 6 31 LGATE0 @PC916
@PC916 PC917
21.5K_0402_1% 95.3K_0402_1% ENABLE ISL6265CHRTZ-T_TQFN48_6X6 LGATE0 680P_0603_50V7K 2 1
Fo
2 1 2 1 7 30
3
2
1
2
RBIAS PVCC 0.1U_0603_16V7K
8 29
OCSET LGATE1
1
PC918 2 1
9 28 1U_0603_16V6K LGATE0
VDIFF0 PGND1 PR926
ISN0
ISP0
10 27 5.11K_0402_1%
FB0 PHASE1
11 26
COMP0 UGATE1
12 25
VW0 BOOT1
COMP1
VDIFF1
VSEN0
VSEN1
2 VSEN1
RTN0
RTN1
ISN0
ISN1
ISP0
VW1
ISP1
FB1
+APU_CORE 2
PR927
1
er TP
13
14
15
16
17
18
19
20
21
22
23
24
49
10_0402_5% PR928
3 0_0402_5% ISP0 3
VSEN1
ISN0
(5) APU_VDD0_RUN_FB_H PR929
1
ISN0
ISP0
2 1 VSEN0
0_0402_5%
yb
0_0402_5% +VDDNBP
2 1 RTN0
Iocp~15A
(5) APU_VDD0_RUN_FB_L PR930
2
10_0402_5%
+1.5VS 2 1
PR932
PR931 +CPU_CORE
0_0402_5%
Iocp~15A
1
DIFF_0 VW0
PR933 PC919
255_0402_1% 2200P_0402_25V7K
2 1 2 1 FB_0 2 1 COMP0 2 1
PC920 PC921
180P_0402_50V8J 1000P_0402_50V7K
4 PR934 PR936 4
1K_0402_5% PR935 PC922 6.81K_0402_1%
2 1 2 1 2 1 2 1
54.9K_0402_1% 1200P_0402_50V7K
1
@ PR937
36.5K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
+CPU_CORE/VDDNBP
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PAWGC
Date: Tuesday, November 30, 2010 Sheet 44 of 47
A B C D E
Version Change List ( P. I. R. List ) for Power Circuit
Request
Page# Title Date Issue Description Solution Description
Owner
power sequence 2010/07/30 HW PR701 change to 0 ohm and PC704 non mount.
Add PL302,PC324 and PC325 for EMC Solution. 2010/10/04 EMC change PJ301 to PL302.
Add PC422 for EMC Solution. 2010/10/06 EMC
Add PQ204 for EM6.0 battery learning function. 2010/11/12 PWR
.ru
m
ru
Fo
er
yb
C
INT_KBD Conn.
KSI[0..7]
ME@
ACES_88514-2401
Lid Switch
KSI[0..7] (31)
26 GND2
KSO[0..15] 25 1 2 +VCC_LID R756 1 2 100K_0402_5%
KSO[0..15] (31) GND1 +3VALW
R755 0_0402_5%
KSI1 24 24
2
KSI7 23 S-5711ACDL-M3T1S_SOT23-3
KSO2 C905 1 23
2 @ 100P_0402_50V8J KSO1 C906 1 2 @ 100P_0402_50V8J KSI6 22
VDD
KSO9 22
21 21
KSO15 C907 1 2 @ 100P_0402_50V8J KSO7 C908 1 2 @ 100P_0402_50V8J KSI4 20 1
KSI5 20
19 19 OUTPUT 3 LID_SW # (31)
D KSO6 C909 1 2 @ 100P_0402_50V8J KSI2 C910 1 2 @ 100P_0402_50V8J KSO0 18 C931 D
KSI2 18 0.1U_0402_16V4Z
17 2
GND
KSO8 C911 1 17 2
2 @ 100P_0402_50V8J KSO5 C912 1 2 @ 100P_0402_50V8J KSI3 16 16
KSO5 15 C932
KSO13 C913 1 15
2 @ 100P_0402_50V8J KSI3 C914 1 2 @ 100P_0402_50V8J KSO1 14 U34 10P_0402_50V8J
1
KSI0 14 1
13 13
KSO12 C915 1 2 @ 100P_0402_50V8J KSO14 C916 1 2 @ 100P_0402_50V8J KSO2 12
KSO4 12
11 11
KSO11 C917 1 2 @ 100P_0402_50V8J KSI7 C918 1 2 @ 100P_0402_50V8J KSO7 10
KSO8 10
9 9
KSO10 C919 1 2 @ 100P_0402_50V8J KSI6 C920 1 2 @ 100P_0402_50V8J KSO6 8
KSO3 8
7
KSO3 C921 1 2 @ 100P_0402_50V8J KSI5 C922 1 2 @ 100P_0402_50V8J KSO12
KSO13
6
7
6 +3VALW
Kill Switch
5
.ru
KSO4 C923 1 5
2 @ 100P_0402_50V8J KSI4 C924 1 2 @ 100P_0402_50V8J KSO14 4 4
100K_0402_5% LSSM12-P-V-T-R_3P
KSO11 3 2 R757 1 3
KSI0 C925 1 3 3
2 @ 100P_0402_50V8J KSO9 C926 1 2 @ 100P_0402_50V8J KSO10 2 2
KSO15 1 1 2 2
KSO0 C927 1 1 (31) KILL_SW #_EC 2
2 @ 100P_0402_50V8J KSI1 C928 1 2 @ 100P_0402_50V8J R886 0_0402_5%
JKB1 1 @ 2
(14) KILL_SW # R887 0_0402_5% 1 1
CONN PIN define need double check
+5VS
Kill SW 1
STATUS
m
ZZZ ZZZ1 ZZZ2 ZZZ3
To TP/B Conn. 1,2(LOW) OFF
C
2,3(HI) ON C
ME@
C933 ACES_88058-060N PCB LA6755P CR2032_0 CR2032_0
8
LED
ru
0.1U_0402_16V4Z GND
7 GND <BOM Structure> <BOM Structure> <BOM Structure>
6 6
TP_CLK 5 LED1
(31) TP_CLK 5
TP_DATA 4 White
(31) TP_DATA 4
1 1 SW /L 3 (31,34) PW R_LED# 1 2 2 1 +5VALW
@ @ SW /R 3 300_0402_5% R763
2 2
C934 C935 1
100P_0402_50V8J 100P_0402_50V8J 1 19-213A-T1D-CP2Q2HY-3T_W HITE
Fo
2 2
JTP1
Orange LED2
BATT_LOW_LED# 1 2 2 1
(31) CHARGE_LED1# +3VALW
470_0402_5% R765
6
5
SMT1-05_4P
PACDN042Y3R_SOT23-3
SW 3 300_0402_5% R764
er BATT_CHG_LED#
White 19-213A-T1D-CP2Q2HY-3T_W HITE
6
5
B SMT1-05_4P @ B
D17 LED3
2 4 Reserve for ESD White
SW /R (30) W LAN_LED# 1 2 1 2 2 1 +5VS
1 3 300_0402_5% R766
RB751V_SOD323
@ 19-213A-T1D-CP2Q2HY-3T_W HITE
yb
SW 4 D18
(33) BT_LED# 1 2
JODD1 RB751V_SOD323
SATA ODD Conn.
1 GND
(15) SATA_ITX_DRX_P1 2 (31) RF_LED# R874 1 2 0_0402_5%
A+
(15) SATA_ITX_DRX_N1 3 A-
4 GND
C875 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5
(15) SATA_DTX_C_IRX_N1 B-
C
1 3 ALLTO_C18518-11305-L
D
A (14) ODD_DA#_FCH A
ME@
G
2
+3VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
14" ONLY
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6755P/7P
Date: Tuesday, November 30, 2010 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1
JKB1
KSI1 1
KSI7 1
2 2
KSI6 3 PCB LA6757P CR2032_0 CR2032_0 CR2032_0 CR2032_0
KSO9 3
4 4
KSI[0..7] KSI4 5
KSI5 5 <BOM Structure> <BOM Structure> <BOM Structure> <BOM Structure> <BOM Structure>
6 6
KSO[0..17] KSO17 C1000 1 2 @ 100P_0402_50V8J KSO0 7
KSI2 7
8 8
KSO16 C1001 1 2 @ 100P_0402_50V8J KSI3 9
KSO5 9
D 10 10 D
KSO2 C905 1 2 @ 100P_0402_50V8J KSO1 C906 1 2 @ 100P_0402_50V8J KSO1 11
KSI0 11
12 12
KSO15 KSO7 C908 1 2 @ 100P_0402_50V8J KSO2 13
KSO4 13
14 14
KSO6 C909 1 2 @ 100P_0402_50V8J KSI2 C910 1 2 @ 100P_0402_50V8J KSO7 15
KSO8 15
16 16
KSO8 C911 1 2 @ 100P_0402_50V8J KSO5 C912 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO13 C913 1 2 @ 100P_0402_50V8J KSI3 C914 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO12 C915 1 2 @ 100P_0402_50V8J KSO14 C916 1 2 @ 100P_0402_50V8J KSO14 21
KSO11 21
22 22
KSO11 C917 1 2 @ 100P_0402_50V8J KSI7 KSO10 23
.ru
KSO15 23
24 24
KSO10 C919 1 2 @ 100P_0402_50V8J KSI6 C920 1 2 @ 100P_0402_50V8J KSO16 25
KSO17 25
26 26
KSO3 KSI5 C922 1 2 @ 100P_0402_50V8J 27 27
28 28
KSO4 C923 1 2 @ 100P_0402_50V8J KSI4 29 31
29 GND
30 30 GND 32
KSI0 C925 1 2 @ 100P_0402_50V8J KSO9 C926 1 2 @ 100P_0402_50V8J
ACES_88514-3001
KSO0 KSI1 C928 1 2 @ 100P_0402_50V8J ME@
m
C C
D17
@
1 2 RF_LED#_R
ru
RB751V_SOD323
D18
@
1 2 R937 1 2 100K_0402_5%
C933 1 2
Fo
R874 0_0402_5% KILL_SW #_R
0.1U_0402_16V4Z
JTP1
1 2
1 R939 0_0402_5%
TP_CLK 1
2 2 1 @ 2
TP_DATA 3 R940 0_0402_5%
SW /L 3
1 1 4 4
@ @ SW /R 5
C934 C935 5
6 6
100P_0402_50V8J 100P_0402_50V8J
2 2
7 GND
8 GND
ACES_88058-060N
ME@
er
3
B B
PACDN042Y3R_SOT23-3
D26
@
yb
1
1 2 ODD_DA#_R
R706 0_0402_5%
6
5
6
5
SMT1-05_4P SMT1-05_4P
2 4 2 4 @ Q118 2N7002_SOT23
SW /L SW /R
1 3 1 3 1 3
D
SW 3 SW 4
G
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
15" ONLY
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6757P
Date: Tuesday, November 30, 2010 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1
.ru
0.2 P23 Delete GND connection of U8.N11 and U8.N12 For new reference circuit
0.2 P21 R344 change to 20K ohms Prevent Q74 damage
0.2 P28 J7 foot-print update Base on DFX request
0.2 P28 Add net CLK_PCI_DB_R and unpop R854 for EMI concern
0.2 P28 Modify PC_Beep circuit Base on vender suggestion
0.2 P23 Delete C421, C422, C431, C432, C433 For new reference circuit
m
0.2 P31 R734 pull-high change to +5VALW For USB ports ACIN leakage
C 0.2 P31 Add BATT_SEL_EC at U33.103 For Battery selection reservation C
ru
0.2 P28 Delete C851, C855 For useless AGND bridge
0.2 P34 Change JP7 to JPWRB1 and JP8 to JCR1 For standard naming
0.2 P34 Del U45, R890 ~ R899, J12, CHR_ON# (U33.70) Deleting USB charge function
0.2 P35 Delete C974 Deleting unnecessary part for +1.1VS
Fo
0.2 P19 Add R945, R946 For HDMI Audio strap
0.2 P13 Delete T79, T80 For layout space needed for SATA calibration
0.2 P28 Add R947, R948 For EMI solution reservation base on vender suggetion
0.2 P28 Delete C857, R694 To delete redundant part base on vender suggestion
0.2 P28 L57 ~ L60 change to 0_0603_5% Base on vender suggestion
0.2 P28 R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO For EMI solution reservation base on vender suggetion
B
0.2
0.2
0.2
0.2
P14
P31
P28
P28
Kill_SW# change from U26.G24 to U26.K1
Add R949, C1002
Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS
Add R953
er Kill_SW# function needs event pin
Requirement of implementing SUSCLK
For customer request (PWR consumption)
For PC Beep circuit
B
0.2 P29 Add R954, R955 For customer request (PWR consumption)
yb
0.2 P13 Add C1003, U48, R956, R957 For PX GPU_RST# function
P18 Delete R556, R841, R889, D28
0.2 P09 Add R961 and R962 For DDR SO-DIMMB strap pin reservation
0.2 P05 Delete T74, T75 For layout limitation
0.3 P29 change +5V_ODD to +5VS_ODD For better net name
P46
0.3 P32 R760 change to 100ohm bead and R761 change back to 15ohm resistor For correct EMI solution
0.3 P21 U47 change to SB00000GV00 footprint For correct symbol
A A
0.3 P05 R958 change to HDMI@ and R422 change to nonHDMI@ For SKU without HDMI function
0.3 P21 Add PX_MODE off page For design correction
Change footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR1
: For cost down purpose to change parts Size Document Number Rev
20100812 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6755P
Date: Tuesday, November 30, 2010 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1
.ru
0.2 P23 Delete GND connection of U8.N11 and U8.N12 For new reference circuit
0.2 P21 R344 change to 20K ohms Prevent Q74 damage
0.2 P28 J7 foot-print update Base on DFX request
0.2 P28 Add net CLK_PCI_DB_R and unpop R854 for EMI concern
0.2 P28 Modify PC_Beep circuit Base on vender suggestion
0.2 P23 Delete C421, C422, C431, C432, C433 For new reference circuit
m
0.2 P31 R734 pull-high change to +5VALW For USB ports ACIN leakage
C 0.2 P31 Add BATT_SEL_EC at U33.103 For Battery selection reservation C
ru
0.2 P28 Delete C851, C855 For useless AGND bridge
0.2 P34 Change JP7 to JPWRB1 and JP8 to JCR1 For standard naming
0.2 P34 Del U45, R890 ~ R899, J12, CHR_ON# (U33.70) Deleting USB charge function
0.2 P35 Delete C974 Deleting unnecessary part for +1.1VS
Fo
0.2 P19 Add R945, R946 For HDMI Audio strap
0.2 P13 Delete T79, T80 For layout space needed for SATA calibration
0.2 P28 Add R947, R948 For EMI solution reservation base on vender suggetion
0.2 P28 Delete C857, R694 To delete redundant part base on vender suggestion
0.2 P28 L57 ~ L60 change to 0_0603_5% Base on vender suggestion
0.2 P28 R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO For EMI solution reservation base on vender suggetion
B
0.2
0.2
0.2
0.2
P14
P31
P28
P28
Kill_SW# change from U26.G24 to U26.K1
Add R949, C1002
Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS
Add R953
er Kill_SW# function needs event pin
Requirement of implementing SUSCLK
For customer request (PWR consumption)
For PC Beep circuit
B
0.2 P29 Add R954, R955 For customer request (PWR consumption)
yb
0.2 P13 Add C1003, U48, R956, R957 For PX GPU_RST# function
P18 Delete R556, R841, R889, D28
0.2 P09 Add R961 and R962 For DDR SO-DIMMB strap pin reservation
0.2 P05 Delete T74, T75 For layout limitation
A 15 only part A
Change footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
: For cost down purpose to change parts Size Document Number Rev
20100812 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6757P
Date: Tuesday, November 30, 2010 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1
.ru
0.3 P20 U10.5, U46.5, and U44.5 change from +3VS to +3VGS For BACO circuit update
0.3 P28 Delete R951 For unnecessary part deletion
0.3 P07 C623 change to unpop Base on AMD checklist
0.3 P16 Delete C734, add C1006, C1007 For ME concern
0.3 P21 R924 cahgne pull-up from +3VS to +3VALW For BACO design correction
0.3 P21 R925 change to pop For BACO design correction
m
0.3 P14 Reserve C1008 at FCH_PWRGD For EMI request
C 0.3 P14 Reserve C1009 at VGATE For EMI request C
ru
0.3 P28 pop C849, C850, R692, R693, R696, C826 For EMI request
0.3 P27 Add C1012, C1013 For EMI request (gas discharge tube)
0.3 P27 Add D1 For EMI request (ESD diode)
0.3 P28 update R672 location For EMI request (RC to GND for codec BIT_CLK)
Fo
0.3 P07 Delete C617 For EMI solution space needed
0.3 P28 Pop D30, D31, unpop R953 For FCH PC-beep function
0.3 P31 R751 and R752 change from 4.7K ohm to 2.2K ohm For PWR team request
0.3 P13 C719, C720 change from 22P to 18P For RTC design
B
1.0
1.0
1.0
1.0
P5
P10
P11
P12
unpop R415
R486, R487 change pull-high to +5VS
R522, R523 change from 2.2K to 2K
reserve R964, R965, change R546 ~ R549 from 4.7K to 2K
er AMD checklist update
AMD checklist update
AMD checklist update
AMD checklist update
B
yb
1.0 P31 BATT_LEN# added to U33.38 PWR team request
1.0 P20 Delete R341 For design update
1.0 P21 Delete R837, R832, R836 For design update
1.0 P28 Delete R947, R948, R950, R952 For design update
1.0 P29 Delete R955, R954, R810 For design update
C
A A
Change footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR2
: For cost down purpose to change parts Size Document Number Rev
20100812 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6755P
Date: Tuesday, November 30, 2010 Sheet 48 of 48
5 4 3 2 1
5 4 3 2 1
0.3 P23 Reserve C1005 For PWR team request reserving a 330u capcitor
0.3 P33 C939 change to 5.9H OS-con For cost saving
0.3 P33 R902 and R942 change to unpop For eSATA function deletion
0.3 P29 U32 change PN to SA000046C00 For main source PN concern
0.3 P05 Delete JHDT1 For layout limitation
0.3 P11 Add F2 and change SM-BUS pull high net name to +5VS_HDMI_F For safety team requirement
.ru
0.3 P21 change J3 footprint For larger jumper footprint
0.3 P21 R856 change from 20K to 39K For VGA power sequence
0.3 P11 Add net name +5VS_HDMI_F For power trace indecation
0.3 P20 Change Q69 ~ Q72 PN For design correction
0.3 P28 Add R963 For 20671-21Z update
0.3 P28 Change U31 PN to SA00003K410 For 20671-21Z PN
m
0.3 P20 U10.5, U46.5, and U44.5 change from +3VS to +3VGS For BACO circuit update
0.3 P28 Delete R951 For unnecessary part deletion
C C
0.3 P07 C623 change to unpop Base on AMD checklist
0.3 P16 Delete C734, add C1006, C1007 For ME concern
ru
0.3 P21 R924 cahgne pull-up from +3VS to +3VALW For BACO design correction
0.3 P21 R925 change to pop For BACO design correction
0.3 P14 Reserve C1008 at FCH_PWRGD For EMI request
0.3 P14 Reserve C1009 at VGATE For EMI request
0.3 P31 Reserve C1010 at VR_ON For EMI request
Fo
0.3 P13 Reserve C1011 at H_PWRGD_L For EMI request
0.3 P28 pop C849, C850, R692, R693, R696, C826 For EMI request
0.3 P27 Add C1012, C1013 For EMI request (gas discharge tube)
0.3 P27 Add D1 For EMI request (ESD diode)
0.3 P28 update R672 location For EMI request (RC to GND for codec BIT_CLK)
0.3 P07 Delete C617 For EMI solution space needed
B
0.3
0.3
0.3
1.0
P28
P31
P13
P5
Pop D30, D31, unpop R953
R751 and R752 change from 4.7K ohm to 2.2K ohm
C719, C720 change from 22P to 18P
unpop R415
er For FCH PC-beep function
For PWR team request
For RTC design
AMD checklist update
B
yb
1.0 P10 R486, R487 change pull-high to +5VS AMD checklist update
1.0 P11 R522, R523 change from 2.2K to 2K AMD checklist update
1.0 P12 Add R964, R965, change R548, R549 from 4.7K to 2K AMD checklist update
unpop R546, R547, Q89
1.0 P46 Kill_SW#_R change from JLED1.5 to JLED1.12 Design change update
1.0 P20 Delete R341 For design update
1.0 P21 Delete R837, R832, R836 For design update
1.0 P28 Delete R947, R948, R950, R952 For design update
1.0 P29 Delete R955, R954, R810 For design update
1.0 P30 unpop C887, C888 For design update
A 1.0 P25 unpop C494, C484, C498, C482, C490 For design update A
Change footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR2
: For cost down purpose to change parts Size Document Number Rev
20100812 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA6757P
Date: Tuesday, November 30, 2010 Sheet 48 of 48
5 4 3 2 1