Measurement xxx (xxxx) xxx

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Measurement
journal homepage: www.elsevier.com/locate/measurement

Variable switching frequency hybrid PWM technique for switching loss

reduction in a three-phase two-level voltage source inverter
Anas Ibrahim ⇑, Muhamad Zahim Sujod
Faculty of Electrical and Electronic Engineering, University Malaysia Pahang, 26600 Pekan, Pahang, Malaysia

a r t i c l e i n f o a b s t r a c t

Article history: Power loss reduction is one of the main objectives in power electronic system design for achieving higher
Received 10 November 2018 efficiencies and enhancing system reliability. In this regard, this paper aims to develop a variable switch-
Received in revised form 8 September 2019 ing frequency hybrid pulse width modulation (VSF-HPWM) method to maximize loss saving while main-
Accepted 19 October 2019
taining the same current total harmonic distortion (THD) of the conventional scheme. In doing so, this
Available online xxxx
technique utilizes the modulation signal and the switching frequency simultaneously. Using a predefined
mathematical representation of current ripple in every switching cycle, the modulating signal (either dis-
Keywords:
continuous or conventional space vector modulation) with lower RMS current ripple is applied.
Voltage source inverter (VSI)
Switching losses
Meanwhile, the number of commutations under the constrains of constant RMS ripple is reduced by vary-
Total harmonic distortion (THD) ing the switching frequency. The performance analysis is validated through MATLAB Simulink which
Discontinuous pulse width modulation shows that the proposed strategy can save up to 53% of switching losses with a similar THD of the con-
(DPWM) ventional scheme.
Conventional space vector modulation Ó 2019 Elsevier Ltd. All rights reserved.
(CSVPWM)
Variable switching frequency (VSF)

1. Introduction
Three-phase two-level voltage source inverter (VSI), shown in
Fig. 1, is the most widely used power electronic technology in sev-
eral applications such as industrial automation, transportation, and
renewable energy [1]. In many of these applications, such as
renewable energy, the high penetration imposes additional
requirement on the system. Modern systems require not only high
current quality, but also lower power losses for improved effi-
ciency [2].
The selection of the pulse width modulation (PWM) strategy
has deep impacts on the current total harmonic distortion (THD),
and the power losses of the inverter. Conventional space vector
modulation (CSVPWM), is the most widely implemented PWM
strategy for three-phase two-level VSI applications. Nevertheless,
the selection of the switching frequency is a compromise between
the THD and the power losses of the inverter. Higher switching fre-
quencies improve the THD on one hand. But this comes at the
expense of increased inverter power losses on the other.
The Power losses of the switching device can be classified into
two main categories including conduction, and switching loss.
The first loss source is static and almost depends on the device
⇑ Corresponding author.
E-mail addresses: MES18001@stdmail.ump.edu.my (A. Ibrahim), zahim@ump.
edu.my (M.Z. Sujod).
technology [3]. On the other hand, switching loss can be varied
among different factors. Mainly, in the case when the dc link volt-
age is constant, the switching loss becomes directly dependent on
the line current amplitude through the switch, and the switching
frequency [4]. Concerning the last two factors, several PWM strate-
gies for switching loss reduction were presented in the literature
which can be classified into: modulation, and variable switching
frequency PWM techniques.
Using the modulation technique, a discontinuous PWM
(DPWM) strategy is proposed. In DPWM, a phase leg is clamped
for 120° duration divided equally between the positive and the
negative dc bus. When the clamped region perfectly align the line
current peak, a 25% switching loss reduction can be achieved [20].
In spite of their superior performance in terms of loss saving, these
modulation schemes have very poor THD compared to the
CSVPWM at low and medium modulation indices which increases
the power losses in the load [6]. To solve the high ripple issue of
the DPWM, a hybrid PWM technique (HPWM) is proposed in [7].
In this technique, the author suggested using both the DPWM
and the CSVPWM in which the selection between them is based
on the total fundamental cycle RMS current ripple. In fact, the
region for which DPWM surpasses the CSVPWM is narrow. There-
fore, the switching loss improvement is only restricted to modula-
tion index higher than 0.85 (0.65 reference voltage vector).
Instead of changing the modulation technique and while still
using CSVPWM strategy, applying variable switching frequency

https://doi.org/10.1016/j.measurement.2019.107192
0263-2241/Ó 2019 Elsevier Ltd. All rights reserved.

Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
two-level voltage source inverter, Measurement, https://doi.org/10.1016/j.measurement.2019.107192
2 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx
Fig. 1. Three phase two-level voltage source inverter.
represents another degree of freedom to reduce the switching loss.
In this technique the switching frequency is varying repeatedly in a
fundamental period to maintain constant ripple requirement. In
general, the existing techniques to vary the switching frequency
are as follows. First, by taking peak current ripple as a reference
(VSF1-CSVPWM) [8,9]. Second, based on the predicted RMS current
ripple (VSF2-CSVPWM) [10,11]. When VSF1-CSVPWM is used, the
switching frequency is always maintained below the nominal
value. Therefore, an appreciable switching loss reduction can be
achieved at high modulation indices where the current ripple vari-
ation is expected to be large. However, this improvement is accom-
panied with considerable harmonic distortion increase compered
to CSVPWM. On the contrary, VSF2-CSVPWM is able to maintain
the same THD levels of the CSVPWM. However, the switching fre-
quency is varying above and below the nominal value and thus
there will be no significant reduction in the switching loss.
It has been noticed that most of the previously mentioned tech-
niques either do not take current THD into consideration, or do not
achieve an acceptable power loss saving. In this context, this paper
proposes a variable switching frequency hybrid PWM (VSF-
HPWM) method. Using a predefined mathematical representation,
the switching cycle RMS current ripple of different PWM schemes
such as DPWM and CSVPWM can be predicted. Consequently, two
actions are taken to control the modulating signal and the switch-
ing frequency. Such that, the total fundamental cycle RMS current
ripple of the CSVPWM strategy is maintained constant. it has been
found that the proposed strategy allows for significant reduction in
switching loss while still meeting the same THD requirement of
the CSVPWM. For detailed explanation, the rest of this paper will
be organized as follows: Section 2, provide an overview of space
vector PWM and current ripple prediction methodology. Section 3
presents the design procedure of the proposed VSF-HPWM. Simu-
lation results are presented in Section 4. Finally, Section 5 con-
cludes this paper.
2. Overview of space vector PWM and current ripple prediction
The three-phase two-level VSI with three upper switches (S1to–
S3), and three lower switches (S4–S6) is shown in Fig. 1. In a two-
level VSI case, the phase voltages (V AN , V BN , or V CN ) can take only
one out of two values, either the dc bus voltage (V dc ) or 0. Talking
phase-A as an example, V AN equals V dc when S1 is closed and S4 is
open. On the other hand, V AN equals 0 when S1 is open and S4 is
closed. The output voltage vector of the VSI with respect to the
negative dc-bus (N) can be expressed as shown in (1) [12].


V O ¼ V AN þ V BN  ejð 3 Þ þ V CN  ejð 3 Þ
2p 4p
ð1Þ
By substituting all possible combinations between V AN , V BN , and
V CN into (1), a total of eight possible voltage vectors can be pro-
duced as shown in Fig. 2. The two zero states V 0 ð000Þ and
Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
two-level voltage source inverter, Measurement, https://doi.org/10.1016/j.measurement.2019.107192
V 7 ð111Þ produces a voltage vector of zero magnitude. On the other
hand, the other states from V 1 to V 6 produce an active voltage vec-
tor each. These active states divide the space vector diagram into
six equivalent sectors with equal magnitudes. The magnitudes
are normalized with respect to V dc .
In the space vector PWM, the voltage reference is given as a
rotating reference vector (see Fig. 2), which is sampled once in
every switching cycle (T s ) using the three nearest vectors. Given
a reference vector of magnitude V ref and angle h in sector-1 as
shown in Fig. 2, the dwell times of active vector V 1 ð100Þ, active
vector V 2 ð110Þ, and the two zero vectors V 0 ð000Þ and V 7 ð111Þ in
a switching cycle are given by T 1 , T 2 , and T 3 respectively in (2)–
(4) [13].
sinð60  hÞ
T 1 ¼ V ref   Ts ð2Þ
sinð60Þ
sinðhÞ
T 2 ¼ V ref   Ts ð3Þ
sinð60Þ
T 3 ¼ T s  ðT 1 þ T 2 Þ ð4Þ
The difference between the applied voltage vector and the ref-
erence voltage vector is referred to as the error voltage vector.
For a given reference voltage vector in sector-1, the error voltage
vector due to the application of vector V x ðx ¼ 0; 1; 2; 7Þ is shown
in Fig. 3(a). The time integral of the error voltage vector is a mea-
sure of the current ripple (Iripple ) which can be defined as follows:
Z
1 Ts  
Iripple ¼  V x  V ref dt ð5Þ
L 0
where L is the load inductance. Using (5) the current ripple can be
analyzed in ab-domain [14], abc-domain [15], and in the dq-domain
[16]. In this paper the dq analyses will be considered due to its sim-
plicity in comparison with the other two domains where the q-axis
is aligned with the reference vector and the d-axis is 90° apart from
the q-axis component as seen in Fig. 3(a). Considering a CSVPWM
and a reference voltage vector in sector-1, the switching sequence
starts with one zero vector and ends with the other such as,
V 0 V 1 V 2 V 7 where T 3 is equally divided between the two zero vec-
tors. The current ripple trajectory for sequence V 0 V 1 V 2 V 7 (or
CSVPWM) is shown in Fig. 3(b). When the switching period starts
at time t ¼ 0, the tip of the current ripple vector is located at the ori-
gin point O. When a zero vector V 0 is used for a time t 2 ð0; T 3 =2 to
synthesize the reference vector, the current ripple vector moves in a
direction similar to the error voltage vector V 0  V ref from point O to
Fig. 2. Inverter states and voltage vectors.
 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx
Fig. 3. (a) Error voltage vectors in sector-1 (b) current ripple trajectory for sequence V 0 V 1 V 2 V 7 (c) current ripple trajectory for sequence V 7 V 2 V 1 .
point ðq1 ; d1 Þ. In the same manner, when the voltage vector V 1 is
applied during time t 2 ðT 3 =2; T 3 =2 þ T 1 , the terminal of the current
ripple vector moves in the same direction of V 1  V ref from point
ðq1 ; d1 Þ to point ðq2 ; d2 Þ. When t ¼ T 1 þ T 3 =2, the tip of the current
ripple vector is at point ðq2 ; d2 Þ. Therefore, when voltage vector V 2
is applied for t 2 ðT 1 þ T 3 =2; T s  T 3 =2, the tip of the current ripple
vector moves in the same direction of V 2  V ref to point ðq3 ; d3 Þ.
Finally, it returns to the origin point again when vector V 7 is
applied. The corner points (qy , dy ; y = 1,2,3) are shown in Table 1,
while the switching cycle RMS current ripple can be numerically
approximated in (6) [8,17].
2
X 2 2 and Emax is the maximum switching energy loss which occurs when
I sequence ¼ Ty  ½q2y þ q2yþ1 þ dy þ dyþ1 þ qy qyþ1 þ dy dyþ1 
y
Similarly, the current ripple trajectory for any given DPWM
scheme can be created in the same fashion as the CSVPWM
scheme. The current ripple trajectory for sequence V 7 V 2 V 1 is
shown in Fig. 3(c) and the corner points are provided in Table 1.
It should be noticed that different load power factors require dif-
ferent types of DPWM scheme to maximize switching loss saving
which is out of the scope of this paper. More details on different
DPWM types could be found in [5,18]. For simplicity, the analysis
in this paper is carried out for sequence V 7 V 2 V 1 only and termed
as DPWM.
3. Proposed variable switching frequency hybrid PWM method
for switching loss reduction (VSF-HPWM)
Switching loss is the type of loss that occurs due to the non-
ideal characteristic of the switching device. When the switch is
turned on, the device current increases from zero to the line cur-
rent, and the blocking voltage drops to almost zero. Since this tran-
sition does not occur instantaneously, both current and voltage are
Table 1
Vertex of the current ripple trajectory for CSVPWM and DPWM.
Modulation Corner points
scheme
n o
CSVPWM ðq1 ; d1 Þ ¼ V ref  T23 ; 0
n
 o
ðq2 ; d2 Þ ¼ cosðhÞT 1  V ref T 1 þ T23 ; sinðhÞT 1
n o
ðq3 ; d3 Þ ¼ V ref  T23 ; 0
 
DPWM ðq1 ; d1 Þ ¼ V ref  T 3 ; 0
 
ðq2 ; d2 Þ ¼ cosð60  hÞT 2  V ref ðT 2 þ T 3 Þ; sinð60  hÞT 2
Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
two-level voltage source inverter, Measurement, https://doi.org/10.1016/j.measurement.2019.107192
3
nonzero which causes some power to be dissipated. During turn
off, the device behaves in vice versa [19]. The power loss due to
switching (P sw ) is given as:
Psw ¼ E  f sw ð7Þ
where E is the switching energy loss, and f sw is the switching fre-
quency. Assuming a sinusoidal line current, the energy loss can be
approximated as follows:
E ¼ Emax  sinðxt  uÞ ð8Þ
where x is the fundamental frequency, u is the power factor angle,
ð6Þ 
the line current reaches its peak (xt  u ¼ 90 ) [2]. As shown in (7),
the switching loss can be minimalized by reducing the switching
frequency. In addition, clamping a phase leg at the line current peak
using DPWM represents another degree of freedom to reduce the
switching loss as seen in (8). The proposed technique aims to opti-
mize both by applying two control actions on the modulating signal
and the switching frequency. In doing so, the control strategy can be
arranged as follows:
3.1. Selection of the modulating signal:
When CSVPWM or DPWM is used to modulate an inverter, the
RMS current ripple over a switching cycle will follow the known
shape which can be predicted by evaluating Table 1 data into (6).
A will-known feature in DPWM scheme over CSVPWM is that the
number of switching transitions during each switching cycle is
reduced from 3 to 2. Hence, to compare both schemes at the same
average switching frequency, a switching cycle duration T s ¼ 23 T nom
has been considered for the DPWM scheme, while T s ¼ T nom for the
CSVPWM [20]. Fig. 4(a) and (b) presents the variation of I2 CSVPWM
and I2 DPWM with the spatial angle h at V ref = 0.75p.u and
V ref = 0.6p.u, respectively. The terms I2 CSVPWM and I2 DPWM are
used to donate the switching cycle RMS current ripple of the
CSVPWM and the DPWM, respectively.
Based on the switching cycle RMS current ripple, the modula-
tion strategy could be selected. Such that, if I2 CSVPWM is less than
I2 DPWM, CSVPWM will be selected, otherwise DPWM is selected.
The DPWM can effectively reduce the switching loss as explained
in [7] and [20]. However, by comparing Fig. 4(a) and (b), it’s found
that the region for which I2 DPWM is less than I2 CSVPWM gradually
reduces as V ref goes down which will significantly reduce the
switching loss saving capabilities. Therefore, in order to maximize
4 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx

(a) (b)
Fig. 4. Switching cycle RMS current ripple variation at (a) V ref = 0.75p.u. (b) V ref = 0.6p.u.

loss saving as much as possible, the switching frequency is also

manipulated as shown in Section 3.2.

3.2. Control on the switching frequency

The RMS ripple for both schemes (DPWM and CSVPWM) is not
constant and keeps changing with respect to V ref and h [see Fig. 4
(a) and (b)]. Therefore, the switching frequency is allowed to be
changed above and below its nominal frequency (f nom ). Such that,
the RMS current ripple in every switching cycle follows the total
fundamental cycle RMS current ripple of the conventional scheme
which is shown in the blue solid line in Fig. 4(a) at V ref = 0.75p.u.
Since the conventional scheme employs CSVPWM as a modulation
strategy, the total fundamental cycle RMS current ripple (Irms ) can
be determined as a function of V ref as follows:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Z 2p
1
Irms ¼ I2 CSVPWM dh ð9Þ
2p 0

Using the predicted switching cycle RMS current ripple in (6),

the switching frequency coefficient (K f ) which keeps Irms constant
in every switching cycle is defined as follows:
if I2DPWM  I2CSVPWM
3 I2 DPWM
K f ðV ref ; hÞ ¼ 
2 Irms
While if I2DPWM > I2CSVPWM
I2 CSVPWM
K f ðV ref ; hÞ ¼
Irms
Fig. 5 shows K f variation in one fundamental cycle with 50 Hz
fundamental frequency and V ref = 0.75p.u. It is clearly shown that
there is an instantaneous change on the switching frequency coef-
ficient in every 60° of the fundamental cycle due to the 3/2 factor
during transmutation from CSVPWM into DPWM. Fig. 5 also indi-
cates a large decrease on the average switching frequency due to
two different factors. First, when a variable switching frequency
is applied on CSVPWM alone, K f decreases below 1 when
I2 CSVPWM is less than Irms around both the boundaries, while it
goes above 1 when I2 CSVPWM is higher than Irms around h = 30°
(see Fig. 4(a)). Due to this action, the switching loss reduction is
not going to be much significant. However, because of the hybrid
scheme in the proposed strategy, the regain around h = 30° is
almost covered by the DPWM especially, at high values of V ref
Fig. 5. K f variation for V ref = 0.75p.u and 50 Hz fundamental frequency.
which describes why K f is always maintained below 1 in Fig. 5
when CSVPWM is applied. Second, the required K f when DPWM
ð10Þ
is applied is much lower than 3/2. This is due to the fact that,
I2 DPWM at this value of V ref is always lower than Irms (see Fig. 4
(a)). Therefore, a significant improvement on the switching loss
saving capabilities is expected.
ð11Þ
4. Simulation result
The simulation is implemented via MATLAB/Simulink to inves-
tigate the operation and performance of the proposed PWM tech-
nique. The discussed PWM technique is tested on an open loop
system with simple RL-load supplied by a three-phase two-level
voltage source inverter (see Fig. 1). The system specifications are
shown in Table 2. Fig. 6 shows a flowchart of the proposed strategy.
The current ripple value I2 CSVPWM and I2 DPWM are calculated
online using the instantaneous value of h and V ref . This value is sent
to a conditional statement block to determine which modulation
strategy is going to be adopted and to vary the switching frequency
(f sw ). In the case when the output of the conditional statement is
true, the switching frequency is calculated as the multiplication

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 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx 5

Table 2 VSF-HPWM, the harmonic components are widely distributed

SYSTEM specification.
Parameter Value
V dc 250 V
Switching device Fuji 2MBI150U2A-060 IGBT
Fundamental frequency 50 Hz
f nom 5 KHz
R 4X
L 0.5 mH
between the nominal frequency (f nom ) and the switching frequency
coefficient given in (10). This value is then used to determine the
dwell times T 1 , T 2 , and T 3 using (2)–(4). Finally, the DPWM switch-
ing pattern is used to generate the PWM signal of the switching
devices. On the other hand, when the output of the conditional
statement is false, the same procedure is adopted. However, the
switching frequency this time is determined as the multiplication
of (11) and f nom while CSVPWM switching pattern is used to apply
the PWM signal of the switching devices. The value Irms is calcu-
lated off-line using (9) and then stored in a lockup table (LUT) to
generate the corresponding value at every V ref .
Fig. 7 shows the frequency spectra of the measured inverter
phase-A line current at f nom = 5 KHz and V ref = 0.75p.u. Fig. 7(a) cor-
responds to CSVPWM, whereas Fig. 7(b) is related to the proposed
VSF-HPWM. When CSVPWM is employed, the harmonic compo-
nents are only concentrated as discrete tonal components around
5 KHz nominal frequency and its multiples. In case of the proposed
along the frequency spectrum, as the first harmonic component
is spread from 2250 Hz to 7300 Hz with a dominant frequency
component between 5100 Hz and 7183 Hz. This is reasonable,
since the DPWM region at this value of the reference voltage vector
is larger [see Fig. 4(a)] which means that most of the frequency
components are shifted by a factor of 3/2. As shown, the large har-
monic components in Fig. 7(a) are significantly mitigated in Fig. 7
(b) because of the wider harmonic distribution which is regarded
as an important issue for the acoustic noise reduction in the induc-
tor [21,10,11].
The line current waveforms are shown in Fig. 8. Where the cal-
culated current THD is 9.87% for CSVPWM [see Fig. 8(a)] and 9.89%
in the case of VSF-HPWM [see Fig. 8(b)]. It can be noticed that, the
current THD of the proposed VSF-HPWM is approximately similar
to that of CSVPWM. Hence, the proposed strategy does not lead to
an additional loss in the load.
To assess the performance of the proposed strategy, a compar-
ison is made with the CSVPWM and the existing HPWM [7] regard-
ing the switching loss saving in the entire V ref range. The power
loss in this paper is evaluated via an existing MATLAB model.
Fig. 9 compares the switching instances in one of the switching
devices (S1) for the three mentioned PWM strategies at half funda-
mental cycle and V ref = 0.75p.u. Fig. 9(a) corresponds to CSVPWM,
whereas Fig. 9(b) and (c) are related to HPWM and the proposed
VSF-HPWM respectively. For more clarity, the nominal switching
frequency in this graph is stepped down to 1 KHz. It’s seen that
both CSVPWM and HPWM switch equally for 20 times in half

Fig. 6. Flowchart of the proposed method.

Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
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6 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx

(a) (b)

Fig. 7. Frequency spectra of the measured inverter phase-A line current at f nom = 5 KHz and V ref = 0.75p.u for (a) CSVPWM, (b) proposed VSF-HPWM.

Fig. 8. Line current waveform for (a) CSVPWM (THD = 9.87%), (b) proposed VSF-HPWM (THD = 9.89%).

fundamental cycle which means that both have the same average
switching frequency of 1 KHz. On the contrary, the proposed
VSF-HPWM switches only 16 times at the same period leading to
20% reduction on the average switching frequency and conse-
quently, a large switching loss reduction.
Fig. 10 shows the normalized switching loss saving for HPWM
(blue) and the proposed VSF-HPWM (red) with respect to the
CSVPWM (green). HPWM selects the modulation strategy based
on the total fundamental cycle RMS current ripple. When
V ref > 0.65p.u, DPWM results in a lower total fundamental cycle
RMS ripple than its CSVPWM counterpart. Hence, a 25% switching
loss saving can be achieved. As V ref goes down below 0.65p.u, the
total fundamental cycle RMS ripple of the CSVPWM surpasses
the DPWM. Therefore, the switching loss saving capabilities of
HPWM reduces to 0% which is clearly shown in Fig. 10. On the
other hand, the proposed VSF-HPWM updates both the switching
frequency and the modulating signal based on the switching cycle
RMS current ripple which allows for higher switching loss saving
compared to HPWM. As shown, the switching loss saving of VSF-
HPWM can be divided into two areas. First, when V ref < 0.52p.u,
the switching cycle RMS current ripple of the CSVPWM is always
lower than its DPWM counterpart, hence there is only 2–4%
switching loss reduction in this area. This is due to the fact that,
when CSVPWM is applied the required switching frequency devia-
tion above the nominal switching frequency in the high ripple
region is slightly lower than its deviation below the nominal fre-
quency in the low ripple region which allows for small reduction
on switching loss. Second, when V ref > 0.52p.u, the proposed strat-
egy also leads to the highest switching loss saving which can reach
up to 53.7% at V ref = 0.866p.u. Similar to the analytical results at
Sections 3.1 and 3.2, due to the increase of the DPWM region at
higher values of V ref the switching loss reduction is higher. In addi-
tion, the high ripple region of the CSVPWM becomes almost cov-
ered by the DPWM strategy which results in a significant
reduction in the switching frequency and consequently a further
reduction in the switching loss.
Table 3 shows the total inverter switching losses for both
CSVPWM and VSF-HPWM. It’s shown that the proposed VSF-
HPWM not only achieve higher switching loss saving than HPWM,
but also expand the improvement region. Since, the current ripple
is evaluated each switching cycle which allows for further exten-
sion of the DPWM region at lower values of V ref . As shown, an
appreciable switching loss saving can be achieved in the range of
V ref between 0.55p.u to 0.866p.u.

Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
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 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx 7

CSVPWM) and the switching frequency. Such that, the total funda-
mental cycle RMS current ripple of the CSVPWM is maintained
constant. Beyond the possibility of minimizing the switching loss
due to the DPWM scheme, the theoretical analysis shows that,
when two modulation schemes are considered in the design, a sig-
nificant reduction in the switching frequency and consequently a
further reduction in the switching loss can be achieved especially,
at high values of V ref . The modulation strategy is tested on an RL-
load and compared to the conventional and existing HPWM strate-
gies, concluding that, the proposed technique is able to achieve the
highest switching loss saving. The proposed technique can save up
to 53% of switching loss (best case at V ref = 0.866p.u). On the other
hand, the THD values of the proposed strategy are kept the same as
the CSVPWM which means that the load losses are not increased.

Acknowledgements

The authors wish to gratefully thank Universiti Malaysia

Pahang (UMP) for the financial support received under project
number RDU1803165.

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Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
two-level voltage source inverter, Measurement, https://doi.org/10.1016/j.measurement.2019.107192
8 A. Ibrahim, M.Z. Sujod / Measurement xxx (xxxx) xxx

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Please cite this article as: A. Ibrahim and M. Z. Sujod, Variable switching frequency hybrid PWM technique for switching loss reduction in a three-phase
two-level voltage source inverter, Measurement, https://doi.org/10.1016/j.measurement.2019.107192