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Introduction
Aggressive scaling down of devices sizes leads to the use of a new kind of devices;
the advantages presented by Multiple-Gate Field Effect Transistors (MuGFET) such as
reduced drain output conductance, quasi ideal gm/IDS, high values of open loop gain, are
very important characteristics taken into account for designers interested in improving the
performance of analog integrated circuits (1). In figure 1 it is presented the schematic of a
FinFET device, as can be noticed high values of series resistance and extrinsic
capacitances can be present in this devices due to the geometry of the transistor.
In recent years the use of MuGFET technology has become a real alternative for digital
applications; nevertheless for analog applications there are some limitations, the main
limitation are the high values of fringing and parasitic capacitances presented in this kind of
devices which affect the performance of analog circuits at high frequencies (2). With a
reduction in the values of the capacitances this technology could be an alternative to planar
CMOS at high frequencies (3).
177
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ECS Transactions, 49 (1) 177-182 (2012)
An analytical and compact FinFET model that can reproduce the electrical behavior of
the transistor in all operation regimes is required for circuit simulation. The Symmetric
Doped Double-Gate Model (SDDGM) (4-5) has been validated for different types of
FinFETs working as a Double-Gate transistor. In addition, the simulation of analog circuits
requires continuous derivatives of the charges at the device terminals allowing the accurate
calculation of the nine intercapacitances. In SDDGM all capacitances can be calculated
using analytical expressions that were validated in previous works (6). The SDDGM was
implemented in Verilog-A and introduced in SmartSPICE (7) considering variable
mobility, short-channel effects and the effect of the temperature variation.
The Miller Operational Amplifier is one of the most important basic blocks for analog
signal processing, A/D and D/A converters and filtering applications. In Figure 2 it is
presented the schematic view of the Miller OpAmp used in this work. The design is the
same of reference (8) and in 2b we present the OpAmp (OA) configured with a gain target
of 20dB.
Vdd
10R
P1 P2 P3
R
R
I Vout -
C Vout
Vin +
inn M1 M2 inp
Vcm Vcm
M3 M4 M5
Vss
(a) (b)
Figure 2. a) Schematic view of the Miller OpAmp; b) Configured with a gain target of 20dB.
In the design of the Miller OA the capacitance has a value of 2pF, the resistance R a
value of 100 k and the geometry for all devices is L = 250 nm, Hfin = 88 nm, Wfin = 55
nm. In Table I the transistor type and the total number of fins are shown. These
characteristics are similar to the Miller OA presented in the literature and used to
calibrate the simulations at room temperature (9)
Table I. Characteristics of the transistors used in the OpAmp
178
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ECS Transactions, 49 (1) 177-182 (2012)
Not many works have done a study of the performance of analog circuits at high
temperatures; previously it was simulated the fabricated Miller OA of reference (8) and
results of simulation show a good agreement with experimental results (9). In this paper we
made the circuit simulation of the Miller OA at high temperatures in order to observe the
effect in the characteristics of the OA.
The effect of temperature is considered in the following expressions: for the thermal
potential [1]; for the bandgap value [2] and for maximum mobility value [3].
k T
t
q [1]
k being the Boltzman constant, T the absolute temperature and q the electron charge.
3002 4 T2
Eg 0 1.08 4.73x10 , [2]
300 636 T 636
o
S 1
1.2 2
T E 3 E
1
300 E1 E2 , [3]
where E1 is the critical field for ion scattering, E2 is the critical field for scattering at the
surface roughness.
With the purpose of simulate the OA, it was necessary to extract a set of few
parameters regarding to the effective mobility, the channel length modulation and the
saturation voltage. The methodology was the same of reference (9) where FinFETs with
different lengths for N-Channel and for P-Channel devices were measured, parameters
were extracted and the results were interpolated according to the design of the Miller OA.
In table II we present the FinFET parameters for the OA including the series
resistance, for N-Channel FinFETs and for P-Channel devices.
Series resistance
Parameters
R (k)
E1 (V/cm) E2(V/cm) E2V vsat 8 fins 64 fins 128fins
N-Channel 4E4 3.5E5 0.03 0.3211 1.953 7.334E6 4 1.1 0.1
P-Channel 3E4 3.4E6 0.04 0.55 1.9 3.56E7 5 3.2 0.3
In figure 3 we show the simulation of an individual FinFET with L= 190 nm; Wfin=
20 nm; 30 fins; equivalent gate oxide thickness (EOT) of 2 nm and TiN metal gate
electrode, at two different temperatures; a good agreement is obtained between
simulation results and measurements.
179
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ECS Transactions, 49 (1) 177-182 (2012)
800
Measured @ T = 300K 1.4 Measured @ T = 300K
100 Simulated @ T = 300K 700 Measured @ T = 473K 2.0
Measured @ T = 473K 1.2 Simulated @ T = 300K
Simulated @ T = 473K 600 Simulated @ T = 473K
1.5
1.0
500
50
Id (A)
gm (mS)
1.0
0.8
gm (S)
Id (mA)
400
0.6 0.5
300
0
0.4
200 0.0
0.2
100
-0.5
-50
0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
Vg (V) Vg (V)
Figure 3. a) Drain current and transconductance of a FinFET at different temperatures at a drain voltage of
50mV; b) Drain current and transconductance at different temperatures at a drain voltage of 1V.
As it can be noticed from figure 3, there is a reduction of the drain current and
consequently in the transconductance, it occurs due to the carrier mobility degradation as
T increases. In figure 4 it is shown the gm/ID ratio as a function of the drain current ID and
the drain output conductance for the same device. We can see that there is a reduction in
the output conductance and it drops almost linearly with temperature.
35
Measured @ T = 473K
Simulated @ T = 473K
30
Measured @ T = 300K
Simulated @ T = 300K
25 1E-3
20
gm/ID
gd (S)
15
Measured @ T = 473K
10 Measured @ T = 300K
Simulated @ T = 473K
5 Simulated @ T = 300K
1E-4
0
1E-7 1E-6 1E-5 1E-4 1E-3 0.0 0.2 0.4 0.6 0.8 1.0
ID (A) Vd (V)
Figure 4. a) Transconductance over drain current ratio at Vd = 1.02V; b) Drain output conductance at Vd =
1.02V.
Figure 5 shows the validation of this simulation where experimental results are compared
with the circuit simulation.
20
Gain A (dB)
10
Simulated
Experimental
0 T=300K
-10
1 2 3 4 5 6 7
10 10 10 10 10 10 10
F (Hz)
Figure 5. Frequency response of the Miller OpAmp, experimental and simulated results.
180
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ECS Transactions, 49 (1) 177-182 (2012)
In figure 6 the temperature effect in the frequency response and the phase of the Miller
OA is shown. As can be noticed the performance is affected with the increase of
temperature; the maximum gain value is reduced from 18.8 dB at 300 K to 15.5 dB at 473
K. From our results it can be seen that there is a nonlinear maximum gain reduction with
the increase of temperature; additionally from our simulations, beyond 573K this OA
stops working with reliability; this is better than ICs made with bulk devices that present
reliability problems at 473K(10).
The change of phase gives the variation in the gain and such variation corresponds to the
apparition of a pole in the break point where the phase is reduced and the apparition of a
zero in the break point where the phase is increased.
The cutoff frequencies are related to only the intrinsic lumped parameter elements (gm,
gd, Cgs and Cgd), as a consequence of the reduction in these characteristics there is a
reduction in these frequencies. The unity gain frequency fT (0 dB) of the amplifier is
reduced; it varies from 3.16 MHz at room temperature to 1.9 MHz at 373 K and to 1.58
MHz at 473 K.
0.2
0.0
20
-0.2
-0.4
Phase (rad)
T=300K
Gain A (dB)
10 T=373K
-0.6 T=473K
T=300K
T=373K -0.8
T=473K
0 -1.0
-1.2
-10 -1.4
1 2 3 4 5 6 7
10
1 2
10 10
3
10
4
10
5 6
10 10
7 10 10 10 10 10 10 10
F (Hz) F (Hz)
Conclusions
181
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ECS Transactions, 49 (1) 177-182 (2012)
zeros as shown in the phase diagram. This model can be used as design tool for analog
circuit design using FinFETs at high temperatures.
Acknowledgments
References
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182
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